WO2015035536A1 - 在基于闪存的存储系统中构建raid的方法及系统 - Google Patents

在基于闪存的存储系统中构建raid的方法及系统 Download PDF

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WO2015035536A1
WO2015035536A1 PCT/CN2013/001074 CN2013001074W WO2015035536A1 WO 2015035536 A1 WO2015035536 A1 WO 2015035536A1 CN 2013001074 W CN2013001074 W CN 2013001074W WO 2015035536 A1 WO2015035536 A1 WO 2015035536A1
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data
raid
data block
read
flash memory
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PCT/CN2013/001074
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English (en)
French (fr)
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周溱
阳学仕
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上海宝存信息科技有限公司
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Priority to US15/021,993 priority Critical patent/US9720770B2/en
Priority to CN201380079608.1A priority patent/CN105556480B/zh
Priority to PCT/CN2013/001074 priority patent/WO2015035536A1/zh
Publication of WO2015035536A1 publication Critical patent/WO2015035536A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G06F11/108—Parity data distribution in semiconductor storages, e.g. in SSD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents

Definitions

  • the present invention relates to a method of constructing a RAID in a flash-based storage system, and a system to which the method is applied.
  • BACKGROUND OF THE INVENTION Data storage technology based on flash memory (NAND Flash) has developed rapidly in the past decade, and has gradually replaced the traditional hard disk drive (HDD) in many applications. The main reasons are: Fast speed: Flash-based data storage is not like traditional HDD relying on mechanical addressing of the head, so that the data read and write speed is essentially improved, meeting the increasingly stringent requirements of the application for data storage throughput.
  • Flash requires a matching controller to communicate with the host for data storage.
  • the maturity of controller technology has enabled flash-based solid-state storage technology to find applications in more and more areas, including applications in high-end data centers and mobile smart phones.
  • the flash controller is the core part of the solid state drive (SSD) system. Its performance and function directly determine the performance and function of the SSD. It is also the most essential difference between consumer SSD and enterprise SSD.
  • RAID Redundancy Check Codes Due to data protection requirements, the calculation and writing of Redundancy Check Codes (RAID) is a must for enterprise applications. Due to the high price of flash memory, RAID methods such as mirroring (ie RAID-1) are not acceptable in normal application environments.
  • the method usually used in SSD is RAID5, that is, n data blocks generate 1 check block (n>>2). If the data is D0, Dl, ..., Dn, the parity code is D0, Dl, '".
  • the present invention will use the data structure of RAID 5 as For example, it should be pointed out that the method and system can also be applied to other RAID structures, such as RAID 6.
  • a major feature of flash memory is its non-rewritability: a page of data stored in flash memory must pass through The entire block in which the page resides can be erased before new data can be written. This poses a challenge to the Flash Translation Layer (FTL), but presents an opportunity for RAID, and RAID's additional write amplification no longer exists.
  • FTL Flash Translation Layer
  • a method for implementing dynamic RAID in an SSD is described in detail in Chinese Patent Application No. 201210256754. 4 "Volatile Memory-Based Dynamic Independent Redundant Array Storage System and Method".
  • the RAID5 data structure under SSD is shown in Figure 1.
  • Data blocks D0, Dl, D2, and D3 form a RAID data band, and DO, Dl, D2, and D3 are XORed to generate parity code D4.
  • D0, Dl, D2, D3 and D4 are stored in different flash units, respectively, in the LUN (logic Unit Number) to ensure that data can be recovered by XOR operation in case of failure of any one flash LUN.
  • LUN logic Unit Number
  • SSDs there are two main types of SSDs on the market: one is a consumer-oriented SSD that does not usually have a RAID5 function; the other is an enterprise-class SSD that includes a RAID5 function, but its performance is not satisfactory under read-write mixing.
  • a massively parallel multi-core multi-thread controller fully tailored for flash control is required to perform independent parallel operation on each flash chip (LUN).
  • RAID5 calculation and writing should consider the following factors: The data from the host is out of order, the subsequent instructions may be executed first; the data from the host is interleaved, one data block is not transmitted, another data block The transmission has started and partially arrived in advance; the parity code is written asynchronously: the verification code is not necessarily ready when the flash memory of the verification device needs to be written, and the read/write of the flash memory is controlled when the verification code is ready.
  • the processing unit may not be ready; the width of RAID5 (the number of data blocks that make up one RAID data strip, or the number of flash LUNs) is different for different applications; one read/write processing unit may control multiple flash chips, bringing more The possibility of deadlocks increases the difficulty of scheduling.
  • the technical problems to be solved by the present invention include: how to reduce the performance cost caused by RAID5 computing to achieve high performance requirements of a storage system such as an SSD; how to reduce the logical area of RAID5 to accommodate a small control unit of a storage system such as an SSD Chemical.
  • the present invention provides a method for constructing a RAID 5 in a flash-based storage system, which is capable of implementing a RAID 5 function in a very small logical area and an approximately negligible time, thereby realizing the function and performance of a storage system such as an enterprise-class SSD.
  • the method includes: submitting a check code programming instruction to a RAID processor, and reading and writing a single processing by the RAID processor Reading the partial data of the data block in the current data band, setting the data block pointer, corresponding to each flash memory unit, recording the input position of the current data block, and reading the data block portion read and written by the processing unit according to the current data block
  • the position of the pointer is used to calculate the parity code, and the result is written back to the parity code buffer, and the data block pointer increases the length value of the input partial data block, after the processing of all the data blocks corresponding to one flash memory unit is completed, that is, the data block When the pointer wraps around to zero, the number of data block processing completions is increased by one.
  • the data in the parity code memory is written into the corresponding flash memory.
  • the check code buffer is cleared, and the calculation of the next RAID data band is started until the data processing is completed.
  • the programming instructions for the check code must be issued before the data programming instructions of the next RAID data strip are submitted after all data programming instructions of the current AID data strip are committed.
  • a label is added to each input partial data block, indicating a read/write processing unit that processes the data block, a RAID processor to which the data block is directed, and a RAID data band to which the data block belongs.
  • the RAID processor broadcasts a short message to all the read/write processing units to prevent the read/write processing unit from crossing the RAID data band.
  • the short message includes the following information:
  • the current read and write processing unit reads data of the RAID processor. With the number; whether the current check code of this RAID processor can be read.
  • a read/write processing unit can control a plurality of flash memory units. When the read/write processing unit finds that the next operation is temporarily an illegal operation, it switches to another thread and operates on another flash memory unit chip.
  • the present invention also provides a flash-based storage system constructed with RAID 5,
  • the system comprises: one or more RAID processors and a plurality of flash memory units, wherein the RAID processor comprises a plurality of read and write processing units, a data block pointer unit, a data block counter, a parity code buffer, and a read/write processing unit
  • the RAID processor comprises a plurality of read and write processing units, a data block pointer unit, a data block counter, a parity code buffer, and a read/write processing unit
  • One or more flash memory units can be controlled, and the programming instructions of the check code are submitted to the RAID processor.
  • the command submission can be initiated by the source to the driver of the host, or initiated by the firmware, and the read/write processing unit reads the current data band.
  • the data block, the data block pointer unit is configured to record the input position of the current data block for each flash memory, the data block counter is used for counting the number of processed data blocks, and the parity code buffer is used for buffering the parity code.
  • the read/write processing unit reads the corresponding partial data block, performs a parity check operation according to the position of the current data pointer and the data in the parity code buffer, and writes the result back to the parity code buffer. After the calculation operation is completed, the data block pointer unit increases the length value of the input data for the data block pointer, and moves the corresponding data block.
  • the data block counter is incremented after the data block corresponding to one flash memory unit is processed, that is, when the data block pointer wraps around to zero, when the number of data blocks recorded by the data block counter reaches the number of data blocks included in the RAID data band.
  • the RAID processor further includes a RAID short message unit for broadcasting a short message to all the read/write processing units to prevent the read/write processing unit from crossing the RAID data band.
  • the short message contains the following information: The data band number currently read by the read/write processing unit allowed by the RAID processor; whether the check code of the current RAID processor can be read.
  • a read/write processing unit can control a plurality of flash memory units. When the read/write processing unit finds that the next operation is temporarily an illegal operation, it switches to another thread and operates on another flash memory unit chip. Also, the programming instructions for the checksum must be issued after the data programming instructions of the next RAID data strip are submitted after the data programming instructions of the current RAID data strip are committed.
  • the invention schedules the execution order between threads and read and write processing units by lock and message transfer, making calculation and correct writing of RAID5 possible; and using simple rules, the submission and execution of instructions are asynchronous and In the case of out-of-order, the instructions submitted under this rule do not deadlock.
  • the invention realizes the dynamic configurable RAID5 width, satisfies the needs of the application, and maximizes the independent autonomy of each read/write processing unit, thereby maximizing performance.
  • the present invention has the advantages that: the RAID parity code is generated by XORs of multiple data blocks, and each data block is stored in an independent storage unit; each data block participating in the RAID calculation is divided into at least two parts.
  • the RAID processor is input, and part of the data belonging to different data blocks is input into the RAID processor in a time division manner; the RAID processor outputs the parity code after all the data blocks belonging to the RAID group are completed; the data block part is input.
  • the position is recorded by the corresponding pointer to the input position to accommodate the interleaved, out-of-order and segmented data input in the RAID group; the data block counter allows the number of data blocks in the adjustable RAID group; the RAID processor adopts the short message broadcast mode scheduling Multiple flash read/write processing units prevent the read/write processing unit from operating across the RAID group; the RAID check code can be output in the data segment of the completed calculation without waiting for all data input of the entire AID group to be output.
  • DRAWINGS 1 shows a data structure of RAID 5 under SSD
  • FIG. 2 shows an example diagram of data block data out-of-order and interleaved input
  • FIG. 3 shows the present invention recording data input position in a RAID processor.
  • FIG. 4 is a block diagram showing the structure of a flash-based storage system to which RAID 5 is applied according to the present invention.
  • FIG. 5 is a block diagram showing the structure of a flash-based storage system to which a plurality of RAID processors are applied according to the present invention. DETAILED DESCRIPTION OF THE INVENTION Since a plurality of data blocks D0, D1, D2, ...
  • each data block will be processed by a corresponding read and write processing unit.
  • the input of the data block is allowed to implement interleaving and out-of-order input.
  • Figure 2 shows an example case of data block data out of order and interleaved input.
  • D0, D1, and D2 represent data blocks in the RAID data band, respectively, and part of the data in the Part0, Part 1, Part 2, ... table data block may be 64 bytes, 1 Kbyte, or any other length of data (less than or Equal to the length of data block D).
  • D2 PartO represents the first portion of data of data block D2
  • Dl Part2 represents the third portion of data of data block D1.
  • RAID5 calculation is to efficiently obtain DO, and the difference of data blocks. Or parity code. It is based on the following facts:
  • a read-write processing unit may control multiple flash units to store different blocks of data, but there is no interleaving between blocks within the same processor. Therefore, in order to ensure the correctness of the check code, the data input needs to meet the following conditions in the construction of RAID5:
  • RAID data band Data in the same RAID data band can be interleaved, but different RAID data bands must not be interleaved;
  • the parity code is calculated as follows: A label is added to each input data block to indicate the read/write processing unit that processes the data block, the RAID processor to which the data block is directed, and the data.
  • the data When the data is received, the data is XORed with the data in the check code buffer pointed to by the corresponding data block pointer and written back to the check code buffer, and the data block pointer increases the pointer value according to the input data length.
  • the data block pointer value reaches the data block length, it wraps around to zero, which means that the XOR operation of one data block is completed, and the data block processed by the processor is incremented by 1.
  • the number of data block processing in the current data band is recorded by the RAID processor, and the check code of the part of the data band that has been calculated is determined according to the number of completed data block processing and the position of each pointer.
  • the RAID processor can notify the corresponding read/write processing unit to start to retrieve the check code and write the corresponding flash memory unit.
  • the buffer is cleared, the calculation of the next RAID data band is resumed, and a new round of looping begins. Since each RAID processor only needs to reserve a full block size cache (usually 16KB), it can be implemented entirely on-chip SRAM, thus avoiding the use of off-chip DRAM and simplifying the design.
  • the RAID processor broadcasts a short message to all read and write processing units to prevent the read and write processing unit from crossing the RAID data band.
  • the short message contains the following information: The data band number currently read by the read/write processing unit allowed by the RAID processor; whether the current check code of the RAID processor can be read.
  • a read/write processing unit can control one or more flash units (LUNs) when the read/write processing unit finds that the next operation is temporarily illegal (for example, corresponding to the next one)
  • LUNs flash units
  • the data in the RAID data band is written), it switches to another thread and operates on another flash cell chip. This way the thread in which the faster flash chip is written will transfer the resource to the slower thread, making the progress of each thread roughly equal.
  • the purpose of the method of the present invention is achieved by minimizing the probability of illegitimate operation so that each read-write processing unit can approach full-load operation, with the measure being as early as possible at the point in time at which the check code begins to be read. Since the read/write processing unit of the corresponding verification device is usually idle, usually the reading of the verification code is completed in a short time after the last data block is processed, and the entire system can write the next data band. This shortens the window where data cannot be transferred. In addition, since the programming time of the flash chip is several times longer than the data transfer time, and two RAID 5 write points can be operated simultaneously in the system, even if one is temporarily disabled, the other can still operate, and therefore, by calculation, RAID 5 is caused.
  • the performance loss caused by the synchronization effect is within 5% in various environments. If a read/write processing unit cannot perform the next step (such as the next step is an illegal operation), it must wait for another processing unit, and so on, forming a loop, which will form a deadlock. Deadlocks must be strictly avoided. Deadlocks are caused by incorrect instruction execution order, and the order of execution of instructions is different from the order in which instructions are issued. Since out-of-order execution in this scheme exists only between different threads and is executed strictly in the same thread, the software can only avoid deadlocks by simply following the following simple rules:
  • the check code programming instruction must be issued after all data programming instructions in the current RAID data band, before all data programming instructions in the next RAID data band.
  • 4 shows a flash-based storage system constructed using the above method, comprising: a RAID processor and a plurality of flash memories, wherein the RAID processor includes a plurality of read/write processing units, a RAID short message unit, and a data block pointer unit.
  • a block counter, a parity buffer, and a read/write processing unit can control one or more flash units (LUNs).
  • the programming instructions of the check code are submitted to the RAID processor, and the command submission may be initiated by the source to the driver of the host or by firmware.
  • the read/write processing unit executes its corresponding instruction and follows the rules of the RAID controller short message during execution.
  • the read/write processing unit reads the data block in the current data band, and can start reading the data of the next RAID data band only after the check code of the current data band is taken by the processor of the verification device.
  • the data block pointer unit is used to record the input position of the current data block for each flash memory, respectively.
  • the data block counter is used to count the number of data blocks processed in one flash memory.
  • the parity code buffer is used to buffer the parity code.
  • the RAID short message unit is used to broadcast a short message to all read/write processing units to prevent the read/write processing unit from crossing the RAID data band.
  • the short message contains the following information: The data band number currently read by the read/write processing unit allowed by the RAID processor; whether the current check code of the RAID processor can be read.
  • the read/write processing unit reads the corresponding data block, performs an exclusive OR operation on the data in the parity code buffer according to the position of the current data pointer, and writes the data to the parity code buffer. When the exclusive OR operation is completed, the data block pointer unit increases the length value of the input data and moves the corresponding data block pointer.
  • the data block counter is incremented after the data block corresponding to one flash LUN is processed, that is, when the data block pointer wraps around to zero.
  • the data block counter reaches the sum of the data blocks contained in the RAID data band, the data in the parity code memory is written to the corresponding flash memory unit.
  • the RAID processor begins the calculation of the next RAID data strip until the data is processed.
  • this architecture can be extended to multiple RAID processor applications, as shown in Figure 5.
  • the advantages are: Multiple RAID processors operate completely independently; RAID is correctly calculated and written in a write sequence without central control; performance loss caused by RAID is close to zero; RAID width can be flexibly configured.

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Abstract

一种构建有RAID的基于闪存的存储系统，包括：一个或多个RAID处理器和多个闪存，其中，RAID处理器包括多个读写处理单元、数据块指针单元、数据块计数器、奇偶校验码缓存器，一个读写处理单元可以控制一个或多个闪存单元。一种在基于闪存的存储系统中构建RAID的方法，能够在非常小的逻辑面积和近似忽略不计的时间内实现RAID功能，使得如企业级SSD的存储系统的功能和性能实现统一。

Description

在基于闪存的存储系统中构建 RAID的方法及系统
技术领域 本发明涉及一种在基于闪存的存储系统中构建 RAID的方法， 以 及应用该方法的系统。 背景技术 基于闪存 (NAND Flash)的数据存储技术在过去十几年发展迅速， 在很多应用中逐渐取代了传统的磁记录硬盘（hard disk drive, HDD)。 主要原因有： 速度快： 基于闪存的数据存储不象传统 HDD依靠磁头机械寻址， 从而在数据读写速度上有本质性的提高，满足了应用对数据存储吞吐 速度的日趋严格的需求。 价格下降： 随着半导体技术的进步， 闪存的容量也随着摩尔定律 每不到两年增加一倍， 单位容量价格也随着下降。 目前 MLC的闪存 每 GB的价格已从 5年前的 $10USD/GB降至现在的低于 $1USD/GB。 控制器技术进步：闪存需要匹配的控制器 (controller)才能与主 机 (host)通信实现数据存储读写。控制器技术的成熟促进了基于闪存 的固态存储技术在越来越多的领域找到相应的应用，包括在高端的数 据中心及移动智能电话中的应用。 闪存控制器是固态硬盘 （SSD) 系统中最核心的部分， 它的性能 及功能直接决定了该 SSD的性能和功能， 也是消费类 SSD与企业级 SSD最本质的区别。 由于数据保护的要求， 冗余校验码 （RAID) 的计 算和写入是企业级应用所必备的。 由于闪存的价格较高， 镜像等 RAID方法 （即 RAID-1)在通常应 用环境下不可接受。 通常在 SSD中使用的方法是 RAID5, 即 n个数据 块产生 1个校验块 （n>〉2 ) 。 如果数据为 D0， Dl， …， Dn的话， 奇 偶校验码即为 D0， Dl, '". Dn的异或 P=D(TDf . . . ~Dn。 本发明将以 RAID 5的数据结构为例子。 需要指出的是该方法与系统也可以应用 于其它 RAID的结构， 如 RAID 6。 ， 闪存的一大特性是其不可重写性： 保存在闪存中的一页 (page) 数据必需要经过其页面所在的整个块 (block)擦除之后才可以写入新 的数据。这对闪存转换层（FTL)带来了挑战，但对 RAID带来了机遇， RAID的附加写放大不再存在。 在 SSD中实现动态 RAID的方法在中国 专利申请 201210256754. 4 "基于非易失性存储器的动态独立冗余阵 列存储系统及方法" 中有详尽描述。
SSD下的 RAID5数据结构如图 1所示， 数据块 D0， Dl, D2， D3 组 成一个 RAID数据带， DO, Dl, D2, D3异或后产生奇偶校验码 D4。 在 通常情况下， D0， Dl, D2, D3 和 D4分别存储在不同的闪存单元， 既 LUN (logic Unit Number)中， 以确保在任何一个闪存 LUN失效的情 况下数据能通过异或操作进行恢复。 当前， 市场上的 SSD主要分为两种， 一种是通常不带 RAID5功能 的消费类的 SSD; 另一种是包含 RAID5功能的企业级 SSD， 但其在读 写混合下性能不尽如人意。 为了达到高性能，需要使用完全为闪存控制量身定做的大规模并 行多核多线程控制器， 对每一块闪存芯片（LUN)做独立并行操作。
RAID5计算和写入要考虑如下因素： 从主机传来的数据是乱序的， 后 发的指令可能先执行； 从主机传来的数据是交织的， 一个数据块没有 传完， 另一个数据块己开始传送， 并部分先期到达； 奇偶校验码的写 入是异步的： 充任校验设备的闪存需要写入的时候校验码未必准备 好，校验码准备好时控制此闪存的读写处理单元未必准备就绪； 不同 应用下对 RAID5的宽度 （既组成一个 RAID数据带的数据块的数量， 或者闪存 LUN的数量）不同； 一个读写处理单元可能控制多个闪存芯 片， 带来更多死锁的可能， 从而加大了调度的难度。 本发明所要解决的技术问题包括：如何降低 RAID5计算所造成的 性能代价， 以达到如 SSD的存储系统的高性能要求； 如何减少 RAID5 的逻辑面积， 以适应如 SSD的存储系统的控制单元的小型化。 技术方案 本发明提供一种在基于闪存的存储系统中构建 RAID5的方法，能 够在非常小的逻辑面积和近似忽略不计的时间内实现 RAID5功能，使 得如企业级 SSD的存储系统的功能和性能实现统一， 所述方法包括： 将校验码编程指令提交给 RAID处理器，由 RAID处理器的读写处理单 元读取当前数据带中的数据块的部分数据， 设置数据块指针， 分别对 应于每个闪存单元， 记录当前数据块的输入位置， 将读写处理单元读 取的数据块部分根据当前数据块指针的位置计算奇偶校验码，并将结 果写回奇偶校验码缓存器， 数据块指针增加输入部分数据块的长度 值， 在对应于一个闪存单元的所有数据块处理完成之后， 即数据块指 针回绕归零时， 数据块处理完成数量加一， 当所记录的数据块处理完 成数量达到 RAID数据带所包含的数据块数量之和时， 奇偶校验码存 储器内的数据被写入相应的闪存单元， 当所有校验码被取走后，校验 码缓存器清零， 开始下一个 RAID数据带的计算， 直到数据处理完毕。 此外， 校验码的编程指令必须在当前 AID数据带的所有数据编 程指令提交之后， 下一 RAID数据带的数据编程指令之前发出。 进一步， 在每一输入的部分数据块内加入了一个标签， 标明处理 该数据块的读写处理单元、 该数据块所面向的 RAID处理器、 该数据 块所属的 RAID数据带。 还有， RAID处理器向所有的读写处理单元广播一个短消息， 用 来防止读写处理单元跨越 RAID数据带， 短消息包含如下信息： 当前 此 RAID处理器所允许读写处理单元读的数据带号；当前此 RAID处理 器的校验码是否可以被读出。一个读写处理单元可以控制多个闪存单 元， 当读写处理单元发现下一个操作暂时为非法操作时，切换到其他 线程， 对另一闪存单元芯片操作。 本发明还提供一种构建有 RAID5的基于闪存的存储系统， 所述 系统包括： 一个或多个 RAID处理器和多个闪存单元， 其中， RAID处 理器包括多个读写处理单元、 数据块指针单元、 数据块计数器、奇偶 校验码缓存器，一个读写处理单元可以控制一个或多个闪存单元， 将 校验码的编程指令提交给 RAID处理器， 指令提交可以由源至于主机 的驱动发起， 或是由固件发起， 读写处理单元读取当前数据带中的数 据块，数据块指针单元用于分别对每个闪存记录当前数据块的输入位 置， 数据块计数器用于对所处理的数据块数量进行记数， 奇偶校验码 缓存器用于缓存奇偶校验码， 读写处理单元读取相应部分数据块， 根 据当前数据指针的位置与奇偶校验码缓存器内的数据进行奇偶校验 码的计算操作，并将结果写回奇偶校验码缓存器，当计算操作完成后， 数据块指针单元为数据块指针增加输入数据的长度值，移动对应的数 据块指针，数据块计数器在对应于一个闪存单元的数据块处理完成之 后， 即数据块指针回绕归零时， 加一， 当数据块计数器所记录的数据 块数量达到 RAID数据带所包含的数据块数量时， 奇偶校验码存储器 内的数据被写入相应的闪存单元， 当所有校验码被取走后， 缓存器清 零， 幵始下一个 RAID数据带的计算， 直到数据处理完毕。 此外， 所述 RAID处理器还包括 RAID短消息单元， 用于向所有的 读写处理单元广播一个短消息， 用来防止读写处理单元跨越 RAID数 据带。 短消息包含如下信息： 当前此 RAID处理器所允许读写处理单 元读的数据带号； 当前此 RAID处理器的校验码是否可以被读出。 一 个读写处理单元可以控制多个闪存单元，当读写处理单元发现下一个 操作暂时为非法操作时，切换到其他线程，对另一闪存单元芯片操作。 还有，校验码的编程指令必须在当前 RAID数据带的所有数据编 程指令提交之后， 下一 RAID数据带的数据编程指令之前发出。 本发明通过锁和消息传递对线程之间和读写处理单元相互之间 的执行次序进行调度， 使得 RAID5的计算和正确写入成为可能； 并利 用简单规则， 在指令的提交和执行是异步和乱序的情况下， 使得在遵 循这一规则下提交的指令不发生死锁。 本发明实现了动态可配置的 RAID5宽度， 满足应用的需要， 并且 最大程度维持了每一个读写处理单元的独立自主，从而实现了性能的 最大化。 综上所述， 本发明的优点在于： RAID奇偶校验码由多个数据块 异或后产生， 每一数据块存储于独立存储单元； 参与 RAID计算的每 一数据块分至少分为两部分输入 RAID处理器， 而属于不同数据块的 部分数据以时分交织的方式输入 RAID处理器； RAID处理器在属于该 RAID组的所有数据块输入完成后， 将输出奇偶校验码； 数据块部分 输入位置由相应指针记录输入位置， 以容纳在 RAID组内交织、 乱序 和分段部分数据输入； 采用数据块计数器允许可调节的 RAID组内数 据块的数量； RAID处理器采短消息广播方式调度多个闪存读写处理 单元， 防止读写处理单元跨 RAID组的操作； RAID校验码可以在完成 计算的数据段部分输出， 而不需等待整个 AID组的所有数据输入之 后输出。 附图说明 图 1示出了 SSD下的 RAID5的数据结构; 图 2 示出了一种数据块数据乱序和交织输入的示例图； 图 3示出了本发明在 RAID处理器内中记录数据输入位置的指针 位置示意图； 图 4示出了根据本发明应用 RAID5的基于闪存的存储系统的结构 框图； 图 5示出了根据本发明应用多个 RAID处理器的基于闪存的存储 系统的结构框图。 具体实施方式 由于 RAID数据带的多个数据块 D0、 Dl、 D2…各自分别对应于不 同的闪存存储单元 LUN， 各数据块将由相应的读写处理单元处理。 为 实现并行化处理， 最大化系统性能， 在本发明的构建 RAID方法中， 将允许数据块的输入实现交织和乱序输入。 图 2示出了一种数据块数据乱序和交织输入的示例情况。 其中， D0、 D1和 D2分别代表 RAID数据带中的数据块，而 Part0、 Part 1、 Part 2……表数据块中的部分数据， 可能是 64byte、 1Kbyte, 或其 它任意长度的数据 （小于或等于数据块 D的长度） 。 例如， D2 PartO 代表数据块 D2的第一部分数据， 而 Dl Part2代表数据块 D1的第三 部分数据。
RAID5的计算目的是高效地获得 DO, 等数据块的异 或奇偶校验码。 其基于以下事实实现:
• 异或操作存在交换律， 所以次序颠倒的数据块并不影响校验码 的正确性。
• 虽然不同的读写处理单元要写入的数据存在交织， 但同一数据 块内不存在乱序的情况。
• 一个读写处理单元可能控制多个闪存单元， 分别存储不同的数 据块， 但在同一处理器内的数据块之间不存在交织。 从而， 为保证校验码的正确性， 在 RAID5的构建中数据输入需要 满足以下条件：
. 同一 RAID数据带内的数据可以乱序， 但不同 RAID数据带之间 不得乱序；
. 同一 RAID数据带内的数据可以交织， 但不同 RAID数据带之间 不得交织；
. 在当前数据带的校验码被校验设备的处理器取走之后， 才能开 始传送下一 RAID数据带的数据。 在 RAID系统中， 奇偶校验码的计算方法如下： 在每一输入的数据块内加入了一个标签，标明处理该数据块的读 写处理单元、 该数据块所面向的 RAID处理器、 该数据块所属的 RAID 数据带； 在 RAID处理器内， 具有一个校验码缓存 （buffer) ， 并为读写 处理单元设置数据块指针（pointer) , 所述数据块指针用于记录当前 数据块在收到输入数据中的位置， 如图 3 所示。 当收到数据时， 此 数据和对应数据块指针指向的校验码缓存内的数据异或并写回校验 码缓存， 数据块指针根据所输入的数据长度增加指针值。 当数据块指 针值达到数据块长度时回绕归零， 代表完成一个数据块的异或操作， 同时将该处理器所完成处理的数据块加 1。 记录 RAID处理器完成当前数据带中的数据块处理的数量， 根据 所完成数据块处理的数量和各个指针的位置，确定已经计算完毕的部 分数据带的校验码。 只要有部分数据带的校验码计算完毕， 则 RAID 处理器可以通知对应的读写处理单元开始取回校验码写入相应的闪 存单元。 当所有校验码被取走后， 缓存器清零， 重新开始下一个 RAID数 据带的计算， 开始新一轮的循环。 由于每一个 RAID处理器仅需要保留一个完整数据块大小的缓存 (通常为 16KB) ， 完全可以使用片内的 SRAM实现， 从而避免了片外 DRAM的使用， 简化了设计。 在消息总线上 RAID处理器向所有的读写处理单元广播一个短消 息， 用来防止读写处理单元跨越 RAID数据带。短消息包含如下信息： 当前此 RAID处理器所允许读写处理单元读的数据带号； 当前此 RAID 处理器的校验码是否可以被读出。 一个读写处理单元可以控制一个或多个闪存单元 （LUN) ， 当读 写处理单元发现下一个操作暂时为非法操作时 （例如对应于下一个 RAID数据带的数据写入） ， 它就切换到其他线程， 对另一闪存单元 芯片操作。这样写入较快的闪存芯片所在的线程将把资源出让给较慢 的线程， 使得各线程进度大致相当。 本发明方法的目的实现取决于尽量降低非法操作的概率，使得每 一个读写处理单元都能接近满负荷工作，所采取的措施是尽可能提前 校验码开始读出的时间点。由于对应校验设备的读写处理单元通常较 为空闲，因此通常最后一个数据块处理完成后很短的时间内校验码的 读取也完成了， 整个系统可以进行下一个数据带的写入， 从而縮短了 无法传输数据的窗口。 另外， 由于闪存芯片的编程时间是数据传输时间的数倍以上， 且 系统内可以同时操作两个 RAID5写入点， 即使一个暂时被禁用， 另一 个仍可操作， 因此， 通过测算， RAID5引起的同步效应造成的性能损 失在各种环境下都在 5%以内。 如果一个读写处理单元无法进行下一步工作（如下一步为非法操 作） ， 必须等待另一个处理单元， 并依此类推， 形成循环， 就会形成 死锁。死锁是必须严格避免的， 死锁是由不正确的指令执行次序造成 的，而指令的执行次序和指令的发出次序是不同的。 由于在本方案中 乱序执行仅存在于不同线程之间， 同一线程内是严格按序执行的， 软 件发出指令只需遵守以下简单规则， 即可避免死锁：
. 仅对应该 RAID处理器的指令有次序要求，其他指令可以任意发 出。 • 同一 RAID数据带内的数据编程指令之间无次序要求。
• 校验码编程指令必须在当前 RAID数据带内的所有数据编程指 令之后， 下一 RAID数据带内所有数据编程指令之前发出。 图 4示出了一种使用上述方法构建的基于闪存的存储系统， 包 括： RAID处理器和多个闪存， 其中， RAID处理器包括多个读写处理 单元、 RAID短消息单元、 数据块指针单元、 数据块计数器、 奇偶校 验码缓存器，一个读写处理单元可以控制一个或多个闪存单元（LUN)。 将校验码的编程指令提交给 RAID处理器， 指令提交可以由源至 于主机的驱动发起， 或是由固件发起。 为防止死锁， 指令提交必须符 合 RAID处理器所制定的规则， 即校验码的编程指令必须在当前 RAID 数据带的所有数据编程指令提交之后， 下一 RAID数据带的数据编程 指令之前发出。 读写处理单元执行其所对应的指令， 在执行过程中遵循 RAID控 制器短消息的规则。读写处理单元读取当前数据带中的数据块，仅在 当前数据带的校验码被校验设备的处理器取走之后，才能开始读取下 一 RAID数据带的数据。 数据块指针单元用于分别对每个闪存记录当前数据块的输入位 置。 数据块计数器用于对一个闪存中所处理的数据块数量进行记数。 奇偶校验码缓存器用于缓存奇偶校验码。 RAID短消息单元用于向所有的读写处理单元广播一个短消息， 用来防止读写处理单元跨越 RAID数据带。 短消息包含如下信息： 当 前此 RAID处理器所允许读写处理单元读的数据带号；当前此 RAID处 理器的校验码是否可以被读出。 读写处理单元读取相应数据块，根据当前数据指针的位置与奇偶 校验码缓存器内的数据进行异或操作，并将数据写入奇偶校验码缓存 器。 当异或操作完成后， 数据块指针单元增加输入数据的长度值而移 动对应的数据块指针。 数据块计数器在对应于一个闪存 LUN的数据块处理完成之后，即 数据块指针回绕归零时， 加一。 当数据块计数器达到 RAID数据带所包含的数据块之和时， 奇偶 校验码存储器内的数据被写入相应的闪存单元。
RAID处理器开始下一个 RAID数据带的计算操作， 直到处理完该 数据。 如前所描述， 该体系架构可以扩展到多个 RAID处理器的应用， 如图 5所示。 其优点在于： 多个 RAID处理器完全独立操作； 在无中 央控制的写序列下实现 RAID的正确计算和写入； RAID带来的性能损 失接近零； RAID宽度可以灵活配置。
最后应说明的是：以上实施方式仅用以说明本发明的技术方案而 非对其进行限制， 本领域的普通技术人员应当理解： 本发明的核心思 想不仅可以在 SSD上采用， 还可以运用到传统基于硬盘的阵列， 或下 一代存储介质的阵列上， 本发明能够以 FPGA、 可编程逻辑、 ASIC、 或专用芯片实施， RAID写入点个数可以根据需要进一步扩充， 每个 写入点可以进一步采取双处理器配置，进一步消除无法进行数据传输 的时间窗口， RAID的方式可以是 RAID5、RAID6 或者其它 RAID结构。 本领域技术人员可以对本发明迸行修改或者等同替换，而这些修改或 者等同替换亦不能使修改后的技术方案脱离本发明技术方案的精神 和范围。

Claims

权 利 要 求 书
1、 一种在基于闪存的存储系统中构建 RAID的方法， 包括： 将校验码编程指令提交给 RAID处理器， 由 RAID处理器的读写处理单元读取当前数据带中的数据块的部分数据， 设置数据块指针， 分别对应于每个闪存单元， 记录当前数据块的输入位置, 将读写处理单元读取的部分数据块根据当前数据块指针的位置计算奇偶校 验码， 并将结果写回奇偶校验码缓存器相应的位置， 数据块指针增加输入部分数据块的长度值， 在对应于一个闪存单元的所有数据块处理完成之后， 即数据块指针回绕归 零时， 数据块处理完成数量加一， 当所记录的数据块处理完成数量达到 RAID数据带所包含的数据块数量之 和时， 奇偶校验码存储器内的数据被写入相应的闪存单元， 当所有校验码被取走后，校验码缓存器清零， 开始下一个 RAID数据带的计 算， 直到数据处理完毕。
2、 如权利要求 1所述的方法， 其特征在于： 校验码的编程指令必须在当前 RAID数据带的所有数据编程指令提交之后， 下一 RAID数据带的数据编程指令 之前发出。
3、如权利要求 1所述的方法， 其特征在于： 在每一输入的部分数据块内加 入了一个标签， 标明处理该数据块的读写处理单元、 该数据块所面向的 RAID 处理器、 该数据块所属的 RAID数据带。
4、 如权利要求 1所述的方法， 其特征在于： RAID处理器向所有的读写处 理单元广播一个短消息，用来防止读写处理单元跨越 ID数据带， 短消息包含 如下信息：当前此 RAID处理器所允许读写处理单元读的数据带号；当前此 RAID 处理器的校验码是否可以被读出。
5、 如权利要求 4所述的方法， 其特征在于： 一个读写处理单元可以控制多 个闪存单元， 当读写处理单元发现下一个操作暂时为非法操作时， 切换到其他 线程， 对另一闪存单元芯片操作。
6、 一种构建有 ID的基于闪存的存储系统， 所述系统包括： 一个或多 RAID处理器和多个闪存单元， 其中， RAID处理器包括多个读写处理单元、 数据块指针单元、 数据块计 器、 奇偶校验码缓存器， 一个读写处理单元可以控制一个或多个闪存单元， 将校验码的编程指令提交给 RAID处理器，指令提交可以由源至于主机的 动发起， 或是由固件发起， 读写处理单元读取当前数据带中的数据块， 数据块指针单元用于分别对每个闪存记录当前数据块的输入位置， 数据块计数器用于对所处理的数据块数量进行记数， 奇偶校验码缓存器用于缓存奇偶校验码， 读写处理单元读取相应部分数据块， 根据当前数据块指针的位置进行奇偶 校验码的计算操作， 并将结果写回奇偶校验码缓存器相应的位置， 当计算操作完成后，数据块指针单元为数据块指针增加输入数据的长度值， 移动对应的数据块指针， 数据块计数器在对应于一个闪存单元的数据块处理完成之后， 即数据块指 针回绕归零时， 加一， 当数据块计数器所记录的数据块数量达到 RAID数据带所包含的数据块数 量时， 奇偶校验码存储器内的数据被写入相应的闪存单元， 当所有校验码被取走后， 缓存器清零， 开始下一个 RAID数据带的计算， 直 到数据处理完毕。
7、 如权利要求 6所述的基于闪存的存储系统， 其特征在于： 所述 RAID处 理器还包括 RAID短消息单元， 用于向所有的读写处理单元广播一个短消息，用 来防止读写处理单元跨越 RAID数据带。 短消息包含如下信息： 当前此 RAID处 理器所允许读写处理单元读的数据带号；当前此 RAID处理器的校验码是否可以 被读出。
8、 如权利要求 7所述的基于闪存的存储系统， 其特征在于： 一个读写处理 单元可以控制多个闪存单元， 当读写处理单元发现下一个操作暂时为非法操作 时， 切换到其他线程， 对另一闪存单元芯片操作。
9、如权利要求 6所述的基于闪存的存储系统， 其特征在于： 校验码的编程 指令必须在当前 RAID数据带的所有数据编程指令提交之后， 下一 RAID数据 ¾ 的数据编程指令之前发出。
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