WO2015027592A1 - 金卤灯类负载用的时间继电器 - Google Patents

金卤灯类负载用的时间继电器 Download PDF

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Publication number
WO2015027592A1
WO2015027592A1 PCT/CN2013/088129 CN2013088129W WO2015027592A1 WO 2015027592 A1 WO2015027592 A1 WO 2015027592A1 CN 2013088129 W CN2013088129 W CN 2013088129W WO 2015027592 A1 WO2015027592 A1 WO 2015027592A1
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WIPO (PCT)
Prior art keywords
circuit
voltage
output
relay
terminal
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Application number
PCT/CN2013/088129
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English (en)
French (fr)
Inventor
于雪峰
苏敏
郑光枢
Original Assignee
浙江正泰电器股份有限公司
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Application filed by 浙江正泰电器股份有限公司 filed Critical 浙江正泰电器股份有限公司
Priority to ES13892350T priority Critical patent/ES2981711T3/es
Priority to TN2016000071A priority patent/TN2016000071A1/en
Priority to EP13892350.3A priority patent/EP3041019B1/en
Priority to AU2013398767A priority patent/AU2013398767B2/en
Publication of WO2015027592A1 publication Critical patent/WO2015027592A1/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H47/00Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
    • H01H47/02Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for modifying the operation of the relay
    • H01H47/18Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for modifying the operation of the relay for introducing delay in the operation of the relay
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05BELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/02Details
    • H05B41/04Starting switches
    • H05B41/048Starting switches using electromagnetic relays
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05BELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14Circuit arrangements
    • H05B41/26Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc
    • H05B41/28Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters
    • H05B41/295Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices and specially adapted for lamps with preheating electrodes, e.g. for fluorescent lamps
    • H05B41/298Arrangements for protecting lamps or circuits against abnormal operating conditions
    • H05B41/2981Arrangements for protecting lamps or circuits against abnormal operating conditions for protecting the circuit against abnormal operating conditions
    • H05B41/2983Arrangements for protecting lamps or circuits against abnormal operating conditions for protecting the circuit against abnormal operating conditions against abnormal power supply conditions

Definitions

  • the present invention relates to the field of low voltage electrical appliances, and in particular to time relays.
  • metal halide lamps have many advantages as a new type of light source.
  • the secondary power-on must be performed after cooling. Otherwise, the high voltage generated by the trigger is likely to burn out the trigger pole and the main electrode lead of the lamp.
  • the reason is that the gas pressure in the lamp is very high when the metal halide lamp is in the ignition state, and the gas pressure is low in the cooling state.
  • the breakdown voltage of the ignition is related to the gas pressure and the electrode distance. The higher the gas pressure, the higher the starting voltage. The more difficult it is to start, if the power is re-energized without cooling, the trigger will generate a very high voltage to illuminate the light source, which will shorten the life of the light source.
  • the life test cycle is to turn on the lights for 11 hours and turn off the lights for 1 hour.
  • a time relay for the metal halide lamp is needed, which is used to control the on/off of the power supply of the metal halide lamp, and has an automatic delay time and delay after the power is turned off.
  • the function of the relay output circuit can be turned on to realize the control of the secondary power-on start after the time required for the cooling of the metal halide lamp to be extinguished.
  • the time relay for this metal halide lamp is not only used for metal halide lamps, but also for other loads that are the same as the delay control process for gold lamps, which will include such loads as gold 13 ⁇ 4 lamps.
  • the time relay used is called a time relay for a metal halide lamp type load.
  • the time relay for the metal halide lamp load has the following delay control process: When the time relay is connected to the power-off signal synchronized with its output contact, the timing control circuit starts timing and goes through a long delay process. In this delay process, the output contact is always disconnected regardless of whether the power is restored or not. After the delay process ends, the output contact continues to be disconnected if it is still in the power-off state. If the current state is still energized, the output contact is switched. To close.
  • the existing time relay cannot be directly used as a metal halide lamp load because of: logic function
  • the delay requirement of the secondary power-on start of the metal halide lamp load cannot be met.
  • the logic requirement of the metal halide lamp delay control is to start the delay time after the light source is turned off (ie, the output contact of the time relay is disconnected). After the delay is over, the output loop of the relay is allowed to be turned on (that is, the output contact of the time relay is allowed to be closed), and its logic function is as shown in the logic timing diagram of the metal halide lamp type load, and the existing time.
  • the logic function of the relay is usually to start the delay timing after receiving the action signal (the action signal is not necessarily related to the on/off of the output contact of the time relay), and the output circuit of the relay is turned on/off after the delay is over.
  • the state ie, the output contact of the time relay is closed/disconnected
  • produces a jump transition the logic function of which is the logic timing diagram of the existing time-delay time relay shown in Figure 1;
  • the delay time of the existing time relay Short generally only can achieve delay control within 3 minutes, but the cooling time of metal halide lamp takes 20 minutes, too short delay can not meet the cooling requirements of metal halide lamp;
  • the output current of the time relay has a small operating current (generally below 5A), which cannot be used to directly control the high-power metal halide lamp; the existing product has no status indicator during the delay control after power-off, which is inconvenient to use. , not intuitive.
  • An object of the present invention is to overcome the deficiencies of the prior art and to provide a time relay for a metal halide lamp type load.
  • the present invention adopts the following technical solutions.
  • a time relay for a metal halide lamp type load comprising a phase line terminal L on a power supply side, a neutral line terminal N, a live line terminal 4 on a load side, a ground line terminal 3, and a control circuit, the neutral line
  • the terminal N is connected to the ground terminal 3
  • the output contact K1 of the relay is connected in series between the phase line terminal L and the live line terminal 4.
  • the control circuit includes a step-down rectifier voltage regulator circuit A and a power failure detection circuit.
  • the two poles of the AC input terminal of the voltage-stabilizing rectifier circuit A are respectively connected to the phase line terminal L and the neutral line terminal N, and the phase line terminal L
  • the neutral line terminal N is energized or de-energized to control the loading voltage or the unloading voltage of the DC output end of the step-down rectification voltage regulator circuit A
  • the P-competing voltage rectifying and regulating circuit A is connected with the relay output circuit E to provide a power source
  • the detection signal input end of the power failure detecting circuit B is connected to the DC output end of the step-down rectification voltage stabilizing circuit A, and the output end is connected with the processing signal input end of the timing control circuit C to provide power to the timing control circuit C.
  • the DC output end of the circuit A is connected to the power input end of the timing control circuit C, and the energy is stored when the DC output terminal is loaded with voltage, and the timing control circuit C is supplied with the voltage when the voltage is unloaded;
  • the control signal output terminal is connected to the control signal input end of the relay output circuit E.
  • the energy storage circuit D supplies power to the timing control circuit C
  • the power failure detection circuit B supplies the timing control circuit C.
  • the output voltage unloading signal, the timing control circuit C enters the long delay timing process, and the control circuit C controls the output contact K1 of the relay through the relay output circuit E to prohibit the closing until the timing of the timing control circuit C ends.
  • the detection signal output end of the power failure detecting circuit B maintains a high level
  • the control signal output terminal of the timing control circuit C maintains a high level at the high level.
  • the relay output circuit E controls the input circuit of the relay to be turned on, and the output contact K1 of the relay remains closed under the excitation control of the voltage applied to the DC output terminal, and the energy storage circuit D is in the energy storage state;
  • the detection signal output terminal of the power-off detection circuit B is switched to a low level, and under the control of the low level, the timing control circuit C enters the long delay timing process and causes the control signal output terminal to be converted to a low level.
  • the relay output circuit E turns off the input circuit of the relay, and at the same time, the output contact K1 of the relay is switched to be disconnected under the control of the unloading voltage at the DC output end, and the energy storage circuit D is converted into the power supply state.
  • the detection signal output terminal of the power failure detecting circuit B is converted to a high level.
  • the timing control circuit C automatically checks whether the last long delay timing process is over. If the long delay timing process is not completed, the control signal output terminal continues to remain low, if the timing process has ended.
  • the control signal output terminal is switched to a high level, and under the excitation control of the high level and the load voltage, the input loop of the relay is turned on and the output contact K1 of the relay is switched to be closed, and the tank circuit D returns to the energy storage state.
  • the step-down rectifier voltage regulator circuit A includes a step-down resistor R4, a fourth capacitor C4, a rectifier bridge IC3, a Zener diode group (VD1, VD2), a rectifier diode D6, a third Zener diode VD3, and a sixth Capacitor C6 and seventh capacitor C7, P competing resistor R4 is connected in series between the power source side live line terminal L and one pole of the AC input end of the rectifier bridge IC3, and the fourth capacitor C4 is connected in parallel at both ends of the P competing resistor R4.
  • the anode of the DC output terminal of the rectifier bridge IC3 is used as the anode node A1 of the DC output terminal of the step-down rectifier voltage regulator circuit A and is connected to the detection signal input terminal of the power failure detection circuit B, and the voltage regulator diode
  • the anode of the first Zener diode VD1 in the tube group (VD1, VD2), the anode of the sixth capacitor C6 and the anode node A1 are connected in parallel, and the anode of the first Zener diode VD1 is connected to the cathode of the second Zener diode VD2,
  • the anode of the second Zener diode VD2 is used as the voltage regulating node A2 of the DC output terminal of the step-down rectifier voltage regulator circuit A, and is connected to the energy storage anode of the power input end of the energy storage circuit D, and the anode of the rectifier diode D6 is connected to the voltage regulating node A2.
  • the anode of the rectifier diode D6, the cathode of the third Zener diode VD3, and the anode of the seventh capacitor C7 are connected in parallel and used as the voltage regulator node A3 of the DC output terminal of the step-down rectifier voltage regulator circuit A, and the voltage regulator node A3 is connected to the energy storage circuit D.
  • the power input terminal of the power input terminal or the timing control circuit C, the negative pole of the sixth capacitor C6, the cathode of the seventh capacitor C7, and the anode of the third Zener diode VD3 are connected in parallel with the ground of the DC output terminal of the rectifier bridge IC3.
  • the ground of the DC output of the rectifier bridge IC3 is used as the ground of the DC output terminal of the buck rectifier circuit A.
  • the power-off detecting circuit B includes a photocoupler IC1, a first resistor R1, a second resistor R2, a second capacitor C2, and a first LED D1.
  • One end of the first resistor R1 serves as a power-off detecting circuit B.
  • the detection signal input terminal is connected to the original voltage node A1 of the DC output end of the step-down rectifier voltage regulator circuit A, the other end of the first resistor R1 is connected to the anode of the input end of the photocoupler IC1, and the cathode of the input end of the photocoupler IC1 is connected to the first light source.
  • the anode of the diode D1, the anode of the output end of the photocoupler IC1 is connected to the power output terminal of the energy storage circuit D, and the cathode of the output end of the photocoupler IC1 is used as the detection signal output end of the power failure detecting circuit B and with the second resistor R2.
  • One end of the second capacitor C2 is connected in parallel, and the other end of the second resistor R2, the other end of the second capacitor C2, and the cathode of the first LED D1 are connected in parallel with the ground of the DC output terminal of the P voltage rectifier rectifier circuit A. connection.
  • the timing control circuit C includes a delay control chip IC2, a crystal oscillator Y1, a first capacitor C1, a third capacitor C3, a ninth resistor R9, a second LED D2, and a first delay control chip IC2.
  • the pin is used as a power input end of the timing control circuit C and is connected to the power output end of the energy storage circuit D.
  • the second pin of the delay control chip IC2 is connected in parallel with one end of the crystal oscillator Y1 and one end of the first capacitor C1.
  • the third pin of the delay control chip IC2 is connected in parallel with the other end of the crystal oscillator Y1 and one end of the third capacitor C3, and the fifth pin of the delay control chip IC2 is used as the processing signal input terminal of the timing control circuit C and Connected to the detection signal output end of the power failure detecting circuit B, the sixth pin of the delay control chip IC2 is used as the control signal output end of the timing control circuit C and is connected with the control signal input end of the relay output circuit E, and the delay control
  • the ninth pin of the chip IC2 is connected to the ninth resistor R9 One end, the other end of the ninth resistor R9 is connected to the anode of the second LED D2, the other end of the first capacitor C1, the other end of the third capacitor C3, the cathode of the second LED D2, and the tenth of the delay control chip IC2.
  • the four pins are connected in parallel with the ground electrode of the DC output terminal of the P voltage rectifier rectifier circuit A.
  • the energy storage circuit D includes a third resistor R3, a third diode D3, a fourth diode D4, a fifth diode D5, and a super capacitor C5.
  • One end of the third resistor R3 serves as an energy storage device.
  • the energy storage anode of the power input end of the circuit D is connected to the voltage regulating node A2 of the DC output terminal of the step-down rectifier voltage regulator circuit A, and one end of the third resistor R3 is connected to the anode of the fourth diode D4, and the fourth diode D4
  • the negative pole is connected in parallel with the positive pole of the super capacitor C5 and the anode of the fifth diode D5, and the anode of the third diode D3 is used as the positive pole of the power input end of the energy storage circuit D and with the buck rectifier circuit A.
  • the voltage regulating node A3 of the DC output terminal is connected, the negative pole of the super capacitor C5 is connected to the ground terminal of the DC output end of the step-down rectification voltage regulator circuit A, and the cathode of the fifth diode D5 is connected with the cathode of the third diode D3 to form an energy storage.
  • the power output end of the circuit D is connected in parallel with the positive terminal of the output end of the power-off detecting circuit B and the power input terminal of the timing control circuit C.
  • the relay output circuit E includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first transistor Q1, a second transistor Q2, and a seventh diode D7.
  • the emitter of the first transistor Q1 is connected in parallel with one end of the fifth resistor R5 and the anode node A1 of the DC output terminal of the step-down rectifier regulator circuit A, and the other end of the fifth resistor R5 is connected to the first transistor Q1.
  • the base and the sixth resistor R6 are connected in parallel at one end, and the collector of the first transistor Q1 is connected in parallel with the anode of the seventh diode D7 and one end of the relay input circuit, and the other end of the relay input circuit and the seventh diode
  • the anode of D7 is connected in parallel with the voltage stabilizing node A3 of the DC output terminal of the step-down rectifier voltage regulator circuit A
  • the other end of the sixth resistor R6 is connected to the collector of the second transistor Q2
  • the emitter of the second transistor Q2 is
  • One end of the seventh resistor R7 is connected in parallel with the ground of the DC output terminal of the step-down rectification voltage regulator circuit A
  • the other end of the seventh resistor R7 is connected in parallel with the base of the second transistor Q2 and one end of the eighth resistor R8.
  • the eighth resistor R8 The other end is used as a control signal input terminal of the relay output circuit E and is connected to the control signal output terminal of the timing control circuit C.
  • the relay is an electromagnetic relay.
  • the timing control circuit C further includes a time setting circuit, and the time setting circuit includes a tenth resistor R10, a potentiometer Rl l, an eighth diode D8, an eighth capacitor C8, and a tenth resistor.
  • the time setting circuit includes a tenth resistor R10, a potentiometer Rl l, an eighth diode D8, an eighth capacitor C8, and a tenth resistor.
  • One end of the RIO is connected to the tenth pin of the delay control chip IC2
  • the other end of the tenth resistor R10 is connected in parallel with the positive electrode of the eighth diode D8, the sliding end of the potentiometer R11, and the end of the eighth capacitor C8.
  • the negative pole of the diode D8 is connected in parallel with a fixed end of the potentiometer R11 and the first pin of the delay control chip IC2, and one end of the eighth capacitor C8 and the other fixed end of the potentiometer R11 and the buck rectifier circuit
  • the ground terminals of the DC output of A are connected in parallel.
  • the time relay for the metal halide lamp type load of the invention meets the requirements of the delay control process and the delay characteristic of the metal halide lamp type load, can replace the manual duty, and automatically controls the connection of the load power circuit according to the preset delay time. It can effectively protect the metal halide lamp load and extend the service life of the metal halide lamp load. Further, the direct control capability of the output contact in the present invention can meet the high power requirement of the metal halide lamp type load.
  • the status indicator can always work during the delay control after power failure, which is convenient for the user to understand the current running status.
  • Figure 1 is a logic timing diagram of a prior art time-delay time relay.
  • Figure 2 is a logic timing diagram required for a metal halide lamp load.
  • Fig. 3 is a circuit diagram showing an embodiment of a time relay for a metal halide lamp type load according to the present invention.
  • Fig. 4 is an enlarged view of the timing control circuit C of the present invention.
  • the time relay for the metal halide lamp type load of the present invention includes: the phase line terminal on the power supply side! ⁇ , neutral terminal N, live terminal 4 on the load side, ground terminal 3, and control circuit and relay.
  • the phase line terminal L and the neutral line terminal N on the power supply side are used to connect a phase line and a neutral line of the AC power grid.
  • the conventional method is adopted when the phase line terminal L, the neutral line terminal N and the AC power grid phase are used.
  • a switching device (not shown) is provided between the line and the neutral line, and by closing or breaking the switching device, The phase line terminal L and the neutral line terminal N are energized or de-energized.
  • the neutral line terminal N is connected to the ground terminal 3, and the output contact K1 of the relay is connected in series between the phase line terminal L and the live line terminal 4, and the live line terminal 4 and the ground line terminal 3 on the load side. It is used to connect the metal halide lamp type load. Therefore, the energization/de-energization of the live wire terminal 4 and the ground terminal 3 connected to the metal halide lamp type load is controlled by the series connection of the switching device and the output contact K1, and the metal halide The energization of the lamp type load must satisfy the condition that the switching device and the output contact K1 are simultaneously closed, and the disconnection of any one of the switching device and the output contact K1 may cause the metal halide lamp type load to be de-energized.
  • the control circuit includes a buck rectifier voltage regulator circuit A, a power failure detection circuit B, and a timing control circuit. , storage circuit 0, relay output circuit E five sub-circuits.
  • the two poles of the AC input terminal of the P voltage rectifier rectifier circuit A are respectively connected to the phase line terminal L and the neutral line terminal N, and the step line terminal L and the neutral line terminal N are energized or de-energized to control the step-down rectifier voltage regulation.
  • a load voltage or an unloading voltage of the DC output terminal of the circuit A that is, a voltage applied to the DC output terminal of the buck rectifier voltage stabilizing circuit A by the closing operation of the switching device, and the voltage is stepped down by the breaking operation of the switching device
  • the DC output terminal of the rectifier voltage regulator circuit A unloads the voltage.
  • the step-down rectifier voltage regulator circuit A and the relay output circuit E are connected to provide power; the detection signal input terminal of the power-off detection circuit B is connected to the DC output terminal of the step-down rectifier voltage regulator circuit A, and the output terminal and timing control
  • the processing signal input end of the circuit C is connected to the timing control circuit C to provide a detection signal for whether the power supply is normal; the power input end of the energy storage circuit D is connected to the DC output end of the buck rectifier voltage regulator circuit A, and the output terminal is timed.
  • the power input end of the control circuit C stores energy when the DC output terminal is loaded with voltage, and supplies power to the timing control circuit C when the voltage is unloaded; the control signal output terminal of the timing control circuit C is connected to the control of the relay output circuit E At the signal input end, at the moment when the DC output terminal is converted from the load voltage to the unloading voltage, the energy storage circuit D supplies power to the timing control circuit C, and the power failure detection circuit B outputs a voltage unloading signal to the timing control circuit C, and the timing control circuit C enters the long During the delay timing process, the control circuit C controls the output contact K1 of the relay to be closed by the relay output circuit E. Until the timing of the timing control circuit C ends.
  • the energy storage circuit D is separately designed from the buck rectifier voltage regulator circuit A, and the voltage value outputted by the buck rectifier voltage regulator circuit A is not affected during the charging process of the energy storage circuit D, and the energy storage circuit D It can also effectively store energy and increase energy storage, which can meet the power demand of long delay control.
  • the circuit structure, the control method, the control process and the control between the sub-circuits of the control circuit The system relationship is as follows: In the process of loading the voltage at the DC output terminal, the P voltage-stabilizing rectifier circuit A supplies DC power to the power-off detection circuit B, the timing control circuit C, the energy storage circuit D, and the relay output circuit E.
  • the energy storage circuit D stores energy; in the process of unloading the voltage at the DC output terminal, the step-down rectifier voltage stabilizing circuit A stops supplying to the power failure detecting circuit B, the timing control circuit C, the energy storage circuit D and the relay output circuit E.
  • the energy storage circuit D supplies DC power to the timing control circuit C; at the instant when the DC output terminal unloads the voltage, the power failure detection circuit B controls the timing control circuit C to automatically enter the long delay timing process, and the control circuit C passes
  • the output contact K1 of the relay output circuit E control relay is converted into a disconnection, and the voltage unloading at the DC output terminal directly controls the relay output circuit E to cause the output contact K1 to be switched to be disconnected, and the output contact K1 is output during the process of unloading the voltage at the DC output terminal.
  • the timing The circuit C controls the output contact K1 of the relay through the relay output circuit E to continue to be disconnected; if the voltage is applied to the DC output terminal after the long delay timing process of the timing control circuit C ends, the relay output circuit E is in the timing control circuit C. Under the dual control of the loading voltage of the DC output, the output contact K1 of the relay is switched to be closed.
  • the moment of the unloading voltage refers to the moment when the load voltage state is converted to the unloading voltage; the process of unloading the voltage refers to the whole process from the moment of unloading the voltage to the state of maintaining the unloading voltage; the process of loading the voltage It refers to the whole process from the moment of loading the voltage to the state of maintaining the load voltage, and the moment of loading the voltage refers to the moment when the state of the unloading voltage is converted to the state of the applied voltage.
  • the long delay timing process refers to the delay time range that can reach more than 4 minutes.
  • a preferred solution is as follows: in the normal state of loading the DC output terminal, the voltage is broken. The detection signal output end of the electric detection circuit B is kept at a high level, and the control signal output end of the timing control circuit C is kept at a high level, and under the control of the high level, the relay output circuit E turns on the input circuit of the relay, and In the excitation control of the DC output terminal, the output contact K1 of the relay remains closed, and the energy storage circuit D is in the energy storage state; at the instant when the DC output terminal unloads the voltage, the detection signal output end of the power failure detection circuit B Converted to a low level, under the control of the low level, the timing control circuit C enters a long delay timing process and causes the control signal output terminal to be converted to a low level, and the relay output circuit E is made under the control of the low level
  • the input loop of the relay is cut off (non-conducting), and at the
  • the relay output circuit E turns off the input loop of the relay, which makes the output contact K1 of the relay cannot be closed; at the moment when the long delay timing process ends, the timing control circuit C
  • the control signal output terminal is switched to a high level.
  • the relay output circuit E allows the input loop of the relay to be turned on. At this time, if the DC output terminal is loaded with voltage, the excitation control at the voltage is performed. The input loop of the lower relay is turned on and the output contact K1 of the relay is switched to be closed. If the DC output terminal has been unloaded, the relay output circuit E continues to disconnect the output contact K1 of the relay due to no excitation voltage.
  • the power circuit D continues to supply power until the power is exhausted; at the moment when the DC output terminal loads the voltage, the power failure detecting circuit B checks The signal output terminal is switched to a high level. Under the control of the high level, the timing control circuit C automatically checks whether the long delay timing process is finished. If the long delay timing process is not completed, the control signal output terminal remains low. Ping, if the timing process has ended, the control signal output is converted to a high level, and under the excitation control of the high level and the load voltage, the input loop of the relay is turned on and the output contact K1 of the relay is switched to be closed, and the energy storage is performed. Circuit D returns to the energy storage state.
  • the timing control circuit C can automatically check the long delay timing process in a variety of ways, which may result in small differences in the use of the time relay function, these tiny The difference is mainly reflected in the execution of multiple power-on/off operations during the same long-delay timing process.
  • the following example is used to further illustrate this problem.
  • Example 1 the long delay timing process automatically checked by the timing control circuit C is the way of the last power-off long delay timing process, assuming that a delay process is 60 minutes, and a break is made 40 minutes after the start of the process.
  • the output contact K1 of the relay is automatically switched to the closing time at the end of the last power-off long delay timing process, that is, the 60th minute after the start of the last power-off long delay timing process.
  • the long delay timing process automatically checked by the timing control circuit C is the mode of the long delay timing process. It is also assumed that a delay process is 60 minutes, and after a power failure of 40 minutes after the start of the process
  • the output contact K1 of the relay is automatically converted to the closing time, which is the time when the power-off long delay timing process ends, that is, the 100th minute after the start of the last power-off long delay timing process.
  • a preferred mode of the present invention is the mode of Example 1, that is, when the voltage is applied to the DC output terminal, the long delay timing process automatically checked by the timing control circuit C is the last power-off long delay timing process.
  • the specific circuit structure of each sub-circuit can have various schemes. The following is a preferred scheme of five sub-circuits.
  • the P voltage-stabilizing rectifier circuit A includes a step-down resistor R4, a capacitor C4, a rectifier bridge IC3, a Zener diode group (VD1, VD2), a rectifier diode D6, a Zener diode VD3, a capacitor C6, and a capacitor C7.
  • the P-compression resistor R4 is connected in series between the power-side live line terminal L and one pole of the AC input terminal of the rectifier bridge IC3, the capacitor C4 is connected in parallel across the resistor R4, and the anode of the DC output of the rectifier bridge IC3 is used as a step-down rectifier.
  • the positive node A1 of the DC output terminal of the voltage stabilizing circuit A is connected to the detection signal input end of the power-off detecting circuit B, and the negative electrode of the Zener diode VD1 and the positive electrode and the positive node of the capacitor C6 in the Zener diode group (VD1, VD2) A1 is connected in parallel, the anode of the Zener diode VD1 is connected to the cathode of the Zener diode VD2, and the anode of the Zener diode VD2 is used as the voltage regulating node A2 of the DC output terminal of the step-down rectifier voltage regulator circuit A and the power input of the energy storage circuit D
  • the anode of the storage energy is connected, the anode of the rectifier diode D6 is connected to the voltage regulation node A2, the cathode of the rectifier diode D6, the cathode of the Zener diode VD3, and the anode of the capacitor C7 are connected in parallel and used as the DC
  • voltage regulator node A3 is connected to the power input terminal of the energy input terminal of the energy storage circuit D or the power input terminal of the timing control circuit C, the negative pole of the capacitor C6, and the negative of the capacitor C7.
  • the positive electrode of the DC output of the bridge rectifier diode VD3 regulator IC3 is connected to pole parallel to the DC output ends of the rectifier bridge as the source IC3 buck regulator circuit A rectifier DC output ends of the earth.
  • the DC output terminal of the rectifier bridge IC3 includes a positive pole and a ground pole, and a voltage divider of the Zener diode VD1, the Zener diode VD2, and the Zener diode VD3 on the anode.
  • Forming three nodes of the anode of the positive electrode node A1, the voltage regulating node A2, and the voltage regulating node A3, and the voltage of the three nodes can be adapted according to the requirements of each sub-circuit, wherein the voltage regulating node A2 and the voltage regulating node A3 are The ground voltage is less than the positive node A1.
  • the positive node A1 is not only used as a power take-off node of the relay output circuit E, but also used as a signal acquisition node of the detection signal input end of the power-off detection circuit B, and the DC output terminal of the step-down rectifier voltage regulator circuit A is loaded with a voltage, That is, the positive node A1 has an operating voltage to the ground, and the DC output terminal unloading voltage of the step-down rectifying and regulating circuit A means that the voltage of the positive node A1 to ground is zero.
  • the voltage regulating node A2 is used as a power take-off node of the energy storage circuit of the energy storage circuit D
  • the voltage stabilizing node A3 is used as a power take-off node of the power transfer circuit of the energy storage circuit D.
  • the voltage node A3 is directly used as the power take-off node of the timing control circuit C. It can be seen that the process of loading the voltage at the DC output terminal through the positive node A1, the voltage regulating node A2 and the voltage stabilizing node A3 In the P voltage-stabilizing rectifier circuit A, the timing control circuit C, the energy storage circuit D and the relay output circuit E are supplied with DC power, and the energy storage circuit D stores energy; of course, at the DC output terminal During the unloading of the voltage, the step-down rectification regulator circuit A stops supplying power to the de-energization detection circuit B, the timing control circuit C, the storage circuit D, and the relay output circuit E.
  • the Zener diode group adopts a structure in which a Zener diode VD1 and a Zener diode VD2 are connected in series.
  • the purpose of using two Zener diodes is to reduce the voltage across each Zener diode. Therefore, the equivalent scheme can be one or More than two Zener diodes.
  • a voltage dividing circuit composed of a Zener diode VD1 and a Zener diode VD2 voltage stabilizing diode VD3 has an ideal voltage stabilizing effect.
  • a disadvantageous solution is to replace the Zener diode with a resistor. Obviously, this inferior solution does not have Voltage regulation function.
  • Another disadvantage is that the rectifier diode D6 and/or the capacitor C7 are omitted. The elimination of the rectifier diode D6 and/or the capacitor C7 does not affect the operation of the circuit, but affects the performance of the circuit, such as the inrush voltage of the input circuit of the relay. Damage to the circuit.
  • the power-off detecting circuit B includes a photocoupler IC1, a resistor R1, a resistor R2, a capacitor C2, and a light-emitting diode D1.
  • One end of the resistor R1 is used as a detection signal input terminal of the power-off detecting circuit B, and the step-down rectifier voltage-stabilizing circuit is connected.
  • the positive terminal of the DC output terminal of A, the other end of the resistor R1 is connected to the positive terminal of the input end of the photocoupler IC1
  • the negative terminal of the input end of the photocoupler IC1 is connected to the anode of the light-emitting diode D1
  • the positive electrode of the output end of the photocoupler IC1 and the storage circuit D power output terminal is connected
  • the negative terminal of the output end of the photocoupler IC1 is used as the detection signal output end of the power failure detecting circuit B and is connected in parallel with one end of the resistor R2 and one end of the capacitor C2, the other end of the resistor R2, and the capacitor C2
  • One end and the cathode of the light-emitting diode D1 are connected in parallel with the ground of the DC output terminal of the step-down rectifier voltage regulator circuit A.
  • the current flows from the positive node A1 of the DC output terminal of the step-down rectifier voltage regulator circuit A, and passes through the resistor R1, the input loop of the photocoupler IC1, and the LED D1 to the ground level.
  • the voltage at the power output of the storage circuit D is loaded to the end of the resistor R1 through the output loop of the photocoupler IC1.
  • One end of the resistor R1 of the detection signal output terminal of the power-off detecting circuit B is maintained at a high level.
  • the timing control circuit C includes a delay control chip IC2, a crystal oscillator Y1, a capacitor C1, a capacitor C3, a resistor R9, and a light-emitting diode D2.
  • the 1 leg of the delay control chip IC2 is used as a power input terminal of the timing control circuit C. And connected to the energy output end of the energy storage circuit D, the 2 pin of the delay control chip IC2 is connected in parallel with one end of the crystal oscillator Y1 and one end of the capacitor C1, and the 3rd pin of the delay control chip IC2 and the other end of the crystal oscillator Y1 And one end of the capacitor C3 is connected in parallel, the 5th pin of the delay control chip IC2 is used as the processing signal input end of the timing control circuit C and is connected with the detection signal output end of the power failure detecting circuit B, and the 6-pin of the delay control chip IC2 is used.
  • the control signal output end of the timing control circuit C is connected to the control signal input end of the relay output circuit E, the 9-pin of the delay control chip IC2 is connected to one end of the resistor R9, and the other end of the resistor R9 is connected to the positive pole of the LED D2, the capacitor The other end of C1, the other end of the capacitor C3, the cathode of the photodiode D2, and the 14-pin of the delay control chip IC2 are connected in parallel with the ground of the DC output terminal of the P-competing rectifier voltage regulator circuit A.
  • the delay control chip IC2 is a single chip microcomputer.
  • the PIC microcontroller with the model number PIC16F684 is selected, and the 1 pin and the 14 pin are respectively the positive pole and the ground pole of the power input end of the delay control chip IC2, and also the power input of the timing control circuit C.
  • the present invention also employs the following characteristics of the delay control chip IC2 to constitute a circuit configuration that satisfies the control requirements of the time relay of the present invention. Applying the delay control characteristic and structure of the delay control chip IC2, the clock source circuit composed of the crystal oscillator Y1, the capacitor C1, and the capacitor C3 connected between the 2 pin and the 3 pin of the delay control chip IC2 is delayed.
  • the control chip IC2 provides a clock for running the program, and its clock precision is high and the stability is good.
  • the delay control chip IC2 can also use the commonly used RC clock circuit to provide clock for program operation, or select the single chip with internal clock.
  • the delay control chip IC2 can be 2 feet and 3 feet. Hanging.
  • the RC clock circuit has a large frequency error, and the internal clock precision is low, which is greatly affected by temperature. Therefore, the clock source circuit of this embodiment is preferable.
  • the clock source is provided for the delay timing of the delay control chip IC2. Since the crystal oscillator Y1 has a large duration, a long delay can be realized.
  • the 5-pin of the delay control chip IC2 is also used as the processing signal input terminal of the timing control circuit C (also the detection signal output terminal of the power-off detection circuit B), and the 6-pin of the delay control chip IC2 is used as the control of the timing control circuit C.
  • the signal output end (also the control signal input end of the relay output circuit E) uses the 9-pin of the delay control chip IC2 as the light-emitting diode D2, that is, the power supply of the delay indicator light, to form the following control relationship for realizing the control requirements of the present invention: Under the control of 5-pin input high level, the output of 6-pin is high; when the 5-pin is converted from high level to low level, the delay control chip IC2 enters the long delay timing process, and 6 feet at the same time.
  • the output pulse voltage causes the LED D2 to flash; at the end of the long delay timing process, the 6-pin is converted to a high level and output to the control relay output circuit E, and the output voltage of the 9-pin is converted to a DC voltage so that the LED D2 is often bright.
  • An alternative preferred solution is to apply the reference voltage of the 10-pin of the delay control chip IC2 to control the delay time of the delay control chip IC2.
  • the timing control circuit C further includes The time setting circuit, the time setting circuit comprises a resistor R10, a potentiometer Rl l, a diode D8, a capacitor C8, one end of the resistor R10 is connected to the 10th pin of the delay control chip IC2, the other end of the resistor R10 is opposite to the anode of the diode D8, The sliding end of the potentiometer R11 is connected in parallel with the end of the capacitor C8.
  • the negative pole of the diode D8 is connected in parallel with a fixed end of the potentiometer R11 and the 1 leg of the delay control chip IC2, and one end of the capacitor C8 is fixed to the other end of the potentiometer R11.
  • the terminal is connected in parallel with the ground terminal of the DC output terminal of the buck rectifier circuit.
  • the energy storage circuit D includes a resistor R3, a diode D3, a diode D4, a diode D5, and a super capacitor C5.
  • One end of the resistor R3 serves as an energy storage anode of the energy input end of the energy storage circuit D and is connected with the step-down rectifier voltage regulator circuit A.
  • the voltage regulating node A2 of the DC output terminal is connected, one end of the resistor R3 is connected to the anode of the diode D4, the cathode of the diode D4 is connected in parallel with the anode of the super capacitor C5 and the anode of the diode D5, and the anode of the diode D3 is used as the electric energy of the tank circuit D.
  • the positive pole of the input terminal is connected to the voltage stabilizing node A3 of the DC output terminal of the step-down rectification voltage regulator circuit A.
  • the cathode of the super capacitor C5 is connected to the ground terminal of the DC output terminal of the step-down rectification voltage regulator circuit A, the cathode of the diode D5 and the diode D3.
  • the negative electrode is connected to form a power output terminal of the energy storage circuit D, and the power output terminal is connected in parallel with the positive terminal of the output terminal of the photocoupler IC1 of the power-off detecting circuit B and the power input terminal of the timing control circuit C.
  • the current flows from the voltage regulating node A2 of the DC output terminal, passes through the resistor R3 and the diode D4, reaches the super capacitor C5, and charges the super capacitor C5, that is, the step-down rectification
  • the voltage stabilizing circuit A supplies DC power to the energy storage circuit D, and the energy storage circuit D is in the energy storage state.
  • the resistor R3 acts as a current limiting voltage divider, ensuring that the voltage of the voltage regulating node A2 and the voltage regulator node A3 is not super Capacitor C5 is pulled low to ensure that the voltage supplied to IC2 in circuit C is normal at the moment of power-on; the current of regulator node A3 flows through diode D3 and flows into the positive terminal of the output of photocoupler IC1 of power-off detection circuit B.
  • the power supply input terminal (1 pin) of the timing control circuit C that is, the buck rectifier voltage regulator circuit A supplies the DC power to the power-off detection circuit ⁇ timing control circuit C; due to the reverse cut-off characteristic of the diode D5, from the voltage regulator node A3 The current flowing out does not flow into the super capacitor C5.
  • the voltage regulation node A2 the voltage regulator node A3 is low, and the super capacitor C5 anode is high, so the super capacitor C5 is discharged, from the positive pole of the super capacitor C5.
  • the current flowing out through the diode D5 flows into the power input terminal (1 pin) of the timing control circuit C, that is, the energy storage circuit D serves as the power source to continue to supply power to the timing control circuit C; due to the control of the unloading voltage of the DC output terminal, the power is turned off.
  • the output loop of the photocoupler IC1 of the detection circuit B is turned off (non-conducting), so the current flowing from the anode of the super capacitor C5 does not flow into the output loop of the photocoupler IC1; due to the reverse cutoff characteristic of the diode D4 and the diode D3 Therefore, the current flowing from the positive pole of the super capacitor C5 does not flow back to the voltage regulating node A2 and the voltage stabilizing node A3. Due to the large capacity of the super capacitor C5, it is equivalent to a battery, which can meet the power supply requirements of the long delay operation of the timing control circuit C.
  • the relay output circuit E includes a resistor R5, a resistor R6, a resistor R7, a resistor R8, a transistor Q1, a transistor Q2, a diode D7 and a relay, an emitter of the transistor Q1 and one end of the resistor R5 and a step-down rectifier circuit A.
  • the positive terminal A1 of the DC output terminal is connected in parallel, and the other end of the resistor R5 is connected in parallel with the base of the transistor Q1 and one end of the resistor R6.
  • the collector of the transistor Q1 is connected in parallel with the anode of the diode D7 and one end of the relay input circuit, and the relay input circuit is connected.
  • the other end is connected in parallel with the positive terminal of the diode D7 and the voltage stabilizing node A3 of the DC output terminal of the step-down rectifier voltage regulator circuit A.
  • the other end of the resistor R6 is connected to the collector of the transistor Q2, the emitter of the transistor Q2 and one end of the resistor R7.
  • the ground terminal of the DC output terminal of the step-down rectifier voltage regulator circuit A is connected in parallel, and the other end of the resistor R7 is connected in parallel with the base of the transistor Q2 and one end of the resistor R8, and the other end of the resistor R8 is used as a control signal of the relay output circuit E.
  • the input terminal is connected to the control signal output terminal of the timing control circuit C.
  • the control signal output terminal of the timing control circuit C When the control signal output terminal of the timing control circuit C outputs a high level (that is, the base of the transistor Q2 is extremely high): If the DC output terminal has been loaded with voltage, the transistor Q1 is controlled under the high level. Turn on, make the ground voltage of the positive node A1 of the DC output (ie load The voltage is applied to both ends of the relay input circuit, causing the relay to sink and the output contact K1 to be closed; if the DC output has been unloaded, the high level cannot control the conduction of the transistor Q1, and no voltage can excite the relay to pull in. , so the output contact K1 of the relay is broken.
  • the relay is preferably a general-purpose electromagnetic relay, and has the advantages that the output contact K1 has a large operating current, a strong breaking capability, and a good price performance ratio. It should be understood that since the present invention adopts the above control circuit, it is possible to select a general-purpose electromagnetic relay, or to use a conventional magnetic holding relay, thereby obtaining the effect of a large operating current of the output contact, which can be directly controlled. Many high-power metal halide lamps.
  • the time relay for the metal halide lamp load of the present invention can well meet the special use requirements of the metal halide lamp type load.
  • These special use requirements are as follows: Only the DC output terminal load voltage and the long delay time are satisfied at the same time. At the end of the process, the control circuit will close the output contact K1 of the relay, that is, the metal halide lamp type load can be energized; if the DC output load voltage and the long delay timing process are not satisfied, or If one of the conditions is not satisfied, the output contact K1 of the relay cannot be closed, that is, the metal halide lamp type load cannot be energized; the moment of the unloading voltage of the DC output terminal of the step-down rectifier voltage regulator circuit A is used as the long delay.
  • the starting point of the timekeeping ensures the reliability and accuracy of the time interval between the two starts; the moment when the end of the long delay timing process is used as the control condition allowing the relay input circuit to be turned on, the time relay product can be twice Start with delay control start and manual operation start two ways; time setting circuit, make time relay Large range and adjustable delay timing accurate and reliable, versatile to meet their requirements.
  • the so-called delay control start means that the switch device is first powered off and then energized before the end of the delay. At the end of the delay, the control circuit automatically energizes the load.
  • the power-on operation of the product in the operation of the artificial operation means that the switching device is first powered off and then energized after the delay is over, and the operation at this moment causes the load to be powered immediately.

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Abstract

金卤灯类负载用的时间继电器,包括控制电路,控制电路包括降压整流稳压电路 A、断电检测电路 B、计时控制电路 C、储能电路 D、继电器输出电路 E;降压整流稳压电路 A与继电器输出电路 E连接,断电检测电路 B接降压整流稳压电路 A;储能电路 D接降压整流稳压电路 A,在整流稳压电路 A的直流输出端加载电压时储能;计时控制电路 C接继电器输出电路 E,在直流输出端转变为卸载电压的瞬间,储能电路 D为计时控制电路 C供电,断电检测电路 B 给计时控制电路 C输出电压卸载信号,计时控制电路 C进入长延时计时过程,通过继电器输出电路 E控制继电器的输出触点 K1禁止闭合直到计时过程结束。符合金卤灯类负载的延时要求,可以有效保护金卤灯类负载。

Description

金卤灯类负载用的时间继电器
技术领域 本发明涉及低压电器领域, 具体涉及时间继电器。
背景技术
众所周知, 金卤灯作为新型光源, 有诸多优点, 但要延长使用寿命, 二次 通电启动必需在冷却后才能进行, 否则触发器产生的高压很可能会将灯的触发 极和主电极引线烧坏, 其原因在于, 金卤灯在燃点状态时灯内的气压非常高, 冷却状态下气压很低, 其点燃的击穿电压是和气压和电极距离是乘积关系, 气 压越高, 启动电压越高, 启动越困难, 如果在没有得到冷却的情况下重新送电, 则需触发器产生很高的电压才能点亮光源, 由此频繁启动会缩短光源的寿命。 按照 IEC标准规定, 寿命试验循环是点灯 11小时, 关灯 1小时。 为了延长金 卤灯的使用寿命, 需要一种金卤灯用的时间继电器, 用它控制金卤灯的电源的 通 /断,并具有在断电后能自动进入长时间延时计时和延时结束后才能接通继电 器输出回路的功能, 以实现在金卤灯熄灭后的一段冷却所需的时间后才能二次 通电启动的控制。 当然, 这种金卤灯用的时间继电器并不仅用于金卤灯, 而且 还可用于与金 1¾灯的延时控制过程相同的其它负载, 在此将包括金 1¾灯在内的 这类负载使用的时间继电器称之为金卤灯类负载用的时间继电器。 显然, 金卤 灯类负载用的时间继电器具有以下延时控制过程: 当时间继电器接到与其输出 触点分断同步的断电信号时, 计时控制电路开始计时, 并经过一段较长的延时 过程, 在此延时过程不管是否恢复通电, 输出触点始终保持分断, 延时过程结 束后, 如果当前仍处于断电状态则输出触点继续保持分断, 如果当前仍处于通 电状态则输出触点转换为闭合。
但现有的时间继电器不能直接用作金卤灯类负载, 其原因在于: 逻辑功能 不能满足金卤灯类负载的二次通电启动的延时要求, 金卤灯的延时控制的逻辑 要求是在灯源熄灭(即时间继电器的输出触点断开)后开始延时计时, 在延时 结束后才允许继电器的输出回路接通(即允许时间继电器的输出触点闭合) , 其逻辑功能如图 2所示的金卤灯类负载所需的逻辑时序图, 而现有的时间继电 器的逻辑功能通常为在接到动作信号(该动作信号不一定与时间继电器的输出 触点的通 /断相关) 开后开始延时计时, 在延时结束后继电器的输出回路的通 / 断状态(即时间继电器的输出触点闭合 /分断状态)产生跳跃式转换, 其逻辑功 能如图 1所示的现有的延时型时间继电器的逻辑时序图; 现有的时间继电器的 延时时间短, 一般只能够实现 3分钟以内的延时控制, 但金卤灯的冷却时间需 要 20分钟, 过短的延时不能满足金卤灯的冷却要求; 现有的时间继电器的输 出触点的工作电流小 (一般在 5A以下) , 不能用于直接控制大功率金卤灯; 现有产品在断电后延时控制的过程中无状态指示灯, 使用不方便, 不直观。
发明内容
本发明的目的在于克服现有技术的缺陷, 提供一种金卤灯类负载用的时间 继电器。
为实现上述目的, 本发明采用了如下技术方案。
一种金卤灯类负载用的时间继电器, 它包括电源侧的相线端子 L、 中性线 端子 N, 负载侧的火线端子 4、 地线端子 3, 以及控制电路, 所述的中性线端 子 N与地线端子 3连接, 所述的继电器的输出触点 K1 串联连接在相线端子 L 与火线端子 4之间, 所述的控制电路包括降压整流稳压电路 A、 断电检测电路 B、 计时控制电路 C、 储能电路0、 继电器输出电路 E, P争压整流稳压电路 A 的交流输入端的两个极分别接相线端子 L、 中性线端子 N, 由相线端子 L、 中 性线端子 N的通电或断电控制降压整流稳压电路 A的直流输出端的加载电压 或卸载电压; 所述的 P争压整流稳压电路 A与继电器输出电路 E连接提供电源; 所述的断电检测电路 B的检测信号输入端接降压整流稳压电路 A的直流输出 端,输出端与计时控制电路 C的处理信号输入端连接为计时控制电路 C提供电 源是否供电正常的检测信号;所述的储能电路 D的电能输入端接降压整流稳压 电路 A的直流输出端,输出端接计时控制电路 C的电源输入端,在所述的直流 输出端加载电压时储能, 卸载电压时为计时控制电路 C供电; 所述的计时控制 电路 C的控制信号输出端接继电器输出电路 E的控制信号输入端,在直流输出 端由加载电压转变为卸载电压的瞬间,储能电路 D为计时控制电路 C供电, 断 电检测电路 B给计时控制电路 C输出电压卸载信号, 计时控制电路 C进入长 延时计时过程, 控制电路 C通过继电器输出电路 E控制继电器的输出触点 K1 禁止闭合直到计时控制电路 C的计时过程结束。
进一步, 在所述的直流输出端加载电压的常态下, 断电检测电路 B的检测 信号输出端保持高电平, 接计时控制电路 C的控制信号输出端保持高电平, 在 该高电平的控制下继电器输出电路 E使继电器的输入回路导通, 并在直流输出 端加载电压的激励控制下继电器的输出触点 K1保持闭合, 储能电路 D处于储 能状态; 在所述的直流输出端卸载电压的瞬间, 断电检测电路 B的检测信号 输出端转换为低电平,在该低电平的控制下接计时控制电路 C进入长延时计时 过程并使控制信号输出端转换为低电平, 在该低电平的控制下继电器输出电路 E使继电器的输入回路截止, 同时在直流输出端卸载电压的控制下继电器的输 出触点 K1转换为分断, 储能电路 D转换为供电状态; 在所述的直流输出端加 载电压的瞬间, 断电检测电路 B的检测信号输出端转换为高电平, 在该高电平 的控制下计时控制电路 C自动检查上一个长延时计时过程是否结束,若长延时 计时过程未结束则使控制信号输出端继续保持低电平, 若计时过程已结束则使 控制信号输出端转换为高电平, 并在该高电平和加载电压的激励控制下继电器 的输入回路导通并继电器的输出触点 K1转换为闭合, 储能电路 D回到储能状 态。
进一步, 所述的降压整流稳压电路 A包括降压电阻 R4、 第四电容 C4、 整 流桥 IC3、 稳压二极管组(VD1、 VD2 ) 、 整流二极管 D6、 第三稳压二极管 VD3、第六电容 C6和第七电容 C7, P争压电阻 R4串联连接在电源侧火线端子 L 与整流桥 IC3的交流输入端的一个极之间, 第四电容 C4并联连接在 P争压电阻 R4的两端, 整流桥 IC3的直流输出端的正极用作降压整流稳压电路 A的直流 输出端的正极节点 A1并与断电检测电路 B的检测信号输入端连接, 稳压二极 管组(VD1、 VD2 ) 中的第一稳压二极管 VD1的负极、 第六电容 C6的正极与 正极节点 A1 并联连接, 第一稳压二极管 VD1 的正极接第二稳压二极管 VD2 的负极, 第二稳压二极管 VD2的正极用作降压整流稳压电路 A的直流输出端 的调压节点 A2并与储能电路 D的电能输入端的储能正极连接,整流二极管 D6 的正极接调压节点 A2, 整流二极管 D6的负极、 第三稳压二极管 VD3的负极、 第七电容 C7的正极并联连接并用作降压整流稳压电路 A的直流输出端的稳压 节点 A3,稳压节点 A3接储能电路 D的电能输入端电源正极或计时控制电路 C 的电源输入端, 第六电容 C6的负极、 第七电容 C7的负极和第三稳压二极管 VD3的正极与整流桥 IC3的直流输出端的地极并联连接,整流桥 IC3的直流输 出端的地极用作降压整流稳压电路 A的直流输出端的地极。
进一步, 所述的断电检测电路 B包括光电耦合器 IC1、 第一电阻 Rl、 第二 电阻 R2、 第二电容 C2、 第一发光二极管 Dl, 第一电阻 R1的一端用作断电检 测电路 B的检测信号输入端接降压整流稳压电路 A的直流输出端的原压节点 A1 , 第一电阻 R1另一端接光电耦合器 IC1的输入端的正极, 光电耦合器 IC1 的输入端的负极接第一发光二极管 D1的正极, 光电耦合器 IC1的输出端的正 极与储能电路 D电能输出端连接,光电耦合器 IC1的输出端的负极用作断电检 测电路 B的检测信号输出端并与第二电阻 R2的一端、 第二电容 C2的一端并 联连接, 第二电阻 R2的另一端、 第二电容 C2的另一端和第一发光二极管 D1 的负极与 P争压整流稳压电路 A的直流输出端的地极并联连接。
进一步, 所述的计时控制电路 C包括延时控制芯片 IC2、 晶体振荡器 Yl、 第一电容 Cl、 第三电容 C3、 第九电阻 R9、 第二发光二极管 D2, 延时控制芯 片 IC2的第一管脚用作计时控制电路 C的电源输入端并与储能电路 D电能输出 端连接,延时控制芯片 IC2的第二管脚与晶体振荡器 Y1的一端和第一电容 C1 的一端并联连接, 延时控制芯片 IC2的第三管脚与晶体振荡器 Y1的另一端和 第三电容 C3的一端并联连接, 延时控制芯片 IC2的第五管脚用作计时控制电 路 C的处理信号输入端并与断电检测电路 B的检测信号输出端连接,延时控制 芯片 IC2的第六管脚用作计时控制电路 C的控制信号输出端并与继电器输出电 路 E的控制信号输入端连接, 延时控制芯片 IC2的第九管脚接第九电阻 R9的 一端, 第九电阻 R9的另一端接第二发光二极管 D2的正极, 第一电容 C1的另 一端、 第三电容 C3的另一端、 第二发光二极管 D2的负极和延时控制芯片 IC2 的第十四管脚与 P争压整流稳压电路 A的直流输出端的地极并联连接。
进一步, 所述的储能电路 D包括第三电阻 R3、 第三二极管 D3、 第四二极 管 D4、 第五二极管 D5、 超级电容 C5, 第三电阻 R3的一端用作储能电路 D的 电能输入端的储能正极并与降压整流稳压电路 A的直流输出端的调压节点 A2 连接, 第三电阻 R3的一端接第四二极管 D4的正极, 第四二极管 D4的负极与 超级电容 C5的正极和第五二极管 D5的正极并联连接, 第三二极管 D3的正极 用作储能电路 D的电能输入端的电源正极并与降压整流稳压电路 A的直流输 出端的稳压节点 A3连接, 超级电容 C5的负极接降压整流稳压电路 A的直流 输出端的地极, 第五二极管 D5的负极与第三二极管 D3的负极连接形成储能 电路 D的电能输出端,该电能输出端与断电检测电路 B的输出端的正极和计时 控制电路 C的电源输入端并联连接。
进一步, 所述的继电器输出电路 E包括第五电阻 R5、 第六电阻 R6、 第七 电阻 R7、 第八电阻 R8、 第一三极管 Ql、 第二三极管 Q2、 第七二极管 D7, 第 一三极管 Q1的发射极与第五电阻 R5的一端和降压整流稳压电路 A的直流输 出端的正极节点 A1并联连接, 第五电阻 R5的另一端与第一三极管 Q1的基极 和第六电阻 R6的一端并联连接, 第一三极管 Q1的集电极与第七二极管 D7负 极和继电器输入回路的一端并联连接, 继电器输入回路的另一端与第七二极管 D7的正极和降压整流稳压电路 A的直流输出端的稳压节点 A3并联连接,第六 电阻 R6的另一端接第二三极管 Q2的集电极, 第二三极管 Q2的发射极与第七 电阻 R7的一端和降压整流稳压电路 A的直流输出端的地极并联连接, 第七电 阻 R7的另一端与第二三极管 Q2的基极和第八电阻 R8的一端并联连接, 第八 电阻 R8的另一端用作继电器输出电路 E的控制信号输入端并与计时控制电路 C的控制信号输出端连接。
进一步, 所述的继电器为电磁继电器。
进一步, 所述的计时控制电路 C还包括时间整定电路, 所述的时间整定电 路包括第十电阻 R10、 电位器 Rl l、 第八二极管 D8、 第八电容 C8, 第十电阻 RIO的一端接延时控制芯片 IC2的第十管脚, 第十电阻 R10的另一端与第八二 极管 D8的正极、 电位器 R11的滑动端和第八电容 C8的一端并联连接, 第八 二极管 D8的负极与电位器 R11的一个固定端和延时控制芯片 IC2的第一管脚 并联连接, 第八电容 C8的一端与电位器 R11的另一个固定端和降压整流稳压 电路 A的直流输出端的地极并联连接。
本发明的金卤灯类负载用的时间继电器符合金卤灯类负载的延时控制过 程和延时特性的要求, 能代替人工值守, 按照预置的延时时间自动控制负载电 源电路的接通, 可以有效保护金卤灯类负载, 延长金卤灯类负载的使用寿命。 进一步本发明中输出触点的直接控制能力能满足金卤灯类负载的大功率要求。 断电后的延时控制过程中状态指示灯能始终保持工作, 方便用户了解当前运行 状态。
附图说明
图 1是现有的延时型时间继电器的逻辑时序图。
图 2是金卤灯类负载所需的逻辑时序图。
图 3是本发明的金卤灯类负载用的时间继电器的实施例的电路示意图。 图 4是本发明计时控制电路 C的放大图。
具体实施方式 以下结合附图 3给出的实施例, 进一步说明本发明的金卤灯类负载用的时 间继电器的具体实施方式。 本发明的金卤灯类负载用的时间继电器不限于以下 实施例的描述。
参见图 3, 本发明的金卤灯类负载用的时间继电器包括: 电源侧的相线端 子!^、 中性线端子 N, 负载侧的火线端子 4、 地线端子 3, 以及控制电路和继电 器。 电源侧的相线端子 L、 中性线端子 N用于连接交流电网的一个相线、 中性 线,使用时需采用常规做法,在相线端子 L、 中性线端子 N与交流电网的相线、 中性线之间需设置开关装置(图中未示出),通过操作开关装置的闭合或分断, 给相线端子 L、 中性线端子 N通电或断电。 所述的中性线端子 N与地线端子 3 连接,所述的继电器的输出触点 K1串联连接在相线端子 L与火线端子 4之间, 而负载侧的火线端子 4、 地线端子 3用于连接金卤灯类负载, 因此, 连接金卤 灯类负载的火线端子 4、 地线端子 3的通电 /断电受所述开关装置和所述的输出 触点 K1 的串联控制, 金卤灯类负载的通电必需满足开关装置和输出触点 K1 同时闭合的条件, 开关装置和输出触点 K1 中的任何一个的分断都会导致金卤 灯类负载的断电。
所述的控制电路包括降压整流稳压电路 A、 断电检测电路 B、 计时控制电 路。、 储能电路0、 继电器输出电路 E五个子电路。 P争压整流稳压电路 A的交 流输入端的两个极分别接相线端子 L、 中性线端子 N, 由相线端子 L、 中性线 端子 N的通电或断电控制降压整流稳压电路 A的直流输出端的加载电压或卸 载电压, 即: 通过所述的开关装置的闭合操作给降压整流稳压电路 A的直流输 出端加载电压,通过所述的开关装置的分断操作给降压整流稳压电路 A的直流 输出端卸载电压。所述的降压整流稳压电路 A与继电器输出电路 E连接提供电 源;所述的断电检测电路 B的检测信号输入端接降压整流稳压电路 A的直流输 出端,输出端与计时控制电路 C的处理信号输入端连接为计时控制电路 C提供 电源是否供电正常的检测信号;所述的储能电路 D的电能输入端接降压整流稳 压电路 A的直流输出端,输出端接计时控制电路 C的电源输入端,在所述的直 流输出端加载电压时储能, 卸载电压时为计时控制电路 C供电; 所述的计时控 制电路 C的控制信号输出端接继电器输出电路 E的控制信号输入端,在直流输 出端由加载电压转变为卸载电压的瞬间, 储能电路 D为计时控制电路 C供电, 断电检测电路 B给计时控制电路 C输出电压卸载信号, 计时控制电路 C进入 长延时计时过程, 控制电路 C通过继电器输出电路 E控制继电器的输出触点 K1禁止闭合直到计时控制电路 C的计时过程结束。
在本发明的控制电路中将储能电路 D与降压整流稳压电路 A分开设计,储 能电路 D充电的过程中不影响降压整流稳压电路 A输出的电压值, 而且储能 电路 D本身也能够有效储能, 增加储能量, 可以满足长延时控制的用电需求。
所述的控制电路的电路结构、 控制方式、 控制过程及其各子电路之间的控 制关系如下: 在所述的直流输出端加载电压的过程中, P争压整流稳压电路 A向 断电检测电路 B、 计时控制电路 C、 储能电路 D和继电器输出电路 E提供直流 电源, 储能电路 D储能; 在所述的直流输出端卸载电压的过程中, 降压整流稳 压电路 A停止向断电检测电路 B、计时控制电路 C、储能电路 D和继电器输出 电路 E提供电源, 但储能电路 D向计时控制电路 C提供直流电源; 在所述的 直流输出端卸载电压的瞬间,断电检测电路 B控制计时控制电路 C自动进入长 延时计时过程, 控制电路 C通过继电器输出电路 E控制继电器的输出触点 K1 转换为分断, 同时直流输出端的电压卸载直接控制继电器输出电路 E致使输出 触点 K1转换为分断, 并在直流输出端卸载电压的过程中输出触点 K1始终保 持在分断; 若在计时控制电路 C的长延时计时过程结束前向直流输出端加载电 压, 则计时控制电路 C通过继电器输出电路 E控制继电器的输出触点 K1继续 保持分断; 若在计时控制电路 C的长延时计时过程结束后向直流输出端加载电 压,则继电器输出电路 E在计时控制电路 C和直流输出端的加载电压的双重控 制下致使继电器的输出触点 K1转换为闭合。 所述的卸载电压的瞬间是指由加 载电压状态转换为卸载电压的瞬间; 所述的卸载电压的过程是指从卸载电压的 瞬间到保持卸载电压状态的全过程; 所述的加载电压的过程是指从加载电压的 瞬间到保持加载电压状态的全过程, 而加载电压的瞬间指由卸载电压状态转换 为加载电压的瞬间。 长延时计时过程是指延时范围能达到大于 4分钟的延时计 时过程。
在各种工作状态下所述的控制电路的各子电路之间电信号的输入输出方式 可有多种方案,一种优选的方案如下:在所述的直流输出端加载电压的常态下, 断电检测电路 B的检测信号输出端保持高电平,接计时控制电路 C的控制信号 输出端保持高电平, 在该高电平的控制下继电器输出电路 E使继电器的输入回 路导通, 并在直流输出端加载电压的激励控制下继电器的输出触点 K1保持闭 合, 储能电路 D处于储能状态; 在所述的直流输出端卸载电压的瞬间, 断电检 测电路 B的检测信号输出端转换为低电平,在该低电平的控制下接计时控制电 路 C进入长延时计时过程并使控制信号输出端转换为低电平,在该低电平的控 制下继电器输出电路 E使继电器的输入回路截止(不导通) , 同时在直流输出 端卸载电压的控制下继电器的输出触点 K1转换为分断, 储能电路 D转换为供 电状态; 在所述的计时控制电路 C处于长延时计时过程中, 不管直流输出端的 电压和检测信号输出端的电平有无变化,接计时控制电路 C的控制信号输出端 始终保持低电平,在该低电平的控制下继电器输出电路 E使继电器的输入回路 截止, 该截止使继电器的输出触点 K1不能闭合; 在所述的长延时计时过程结 束的瞬间, 计时控制电路 C的控制信号输出端转换为高电平, 在该高电平的控 制下继电器输出电路 E允许继电器的输入回路导通, 此时, 若所述的直流输出 端已加载电压则在该电压的激励控制下继电器的输入回路导通并继电器的输 出触点 K1转换为闭合, 若所述的直流输出端已卸载电压则继电器输出电路 E 因无激励电压而使继电器的输出触点 K1继续保持分断, 储能电路 D继续供电 直至电能耗尽; 在所述的直流输出端加载电压的瞬间, 断电检测电路 B的检测 信号输出端转换为高电平,在该高电平的控制下计时控制电路 C自动检查长延 时计时过程是否结束, 若长延时计时过程未结束则使控制信号输出端继续保持 低电平, 若计时过程已结束则使控制信号输出端转换为高电平, 并在该高电平 和加载电压的激励控制下继电器的输入回路导通并继电器的输出触点 K1转换 为闭合, 储能电路 D回到储能状态。 在所述的直流输出端加载电压的瞬间时, 计时控制电路 C自动检查的长延时计时过程的具体方式可以有多种,这些不同 的方式会导致时间继电器的使用功能的微小差别, 这些微小差别主要体现在同 一个长延时计时过程中执行多次通电 /断电操作上,下面通过举例来进一步说明 这个问题。 例 1, 计时控制电路 C自动检查的长延时计时过程是上一个断电长 延时计时过程的方式, 假设一个延时过程为 60分钟, 在此过程的开始后的 40 分钟作了一次断电后再通电操作, 那么继电器的输出触点 K1 自动转换为闭合 时间是在上一个断电长延时计时过程结束的时刻, 即上一个断电长延时计时过 程开始后的第 60分钟。操作。 例 2, 计时控制电路 C自动检查的长延时计时过 程是本长延时计时过程的方式, 同样假设一个延时过程为 60分钟, 在此过程 的开始后的 40分钟作了一次断电后再通电操作,那么继电器的输出触点 K1 自 动转换为闭合时间是本断电长延时计时过程结束的时刻, 即上一个断电长延时 计时过程开始后的第 100分钟。 本发明优选的方式是例 1的方式, 即: 在所述 的直流输出端加载电压的瞬间时,计时控制电路 C自动检查的长延时计时过程 是上一个断电长延时计时过程。 各子电路的具体电路结构可有多种方案, 下面是五个各子电路的一种优选 方案。
所述的 P争压整流稳压电路 A包括降压电阻 R4、 电容 C4、 整流桥 IC3、 稳 压二极管组(VD1、 VD2 ) 、 整流二极管 D6、 稳压二极管 VD3、 电容 C6和电 容 C7。 P争压电阻 R4串联连接在电源侧火线端子 L与整流桥 IC3的交流输入端 的一个极之间, 电容 C4并联连接在电阻 R4的两端,整流桥 IC3的直流输出端 的正极用作降压整流稳压电路 A的直流输出端的正极节点 A1并与断电检测电 路 B 的检测信号输入端连接, 稳压二极管组(VD1、 VD2 ) 中的稳压二极管 VD1的负极、 电容 C6的正极与正极节点 A1并联连接, 稳压二极管 VD1的正 极接稳压二极管 VD2的负极, 稳压二极管 VD2的正极用作降压整流稳压电路 A的直流输出端的调压节点 A2并与储能电路 D的电能输入端的储能正极连接, 整流二极管 D6的正极接调压节点 A2,整流二极管 D6的负极、稳压二极管 VD3 的负极、 电容 C7的正极并联连接并用作降压整流稳压电路 A的直流输出端的 稳压节点 A3,稳压节点 A3接储能电路 D的电能输入端电源正极或计时控制电 路 C的电源输入端, 电容 C6的负极、 电容 C7的负极和稳压二极管 VD3的正 极与整流桥 IC3的直流输出端的地极并联连接, 整流桥 IC3的直流输出端的地 极用作降压整流稳压电路 A 的直流输出端的地极。 从上降压整流稳压电路 A 的优选实施例可见, 整流桥 IC3的直流输出端包括正极和地极, 在正极上通过 稳压二极管 VD1、 稳压二极管 VD2、 稳压二极管 VD3的分压, 形成正极节点 Al、调压节点 A2、稳压节点 A3直流输出的正极的三个节点, 三个节点的电压 可根据各子电路的要求适配, 其中并且调压节点 A2、稳压节点 A3的对地电压 小于正极节点 Al。 正极节点 A1不仅用作继电器输出电路 E的取电节点, 而且 还用作断电检测电路 B的检测信号输入端的信号采集节点,所述的降压整流稳 压电路 A的直流输出端加载电压, 就是指正极节点 A1有对地的工作电压, 所 述的降压整流稳压电路 A的直流输出端卸载电压, 就是指正极节点 A1对地的 电压为零。 调压节点 A2用作储能电路 D的储能回路的取电节点, 而稳压节点 A3用作储能电路 D的转接电源回路的取电节点, 当然, 一种等同的电路结构 就是稳压节点 A3直接用作计时控制电路 C的取电节点。 由此可见, 通过正极 节点 Al、 调压节点 A2和稳压节点 A3, 在所述的直流输出端加载电压的过程 中, P争压整流稳压电路 A向断电检测电路^ 计时控制电路 C、 储能电路 D和 继电器输出电路 E提供直流电源, 储能电路 D储能; 当然, 在所述的直流输出 端卸载电压的过程中, 降压整流稳压电路 A停止向断电检测电路 B、 计时控制 电路 C、储能电路 D和继电器输出电路 E提供电源。稳压二极管组采用稳压二 极管 VD1与稳压二极管 VD2串联组成的结构, 其用两个稳压二极管的目的在 于降低每个稳压二极管两端的电压, 所以, 与之等同的方案可以是一个或两个 以上稳压二极管。 由稳压二极管 VD1、 稳压二极管 VD2稳压二极管 VD3构成 的分压电路,具有理想的稳压效果,一种变劣的方案是用电阻替代稳压二极管, 显然这种变劣的方案不具有稳压功能。 还有一种变劣的方案是省略整流二极管 D6和 /或电容 C7, 省略整流二极管 D6和 /或电容 C7虽然不影响电路的工作, 但影响电路的性能, 如不能防止继电器的输入回路的冲击电压对电路的破坏。
所述的断电检测电路 B包括光电耦合器 IC1、 电阻 Rl、 电阻 R2、 电容 C2、 发光二极管 Dl,电阻 R1的一端用作断电检测电路 B的检测信号输入端接降压 整流稳压电路 A的直流输出端的正极节点 Al, 电阻 R1 另一端接光电耦合器 IC1的输入端的正极, 光电耦合器 IC1 的输入端的负极接发光二极管 D1 的正 极, 光电耦合器 IC1的输出端的正极与储能电路 D电能输出端连接, 光电耦合 器 IC1的输出端的负极用作断电检测电路 B的检测信号输出端并与电阻 R2的 一端、 电容 C2的一端并联连接, 电阻 R2的另一端、 电容 C2的另一端和发光 二极管 D1的负极与降压整流稳压电路 A的直流输出端的地极并联连接。 在所 述的直流输出端加载电压的常态下, 电流从降压整流稳压电路 A的直流输出端 的正极节点 A1 流出并经电阻 Rl、 光电耦合器 IC1 的输入回路、 发光二极管 D1到地级, 点亮发光二极管 Dl, 即电源接通指示灯, 同时使光电耦合器 IC1 的输出回路导通,储能电路 D电能输出端的电压通过光电耦合器 IC1的输出回 路加载到电阻 R1的一端,使用作断电检测电路 B的检测信号输出端的电阻 R1 的一端保持高电平。 在所述的直流输出端卸载电压的瞬间并保持在卸载电压的 状态下, 由于光电耦合器 IC1 的输入回路中没有电流流过, 所以发光二极管 D1熄灭并光电耦合器 IC1的输出回路截至(不导通)储能电路 D电能输出端 的电压不能加载到作为断电检测电路 B的检测信号输出端的电阻 R1的一端, 断电检测电路 B的检测信号输出端转换为并保持在低电平。 所述的计时控制电路 C包括延时控制芯片 IC2、 晶体振荡器 Yl、 电容 Cl、 电容 C3、 电阻 R9、发光二极管 D2, 延时控制芯片 IC2的 1脚用作计时控制电 路 C的电源输入端并与储能电路 D电能输出端连接, 延时控制芯片 IC2的 2 脚与晶体振荡器 Y1的一端和电容 C1的一端并联连接,延时控制芯片 IC2的 3 脚与晶体振荡器 Y1 的另一端和电容 C3 的一端并联连接, 延时控制芯片 IC2 的 5脚用作计时控制电路 C的处理信号输入端并与断电检测电路 B的检测信号 输出端连接,延时控制芯片 IC2的 6脚用作计时控制电路 C的控制信号输出端 并与继电器输出电路 E的控制信号输入端连接,延时控制芯片 IC2的 9脚接电 阻 R9的一端, 电阻 R9的另一端接发光二极管 D2的正极, 电容 C1的另一端、 电容 C3的另一端、 光二极管 D2的负极和延时控制芯片 IC2的 14脚与 P争压整 流稳压电路 A的直流输出端的地极并联连接。 延时控制芯片 IC2为单片机, 本 实施例中选用型号为 PIC16F684的 PIC单片机, 其 1脚和 14脚分别为延时控 制芯片 IC2的电源输入端的正极和地极,也是计时控制电路 C的电源输入端的 正极和地极, 除此之外, 本发明还应用延时控制芯片 IC2的以下特性构成了满 足本发明的时间继电器的控制要求的电路结构。 应用延时控制芯片 IC2的延时 控制特性和结构, 在延时控制芯片 IC2的 2脚与 3脚之间连接的由晶体振荡器 Y1及电容 Cl、 电容 C3构成的时钟源电路, 为延时控制芯片 IC2提供程序运 行的时钟, 其时钟精度高稳定性好。 延时控制芯片 IC2还可选用常用的 RC时 钟电路为程序运行提供时钟, 或者选用带有内部时钟的单片机, 当以内部时钟 作为程序运行的时钟, 延时控制芯片 IC2的 2脚与 3脚可悬空。 RC时钟电路 误差大频率低, 内部时钟精度低受温度影响大, 因此优选本实施例的时钟源电 路。 为延时控制芯片 IC2的延时计时提供时钟源, 由于晶体振荡器 Y1的时长 范围很大, 所以可实现长延时。 用延时控制芯片 IC2的 5脚也作为计时控制电 路 C的处理信号输入端(也是断电检测电路 B的检测信号输出端), 用延时控 制芯片 IC2的 6脚作为计时控制电路 C的控制信号输出端(也是继电器输出电 路 E的控制信号输入端) , 用延时控制芯片 IC2的 9脚作为发光二极管 D2, 即延时指示灯的电源, 形成了实现本发明控制要求的以下控制关系: 在 5脚输 入高电平的控制下, 6脚的输出为高电平; 在 5脚由高电平转换为低电平的瞬 间, 延时控制芯片 IC2进入长延时计时过程, 同时 6脚也转换为低电平, 9脚 输出脉冲电压使发光二极管 D2 闪烁; 在长延时计时过程结束的瞬间, 6脚转 换为高电平并输出给控制继电器输出电路 E, 而 9脚的输出电压转换为直流电 压使发光二极管 D2常亮。一种可选择的优选方案,就是应用延时控制芯片 IC2 的 10脚的参考电压实现对延时控制芯片 IC2的延时时长的控制, 具体的电路 结构为: 所述的计时控制电路 C还包括时间整定电路, 所述的时间整定电路包 括电阻 R10、 电位器 Rl l、 二极管 D8、 电容 C8, 电阻 R10的一端接延时控制 芯片 IC2的 10脚, 电阻 R10的另一端与二极管 D8的正极、 电位器 R11的滑 动端和电容 C8的一端并联连接, 二极管 D8的负极与电位器 R11的一个固定 端和延时控制芯片 IC2的 1脚并联连接, 电容 C8的一端与电位器 R11的另一 个固定端和降压整流稳压电路 A的直流输出端的地极并联连接。 当通过人为操 作给电位器 R11的滑动端输入一个机械的位移量时, 就可改变 10脚的参考电 压值, 而通过改变 10脚的参考电压值来设置延时控制芯片 IC2延时计时的时 间长度。显然,通过时间整定电路, 不仅可以为用户提供延时长度的自主设定, 而且还可以提供精准的延时时长精度和极大的延时时长范围, 从而可扩展产品 的使用功能,如:在用作金卤灯的通电 /断电控制时,用户可根据金卤灯的型号、 季节或使用场合自主设定延时时长; 在用作电源控制时, 可根据实际的用电管 理要求进行通电 /断电时间的精确控制。
所述的储能电路 D包括电阻 R3、 二极管 D3、 二极管 D4、 二极管 D5、 超 级电容 C5,电阻 R3的一端用作储能电路 D的电能输入端的储能正极并与降压 整流稳压电路 A的直流输出端的调压节点 A2连接, 电阻 R3的一端接二极管 D4的正极, 二极管 D4的负极与超级电容 C5的正极和二极管 D5的正极并联 连接, 二极管 D3的正极用作储能电路 D的电能输入端的电源正极并与降压整 流稳压电路 A的直流输出端的稳压节点 A3连接, 超级电容 C5的负极接降压 整流稳压电路 A的直流输出端的地极, 二极管 D5的负极与二极管 D3的负极 连接形成储能电路 D的电能输出端,该电能输出端与断电检测电路 B的光电耦 合器 IC1的输出端的正极和计时控制电路 C的电源输入端并联连接。在降压整 流稳压电路 A的直流输出端加载电压时: 电流从直流输出端的调压节点 A2流 出, 经电阻 R3、 二极管 D4后到达超级电容 C5并为超级电容 C5充电, 即由 降压整流稳压电路 A向储能电路 D提供直流电源, 而储能电路 D处于储能状 态; 在超级电容 C5充电期间, 当超级电容 C5两端的电压很低(甚至为 0 )时, 电阻 R3起到限流分压作用, 保证调压节点 A2、 稳压节点 A3的电压不被超级 电容 C5的充电拉低,以确保在通电瞬间对电路 C中 IC2供电的电压是正常的; 稳压节点 A3的电流经过二极管 D3后流入断电检测电路 B的光电耦合器 IC1 的输出端的正极和计时控制电路 C的电源输入端 (1脚) , 即由降压整流稳压 电路 A向断电检测电路^ 计时控制电路 C提供直流电源; 由于二极管 D5的 反向截止特性, 从稳压节点 A3流出的电流不会流入超级电容 C5。 在降压整流 稳压电路 A的直流输出端卸载电压时: 调压节点 A2、稳压节点 A3为低电位, 而超级电容 C5正极为高电位, 故而超级电容 C5放电, 从超级电容 C5的正极 流出的电流经二极管 D5后流入计时控制电路 C的电源输入端 (1脚) , 即由 储能电路 D作为电源继续为计时控制电路 C提供电源;由于受直流输出端卸载 电压的控制, 断电检测电路 B的光电耦合器 IC1的输出回路截止(不导通) , 所以从超级电容 C5的正极流出的电流不会流入光电耦合器 IC1的输出回路; 由于二极管 D4、 二极管 D3的反向截止特性, 所以从超级电容 C5的正极流出 的电流不会流回调压节点 A2、 稳压节点 A3。 由于超级电容 C5的超大容量特 性,它相当于一个电池,能满足计时控制电路 C的长延时计时运行的供电要求。
所述的继电器输出电路 E包括电阻 R5、 电阻 R6、 电阻 R7、 电阻 R8、 三 极管 Q1、 三极管 Q2、 二极管 D7和继电器, 三极管 Q1的发射极与电阻 R5的 一端和降压整流稳压电路 A的直流输出端的正极节点 A1 并联连接, 电阻 R5 的另一端与三极管 Q1的基极和电阻 R6的一端并联连接, 三极管 Q1的集电极 与二极管 D7负极和继电器输入回路的一端并联连接, 继电器输入回路的另一 端与二极管 D7的正极和降压整流稳压电路 A的直流输出端的稳压节点 A3并 联连接, 电阻 R6的另一端电阻 R6接三极管 Q2的集电极, 三极管 Q2的发射 极与电阻 R7的一端和降压整流稳压电路 A的直流输出端的地极并联连接, 电 阻 R7的另一端与三极管 Q2的基极和电阻 R8的一端并联连接, 电阻 R8的另 一端用作继电器输出电路 E的控制信号输入端并与计时控制电路 C的控制信号 输出端连接。 在接计时控制电路 C 的控制信号输出端输出高电平 (即三极管 Q2 的基极为高电平) 的现况下: 如果直流输出端已加载电压, 则在该高电平 的控制下三极管 Q1导通, 使直流输出端的正极节点 A1 的对地电压 (即加载 电压)加载在继电器输入回路的两端, 致使继电器吸合并输出触点 K1 闭合; 如果直流输出端已卸载电压, 则该高电平不能控制三极管 Q1导通, 同时也无 电压可激励继电器吸合, 所以继电器的输出触点 K1分断。 在接计时控制电路 C的控制信号输出端输出低电平 (即三极管 Q2的基极为低电平) 的现况下: 即使直流输出端已加载电压,则在该低电平的控制下三极管 Q1截止(不导通), 从而使直流输出端的正极节点 A1 的对地电压 (即加载电压) 不能加载在继电 器输入回路的两端, 继电器的输入回路因得不到激励电压而致使输出触点 K1 分断; 当然, 在直流输出端已卸载电压现况下, 还是因三极管 Q1截止(不导 通)和继电器的输入回路得不到激励电压而致使输出触点 K1分断。
所述的继电器优选为通用电磁继电器, 其优点是输出触点 K1 的工作电流 大、 分断能力强, 价格性能比好。 应该能理解到, 由于本发明采用了上述控制 电路, 所以使选用通用电磁继电器成为可能, 或者说, 可不采用常规的磁保持 继电器, 从而可获得输出触点的大工作电流的效果, 可以直接控制许多大功率 的金卤灯。
从上可见, 本发明的金卤灯类负载用的时间继电器能很好满足金卤灯类负 载的特殊使用要求, 这些特殊使用要求如: 只有在同时满足直流输出端加载电 压和长延时计时过程结束两个条件下, 其控制电路才会闭合继电器的输出触点 K1 , 即才能给金卤灯类负载通电; 若不满足直流输出端加载电压和长延时计时 过程结束两个条件, 或者不满足其中一个条件, 则都不能使其的继电器的输出 触点 K1闭合, 即都不能给金卤灯类负载通电; 用降压整流稳压电路 A的直流 输出端的卸载电压的瞬间作为长延时计时的起点, 确保了两次启动之间的时间 间隔的可靠性和精准性; 用长延时计时过程结束的瞬间作为允许继电器输入回 路导通的控制条件, 可使时间继电器产品的二次启动具有延时控制启动和人为 操作启动两种方式; 时间整定电路, 使时间继电器产品的延时范围大且可调、 定时准确又可靠, 满足其多用途的要求。 所谓延时控制启动是指, 对开关装置 先作断电操作, 然后在延时结束前作通电操作, 则在延时结束时控制电路自动 给负载通电。 人为操作启动中的产品在后马上通电操作是指, 对开关装置先作 断电操作, 然后在延时结束后作通电操作, 则此刻的操作使负载马上得电。

Claims

权 利 要 求 书
1. 一种金卤灯类负载用的时间继电器, 它包括电源侧的相线端子 L、 中性 线端子 N, 负载侧的火线端子 (4 ) 、 地线端子 (3 ) , 以及控制电路, 所述的 中性线端子 N与地线端子 (3 )连接, 所述的继电器的输出触点 K1 串联连接 在相线端子 L与火线端子 (4 )之间, 其特征在于:
所述的控制电路包括降压整流稳压电路 A、 断电检测电路 B、 计时控制电 路。、 储能电路0、 继电器输出电路 E, 降压整流稳压电路 A的交流输入端的 两个极分别接相线端子!^、 中性线端子 N, 由相线端子 L、 中性线端子 N的通 电或断电控制 P争压整流稳压电路 A的直流输出端的加载电压或卸载电压; 所述的 P争压整流稳压电路 A与继电器输出电路 E连接提供电源;所述的断 电检测电路 B的检测信号输入端接降压整流稳压电路 A的直流输出端,输出端 与计时控制电路 C的处理信号输入端连接为计时控制电路 C提供电源是否供电 正常的检测信号; 所述的储能电路 D的电能输入端接降压整流稳压电路 A的 直流输出端, 输出端接计时控制电路 C的电源输入端, 在所述的直流输出端加 载电压时储能, 卸载电压时为计时控制电路 C供电;
所述的计时控制电路 C的控制信号输出端接继电器输出电路 E的控制信号 输入端, 在直流输出端由加载电压转变为卸载电压的瞬间, 储能电路 D为计时 控制电路 C供电, 断电检测电路 B给计时控制电路 C输出电压卸载信号, 计 时控制电路 C进入长延时计时过程, 控制电路 C通过继电器输出电路 E控制 继电器的输出触点 K1禁止闭合直到计时控制电路 C的计时过程结束。
2. 根据权利要求 1所述的金卤灯类负载用的时间继电器, 其特征在于: 在所述的直流输出端加载电压的常态下, 断电检测电路 B的检测信号输出 端保持高电平, 接计时控制电路 C的控制信号输出端保持高电平, 在该高电平 的控制下继电器输出电路 E使继电器的输入回路导通, 并在直流输出端加载电 压的激励控制下继电器的输出触点 K1保持闭合, 储能电路 D处于储能状态; 在所述的直流输出端卸载电压的瞬间, 断电检测电路 B的检测信号输出端 转换为低电平,在该低电平的控制下接计时控制电路 C进入长延时计时过程并 使控制信号输出端转换为低电平, 在该低电平的控制下继电器输出电路 E使继 电器的输入回路截止, 同时在直流输出端卸载电压的控制下继电器的输出触点 K1转换为分断, 储能电路 D转换为供电状态;
在所述的直流输出端加载电压的瞬间, 断电检测电路 B的检测信号输出端 转换为高电平,在该高电平的控制下计时控制电路 C自动检查上一个长延时计 时过程是否结束, 若长延时计时过程未结束则使控制信号输出端继续保持低电 平, 若计时过程已结束则使控制信号输出端转换为高电平, 并在该高电平和加 载电压的激励控制下继电器的输入回路导通并继电器的输出触点 K1转换为闭 合, 储能电路 D回到储能状态。
3.根据权利要求 1所述的金卤灯类负载用的时间继电器,其特征在于: 所 述的 P争压整流稳压电路 A包括降压电阻 R4、 第四电容 C4、 整流桥 IC3、 稳压 二极管组(VD1、 VD2 ) 、 整流二极管 D6、 第三稳压二极管 VD3、 第六电容 C6和第七电容 C7, P争压电阻 R4串联连接在电源侧火线端子 L与整流桥 IC3 的交流输入端的一个极之间, 第四电容 C4并联连接在降压电阻 R4的两端,整 流桥 IC3的直流输出端的正极用作 P争压整流稳压电路 A的直流输出端的正极节 点 A1并与断电检测电路 B的检测信号输入端连接,稳压二极管组(VD1、VD2 ) 中的第一稳压二极管 VD1的负极、 第六电容 C6的正极与正极节点 A1并联连 接, 第一稳压二极管 VD1的正极接第二稳压二极管 VD2的负极, 第二稳压二 极管 VD2的正极用作降压整流稳压电路 A的直流输出端的调压节点 A2并与储 能电路 D的电能输入端的储能正极连接,整流二极管 D6的正极接调压节点 A2, 整流二极管 D6的负极、 第三稳压二极管 VD3的负极、 第七电容 C7的正极并 联连接并用作降压整流稳压电路 A的直流输出端的稳压节点 A3,稳压节点 A3 接储能电路 D的电能输入端电源正极或计时控制电路 C的电源输入端,第六电 容 C6的负极、第七电容 C7的负极和第三稳压二极管 VD3的正极与整流桥 IC3 的直流输出端的地极并联连接, 整流桥 IC3的直流输出端的地极用作降压整流 稳压电路 A的直流输出端的地极。
4. 根据权利要求 1 所述的金卤灯类负载用的时间继电器, 其特征在于: 所述的断电检测电路 B包括光电耦合器 IC1、 第一电阻 Rl、 第二电阻 R2、 第 二电容 C2、 第一发光二极管 Dl, 第一电阻 R1的一端用作断电检测电路 B的 检测信号输入端接降压整流稳压电路 A的直流输出端的原压节点 Al, 第一电 阻 R1另一端接光电耦合器 IC1的输入端的正极, 光电耦合器 IC1的输入端的 负极接第一发光二极管 D1的正极, 光电耦合器 IC1的输出端的正极与储能电 路 D电能输出端连接,光电耦合器 IC1的输出端的负极用作断电检测电路 B的 检测信号输出端并与第二电阻 R2的一端、第二电容 C2的一端并联连接, 第二 电阻 R2的另一端、 第二电容 C2的另一端和第一发光二极管 D1的负极与降压 整流稳压电路 A的直流输出端的地极并联连接。
5. 根据权利要求 1 所述的金卤灯类负载用的时间继电器, 其特征在于: 所述的计时控制电路 C包括延时控制芯片 IC2、第九电阻 R9、第二发光二极管 D2,延时控制芯片 IC2的第一管脚用作计时控制电路 C的电源输入端并与储能 电路 D电能输出端连接,延时控制芯片 IC2的第五管脚用作计时控制电路 C的 处理信号输入端并与断电检测电路 B 的检测信号输出端连接, 延时控制芯片 IC2的第六管脚用作计时控制电路 C的控制信号输出端并与继电器输出电路 E 的控制信号输入端连接,延时控制芯片 IC2的第九管脚接第九电阻 R9的一端, 第九电阻 R9的另一端接第二发光二极管 D2的正极, 第二发光二极管 D2的负 极和延时控制芯片 IC2的第十四管脚与 P争压整流稳压电路 A的直流输出端的地 极并联连接。
6. 根据权利要求 1 所述的金卤灯类负载用的时间继电器, 其特征在于: 所述的储能电路 D包括第三电阻 R3、 第三二极管 D3、 第四二极管 D4、 第五 二极管 D5、 超级电容 C5, 第三电阻 R3的一端用作储能电路 D的电能输入端 的储能正极并与降压整流稳压电路 A的直流输出端的调压节点 A2连接, 第三 电阻 R3 的一端接第四二极管 D4的正极, 第四二极管 D4的负极与超级电容 C5的正极和第五二极管 D5的正极并联连接, 第三二极管 D3的正极用作储能 电路 D的电能输入端的电源正极并与降压整流稳压电路 A的直流输出端的稳 压节点 A3连接, 超级电容 C5的负极接降压整流稳压电路 A的直流输出端的 地极, 第五二极管 D5的负极与第三二极管 D3的负极连接形成储能电路 D的 电能输出端,该电能输出端与断电检测电路 B的输出端的正极和计时控制电路 C的电源输入端并联连接。
7. 根据权利要求 1 所述的金卤灯类负载用的时间继电器, 其特征在于: 所述的继电器输出电路 E包括第五电阻 R5、 第六电阻 R6、 第七电阻 R7、 第八 电阻 R8、 第一三极管 Ql、 第二三极管 Q2、 第七二极管 D7, 第一三极管 Q1 的发射极与第五电阻 R5的一端和降压整流稳压电路 A的直流输出端的正极节 点 A1 并联连接, 第五电阻 R5的另一端与第一三极管 Q1 的基极和第六电阻 R6的一端并联连接, 第一三极管 Q1的集电极与第七二极管 D7负极和继电器 输入回路的一端并联连接, 继电器输入回路的另一端与第七二极管 D7的正极 和降压整流稳压电路 A的直流输出端的稳压节点 A3并联连接, 第六电阻 R6 的另一端接第二三极管 Q2的集电极, 第二三极管 Q2的发射极与第七电阻 R7 的一端和降压整流稳压电路 A的直流输出端的地极并联连接, 第七电阻 R7的 另一端与第二三极管 Q2的基极和第八电阻 R8的一端并联连接, 第八电阻 R8 的另一端用作继电器输出电路 E的控制信号输入端并与计时控制电路 C的控制 信号输出端连接。
8. 根据权利要求 1 所述的金卤灯类负载用的时间继电器, 其特征在于: 所述的继电器为电磁继电器。
9.根据权利要求 5所述的金卤灯类负载用的时间继电器, 其特征在于: 所 述的计时控制电路 C还包括时间整定电路,所述的时间整定电路包括第十电阻 R10、 电位器 Rl l、 第八二极管 D8、 第八电容 C8, 第十电阻 R10的一端接延 时控制芯片 IC2的第十管脚,第十电阻 R10的另一端与第八二极管 D8的正极、 电位器 R11的滑动端和第八电容 C8的一端并联连接, 第八二极管 D8的负极 与电位器 R11的一个固定端和延时控制芯片 IC2的第一管脚并联连接, 第八电 容 C8的一端与电位器 Rl 1的另一个固定端和降压整流稳压电路 A的直流输出 端的地极并联连接。
10. 根据权利要求 5所述的金卤灯类负载用的时间继电器, 其特征在于: 所述的计时控制电路 C还包括由晶体振荡器 Yl、 第一电容 Cl、 第三电容 C3 构成的时钟源电路, 所述延时控制芯片 IC2的第二管脚与晶体振荡器 Y1的一 端和第一电容 CI的一端并联连接, 延时控制芯片 IC2的第三管脚与晶体振荡 器 Y1的另一端和第三电容 C3的一端并联连接, 所述第一电容 C1的另一端、 第三电容 C3的另一端和降压整流稳压电路 A的直流输出端的地极并联连接。
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