WO2014194025A1 - Techniques for chip scale packaging without solder mask - Google Patents

Techniques for chip scale packaging without solder mask Download PDF

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Publication number
WO2014194025A1
WO2014194025A1 PCT/US2014/039904 US2014039904W WO2014194025A1 WO 2014194025 A1 WO2014194025 A1 WO 2014194025A1 US 2014039904 W US2014039904 W US 2014039904W WO 2014194025 A1 WO2014194025 A1 WO 2014194025A1
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WO
WIPO (PCT)
Prior art keywords
csp
mesa
mems device
solder
flux material
Prior art date
Application number
PCT/US2014/039904
Other languages
French (fr)
Inventor
Roberto Gaddi
Robertus Petrus Van Kampen
Paul Albert Castillou
Original Assignee
Cavendish Kinetics, Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cavendish Kinetics, Inc filed Critical Cavendish Kinetics, Inc
Publication of WO2014194025A1 publication Critical patent/WO2014194025A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
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    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/171—Disposition
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    • H01L2224/81143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
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    • H01L2224/818—Bonding techniques
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K1/02—Details
    • H05K1/0284—Details of three-dimensional rigid printed circuit boards
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
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    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • Embodiments of the present invention generally relate radio frequency chip scale packaging (CSP) components based on monolithically integrated complementary metal oxide semiconductor (CMOS) and low loss passive components and switches.
  • CSP radio frequency chip scale packaging
  • the present invention generally relates to techniques and structures that permit a CSP RF-MEMS to be assembled without the need for a solder mask.
  • a CSP RF-MEMS By having a mesa above the substrate, and having the chip soldered to traces on top of the mesa, the traces do not need a solder mask thereover outside of the mesa. If any solder mask is present, the solder mask is present only on top of the mesa and not on the sidewalls of the mesa or on the substrate.
  • a CSP RF-MEMS device comprises a carrier substrate having a mesa thereover, the mesa extending above the substrate; a first metal trace coupled to the substrate and extending along a sidewall of the mesa and at least a portion of a top surface of the mesa; a solder bump coupled to the first metal trace; a chip; and a pad coupled to the chip and to the solder bump, wherein the mesa delimits a solder reflow region in a surface mount component footprint.
  • Figure 1 is a schematic cross-sectional illustration of a CSP of a MEMS device.
  • Figure 2 is a schematic cross-sectional illustration of CSP for a MEMS device according to one embodiment.
  • Figure 3 is a schematic top view of a layout of a MESA defined CSP footprint according to one embodiment.
  • Figure 4 is a schematic cross-sectional illustration of CSP for a MEMS device according to another embodiment.
  • the present invention generally relates to techniques and structures that permit a CSP RF-MEMS to be assembled without the need for a solder mask.
  • a CSP RF-MEMS By having a mesa above the substrate, and having the chip soldered to traces on top of the mesa, the traces do not need a solder mask thereover outside of the mesa. If any solder mask is present, the solder mask is present only on top of the mesa and not on the sidewalls of the mesa or on the substrate.
  • a standard chip scale packaging (CSP) component is made of a bare chip (1 ), of thickness in the 100's of micrometer range.
  • the die has a front side (10) and a back side (4).
  • the back side is typically coated (20) and marked.
  • the front side integrates the active CMOS circuitry, the back-end metallization embedded in the passivation layers.
  • the passivation has openings and pads (1 1 ) and on top of such pads conductive bumps or pillars are manufactured (12).
  • the die is flipped and mounted on a PCB (30), so that the front side will face the top side of the PCB.
  • a PCB On the top side of the PCB there are metal traces (40, 41 , 42) covered typically with a solder mask layer (31 ).
  • the solder bumps or pillars of the CSP die are going to make electrical and mechanical contact with the PCB metal in locations where the solder mask have openings.
  • solder mask (31 ) is there used to stop the solder material from wetting the whole conductor trace. As a result, a pillar of solder is formed and the CSP die is attached to the PCB while maintaining a safe stand-off distance in-between.
  • a technology that does not allow placing a solder mask on top of the conductor pattern will pose issues in assembling CSP components.
  • One example of such technology is the laser direct structuring (LDS) typically used to generate fully 3D shapes with conductor patterns running on the surface. Due to the 3-dimensional nature of such LDS structures, it is not possible to apply thin layers of solder mask and subsequently generate small opening in the same solder mask layer in order to generate the CSP pads footprint.
  • LDS laser direct structuring
  • Figure 2 describes one embodiment of this invention, the carrier substrate (50) being a 3-dimensional shape with conductor patterns defined on its surface (41 , 42 and 43).
  • a MESA structure is fabricated underneath the CSP die (51 ), having therefore an elevated region which size is slightly larger than the size of the die.
  • the mesa extends above the surface of the PCB by a distance.
  • the conductor traces can be patterned both on the top side (41 ) and along the side-walls (43) of such MESA.
  • a solder flux can be applied using printing process. This leaves flux material only on the top surfaces (60) of the conductor traces that are running onto the MESA and not on the side-walls (61 ).
  • the flux material facilitates the wetting of the conductor by the melted solder during the temperature reflow phase.
  • the solder bump 13 will therefore reflow up to the conductor edge and not further.
  • the MESA structure has therefore implemented a stop mechanism for the solder during reflow, allowing a die attach without solder mask with good stand-off distance between die and carrier substrate.
  • the flux material is placed on the desired surfaces where the solder should be present.
  • the solder will then, once applied, flow, upon melting, over the flux material. Due to wetting, the solder will not flow past the flux material and thus be contained in the desired area.
  • the solder remains on the flux material.
  • the flux material is disposed only on the top surfaces 60 of the conductor patterns.
  • the flux material is not present on the sidewalls of the conductor patterns that run along the sidewalls of the mesa. As such, the solder will not flow down the sidewalls of the mesa. In other words, the mesa, and the flux material contribute to containing the solder in a desired location.
  • the flux material may be used individually or collectively to contain the solder.
  • the flux material and the solder compabide the same material such as ALPHA® based solders and flux material available from Cookson Electronics.
  • the solder and flux material are lead free.
  • Figure 3 shows a top layout view of a possible embodiment of the MESA defined CSP footprint.
  • a number of pads (70) are patterned on top of the MESA structure (71 ) and conductor traces running to the pads (72) cross the MESA edges. These conductor traces will be defined also on the side- wall of the MESA (73), bringing the electrical paths up to the pads.
  • the manufacturing limitations for implementing a conductor pattern (43) on the side-wall of the MESA structure are accommodated.
  • the slope of the MESA's side-walls is at an angle which is smaller than 90 degrees. This angle should be as close as possible to 90 degrees, but small enough in order for the manufacturing process to generate a continuous conductor pattern on the side-walls.
  • Advantages of this invention are related to reduced costs and increased miniaturization of electronic devices based on integrating chips scale packaging (CSP) components inside a 3-dimensional circuit such as an antenna.
  • CSP chips scale packaging

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention generally relates to techniques and structures that permit a CSP RF-MEMS to be assembled without the need for a solder mask. By having a mesa above the substrate, and having the chip soldered to traces on top of the mesa, the traces do not need a solder mask thereover outside of the mesa. If any solder mask is present, the solder mask is present only on top of the mesa and not on the sidewalls of the mesa or on the substrate.

Description

TECHNIQUES FOR CHIP SCALE PACKAGING WITHOUT SOLDER MASK
BACKGROUND OF THE INVENTION
Field of the Invention
[0001] Embodiments of the present invention generally relate radio frequency chip scale packaging (CSP) components based on monolithically integrated complementary metal oxide semiconductor (CMOS) and low loss passive components and switches.
Description of the Related Art
[0002] The constant demand for miniaturization of electrical appliances and portable electronic devices such as mobile phones and tablets poses continuous pressure on the manufacturing processes of electronic circuits for allowing for more integration in reduced volume. Following this trend, it is desirable to assemble electronic components on the surface of carrier substrates that are manufactured not following standard printed circuit board (PCB) technology. One example is the laser direct structuring (LDS) technology that allows generating a fully 3-dimensional shape with electrical conductor patterns on its surface.
[0003] Direct assembly of high quality chips scale packaging (CSP) electronic components of such 3D carriers poses issues and is as of today not available, due to the difficulties in patterning a solder mask on the surface of such carriers. Therefore flexible PCB solutions are used nowadays to be able to generate a quasi-3D solution to this problem.
[0004] There is a need in the art for a design solution that allows the assembly process of CSP components directly on 3-dimenional carriers without the need of a solder mask.
SUMMARY OF THE INVENTION
[0005] The present invention generally relates to techniques and structures that permit a CSP RF-MEMS to be assembled without the need for a solder mask. By having a mesa above the substrate, and having the chip soldered to traces on top of the mesa, the traces do not need a solder mask thereover outside of the mesa. If any solder mask is present, the solder mask is present only on top of the mesa and not on the sidewalls of the mesa or on the substrate.
[0006] In one embodiment, a CSP RF-MEMS device comprises a carrier substrate having a mesa thereover, the mesa extending above the substrate; a first metal trace coupled to the substrate and extending along a sidewall of the mesa and at least a portion of a top surface of the mesa; a solder bump coupled to the first metal trace; a chip; and a pad coupled to the chip and to the solder bump, wherein the mesa delimits a solder reflow region in a surface mount component footprint.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
[0008] Figure 1 is a schematic cross-sectional illustration of a CSP of a MEMS device.
[0009] Figure 2 is a schematic cross-sectional illustration of CSP for a MEMS device according to one embodiment.
[0010] Figure 3 is a schematic top view of a layout of a MESA defined CSP footprint according to one embodiment.
[0011] Figure 4 is a schematic cross-sectional illustration of CSP for a MEMS device according to another embodiment.
[0012] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.
DETAILED DESCRIPTION
[0013] The present invention generally relates to techniques and structures that permit a CSP RF-MEMS to be assembled without the need for a solder mask. By having a mesa above the substrate, and having the chip soldered to traces on top of the mesa, the traces do not need a solder mask thereover outside of the mesa. If any solder mask is present, the solder mask is present only on top of the mesa and not on the sidewalls of the mesa or on the substrate.
[0014] A standard chip scale packaging (CSP) component is made of a bare chip (1 ), of thickness in the 100's of micrometer range. The die has a front side (10) and a back side (4). The back side is typically coated (20) and marked. The front side integrates the active CMOS circuitry, the back-end metallization embedded in the passivation layers. The passivation has openings and pads (1 1 ) and on top of such pads conductive bumps or pillars are manufactured (12).
[0015] During CSP packaging the die is flipped and mounted on a PCB (30), so that the front side will face the top side of the PCB. On the top side of the PCB there are metal traces (40, 41 , 42) covered typically with a solder mask layer (31 ). During assembly, the solder bumps or pillars of the CSP die are going to make electrical and mechanical contact with the PCB metal in locations where the solder mask have openings.
[0016] When performing CSP assembly, the area on the PCB pad that will make mechanical and electrical contact with the solder bump during a solder reflow process has to be delimited and defined. Depending on the PCB technology, which drives the cost level of the application, several alternatives are possible. The scope of this invention is limited to low-cost solutions which do not allow miniature via's under pad. In this situation, since a conductor trace is always going to intercept the pad geometry, there is a need to use solder mask to stop the solder from reflowing away from the pad.
[0017] In Figure 1 , the conductor trace (40) runs into a pad. Solder mask (31 ) is there used to stop the solder material from wetting the whole conductor trace. As a result, a pillar of solder is formed and the CSP die is attached to the PCB while maintaining a safe stand-off distance in-between.
[0018] A technology that does not allow placing a solder mask on top of the conductor pattern will pose issues in assembling CSP components. One example of such technology is the laser direct structuring (LDS) typically used to generate fully 3D shapes with conductor patterns running on the surface. Due to the 3-dimensional nature of such LDS structures, it is not possible to apply thin layers of solder mask and subsequently generate small opening in the same solder mask layer in order to generate the CSP pads footprint.
[0019] Figure 2 describes one embodiment of this invention, the carrier substrate (50) being a 3-dimensional shape with conductor patterns defined on its surface (41 , 42 and 43). A MESA structure is fabricated underneath the CSP die (51 ), having therefore an elevated region which size is slightly larger than the size of the die. As shown in Figure 2, the mesa extends above the surface of the PCB by a distance. The conductor traces can be patterned both on the top side (41 ) and along the side-walls (43) of such MESA. During the assembly process, a solder flux can be applied using printing process. This leaves flux material only on the top surfaces (60) of the conductor traces that are running onto the MESA and not on the side-walls (61 ). The flux material facilitates the wetting of the conductor by the melted solder during the temperature reflow phase. The solder bump 13 will therefore reflow up to the conductor edge and not further. The MESA structure has therefore implemented a stop mechanism for the solder during reflow, allowing a die attach without solder mask with good stand-off distance between die and carrier substrate.
[0020] To put it another way, the flux material is placed on the desired surfaces where the solder should be present. The solder will then, once applied, flow, upon melting, over the flux material. Due to wetting, the solder will not flow past the flux material and thus be contained in the desired area. In the embodiment shown in Figure 2, the solder remains on the flux material. The flux material is disposed only on the top surfaces 60 of the conductor patterns. The flux material is not present on the sidewalls of the conductor patterns that run along the sidewalls of the mesa. As such, the solder will not flow down the sidewalls of the mesa. In other words, the mesa, and the flux material contribute to containing the solder in a desired location. It is envisioned that either the flux material, or the mesa, may be used individually or collectively to contain the solder. In one embodiment, the flux material and the solder compreise the same material such as ALPHA® based solders and flux material available from Cookson Electronics. In another embodiment, the solder and flux material are lead free.
[0021] Figure 3 shows a top layout view of a possible embodiment of the MESA defined CSP footprint. A number of pads (70) are patterned on top of the MESA structure (71 ) and conductor traces running to the pads (72) cross the MESA edges. These conductor traces will be defined also on the side- wall of the MESA (73), bringing the electrical paths up to the pads.
[0022] In a different embodiment shown in Figure 4, the manufacturing limitations for implementing a conductor pattern (43) on the side-wall of the MESA structure are accommodated. The slope of the MESA's side-walls is at an angle which is smaller than 90 degrees. This angle should be as close as possible to 90 degrees, but small enough in order for the manufacturing process to generate a continuous conductor pattern on the side-walls. [0023] Advantages of this invention are related to reduced costs and increased miniaturization of electronic devices based on integrating chips scale packaging (CSP) components inside a 3-dimensional circuit such as an antenna.
[0024] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

Claims:
1 . A CSP RF-MEMS device, comprising:
a carrier substrate having a mesa thereover, the mesa extending above the substrate;
a first metal trace coupled to the substrate and extending along a sidewall of the mesa and at least a portion of a top surface of the mesa;
a solder bump coupled to the first metal trace;
a chip; and
a pad coupled to the chip and to the solder bump, wherein the mesa delimits a solder reflow region in a surface mount component footprint.
2. The CSP RF-MEMS device of claim 1 , wherein the mesa has sloped sidewalls.
3. The CSP RF-MEMS device of claim 2, wherein the sidewalls are sloped at an angle of less than 90 degrees.
4. The CSP RF-MEMS device of claim 1 , further comprising flux material disposed on the first metal trace.
5. The CSP RF-MEMS device of claim 4, wherein the solder bump is disposed on the flux material.
6. The CSP RF-MEMS device of claim 5, wherein the solder bump and the flux material comprise the same material.
7. The CSP RF-MEMS device of claim 6, wherein the flux material and the solder are lead free.
8. The CSP RF-MEMS device of claim 5, wherein the mesa has sloped sidewalls.
9. The CSP RF-MEMS device of claim 8, wherein the solder bump and the flux material comprise the same material.
10. The CSP RF-MEMS device of claim 9, wherein the flux material and the solder are lead free.
1 1 . The CSP RF-MEMS device of claim 8, wherein the sidewalls are sloped at an angle of less than 90 degrees.
12. The CSP RF-MEMS device of claim 1 1 , wherein the solder bump and the flux material comprise the same material.
13. The CSP RF-MEMS device of claim 12, wherein the flux material and the solder are lead free.
PCT/US2014/039904 2013-05-29 2014-05-29 Techniques for chip scale packaging without solder mask WO2014194025A1 (en)

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