WO2014188229A1 - Electronic ballast control - Google Patents

Abstract

A ballast control circuit comprising a first switching node, a second switching node, a detection node, and a decision circuit is disclosed. The decision circuit is to monitor voltage (or more specifically voltage variation) at the detection node and to toggle the first switching node from a turn off state to a turn on state upon detection of an event corresponding to an end of voltage rising at the detection node during run mode or steady state operation and when the second switching node is at a turn off state.

Description

ELECTRONIC BALLAST CONTROL

FIELD

[001 ] The present disclosure relates to lighting apparatus power supply control such as electronic ballasts and ballast control circuits for electronic ballasts, and more particularly, to power supply control such as ballast controls for fluorescent lamps.

BACKGROUND

[002] Many lighting apparatus such as LED (light emitting diode) lamps, fluorescent lamps and compact fluorescent lamps (CFL) are operated with a power supply control apparatus comprising a high frequency switching circuit. The high frequency switching circuit may be for DC-DC conversion, frequency conversion or current control. This type of power supply control apparatus is also commonly referred to as a switched mode power supply or SMPS.

[003] Electronic ballast is an example of such power supply control apparatus. Typical electronic ballast comprises a high frequency switching circuit for converting a rectified output of the mains supply to a high frequency supply to drive a fluorescent lamp. Although a fluorescent lamp can be operated by alternating current (AC) of different waveforms, sinusoidal AC is known to give the best efficiency. Therefore, fluorescent lamps are usually connected to a switched power supply as being part of a resonant loading circuit.

[004] A fluorescent lamp may be considered as a single load resistor R_L having negative impedance characteristics. A typical resonant loading circuit comprises a resonance capacitor C_R in parallel connection with the fluorescent lamp, a current limiting inductor L_R in series connection with the power supply and the assembly comprising the fluorescent lamp and the resonance capacitor, a first blocking capacitor C_M in series connection with the assembly, and a second blocking capacitor C_CSL in connection with the assembly, the power supply and the reference ground as shown in Figure 1 . The resonant loading circuit is provided to enhance the AC sinusoidal characteristics of the current supply to the fluorescent lamp and to limit transient current. In use, the loading circuit comprising the fluorescent lamp is driven by a power inversion bridge which is operated by a ballast control circuit.

[005] The power inversion bridge comprises a first switching device and a second switching device connected in series and defines a switched power output of a power source at a terminal interconnecting the first and the second switching devices. The non-interconnected terminals of the first and second switching devices are connected to terminals such as a high potential terminal (or the bus terminal) and a low potential terminal (such as a reference ground) of the power source.

[006] The power source is usually a direct current supply which is a rectified output of the mains supply. The mains supply is typically at AC 1 10V or 220V. Power MOSFETs are probably the most widely used switching devices for operation of fluorescent lamps, although IGBT, bipolar transistors and other solid state semiconductor switching elements are also used.

[007] Current for operation of the fluorescent lamp is tapped from the output node which is between the first and the second switching devices through alternate switching of the first and the second switching devices controlled by a control circuit as depicted in Figure 1 . In the example depicted in Figure 1 , the first switching device MHS is also high side switch while the second switching device MLS is also referred to as the low side switch.

[008] The control circuit operates the first and second switching devices whereby an AC output voltage in the form of a square wave pulse train appears at the output node. As the first and the second switching devices are tied respectively to a high potential end and a low potential end of the rectified power supply, the output node will be pulled to a high potential when the first switching device is turned on and the second switching device is turned off. When the first switching device is turned off and the second switching device is turned on, the output node will be pulled to the low potential, which is usually at the reference ground of the control circuit. The situation when both the first and the second switching devices are turned on is undesirable and is to be avoided because such a situation will result in a high "shoot-through" current. The shoot through current is typically over 20A and the resulting voltage and current spikes can cause circuit damage as well as unacceptable EMI (electromagnetic interference).

[009] In order to prevent shooting through, the control circuit introduces a 'dead time' at the moment when one switching device is turned off and another switching device is to be turned on to mitigate the risk of simultaneous turning on of both the first and the second switching devices of the power inversion bridge. When a dead time is inserted, operation of the power inversion bridge can be divided into four output states, namely, HIGH, LOW, FALLING and RISING.

[0010] The HIGH state refers to the situation when the output node is tied to the bus line. The LOW state refers to the situation when the output node is tied to the reference ground. The FALLING state refers to the situation when the output node is disconnected from the bus line and to be connected to the reference ground. The RISING state refers to the situation when output node is disconnected from the reference ground and to be connected to the bus line. [001 1 ] When entering the FALLING state from the HIGH state, the output voltage at the output node will start falling since electrical charges are drawn by the resonant inductor L_REs from the output node to the load. If the dead time is shorter than the falling time, the low side switch MLS will be turned on before the output voltage falls to zero. If the dead time is too long, output voltage will fall to zero, stay at zero before the inductor's current cross zero ampere and rise again because the blocking capacitor C_M (normally at half bus line voltage) discharges to the output node via the inductor. Low side switch will also be switched on when output voltage is not zero. The situation is similar when the half bridge is in the RISING state.

[0012] The duration of falling time, staying time and rising time depends on a number of factors such as the bus line voltage, the inductor current and inductance, total capacitance at the output node, including resonant capacitor C_REs and blocking capacitor C_M and parameters like ambient temperature that affect the electrical characteristics of the circuit components. Hence the required dead time is not constant and an adaptive circuit is required to detect the rising time and falling time in order to feature zero-voltage switching operation.

[0013] The present disclosure will be explained by way of example with reference to the accompanying Figures, in which:-

[0014] Figure 1 is a simplified block diagram depicting a fluorescent lamp connected to AC mains via an electronic ballast.

[0015] Figure 2 is a schematic block and circuit diagram depicting a lighting apparatus comprising a fluorescent lamp and an example electronic ballast comprising an example ballast control circuit,

[0016] Figure 3 is an enlarged schematic diagram showing the low side driver of the ballast control circuit of Figure 2,

[0017] Figure 4 is an enlarged schematic diagram showing the high side driver of the ballast control circuit of Figure 2,

[0018] Figure 5 is a state diagram depicting an example operation of the low side driver of Figure 3,

[0019] Figure 6 is a state diagram depicting an example operation of the high side driver of Figure 4, [0020] Figure 7 is a diagram showing example operating waveforms of the ballast control circuit of Figure 2,

[0021 ] Figure 7 A is an enlarged view of a portion of Figure 7 showing corresponding waveforms when the high side switch is to be turned on (V_out rising to bus line voltage), and

[0022] Figure 7B is an enlarged view of a portion of Figure 7 showing corresponding waveforms when the high side switch is to be turned on (V_out falling to reference ground).

[0023] An electronic ballast is commonly used to drive a power supply arrangement such as a bridge-type or a half bridge-type power switching arrangement to generate an output of a substantially higher frequency than that of the source power supply. A typical bridge-type or a half bridge-type power switching arrangement comprises a high side switching device and a low side switching device which are connected in series, and an output node is provided at the interconnection of the high side and low side switching devices. The switching devices are so- named because the high side switching device is usually connected to the high potential side of a power supply rail while the low side switching device is usually connected to the low potential side of the power supply rail. In operation, the output of power supply arrangement will swing periodically between a voltage maximum which is equal or close to the maximum supply rail voltage and a voltage minimum which is equal or close to the supply rail voltage maximum. The periodic voltage swinging is typically by alternately turning on the high side switching and the low side switching device while the other one of the switching device is off. The periodic voltage swinging is typically by alternately turning on the high side switching and the low side switching device while the other one of the switching device is off. While electronic ballasts are widely used to operate fluorescent lamps, they are also useful for devices, apparatus or appliances that require a power supply.

[0024] A ballast control circuit comprising a first switching node, a second switching node, a detection node, and a decision circuit is disclosed herein. The decision circuit is to monitor voltage (or more specifically voltage variation) at the detection node and to toggle the first switching node from a turn off state to a turn on state upon detection of an event corresponding to an end of voltage rising at the detection node during run mode or steady state operation and when the second switching node is at a turn off state.

[0025] An electronic ballast having a decision circuit to monitor voltage at a detection node and to activate a first switching node upon detection of an end of voltage rising at the detection node is useful to operate the switching devices of a switching mode power supply to achieve zero voltage switching (ZVS) or near ZVS. For example, the detection node can be used to monitor voltage, for example, voltage rising, at the output terminal of the high side switching device. The end of voltage rising at that output terminal would mean that the voltage at that output terminal of the high side switching device has reached the maximum voltage close to the supply rail voltage maximum suitable for switching on the high side switching device whereby the output node is conductively connected to the high potential power supply rail by the high side switching device. The voltage rising before the high side switching device is conductive ca, for example, be due to discharge of a resonant load such as a fluorescent lamp during steady or run mode operation.

[0026] For example, the ballast control circuit may comprise a switching control circuit which is to toggle the first switching node from a turn off state to a turn on state upon receipt of the end- of-voltage-rising trigger signal from the decision circuit while the low side switching device is at an off state.

[0027] The decision circuit may comprise a detection circuit to detect a rise of voltage relative to the detection node and to general an end-of-voltage-rising trigger signal to the switching control circuit to activate the first switching node upon detection of a rise of voltage relative to that of the detection node as an event corresponding to an end of voltage rising at the detection node.

[0028] The decision circuit may monitor voltage, especially voltage variation, at the detection node and to generate an end-of-voltage-falling trigger signal to toggle the second switching node from a turn off state to a turn on state upon receipt of the end-of-voltage-falling trigger signal during run mode or steady state operation and when the first switching node is at an off state.

[0029] For example, the ballast control circuit may comprise a switching control circuit which is to toggle the second switching node from a turn off state (or 'off state' in short') to a turn on state (or 'on state' in short) upon receipt of the end-of-voltage-falling trigger signal from the decision circuit while the high side switching device is at an off state.

[0030] To facilitate ZVS or near ZVS switching at the low side switching device, the detection node can be used to monitor voltage, especially voltage falling, at the output terminal of the low side switching device. In an application, the end of voltage falling at the output terminal would mean that the voltage at the output terminal of the low side switching device has reached the minimum voltage close to the supply rail voltage minimum suitable for switching on the low side switching device whereby the output node is conductively connected to the low potential power supply rail (which is usually a reference ground) by the low side switching device. The voltage falling before the low side switching device is conductive can, for example, be due to discharge of a resonant load such as a fluorescent lamp during steady mode or run mode operation.

[0031 ] The ballast control circuit would usual operate with a train of clock pulses which defines a ballast switching frequency. In an example, the decision circuit and the switching control circuit are to toggle a switching node from the turn on state to the turn off state upon detection of an edge transition of a clock pulse, and to alternately set the first switching node and the second switching node to the turn on state when both the first switching node and the second switching node are set at the turn off state.

[0032] As the voltage variation (that is, voltage rising and voltage falling) associated with typical resonant loads usually complete in about 100ns-200ns, this voltage variation time, such as the voltage rising time Τι and voltage falling time τ₂, is comparable to the edge transition time of a clock pulse of the ballast switching clock, the end-of-voltage variation detection schemes disclosed herein is highly advantageous to mitigate problems associated with conventional ballast controls, since the voltage difference between the high and low potential power supply rails is usually several hundred volts, for example, 200 to 400 V.

[0033] in an example, the ballast control circuit comprising a first switching node for sending a switching signal to operate a first semiconductor switching device, a second switching node for sending a switching signal to operate a second semiconductor switching device, a detection node, a decision circuit to determine voltage variation at the detection node, and a switching control circuit to send switching signals to the first switching node and second switching node to respectively operate the first semiconductor switching device and the second semiconductor switching device during steady state or run mode operation; wherein the switching control circuit is to generate and send a turn on signal to the first switching node or to generate and send a turn on signal to the second switching node when both the first and second switching nodes are at a turning off state and upon detection of a condition corresponding to a completion in voltage rising or a completion in voltage falling at the detection node.

[0034] The turn on signals are useful to facilitate ZVS (zero voltage switching) because the end of voltage rising at the detection node would signify that the voltage at the detection node has reached its maximum voltage ready for turning on of the high side switch. It will be appreciated that the voltage difference across the conductive terminals of the high side switch is minimum when the detection node has reached its maximum voltage. Likewise, the end of voltage falling at the detection node would signify that the voltage at the detection node has reached its voltage minimum ready for turning on of the low side switch. The voltage difference across the conductive terminals of the low side switch is the minimum when the detection node has reached its minimum voltage or reference ground voltage.

[0035] An electronic ballast comprising a power supply arrangement such as any of the ballast control circuits disclosed herein is also disclosed.

[0036] A lighting apparatus depicted in Figures 1 to 4 comprises a fluorescent lamp 10 and an electronic ballast 100 for driving the fluorescent lamp 10. The electronic ballast 100 is for controlling overall operation of the fluorescent lamp 10 and comprises a half bridge 110 and a ballast control circuit 120 to drive the half bridge 110.

[0037] The half bridge 110 is adapted for connection to a power supply 102 and comprises a first semiconductor switch MHS, a second semiconductor switch MLS that is in series with the first semiconductor switch and an output node 'OUT in common connection with the first and second semiconductor switches. The power supply 102 is a rectified output of the mains supply and has a characteristic supply voltage of V_pp. Since the power to operate the half-bridge is a direct current (DC) power source, the semiconductor switch that is connected to the high potential side of the power supply will be referred to as a 'high side switch' and that connected to the low potential side will be referred to a 'low side switch'.

[0038] The ballast control circuit 120 comprises switching control circuits and decision circuits. The switching control circuits are to drive the half bridge 110 whereby the high side switch and the low side switch of the half bridge are turned on alternately during steady state operation such that when one switch is turned on, the other switch will be turned off and vice versa. The decision circuits are to operate the switching control circuits such that only one of the two switches will be conducting at the same time during steady state operation and to mitigate the adverse condition wherein both the high side switch and the low side switch are conducting.

[0039] As a result of steady state switching operations by the ballast control circuit 120, the voltage at the output node OUT of the half bridge 110 will swing between the supply voltage and the reference ground at a frequency suitable for optimally driving the fluorescent lamp into rated or normal luminescence. When the fluorescent lamp is generating the rated or normal luminescence, the ballast control circuit 120 is said to be in a steady state operation or in 'run mode'. [0040] To facilitate switching operations to produce the voltage swing, the switching control circuit is required to generate high frequency switching signals to operate the half bridge whereby the lower frequency voltage supply voltage V_pp of the power supply 102 is converted into an output voltage of a substantially higher frequency V_out.

[0041 ] An example frequency range suitable for optimal steady state operation of a fluorescent lamp is between 20 kHz to 50 kHz, although a range of between 10 kHz to 100 kHz is also used. The terms 'High frequency' or 'higher frequency' in the present context means a frequency in the range of 10 kHz to 100 kHz, as in contrast to the low or lower frequency of the mains supply at 50 Hz or 60 Hz. Of course, the optimal frequency to operate a fluorescent lamp may change from time to time or according to update of specifications of such lamps without loss of generality. It shall be appreciated that the electronic ballast described herein may be used to operate other types of lighting apparatus such as LED lamps or halogen lamps without loss of generality.

[0042] The example half bridge 110 comprises a first semiconductor switch 112 (MHS) and a second semiconductor switch 114 (MLS) which are connected in series across the DC power supply 102 which is a rectified output of the AC mains supply. An output node OUT 116 is provided at an interconnection or junction between the first and the second semiconductor switches.

[0043] The half bridge is to operate to convert the power supply 102 from a low frequency input to a high frequency output by switching operation such that the voltage at the output node swings between a high voltage output level and a low voltage output level at that switching frequency. This frequency conversion is achieved by alternately turning on the first semiconductor switching device on when the second semiconductor switching device is turned off, and turning on the second semiconductor switching device while the first semiconductor switching device is turned off, at the switching frequency.

[0044] Each of the semiconductor switches 112 and 114 is a three terminal device having a control terminal that controls the impedance between the other two terminals during operation such that the impedance between that other two terminals is extremely low or negligible when the control terminal is at an "on" state, and that the impedance between that other two terminals is extremely high or non-conductive when the control terminal is at an "off" state. As the other two terminals are adapted for current conduction, they are also referred to as 'conduction' or 'conductive' terminals of a semiconductor switch herein. [0045] When the first semiconductor switch is turned on and the second semiconductor switch is turned off, the output node will be at a first voltage which is the voltage of the power supply terminal tied to the first semiconductor switch. On the other hand, when the first semiconductor switch is turned off and the second semiconductor switch is turned on, the output node will be at a second voltage which is the voltage of the power supply terminal tied to the second semiconductor switch. By switching the half bridge alternately between these two switching states, the output voltage at the output node will swing between the first voltage and the second voltage at the switching frequency and the high frequency voltage thus generated at the output node will appear as a train of square or rectangular voltage pulses.

[0046] While power MOSFETs are probably the most commonly widely semiconductor switching devices for electronic ballasts, IGBT (insulated gate bipolar transistor) and bipolar transistors are also commonly used.

[0047] It is desirable that the situation that two semiconductor switches are turned on at the same time is to be avoided to alleviate high in-rush currents since such the in-rushed current can be as high as 20A, if not higher.

[0048] In order that the fluorescent lamp is to operate with a sinusoidal AC current waveform to achieve good efficiency and a long life span, the fluorescent lamp forms part of a resonant loading circuit comprising a resonant inductor L_R which is connected in series with a parallel connection of the fluorescent lamp and a resonant capacitor C_R and a pair of capacitors C_M & CSL- This loading circuit will produce a sinusoidal current waveform at the fluorescent lamp when a train of stepped or square voltage pulses is applied at the output node 1 16.

The ballast control circuit 120

[0049] The ballast control circuit 120 of Figures 2 to 4 comprises detection circuits, switching circuits and switching control circuits. The switching circuits are adapted to operate the high side switch and the low side switch and comprise a high side switching circuit for switching the high side switch and a low side switching circuit for switching the low side switch, although both the low and high side switching circuits are controlled by the low side switching circuit. The low side switching circuit includes an oscillator such as a voltage controlled oscillator (VCO) to generate high frequency switching signals such as a train of high frequency pulses to convert a low frequency power supply to a high frequency power supply to appear at the OUT node.

[0050] The detection circuit is to detect the state of operation of the half-bridge and to switch on one of the two semiconductor switches of the half bridge when the other one of the two semiconductor switches is in the off (non-conducting) state and at a time when the voltage across the conductive terminals of the semiconductor switch to be turned on is at zero or near- zero to achieve what is commonly known as 'zero voltage switching' (ZVS). For the avoidance of doubt, ZVS means switching at a voltage at or near zero voltage but not necessarily only zero voltage.

[0051 ] In order to achieve ZVS on the side of the half bridge to be turned on, the detection circuit is to monitor the OUT node and to identity a moment when zero voltage or a near-zero voltage condition occurs on that side of the half bridge such that the semiconductor switch will be ready to turn on.

[0052] In an example depicted herein, the detection circuits are to monitor the voltage at the OUT node and to trigger the switching circuits to activate the semiconductor switch which is waiting to be turned on next when the voltage at the OUT node just stops rising or just stop falling.

[0053] The detection circuits include a high side detection circuit for detecting end of falling at the OUT node and a low side detection circuit for detecting end of rising at the OUT node. As voltage falling will begin at the OUT node at the time when the high side switched is turned from on to off, detecting the end of voltage falling would signify that the voltage at the OUT node has reached a voltage ready for the low side switch to be turned on. Likewise, voltage rise will begin at the OUT node at the time when the low side switched is turned from on to off, detecting the end of voltage rising would signify that the voltage at the OUT node has reached a voltage ready for the high side switch to be turned on. The switching control circuits are adapted to operate the high side switch and low side switch upon receipt of control signals from the detection circuits.

[0054] The ballast control circuit 120 is implemented in the form of an integrated circuit (IC) with multi-chip package to drive a half bridge comprising two 600V power MOSFETs MLS, MHS, as semiconductor switching elements. The ballast control circuit 120 is fabricated in 18V CMOS technology and comprises two driver circuits, namely, a high side driver 130 and a low side driver 140. The high side driver includes a high side control node GH for controlling the switching of the high side switch MHS and the low side driver includes a low side control node GL for controlling the switching of the low side switch MLS. The OUT node of the ballast control circuit 120 is an interface pin connection of the IC to facilitate sensing and monitoring of the instantaneous voltage at the half bridge output node OUT and the input node of the resonant loading circuit comprising the fluorescent lamp. Low ssde dri e

[0055] The low side driver as depicted in Figures 2 and 3 is adapted to provide switching or switching control signals at node GL to operate the low side switch MLS of the half bridge as well as the overall operation of the electronic ballast.

[0056] The low side driver comprises a voltage control oscillator (VCO) U12 which is to generate a train of clock pulses CLK at a clock frequency selectable between 10 kHz and 100 kHz. The VCO U12 includes a pin node RT in connection with an external resistor R3 and a pin node CPH in connection with an external capacitor C2.

[0057] Two sets of fall and rise detectors and a buffer U9 are connected to the CLK line or clock output of the VCO. The first set of fall and rise detectors comprises a low side fall detect circuit U5 and a low side rise detect circuit U6. The second set of fall and rise detectors comprises a high side fall detect circuit U8 and a high side rise detect circuit U10. Each one of the fall detect circuits U5, U8 is adapted to transmit a pulse when triggered by a falling voltage. Each one of the rise detect circuits U6, U10 is adapted to transmit a pulse when triggered by a rising voltage. Pin node CL is connected to the CLK line via a series connection of a resistor RP1 and the buffer U9, with the buffer connected intermediate the resistor RP1 and the CLK line.

[0058] The low side driver comprises a high side control portion and a low side control portion. The high side control portion is to provide control signals to the high side driver to facilitate high side switching by the high side driver and comprises a rise detect U10, a fall detect U8, a series connection of resistor RP1 and buffer U9, and an inverter half bridge comprising semiconductor switches MP1 and MN1. MP1 and MN1 are MOSFET semiconductor switches connected in series to form a half bridge or an inverter half bridge. The interconnection node between MP1 and MN1 is connected to pin node CL. Pin node CL is connected to pin node CH of the high side driver by capacitor Cx. Pin node CL is also connected to the CLK line via the series connection of resistor RP1 and buffer U9. Pin node CL is an interfacing node between the high side driver and the low side driver and is also referred to as an interfacing node herein.

[0059] The control terminal of MOSFET MP1 is connected to the output of the high side rise detect circuit U10 such that the turning on and off of MP1 is determined by the high side rise detect circuit U10. This control terminal is the gate terminal of MP1 while the drain and source are the conductive terminals. The conductive terminal of MP1 which is in interconnection with MN1 is connected to the circuit supply node Vcc such that the voltage at the interconnection node between MP1 and MN1 will be pulled to V_cc when MP1 is on while MN1 is off. The conductive terminal of MN1 which is not in interconnection with MP1 is connected to the reference ground such that the voltage at the interconnection node between MP1 and MN1 will be pulled to the reference ground when MP1 is off while MN1 is on. The voltage at node VCC is clamped at 16V by a Zener diode DZ1. A diode D2 is forwardly connected from node CL to node VCC, and another diode D1 is reversely connected from node CL to the reference ground of the low side driver.

[0060] During steady state operation, high side rise detect circuit U10 will generate a triggering pulse and turn on MP1 upon detection of an upward transition at the CLK line from Low to High, thereby pulling node CL up to a voltage very close to Vcc. On the other hand, the high side fall detect circuit U9 will generate a triggering pulse to turn on MN1 upon detection of a downward transition at the CLK line from High to Low, thereby pulling node CL down to a voltage very close to the reference ground of the low side driver.

[0061 ] The low side control portion comprises a rise detect U6, a fall detect U5, a latch U3 connected to outputs of U5 and U6, and a buffer U2 connected to the output of latch U3 whereby the output of the latch is amplified when reaching node GL for driving MLS. Nodes blank 1 and blank 2 of U6 are connected respectively to the CLK line and the output node of rise detect circuit U10. An input node of the rise detect U6 is connected to node CL to monitor voltage variations at node CL.

[0062] With the above connections, the low side rise detect circuit U6 will generate a trigger signal upon detection of a rising voltage at node CL when there is no blanking signal applied. The rise detect circuit U6's output is blanked out when the CLK line is low or rise detect circuit U10's output is low. The triggering signals will operate to turn on MLS to be explained.

[0063] The low side fall detect circuit U5 is adapted to generate a trigger signal to turn off the low side switch when a falling voltage signifying a transition of the CLK pulse from High to Low is detected.

[0064] During steady state operation, the low side fall detect circuit U5 will transmit a triggering pulse FD to the latch U3 upon detection of a downward transition at the CLK line from High to Low, and the latch U3 will turn off MLS upon receipt of the FD triggering pulse. On the other hand, the low side rise detect circuit U6 will transmit a triggering pulse RD to the latch U3 upon detection of an upward transition of voltage on occurrence of the event mentioned above. [0065] The high side driver as depicted in Figures 2 and 4 comprises a toggle flip flop U14 which is connected to the high side control node GH via a buffer U13. An input node of the toggle flip flop U14 is connected to node CH via a buffer U17. Node CH is connected to node VB via a diode D4 which is forwardly connected from node CH to node VB. Node OUT is connected to node CH by means of a diode D3 which is forwardly connected from node OUT to node CH. Node VB is connected to another input node R2 of the toggle flip flop U14 via a comparator U19, with a voltage offset source V3 connected in series between node VB and the negative input terminal of comparator U19. The positive input terminal of U19 is connected to node CH. Node VB is connected to a negative input terminal of voltage comparator U18 and the output of the voltage comparator U18 is connected to yet another input node R3 of the toggle flip flop U14. The positive terminal of the voltage comparator U18 is connected to a voltage source V2. The voltage offset due to V2 is set to 12V in this circuit example. The output node of toggle flip flop U14 is connected to node CH via a series connection of an inverter U16 and resistor RP2, with RP2 intermediate node CH and U16. The output node of toggle flip flop U14 is also connected to yet another input node R1 of U14 via a 'Max on-time' device. The reference ground of the high side driver is at the OUT node which means that the reference ground of the high side drive follows the voltage of the OUT node.

[0066] The high side driver is adapted to provide switching signals to the high side control node GH to drive the high side switch MHS.

odes of o eration

[0067] The electronic ballast operates in various modes such as the under-voltage lockout ('UVLO') mode, the pre-heat mode and the run mode as depicted in Figures 5 and 6.

UVLO m de

[0068] During power-on, power-off or power fault at the bus line voltage VPP, the electronic ballast will enter the under-voltage lockout (UVLO) mode when the circuit supply voltage V_cc is lower than the turn-off threshold, which is 10V for the present example. The input and output pins RT, CPH, GL and CL are pulled to reference ground V_Ss in this mode. The overall current consumption is less than 50uA. In normal case, the start-up resistor R1 will pull up the supply voltage V_Cc- Once the supply voltage has reached the turn-on threshold, which is 12V for this example, the electronic ballast will move into the preheat mode. When this happens, the electronic ballast has sufficient voltage to drive the MOSFET MLS and implement other essential functions. The circuit supply voltage V_Cc is clamped at 16V by the shunt regulator which comprises a Zener diode DZ1. [0069] In the preheat mode, pin RT is first regulated to 5V and a preheat current l_PH (1 uA) is supplied to pin CPH of U12. The preheat frequency f_PH and running frequency f UN are determined by resistor R3 which is connected to pin RT. The preheat duration t_PH is determined by the capacitor C2 which is connected to pin CPH as follows:

worn

t_PH = - x 2.SV

[0070] When VCO U12 starts oscillation, node CL and low side switch MLS will start switching. However, there is not yet a switched voltage output at node OUT since the high side switch MHS is still off. During the preheat mode, OUT is pulled to reference ground by low side switch MLS. The high side supply voltage V_B of the high side driver is pulled up by high side start-up resistor R₂ and the connection capacitor C_X. In some implementations, the high side start-up resistor R₂ can be disconnected and the high side supply voltage can totally reply on the switching capacitor C_X for rising to the turn-on threshold (12V).

Bun mode or steady ste e o e tio mode

[0071 ] Once the high side driver enters into the run mode, the half bridge will start voltage switching to bring about voltage swinging. As a result, the OUT node will oscillate between the bus line voltage Vpp and the reference ground, and capacitive charge-pumps will operate at maximum power. The capacitive charge pumps of this electronic ballast are such that the high side driver and the low side driver are operated primarily on energy coming from the charge- pumps. For example, charges are pumped to the low side reservoir capacitor C1 during output rising and to the high side reservoir capacitor C3 during output falling. C1 and C3 are of the magnitude of about 100nF in this circuit example.

[0072] Figures 5 and 6 are state diagrams depicting the operation of the high side and low side drivers. The average charging current ICHRG is mainly determined by switching frequency, C_X capacitance and bus line voltage V_PP as follows:

1 CHRG ^¾ fsw^xVpp [0073] The average charging current is set to larger than the operating current of the low side driver. The conversion efficiency (from bus line to reservoirs) of the charge-pump depends on a number of factors and can be set to over 90%. The key point is to limit the output rising and falling slope to minimize losses by the equivalent series resistors in connection with C_X, C_SL, C_R and C_M.

[0074] The rising and falling slope of the OUT node is mainly determined by C_X, C_SL, inductor L_R and bus line voltage. C_X is mainly used to set the charging current. C_SL is added to adjust the overall rising and falling rate for better EMI performance. As Cx is to operate to facilitate nanosecond pulse or transition times, Cx is in the hundred pF region and is set to be 100pF in this circuit example since the pulse and transition times are in the region of 100ns.

[0075] The detection circuits are to detect end of voltage rising or end of voltage falling at the output node 1 16 and to send a switching signal to the switching control circuits during 'steady state' or 'run mode' operation. The switching circuits are to generate a train of high frequency switching pulses to drive the half bridge whereby a high frequency power output is generated from the low frequency power available from the mains or other supply. The switching pulses typically comprise on- and off- pulses of an equal period. The switching control circuit will turn on the first semiconductor switch or the second semiconductor according to whether it is the end of voltage rising or voltage falling at the output node 1 16.

[0076] During steady state operation of the fluorescent lamp when the fluorescent lamp is switched on and driven by a train of high frequency voltage pulse at the output node 1 16 to give rated or near rated luminance, the electronic ballast will be in the 'Run Mode', and the first and second semiconductor switching devices will repeatedly go through the switching cycle below until the fluorescent lamp is turned off:

Table 1

[0077] In this example arrangement, the first semiconductor switching device MHS is also referred to as the 'high side switch' as it is connected to the bus line at a bus voltage of V_pp and the second semiconductor switching device MLS is also referred to as the 'low side switch' as it is connected to the reference ground or zero voltage bus. A complete switching cycle of the half bridge comprises the sequential switching states 1 to 4 above and example operation of the half bridge in the Run Mode will be described below.

[0078] In this example arrangement, the first semiconductor switching device MHS is also referred to as the 'high side switch' as it is connected to the bus line at a bus voltage of V_pp and the second semiconductor switching device MLS is also referred to as the 'low side switch' as it is connected to the reference ground or zero voltage bus. A complete switching cycle of the half bridge comprises the sequential switching states 1 to 4 above and example operation of the half bridge in the Run Mode will be described below.

[0079] When the half bridge is at switching state 1 , MHS is on, MLS is off, and the voltage at the output node OUT 116 is at bus voltage V_pp.

[0080] When the half bridge is at switching state 3, MHS is off, MLS is on, and the voltage at the output node 1 16 is at the zero voltage or a reference ground potential Vss.

[0081 ] When the half bridge is to transition from state 1 to state 3, the half bridge will first enter state 2 when both MHS and MLS are off to avoid turning on of MLS while MHS is still on. When the half bridge transitions from state 1 to state 3, the output voltage at node 116 will gradually fall from the bus voltage V_pp to the reference ground potential V_ss due to reluctance of the resonant loading circuit. The duration of state 2 is referred to as a 'dead time' and is identified as 'dead time 1 ' or 'falling dead time' herein.

[0082] Likewise, when the half bridge is to transition from state 3 to state 1 , the half bridge will first enter state 4 when both MHS and MLS are off to avoid turning on of MHS while MLS is still on. When the half bridge transitions from state 3 to state 1 , the output voltage at node 116 will gradually rise from the ground potential V_ss to the bus voltage V_pp, also due to reluctance of the resonant loading circuit. The duration of state 4 is also a 'dead time' and is identified as 'dead time 2' or 'rising dead time' herein.

[0083] The voltage conditions at the several pin nodes at the non-transition states are set out below.

SI ates

1 2 (fallinq) 3 4 (risinq)

MHS ON OFF OFF OFF MLS OFF OFF ON OFF

CLK Lo Lo to Hi Hi Hi to Lo

VcL Lo Hi

Table 2

[0084] While insertion of dead times will mitigate current shoot through due to simultaneous turning on of MHS and MLS, an accurate control of the dead time is desirable for the following reasons.

[0085] For example, if dead time 1 is shorter than the actual falling time of the voltage at the output node 116 after the high side switch is turned off, the low side switch will be turned on before the output voltage has fallen to zero. On the other hand, if the dead time is too long, the output voltage may have crossed zero and rise again due to discharge by the blocking capacitor C_M via the inductor L_res, and the rise can be up to half the bus voltage V_pp.

[0086] The situation on dead time 2 is similar.

[0087] While accurate dead time control is desirable, it is noted that the actual circuit falling time, staying time and rising time are variable and depend on a number of factors including bus line voltage, inductor's current and inductance, total capacitance at the output node, including capacitive values of the resonant capacitor C_REs and the blocking capacitor C_M, as well as other parameters such as ambient temperature that may affect performance characteristics of the circuit components.

[0088] Another factor that has complicated dead time insertion is the non-symmetric rising time and falling time at the output node 116.

[0089] The example high frequency switching circuit of the electronic ballast comprises a voltage controlled oscillator (VCO) which generates a train of clock pulses CLK for turning on and turning off the semiconductor switching devices of the half bridge whereby a lower frequency power supply available at the input of the half bridge is converted into a higher frequency power supply adapted for fluorescent lamp operation. Each clock pulse is usually either at a high logic level (High) or at a low logic level (Low).

[0090] In this example, the switching control circuit is adapted such that the high side switch will be at the off state when the clock pulse is at a High state and the low side switch will be at the off state when the clock pulse is at a Low state. To mitigate the situation when both the high side and side switches are conductive at the same time, the switching control circuit is arranged such that: i) the high side switch will be turned off when the clock pulse transitions from Low to High, such that the high side switch is off when CLK is at High, but the low side switch will be turned on only when the voltage at the output node has stopped falling, and ii) the low side switch will be turned off when the clock pulse transitions from Low to High, such that the low side switch is off when CLK is at Low, and the high side switch will be turned on only when the voltage at the output node has stopped rising.

[0091 ] An implementation example of the above switching control will be explained with reference to the ballast of Figures 2 to 4 in its run mode as follows:

State 1 ( igh ssdo "OFT\ tow s de "OFF")

[0092] When the half bridge is at state 1 , the high side switch is on and conducting, the low side switch is off, the clock signal CLK is at Low, the voltage V_out at node OUT is pulled to V_pp (or more exactly V_pp - V_on, where V_on is the voltage drop due to the on-resistance of MHS), the voltage V_CL at node CL is pulled to the reference ground V_Ss of the low side driver by the Lo CLK signal through resistor RP1 and buffer U9, V_B is at V_PP+16V, and the voltage V_CH at node CH is pulled to V_out by resistor RP2 and inverter U16.

Stats 1 to state 2 (iurn mg hig h skle from "ON" to ^!iOFF"

[0093] When the half bridge is at state 1 and the clock signal CLK changes from 'Low' to 'High', the half bridge will transition from state 1 to state 2 in which both the high side switch and the low side switch are turned off.

[0094] Upon detection of a rise in the CLK signal from Low to High, the rise detect circuit U10 will send a short turn-on pulse to turn on the semiconductor switching device M P1 for a short duration. The turn-on pulse is for example of the magnitude of 100ns and MP1 will only be turned on for such a short while. As a result, the voltage at node CL will be pulled by MP1 and rise to V_cc (since the voltage maximum at node CL is clamped by the circuit supply voltage V_cc), and node CH will follow the voltage of node CL and rise due to the capacitance of the capacitor C_X. The voltage rising at node CH also sends a toggling pulse of a short duration to the toggle flip flop U14 via the buffer U17 to turn off the high side switch MHS to enter state 2 when both MLS and MHS are off.

State (h igh ssd OFF, t w s de OFF, low side to e tornod on oext) [0095] At state 2, both the high side switch and the low side switch are off. At the beginning of state 2, the voltage at the OUT node will be at V_pp (or more exactly Vp_P-V_on),the voltage at node VB is Vp_P+16V, the voltage at node CH is at V_PP+16V; the voltage at node CL will be at V_cc. Example values for reference are V_pp = 300V, V_CC=16V, V_on ~ 0.2V and the toggling pulse has a duration of about 100ns, where MP1 & MP2 are MOSFET switches.

State 2 to state 3 fde eel volt ge faf f ing at OUT aad turn on low side a s d of faf f ing)

[0096] When the half bridge has entered into state 2, OUT node will be in a floating state, since it is isolated from the supply bus V_pp by the high side switch and isolated from V_ss by the low side switch. After entry into state 2, the voltage V_out at the out node will begin to fall from V_pp, and the voltage falling rate will depend on the circuit characteristics of the resonant loading circuit.

[0097] When V_out falls, V_B will follow V_out to fall due to capacitive coupling by C₃, V_CH will follow V_B to fall due to diode D4, and V_CL will follow V_CH to fall due to capacitive coupling by C_x. As the voltage V_CL at node CL is clamped not lower than Vss-V_di₀de, V_CL will fall from V_Cc to Vss-V_di₀de (which is approximately -0.6V) in the time when V_out falls from V_pp of about 300V to about 284V, and then V_CL will stay at the voltage minima of V_Ss-V_di_0de due to the built-in diode D1 of the MOSFET MN1 . While the voltage at node OUT is falling, the voltage at node CH is also falling and the capacitor C_x will draw current from node CL. The voltage at node OUT will be clamped not lower than Vss-V_diode where V_diode is the body diode of the lower side switch MLS. Once the voltage at node OUT stops falling, the capacitor C_x will no longer draw current from node CL and the voltage at node CL will begin to rise due to pulling up by Hi CLK line by resistor RP1 and buffer U9.

[0098] The voltage rise at node CL upon detection by the rise detect device U5 will send a trigger pulse to toggle the toggle flip flop U3 to turn on MLS. As V_out is close to 0V at this point, low side ZVS is achieved. An example of the relevant voltage waveforms during this voltage falling transition is depicted in Figures 7 and 7B.

State 3 (a f g skle OFF, f e side ON)

[0099] When the half bridge is at state 3, the CLK line is at High, the low side switch is on, the high side switch is off, and the output node OUT is pulled down to the reference ground V_ss. At this state, node CL is pulled up by resistor RP1 and buffer U9 to VCC, and node CH is pulled up to V_B by resistor RP2 and inverter U16. Stats 3 o state 4 { low side from "ON" o "OFF")

[00100] When the CLK pulse makes transition from High to Low while in state 3, falling edge detector U5 upon detection of this High-to-Low transition will turn off the low side switch and the half bridge will enter state 4 in which MHS is off and M LS is off.

State 4 ( sg side OFF, low side OFF, ig side to bo turned oo next)

[00101] When the half bridge enters state 4, OUT node will be isolated from V_pp by the high side switch and isolated from V_ss by the low side switch. When this occurs, OUT node will be in a floating state and its voltage will depend on the voltage of the resonant loading circuit. At the beginning of state 4, the voltage V_out at the out node is at the reference ground V_ss, node CL is pulled to reference ground by resistor RP1 via buffer U9 and MOSFET MN1 , and node CH is pulled to its reference ground on the high side driver by C_X when C_L is pulled to its reference ground on the low side driver.

State 4 to state 1 Cdeteel voitaae risina at OUT and turn on Μ aide at and at risi ng)

[00102] After the half bridge has entered into State 4, the voltage V_out at the OUT node will begin to rise due to current flowing out of the resonant loading circuit and the voltage rising rate will be dependent on the circuit characteristics of the loading circuit. When the voltage at output node OUT rises, the voltage V_CH at output node CH will be at V_OUT -V_diode and also rise, where V_diode is due to diode forward voltage of D3. The voltage at node VB is always clamped at 16 V above V_out by Zener diode DZ2 since the OUT node is also the reference ground of the high side driver.

[00103] When the voltage at node OUT rises due to discharge of the resonant loading circuit, the voltage V_CH will rise due to diode D3, and the voltage V_CL at node CL will also rise due to capacitive coupling between node CH and node CL by the capacitor C_X. The voltage rise means that capacitor C_X will draw current from node CH, and this current comes from diode D3 and the series connection of RP2 and inverter U16. When V_out has reached V_Pp+V_diode (body diode of high side switch MHS), no more current can be drawn through D3, and node CH will be pulled towards V_B by the output node of the toggle flip flop U14 via RP2 and inverter U16. It will be noted that the voltage V_B is the high potential level while voltage V_out is the low potential level or reference ground of the high side driver. This further rise of voltage at node CH is a rise relative to the reference ground of the high side driver and will be detected by a rise detector U17 which is a threshold detector. The rise detector U17 upon detection of a voltage rise at node CH relative to the reference ground of node OUT will send a turn on signal to toggle U14 and turn on the high side switch. As the occurrence of voltage rise at U17 is at or close to V_pp, ZVS at the high side switch is also achieved. An example of the relevant voltage waveforms during this voltage rising transition is depicted in Figures 7 and 7A.

[00104] When V_out begin to rise from its lowest potential V_ss (more exactly V_ss + V_on) towards its highest potential V_pp (more exactly V_PP - V_on), the voltage at node CL will also rise due to capacitive coupling between node CH and node CL by capacitor C_x. As node CL is clamped to the supply voltage of the low side driver V_Cc by diode D2, and V_Cc is clamped by Zener diode DZ1 at 16V, the voltage at node CL will not rise further and stay at the clamped voltage of V_Cc + V_dio_de. During the time when V_out is rising while V_CL is clamped, a large portion (say 90%) of the current from C_x will be drained through diode D2 while a small portion (say 10%) of the current will drain through RP2 and the buffer U9. When the voltage at node CH stops rising after having reached its maximum, there is no more current available from C_x and the voltage at node CL will begin to fall due to current flowing from node CL into the buffer U9 via resistor RP1 .

[00105] The OUT node voltage fall time Τι and the OUT node voltage rising time τ₂ are very small compared to a period of the switching frequency. Therefore both Τι and τ₂ are in the region of nanoseconds, such as 100 ns to 200 ns in this example. In the description herein, "ON" and "on" are interchangeably used and a switch will be at the "ON" or "on" state when it is turned on. Likewise, "OFF" and "off" are interchangeably used and a switch will be at the "OFF" or "off" state when it is turned off without loss of generality.

[00106] In addition, over-current protection is also enabled whenever the half bridge starts switching. This function is implemented by a current detector U1 together with a current sense resistor RCS (0.8Ω). The current detector will react upon detection of an abnormal condition and flags errors. Whenever the low side switch is turned on, the detector will check if the voltage at CS pin node is higher than a threshold voltage VSC (1 V). If it is higher, it means the resonant inductor's current is higher than 1 .25A (1 V/RCS) and the detector will flag short-circuit fault. The IC will turn off the low side switch once short-circuit fault exist. At the end of each turn-on cycle, the detector will check if CS pin's voltage is lower than VOPEN (0.01 V) and higher than VOC (0.4V). The two results will be stored for 32 cycles. If they exist for over 32 cycles, the detector will flag the corresponding errors (open load and over-current). All these three error flags will not set the fault latch U4 in preheat mode and ignition mode. They will set the latch during run mode and the detector is not enabled in other non-switching modes (UVLO mode and fault mode).

[00107] While an electronic ballast has been described as an example herein, it should be appreciated that the ballast is only an example to illustrate the disclosure and should not be used to limit its scope. For example, while a CLK Hi corresponds to high side switch off and a CLK Lo corresponds to the low side switch off herein, the correspondence can be swapped or modified without loss of generality, although the specific circuit arrangement will be modified accordingly.

[00108]

Table of Numerals

Claims

A ballast control circuit comprising a first switching node, a second switching node, a detection node, and a decision circuit, wherein the decision circuit is to monitor voltage at the detection node and to toggle the first switching node from a turn off state to a turn on state upon detection of an event corresponding to an end of voltage rising at the detection node during run mode or steady state operation and when the second switching node is at a turn off state.

A ballast control circuit according to Claim 1 , wherein the ballast control circuit comprises a switching control circuit to toggle the first switching node from a turn off state to a turn on state upon receipt of an end-of-voltage-rising trigger signal, and the decision circuit is to generate an end-of-voltage-rising trigger signal to the switching control circuit upon detection of an event corresponding to an end of voltage rising at the detection node.

A ballast control circuit according to Claims 1 or 2, wherein the decision circuit is to toggle the second switching node from a turn off state to a turn on state upon detection of an event corresponding to an end of voltage falling at the detection node during run mode or steady state operation and when the first switching node is at a turn off state.

A ballast control circuit according to Claim 3, wherein the ballast control circuit comprises a switching control circuit to toggle the second switching node from a turn off state to a turn on state upon receipt of an end-of-voltage-falling trigger signal, and the decision circuit is to generate an end-of-voltage-falling trigger signal to the switching control circuit upon detection of an event corresponding to an end of voltage falling at the detection node.

A ballast control circuit according to any preceding Claims, wherein the ballast control circuit is to operate with a train of clock pulses which defines a ballast switching frequency; and wherein the decision circuit and the switching control circuit are to toggle a switching node from the turn on state to the turn off state upon detection of an edge transition of a clock pulse, and to alternately set the first switching node and the second switching node to the turn on state when both the first switching node and the second switching node are set at the turn off state.

6. A ballast control circuit according to any preceding Claims, wherein the detection node (OUT) is connected to a first input node (CH) of the decision circuit to facilitate voltage monitoring by the decision circuit, and the decision circuit is such that voltage at the first input node is to rise relative to the voltage at the detection node when the voltage at the detection node stops rising; and wherein the decision circuit is to generate the end-of- voltage-rising trigger signal upon detection of voltage rising at the first input node relative to the detection node.

7. A ballast control circuit according to Claim 6, wherein a one-way conductive device, such as a diode (D3), is connected from the detection node (OUT) to the first input node (CH) whereby voltage information at the detection node is forwarded to the decision circuit.

8. A ballast control circuit according to Claims 6 or 7, wherein the decision circuit is to detect a rise of voltage at the first input node (CH) relative to the voltage at the detection node as an event corresponding to the end of voltage rising at the detection node.

9. A ballast control circuit according to any of Claims 6 to 8, wherein the first input node (CH) of the decision circuit is connected to a first power supply node (VB) of the decision circuit by a one-way conductive device such as a diode (D4) which is forwardly conductive from the first input node (CH) to the first power supply node (VB), and the first power supply node (VB) is clamped at a first operating voltage (V_B) of the decision circuit; and wherein a capacitive charge pump (C3) is connected between the first input node (CH) and the first power supply node (VB).

10. A ballast control circuit according to Claim 9, wherein the capacitive charge pump (C3) is such that voltage at the first power supply node (VB) is at the first operating voltage above the voltage of the detection node when the voltage at the detection node begins to rise following setting of the second switching node into the turn off state by the switching control circuit when the first switching node is already at the off state.

1 1. A ballast control circuit according to any preceding Claims, wherein the ballast control circuit comprises an oscillator to generate the train of clock pulses and the decision circuit is to produce a turn off signal to set the first switching node at the turn off state in response to an edge transition of a clock pulse, and wherein the turn off signal in response to the edge transition of the clock pulse is transmitted to the first input node of the decision circuit by a first capacitive coupling.

12. A ballast control circuit according to any preceding Claims, wherein the detection node (OUT) is connected to a second input node (CL) of the decision circuit to facilitate monitoring of voltage falling at the detection node by the decision circuit, wherein the voltage at the second input node (CL) is to fall when the voltage at the detection node begins to fall but will begin to rise when the voltage at the detection node stops falling; and wherein the decision circuit is to generate the end-of-voltage-falling trigger signal upon detection of voltage rising at the second input node (CL).

13. A ballast control circuit according to Claim 12, wherein the decision circuit is to detect the rise of voltage after the initial voltage fall at the second input node (CL) as an event corresponding to the end of voltage falling at the detection node.

14. A ballast control circuit according to Claims 12 or 13, wherein the second input node (CL) is connected to the first input node (CH) and then to the detection node (OUT) whereby voltage falling at the detection node is monitored, the first input node and the second input node of the decision circuit being connected by a second capacitive coupling whereby voltage changing information at the detection node is coupled from the first input node to the second input node (CL) by said second capacitive coupling.

15. A ballast control circuit according to Claim 14, wherein said first capacitive coupling and said second capacitive coupling are by the same capacitor (C_x).

16. A ballast control circuit according to any of Claims 12 to 15, wherein the second input node (CL) of the decision circuit is connected to a second power supply node (VCC) of the decision circuit by a one-way conductive device such as a diode (D2) which is forwardly conductive from the second input node (CL) to the second power supply node (VCC), and the second power supply node (VCC) is clamped at a second operating voltage (V_cc) of the decision circuit; and wherein a capacitive charge pump (C1 ) is connected between the second input node (CL) and the second power supply node (VCC).

17. A ballast control circuit according to Claim 16, wherein the voltage at the input node (CL) of the decision circuit is pulled up to the second operating voltage (V_cc) when the first switching node is turned from the turn on state to the turn off state before the voltage at the second input node (CL) is to fall with the voltage of the detection node.

18. A ballast control circuit according to any preceding Claims, wherein the first and second switching nodes, the first and second input nodes of the decision circuitry, and the detection node are nodes of an integrated circuit such as a CMOS integrated circuit.

19. A ballast control circuit according to any of the preceding Claims, wherein the capacitive charge pumps (C1 ,C3) are discrete capacitors to provide operation power to the decision circuit and the switching control circuit.

20. An electronic ballast comprising a half bridge and a ballast control circuit according to any of the preceding Claims, the half bridge comprising a high side semiconductor switching device for connection to a high potential terminal of a power supply, a low side semiconductor switching device for connection to a low potential terminal of a power supply, and an output node at an interconnection between the high side semiconductor switching device and the low side semiconductor switching device; wherein the first switching node of the ballast control circuit is connected to a control terminal of the high side semiconductor switching device, the second switching node of the ballast control circuit is connected to a control terminal of the low side semiconductor switching device, and the detection node of the ballast control circuit is at the output node of the half bridge.