CN101061446A - Half bridge adaptive dead time circuit and method - Google Patents

Abstract

A high voltage offset detection circuit registers the voltage at the midpoint of a switching half-bridge and may determine when the midpoint voltage reaches a given value to avoid hard-switching in the half-bridge switches. The midpoint voltage of the switching half-bridge is applied through a buffer to a MOSFET that is current limited to produce a voltage that reflects the voltage of the midpoint of the switching half-bridge. The voltage produced by the MOSFET may be supplied to a comparator with a threshold input to obtain a signal that indicates when the switches of the switching half-bridge may be turned on to avoid hard-switching. An adaptive dead-time circuit and method may comprise the above sensing circuit, a first circuit for generating a first signal indicative of a high to low transition of the midpoint voltage; and an output circuit for generating an adaptive dead-time output signal based thereon. A second circuit may generate a second signal indicative of a low to high transition of the voltage; wherein the output circuit generates the adaptive dead-time output signal based on both the first and second signals. The second circuit preferably generates the second signal by reproducing the first signal. The first circuit may generate the first signal by charging a capacitor in response to pulses, and the second circuit may generate the second signal by charging a second capacitor corresponding to said first capacitor, and the adaptive dead-time output signal may be responsive to the charges on the first and second capacitors.

Description

Circuit and the method for half bridge adaptive idle time

The cross reference of related application is quoted

The sequence number that the application submits on February 19th, 2004 based on people such as inventor Iulia RUSU is 60/546361 U.S. Provisional Application (IR-2198 PROV), and requires the right of priority of above-mentioned application, by reference it is comprised in this application.It is 10/806688 U. S. application (IR-2461) that the application relates to sequence number that Dana WILHELM submits on March 23rd, 2004, also by reference it is comprised in this application.

Technical field

The present invention relates to a kind of Method and circuits that adapts to idle time realizes, it is specially adapted to half bridge driver integrated circuit (IC) such as IR-2161 halogen convertor control integrated circuit, it is 60/343236 U.S. Provisional Application (IR-2082 PROV) that this integrated circuit is described in the sequence number of submitting to Dec 31 calendar year 2001, the sequence number of submitting on July 22nd, 2002 is that 60/398298 U.S. Provisional Application (IR-2082 PROV II) and the sequence number submitted on May 21st, 2003 are in 10/443525 the U. S. application (IR-2082), by reference each application to be comprised in this application.

The invention still further relates to a kind of high voltage bias testing circuit, this circuit can combine with the bridge gate driver circuit, particularly in the monolithic integrated circuit solution.

Background technology

Self-oscillasion semi-bridge circuit based on bipolar power transistor or other switch power devices will be effectively in itself, because soft switch is always incited somebody to action by this system.These circuit are well-known, and therefore here will no longer illustrate.For the similar performance of realization in half-bridge circuit, independent oscillator drives low side and high-side driver in this circuit, soft switch is not intrinsic, so preferably is fixed to a value idle time, this value is corresponding with the switching time of half-bridge.Electric capacity and inductance and the load current in the output circuit depended in this variation.

The high voltage half bridge driver circuit uses in the electric ballast of various application such as motor driven, fluorescent light and power supply.Half-bridge circuit is used the transistor that a pair of totem-pole connects, and this is positioned on high-voltage direct-current (DC) power supply transistor.Fig. 1 is schematically shown and is basic half-bridge circuit.Transistor M1 is that power device (mos field effect transistor (MOSFET)) and their mid point are connected with M2, and node " A " is the output that connects load.Transistor M1 and M2 have the gate drive buffers (being respectively DRV1 and DRV2) of himself, and this driving impact damper provides appropriate signals to come conducting or "off" transistor M1 and M2.

In various application, know the mid point of when exporting half-bridge, node A is transformed into low state or is of great value from low state exchange to the high state this point from high state.This application is the electric ballast that is used for fluorescent light.Figure 2 illustrates the simplicity of illustration of this ballast resistor.As what can find out, the load of half-bridge is the resonant circuit that is made of L1, C1 and lamp 1.Alternately conducting and ending of transistor M1 and M2 during operation, this has caused electric current to be fixed in the resonant load circuit that is connected to node A.For example: when the M1 conducting, the voltage of node A is drawn (conversion) electromotive force to the DC high voltage bus, and electric current begins to be fixed in the resonant load.When M1 ended, the electric current that flows in resonant load made the voltage at node A place change to lower electromotive force.Suppose the resonance frequency of the switching frequency of half-bridge greater than load circuit.After postponing certain " idle time ", the voltage at transistor M2 conducting and node A place is pulled to the bus voltage that is lower than DC, and this bus voltage typically is zero potential.Postpone to prevent M1 and M2 conducting simultaneously this idle time, the meeting of conducting simultaneously produces short circuit.

Before the M2 conducting, the voltage transitions of node A will spend some limited time quantums and fully change, and be transformed into lower DC bus voltage from DC high voltage bus electromotive force.Under certain condition, the voltage at node A place can not fully be transformed into lower electromotive force in the time of M2 conducting.M2 will move the voltage of node A to lower voltage in this case.

This so-called " hard switching " is the source of switching loss, and causes half-bridge transistors M1 and M2 heating, and this will cause these transistors malfunctioning.

In order to minimize switching loss, can be by having guaranteed before the M2 conducting that fully the voltage of switching node A stops hard switching.This can by increase M1 (M2) by and the conducting of M2 (M1) between delay idle time, or the effective capacitance load that reduces node A is arranged.Yet these measures may reduce switching speed or available lamp ratings.

Summary of the invention

For further improvement, circuit disclosed herein and method provide adaptation function idle time that can realize in the design of halogen convertor (electronic transformer) control integrated circuit and many other application.

An aspect of this function is the method and system that is used for the voltage potential at detection node A place, and this can be integrated in the monolithic integrated circuit solution.This circuit does not need the external module that adds, and has therefore simplified the circuit of final application.This circuit is suitable for being included in the high pressure self-oscillasion semi-bridge gate drivers integrated circuit, in a special integrated circuit, wherein high voltage half-bridge gate drive buffers and level conversion is included in the monolithic integrated circuit.In sort circuit, preferably high-end gate drive buffers DRV1 is arranged in the high-end trap of insulation, this trap can float to the DC high voltage potential, and this DRV1 is positioned node " A ".

According to feature of the present invention, provide a signal to avoid hard switching in the half-bridge, this signal indication is used for the secure threshold of switch.Can provide this signal based on comparing,, can selectively provide threshold level to be used for special switch parameter for special application with the programmable threshold level.

According to another feature of the present invention, provide high-voltage switch so that in the detection of the node A place of half-bridge acquisition to voltage.Thereby can control this high-voltage switch gear so that be switched on or switched off at this voltage of half-bridge node A place measurement.

According to another feature of the present invention, the voltage at half-bridge node A place is sent to a high voltage sensing circuit, by the low terminal voltage of half-bridge to this circuit and power, and provide can be high voltage withstanding the low-voltage sensing circuit.

According to another feature of the present invention, tension measuring circuit detects voltage according to switch connection and threshold ratio.

According to other aspects of the invention, adaptation circuit idle time that is used for the oscillator drives half-bridge circuit can comprise testing circuit, is used for the voltage at detector switch half-bridge mid point place; First circuit is used to produce first signal, shows the conversion from high to low of described voltage; And output circuit, being used to produce one and adapting to output signal idle time, this signal is suitable for controlling the described output signal of described oscillator at least based on described first signal.Second circuit advantageously produces secondary signal, shows the conversion from low to high of described voltage; Wherein said output circuit produces described adaptation output signal idle time, and this signal is based on described secondary signal and described first signal.

This first circuit can begin place's generation first pulse to low conversion near described height, and is producing second pulse near described EOC place, and produces described first signal based on described first and second pulses.This second circuit preferably produces described secondary signal by duplicating described first signal.First circuit can charge to capacitor and produces described first signal by responding described first and second pulses, so that produce charging, this first signal list reveals described conversion from high to low, and described second circuit can produce described secondary signal by charging for second capacitor, so that produce charging, this charging is corresponding with the described charging on described first capacitor, so secondary signal shows described conversion from low to high; Can correspondingly produce described adaptation output signal idle time with described output circuit, described charging on described first and second capacitors of this signal response, described thus output signal is suitable for controlling described oscillator, the from high to low described and conversion from low to high at the described half-bridge mid point of this signal response place.

With reference to the accompanying drawing of back, to the explanation of embodiment of the present invention, other features and advantages of the present invention will be obviously by hereinafter.

Description of drawings

Fig. 1 is the rough schematic view of conventional half bridge topology.

Fig. 2 is the rough schematic view of conventional electronic ballast.

Fig. 3 is the synoptic diagram according to the half-bridge midpoint voltage testing circuit of first embodiment of the invention.

Fig. 4 is presented to adapt to the signal series of drawing that exists during the circuit operation idle time.

Fig. 5 is the synoptic diagram of pulse-generating circuit PGEN.

Fig. 6 is the synoptic diagram that adapts to circuit idle time.

Fig. 7 is the logical diagram of output logic circuit.

Fig. 8 is the synoptic diagram of low side driver circuit.

Embodiment

Half-bridge midpoint voltage detects

Fig. 3 is the synoptic diagram of arranging according to the half-bridge mid point node A voltage detecting of first embodiment of the invention, has also described this structure in the sequence number of above-mentioned reference is 10/806688 U. S. application.The circuit that surrounds in dotted line is included in the solution of monolithic integrated circuit; Circuit shown in should be noted that is emphasized new testing circuit.Other gate driver circuits that may be included in the complete bridge gate driver do not show, because it does not influence the present invention.

For the voltage at detection node A place, need to withstand the device of high DC bus voltage.The device that uses is M12, and it is high voltage lateral diffused metal oxide emiconductor (LDMOS) transistor.The high-end output of transistor M12 and driving transistors M1 is switch synchronously.When transistor M1 conducting, M12 is ended by giving detection input node supply logic level height.In transistor M1 conduction period, the voltage at node A place will be presented identical with the DC high voltage effectively.But when transistor M1 ended, the voltage at node A place can be that the DC high voltage is presented and any value between zero.Same according to the reactive load that is connected with node A, might be lower than zero about the voltage of return node.Just as will be described below, the voltage amplitude of node A is equal to the voltage of node C, and the voltage of node C occurs to low side and at node D by transistor M12 level shift.

The voltage of node D only has zero scope to VCC (low-side well supply voltage).So, transistor M1 by and the voltage of node A greater than any time of VCC, the voltage of node D will equal VCC.But in case the voltage of node A is lower than the VCC amplitude, the voltage of node D is equal to the voltage of node A.

Can be then the voltage of this node D be connected to comparer, COMP1 shown in Fig. 3, input end and this voltage and threshold value are compared, this threshold value can be adjusted and/or be arranged to zero.Output E with comparator C OMP1 is used to send signal then, at the mid point of half-bridge, i.e. node A, voltage reach a level, concerning all actual purposes, this level is enough must be low, will not have hard switching like this in half-bridge transistors M1 and M2.The output of this comparer can be connected to the steering logic of half-bridge driver, and take to move to prevent or to minimize the potential hard loss in the half-bridge transistors.

When the detection in the node connected logic high, the grid of transistor M12 remained to zero volt by INV1.The source/body terminal of transistor M12 is that node D also remains to zero volt by transistor M13.This makes transistor M12 end and does not have electric current to flow in its drain electrode.When detection input node was pulled to logic low, the grid of transistor M12 was moved VCC to by INV1.Meanwhile with transistor M13 by and node D by current source I1 pulled toward zero volts.Transistor M12 conducting and electric current begin to flow; The voltage amplitude that should be noted that this hypothesis node C place is greater than zero.Transistor M12 is connected as source follower, and because its drain voltage, i.e. the voltage of node C, greater than zero, the same magnitude that provides near current source I1 is provided the voltage at node D place.If the voltage of node C is greater than the amplitude of VCC, the voltage of node D will increase to VCC.If the voltage of node D deducts the conduction threshold of M12 near VCC, M12 will enter the saturation region of work, and current amplitude is identical with the current amplitude that current source I1 is provided.This with the voltage limit at node D place to the voltage level that always is lower than VCC.Voltage amplitude difference between node C and the node D voltage appears on the transistor M12, M12 high voltage lateral diffused metal oxide emiconductor (LDMOS) device, and it can stand huge voltage difference.

The voltage of node C is provided by the transistor M10 that is connected with source follower.The voltage that the voltage at node C place equals Node B deducts the conduction threshold of transistor M10.The voltage of Node B is from the transistor M11 that is connected with diode, the source/body terminal connected node A of M11.Connect in the gate/drain of transistor M11, i.e. Node B, voltage draw high by current source I2.So the voltage that the voltage of Node B equals node A adds the conduction threshold of transistor M11.Select the amplitude of current source I1 and I2 to equate, and transistor M10 and M11 mate.Have the identical currents that flows in the drain electrode of transistor M10 and M11, the conduction threshold of M10 and M11 also will be equal to.Can see that by inferring the voltage of egress C then is equal to the voltage of node A.

Adapt to function idle time

Adapt to function idle time (Fig. 4-7) and detect the voltage VS that MOSFET half-bridge mid point (being called node A in the discussion in front) is located.When high-end MOSFET ends, because the outputting inductance of MOSFET and the electric capacity of drain-to-source, voltage VS will be turned back to 0V.When voltage VS arrived low amplitude near 0V, this was the orthochronous of low MOSFET conducting.The integrated high voltage bias testing circuit of describing in conjunction with Fig. 3 produces a signal at the node C of integrated circuit low side circuitry, and this signal is followed VS from the point that its revolution is lower than VCC, and detection provides reference information to no-voltage.

Waveform VS has been shown among Fig. 4, has also shown is pulse SPN-G and RPN-G, the grid of Fig. 5 MN30 and MN31 is presented in these pulses respectively, and these pulses have produced SPN and RPN input, and these inputs are provided with and the high-end output HO that resets.

With reference to figure 4, can find out that pulse LTRIG is present in the zero hour that VS changes from high to low, and when the voltage at VS place is turned back to almost 0V, produce pulse ADT.Cycle between these pulses will be determined idle time.

These signal feedback are given adaptation circuit idle time of Fig. 6.RRS1 is set and RRS1 is resetted by LTRIG,, make this system default be fixing idle time if detect conversion less than from high to low for a certain reason by ADT or OON from oscillator.When RRS1 was set, MP11 disconnected and makes electric current flow to capacitor CB by the mirror current source that MP9 and MP10 constitute.Therefore voltage will exist on CB, and it is directly proportional with the VS gyration time from high to low that detects.

Because can not detect gyration time from low to high in an identical manner, this system determines correct idle time by the gyration time of duplicating from high to low, can suppose that gyration time from high to low is similar.When the LO step-down, the HTRIG pulse appears as shown in Figure 6, and this pulse is provided with trigger RRS2.At that point, another is begun charging by identical current source startup and CA that MP13 and MP14 constitute.When the voltage on the CA exceeds voltage on the CB, the output of comparator C MP3 will uprise, and therefore repeat described gyration time from high to low.When the output of CMP3 uprises, reset flip-flop RRS2, thus produce correct pulse idle time that is used for changing from low to high in the Q of RRS2 output.Will from the Q of trigger RRS1 and RRS2 output be fed to or non-(NOR) door NOR7 in so that produce ADTO output, this output provides a signal, this signal is low during idle time, and this signal is high when LO or HO are high.Described ADTO signal produces a pulse in RSET output place when finish each idle time, give oscillator with this impulse feeding, so that time capacitor CT (not shown) is discharged and begins next cycle.For this equipment is provided, this oscillator is such type, promptly produces ramp waveform in oscillator, and when the voltage on the CT increases, output LO and HO will alternately be high, and when the voltage on the CT reduced, LO and HO will be for low like this.In most of half bridge driver integrated circuits that international rectifier is produced, use such oscillator and output logic, and therefore do not need to further describe.

In this mode, oscillator shown in Figure 4 output OO will follow and adapt to circuit idle time, and can the output counter-rotating, and then will export through signal OON and be fed to output logic circuit shown in Figure 7, signal OON warp and (AND) door, AND2 and AND3 provide the blanking of LO and HO.

In Fig. 7, as under the situation of cold-cathode lamp, when detecting high VCS (current sense pin voltage), the CS input is used for output latch is disconnected (latch off).

Although invention has been described in conjunction with the specific embodiments thus, for a person skilled in the art, much other changes and change and other use are clearly.Therefore, the present invention be not by here especially disclosed content limited.

Claims (20)

1, a kind of adaptation circuit idle time that is used for the oscillator drives half-bridge circuit comprises:

Testing circuit is used for the voltage at detector switch half-bridge mid point place;

First circuit is used to produce first signal, shows the conversion from high to low of described voltage; With

Output circuit is used to produce an output signal that adapts to idle time, and this signal is suitable for controlling the described output signal of described oscillator at least based on described first signal.

2, as the circuit in the claim 1, further comprise:

Second circuit is used to produce secondary signal, shows the conversion from low to high of described voltage;

Wherein said output circuit produces described adaptation output signal idle time, and this signal is based on described secondary signal and described first signal.

3, as the circuit in the claim 1, wherein said first circuit is beginning place's generation first pulse near described height to low conversion, and is producing second pulse near described EOC place, and produces described first signal based on described first and second pulses.

4, as the circuit in the claim 3, wherein said second circuit produces described secondary signal by duplicating described first signal.

5, as the circuit in the claim 4, wherein said first circuit charges to capacitor and produces described first signal by responding described first and second pulses, so that produce charging, this first signal list reveals described conversion from high to low, and described second circuit produces described secondary signal by charging for second capacitor, so that produce charging, this charging is corresponding with the described charging on described first capacitor, so secondary signal shows described conversion from low to high; With

Described output circuit produces described adaptation output signal idle time, described charging on described first and second capacitors of this signal response, described thus output signal is suitable for controlling described oscillator, the from high to low described and conversion from low to high at the described half-bridge mid point of this signal response place.

6, as the circuit in the claim 2, wherein said second circuit produces described secondary signal by duplicating described first signal.

7, as the circuit in the claim 6, wherein said first circuit charges to capacitor and produces described first signal by responding described first and second pulses, so that produce charging, this first signal list reveals described conversion from high to low, and described second circuit produces described secondary signal by charging for second capacitor, so that produce charging, this charging is corresponding with the described charging on described first capacitor, so secondary signal shows described conversion from low to high; With

Described output circuit produces described adaptation output signal idle time, described charging on described first and second capacitors of this signal response, described thus output signal is suitable for controlling described oscillator, the from high to low described and conversion from low to high at the described half-bridge mid point of this signal response place.

8, as the circuit in the claim 1, the described testing circuit that wherein is used to detect at switch half-bridge midpoint voltage comprises:

High voltage device is coupled to the switch half-bridge mid point, so that record detects voltage, this voltage is relevant with the voltage of this switch half-bridge midpoint; With

The voltage detecting output circuit is coupled to high tension apparatus, is used to receive detect voltage and export a signal so that help the work of half-bridge circuit, thereby avoids the hard switching based on half-bridge circuit midpoint voltage.

9, as the circuit in the claim 8, wherein said high voltage device is mos field effect transistor (MOSFET).

10,, wherein when the high-end switch in the cut-off switch half-bridge, encourage this high voltage device as the circuit in the claim 8.

11, a kind of generation is used for the method for adaptation signal idle time of oscillator drives half-bridge circuit, comprises step:

The voltage at detector switch half-bridge mid point place;

Produce first signal, show the conversion from high to low of described voltage; With

Produce adaptation output signal idle time, this signal is suitable for controlling the described output signal of described oscillator at least based on described first signal.

12,, further comprise step as the method in the claim 11:

Produce secondary signal, show the conversion from low to high of described voltage;

Wherein produce described adaptation output signal idle time based on described secondary signal and described first signal.

13, as the method in the claim 11, wherein produce described first signal: beginning place's generation first pulse to low conversion near described height by several steps, and producing second pulse, and produce described first signal based on described first and second pulses near described EOC place.

14,, wherein produce described secondary signal by duplicating described first signal as the method in the claim 13.

15, as the circuit in the claim 14, wherein charge to capacitor and produce described first signal by responding described first and second pulses, so that produce charging, this first signal list reveals described conversion from high to low, and produce described secondary signal by charging for second capacitor, so that produce charging, this charging is corresponding with the described charging on described first capacitor, so secondary signal shows described conversion from low to high; With

Produce described adaptation output signal idle time, described charging on described first and second capacitors of this signal response, described thus output signal is suitable for controlling described oscillator, the from high to low described and conversion from low to high at the described half-bridge mid point of this signal response place.

16,, wherein produce described secondary signal by duplicating described first signal as the method in the claim 12.

17, as the method in the claim 16, wherein charge to capacitor and produce described first signal by responding described first and second pulses, so that produce charging, this first signal list reveals described conversion from high to low, and produce described secondary signal by charging for second capacitor, so that produce charging, this charging is corresponding with the described charging on described first capacitor, so secondary signal shows described conversion from low to high; With

Produce described adaptation output signal idle time, described charging on described first and second capacitors of this signal response, described thus output signal is suitable for controlling described oscillator, the from high to low described and conversion from low to high at the described half-bridge mid point of this signal response place.

18, as the method in the claim 11, wherein said detection step comprises step:

High voltage device is coupled to the mid point of switch half-bridge, so that write down the detection voltage on the high voltage device, it is relevant with the voltage bias of switch half-bridge midpoint that this detects voltage; And

Provide a signal based on the detection voltage that writes down on high voltage device, so that when connecting the low-end switch of switch half-bridge, show that when the voltage of switch half-bridge midpoint has reached a value, this value is enough to avoid hard switching.

19,, further comprise MOSFET is provided the step as the high-voltage switch device as the method in the claim 18.

20,, comprise also that when the high-end switch in the switch half-bridge is disconnected the excitation high voltage device is so that record detects the step of voltage as the method in the claim 18.

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