WO2014183525A1 - Procede de traitement de paquet et puce en cascade - Google Patents

Procede de traitement de paquet et puce en cascade Download PDF

Info

Publication number
WO2014183525A1
WO2014183525A1 PCT/CN2014/075494 CN2014075494W WO2014183525A1 WO 2014183525 A1 WO2014183525 A1 WO 2014183525A1 CN 2014075494 W CN2014075494 W CN 2014075494W WO 2014183525 A1 WO2014183525 A1 WO 2014183525A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
packet
cascading
processing
information
Prior art date
Application number
PCT/CN2014/075494
Other languages
English (en)
Chinese (zh)
Inventor
范力涵
陈春雷
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2014183525A1 publication Critical patent/WO2014183525A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/64—Hybrid switching systems
    • H04L12/6418—Hybrid transport

Definitions

  • the present invention relates to the field of communications, and in particular, to a packet processing method and a cascade chip.
  • IP Internet Protocol
  • BACKGROUND With the development of the Internet technology, new application scenarios of the Internet Protocol (IP) network are constantly appearing, various new types of services are being developed and deployed, and the number of users is exploding, and the demand for bandwidth is increasing. The bigger. These developments place extremely high demands on the forwarding performance and service functions of network devices.
  • IP Internet Protocol
  • the message message is processed on a processing chip having the capability of processing a plurality of service functions. After the forwarding performance is insufficient or a new service appears, the above processing chip must be updated.
  • the upgraded processing chip Due to the need for backward compatibility, the upgraded processing chip must not only have the ability to handle all of the business functions of the previous processing chip, but also be able to support new business functions. Due to the redesign of the entire processing chip, while adding new services and satisfying certain forwarding performance, the cost of research and development is necessarily higher, and the complexity of design is also improved. After the development is completed, the processing chip is applied. The entire processing chip must be updated to further increase the cost of updating the processing chip. Moreover, the demand for business is constantly growing, and new businesses are constantly appearing. When the business needs are insufficient or whenever a new service appears, the entire processing chip must be re-designed and replaced with a newly designed processing chip, which will inevitably lead to a shortened actual use period of the old processing chip. waste.
  • the embodiments of the present invention provide a packet processing method and a cascading chip, so as to at least solve the problem that the research and development cost of the processing chip is high due to the continuous growth of services in the related art.
  • a method for processing a packet including: adding, by a front-end chip in a cascading chip, identification information to a packet that needs to be processed by a chip at a back end thereof, and adding an identification letter
  • the message of the interest is sent to the next-level chip; the next-level chip processes the received message according to the identification information.
  • the front-end chip adds the identification information to the packet processed by the chip that needs the back end thereof, and the front-end chip adds a pre-processing packet header to the packet processed by the chip that needs the back end thereof, where the pre-processing packet header includes the identifier. information.
  • the pre-processing packet header further includes at least one of the following: source port information, destination port information, forwarding domain information, and egress encapsulation information.
  • the processing of the received message by the next-level co-chip is performed according to the identification information, where: the next-level co-chip performs service processing on the packet if it determines that the received message includes the identification information, And forwarding the processed message; and if it is determined that the received message does not include the identification information, the message is transparently transmitted.
  • the processing of the packet by the next-level chip includes: the next-level chip performs service processing on the packet according to the source port information in the packet.
  • the next-level cascading chip transparently transmits the packet to include: the next-level cascading chip does not perform the service processing on the packet, and only forwards the packet directly according to the destination port information in the packet.
  • a cascading chip is provided, wherein a front-end chip in a cascading chip includes: an adding module, configured to add identification information to a message for performing service processing on a chip that needs a back end thereof; And a sending module, configured to send the packet with the added identification information to the next-level integrated chip; the next-level integrated chip includes: a receiving module, configured to receive the message; and a processing module, configured to receive the received message according to the received message The identification information in the message is processed.
  • each chip in the cascading chip has a cascading interface attribute, wherein the cascading interface attribute is used to determine whether there are other chips concatenated at the front end and/or the back end of the chip.
  • the cascading interface attributes include: an ingress cascading identifier and an egress cascading identifier; or, an ingress cascading identifier, an ingress cascading identifier length information, an egress cascading identifier, and an egress cascading identifier length information.
  • the processing module in the next-level integrated chip includes: a service processing unit, configured to perform service processing on the packet after determining that the packet received by the receiving module includes the identifier information, and processing the processed packet The packet is forwarded; and the transparent transmission unit is configured to transparently transmit the packet if the identifier received by the receiving module does not include the identifier information.
  • the front-end chip in the cascading chip adds the identification information to the packet that needs to be processed by the back-end chip, and sends the packet with the added identification information to the next-level cascading chip;
  • the chip processes the received message according to the identification information, and solves the problem that the continuous development of the service leads to high research and development cost of the processing chip, and reduces the complexity and research and development cost of the chip development.
  • FIG. 1 is a flow chart of a method for processing a message according to an embodiment of the present invention
  • FIG. 2 is a block diagram showing the structure of a cascode chip according to an embodiment of the present invention
  • FIG. 3 is a stage according to a preferred embodiment of the present invention.
  • FIG. 4 is a block diagram showing the structure of inter-chip cascades in accordance with a preferred embodiment of the present invention
  • FIG. 5 is a flow chart of a preferred method of inter-chip cascade cooperation in accordance with a preferred embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. The invention will be described in detail below with reference to the drawings in conjunction with the embodiments. It should also be noted that the steps illustrated in the flowchart of the figures may be performed in a computer system such as a set of computer-executable instructions, and, although the logical order is illustrated in the flowchart, in some cases The steps shown or described may be performed in an order different from that herein.
  • the embodiment of the present invention provides a method for processing a packet.
  • Step S102 in a cascading chip
  • the front-end chip adds the identification information to the packet that needs to be processed by the chip at the back end, and sends the packet with the identifier information to the next-level chip
  • Step S104 the next-level chip receives the packet according to the identifier information.
  • the message arrived is processed.
  • the front-end chip may add a pre-processing header to the packet processed by the chip that needs the back end thereof, where the pre-processing header includes the identifier information.
  • the pre-processing packet header may be an extension of the original packet header of the packet. In this way, the operability and compatibility of the method are improved.
  • the pre-processing packet header may further include at least one of the following: source port information, destination port information, forwarding domain information, and egress encapsulation information.
  • the method is simple and practical, and has high operability.
  • the next-level cascode chip determines the received message, and includes the identifier information of the packet that needs to be processed by the chip at the back end to perform service processing. Performing service processing, and forwarding the processed message; and transparently transmitting the message if it is determined that the received message does not include the identification information. After the processed packet does not need to be processed by the back end chip, the chip at the back end forwards the packet to the next exit.
  • the next-level chip processes or forwards the packets, which are based on the identification information. That is to say, the requirements of transparent transmission and opaque transmission are indicated by the identification information.
  • Transparent transmission means that packets are sent directly from the designated port without the need for the next level of chip processing, and are transmitted transparently without carrying the identification information.
  • Whether the packet received by the next-level chip includes identification information can be determined by the attributes of the cascade port. If the attribute indicates that the packet coming from the port does not carry the identifier information, the chip is processed according to normal Ethernet.
  • the next-level chip can perform the service on the packet according to the source port information in the packet. deal with.
  • the next-level co-chip does not perform the service processing on the received packet, and only forwards the packet according to the destination port information in the packet.
  • the destination port information here can be located in the pre-processing header.
  • the embodiment of the invention further provides a cascading chip, which can be used to implement the processing method of the above message.
  • 2 is a structural block diagram of a cascode chip according to an embodiment of the present invention. As shown in FIG. 2, the cascode chip includes a front end chip 22 and a lower cascode chip 24.
  • the front-end chip 22 includes: an adding module 222 and a sending module 224, and the adding module 222 is coupled to the sending module 224, and is configured to add identification information to the packet for which the chip that needs the back end performs service processing, and the sending module 224 is coupled to the next level.
  • the chip 24 is configured to send the message to which the identification information has been added to the next-level cascode 24; the next-level cascode 24 includes: the receiving module 242 and processing
  • the receiving module 242 is coupled to the sending module 224, and is configured to receive the packet.
  • the processing module 244 is coupled to the receiving module 242, and configured to process the packet according to the identifier information in the received packet.
  • the front-end chip 22 and the lower-level integrated chip 24 jointly process the service, the different service functions that need to be processed in the packet are respectively processed in the corresponding chips of the cascading chip, so that when the chip is developed or updated, It only needs to research and develop or update the chip that handles the corresponding business function, and solves the problem that the development of the related technology leads to the high research and development cost of the processing chip. Compared with the related technology, it is necessary to research and develop the entire chip for processing the integrated business function. The update reduces the complexity of the development process and reduces the cost of development.
  • the sending module 224 in the front-end chip 22 can determine whether to adopt different packages according to the attributes of the sending port (for example, whether to carry/peel/replace the above-mentioned identification information), and the receiving module in the next-level integrated chip 24 242 may also determine, according to the attributes of the receiving port, whether to parse the packet according to the identifier information format.
  • each chip in the cascading chip has a cascading interface attribute, wherein the cascading interface attribute is set to determine whether there are other chips concatenated at the front end and/or the back end of the chip.
  • the cascading interface attributes include: an ingress cascading identifier and an egress cascading identifier; or an ingress cascading identifier, an ingress cascading identifier length information, an egress cascading identifier, and an egress cascading identifier length information.
  • the length information of the ingress cascading identifier and the length information of the egress cascading identifier in the cascading interface attribute can process the cascading identification information of different lengths, thereby improving the flexibility of the system.
  • 3 is a structural block diagram of a cascode chip according to a preferred embodiment of the present invention. As shown in FIG.
  • the processing module 244 in the next cascode includes: a service processing unit 2442, configured to determine at the receiving module 242. If the packet includes the identifier information, the packet is processed by the service, and the processed packet is forwarded.
  • the transparent transmission unit 2444 is configured to not include the packet received by the receiving module 242. In the case of the above identification information, the message is transparently transmitted.
  • FIG. 4 is a schematic structural diagram of inter-chip cascading according to a preferred embodiment of the present invention.
  • the chips in the system are connected by cascading, wherein m represents the number of receiving ports of the chip 1, n represents the number of outgoing ports of the chip 1 or the number of receiving ports of the chip 2, and k represents the number of outgoing ports of the chip 2.
  • m represents the number of receiving ports of the chip 1
  • n represents the number of outgoing ports of the chip 1 or the number of receiving ports of the chip 2
  • k represents the number of outgoing ports of the chip 2.
  • Step 1 Define a packet header (corresponding to the foregoing pre-processing header), which is referred to herein as a preHeader, for the current chip advertisement information to the next-level concatenated chip.
  • the preHeader includes a bypass flag for indicating whether the next-level concatenated chip processes the message.
  • the current level 1 chip will process the message. Only when the current chip is transparently transmitted, the previous chip will set the bypass flag. When the message still needs further processing by the current chip, the bypass flag needs to be cleared in the previous chip.
  • the preHeader contains source port information, here abbreviated as S r C Port.
  • the source port can be set to the inbound interface number of the front-end chip according to service requirements, or set to the mapped interface number according to service requirements.
  • the outbound interface information is included, and is abbreviated as destPort.
  • the front-end chip needs to fill the final outgoing interface number of the packet into the destPorto.
  • the pre-header can carry other information, such as the forwarding domain information and the egress. Package information, etc.
  • Step 2 By configuring (or automatically identifying) the attribute, the chip interface senses its position in the entire processing flow to identify whether the received message type and the sent message type have a preHeader, for example, adding an in_preHeade to the chip interface. Attributes and out_preHeader attributes. When the chip location is not the front-end chip, the in-preHeader attribute of the corresponding interface can be turned on according to the service requirement. When the chip exit is further connected to the chip, the out_preHeader attribute can be turned on according to business needs.
  • the in_preHeader_size and out_preHeader_size attributes may be added to the interface attributes, and the received preHeader length and the issued preHeader length are respectively divided.
  • This method can further improve the flexibility of the chip and facilitate compatibility and upgrade.
  • the preHeader attribute of the inbound and outbound interfaces can be extended to the chip global attribute. Step 3: When the chip receives the packet, it queries the iiupreHeader attribute according to the inbound interface. If the in_preHeader attribute is enabled, the packet is considered to carry the preHeader, and the chip further performs the next processing according to the preHeader information.
  • the out-preHeader attribute of the interface is determined. If the out_preHeader attribute is enabled, the preHeader header is added to the front end of the message, and the corresponding information is filled in and sent out from the interface.
  • the chip receives the message it searches for the in-preHeader attribute according to the receiving interface. If the iiUpreHeader attribute is not enabled, the packet is considered to be the default processing format packet, and the default process is processed.
  • the chip receives the message it searches for the in-preHeader attribute according to the receiving interface. If the in_preHeader attribute is enabled, the bypass flag in the preHeader is determined.
  • the pre-header is stripped and the packet is directly forwarded to the outbound interface of the destination interface.
  • the destination interface is specified by the destPort in the preHeader. If the bypass flag is not enabled, the pre-header is stripped and the remaining packets are considered as By default, the format packet is processed.
  • the srcPort in the preHeader is used as the source port information, and the default processing flow is taken.
  • the chip finds the out_preHeader attribute of the out interface according to the outbound interface number. If the out_preHeader attribute is enabled, the preHeader header is encapsulated.
  • the cascaded plurality of chips can collectively form a message processing system, and the chips can cooperate without barriers, and each chip only needs to support some functions.
  • the chips designed later need only provide new business functions or replace chips that cannot meet the business requirements, which greatly reduces the design difficulty and cost.
  • the method reduces the burden on the chip, it is easier to improve the forwarding performance.
  • FIG. 5 is a flow chart of a preferred method of inter-chip cascade cooperation according to a preferred embodiment of the present invention, as illustrated in FIG.
  • Step S502 the chip receives the message; Step S504, it is determined whether the interface of the packet is in the preHeaher mode, if the determination is yes, step S406 is performed, otherwise step S510 is performed; Step S506, taking the preHeader header, setting the source port to the srcPort in the preHeader, and deleting the preHeader from the message; Step S508, determining whether the bypass identifier in the preHeader is zero, and executing the step S510 if the determination is yes, otherwise Step S512, step S510, executing a default message processing flow, and then performing step S514; Step S512, querying the outgoing interface according to the destPort (ie, the outbound interface information) in the preHeader, and then performing step S514; Step S514, determining whether the interface is In the preHeader mode, if the determination is yes, step S516 is performed, otherwise step S518 is performed; step S516, preHeader is added
  • the chips can be cascaded in multiple stages, and the system functions can be tailored, and the complex services and the simple services are not interfered with each other.
  • the completeness, complexity, performance and cost of the functions are contradictory, which solves the problem of high processing and development cost of the processing chip due to the continuous growth of the business.
  • certain features of the embodiments, embodiments, and embodiments of the above-described embodiments, preferred embodiments, and preferred methods, and combinations thereof, respectively, can achieve the following beneficial effects:
  • preHeader attribute is not enabled, it is identical to the original chip process and has good compatibility.
  • the chip design does not need to implement all the business functions on one chip, and only needs to divide the business functions into different chips, which reduces the difficulty of chip design.
  • the same forwarding system can be composed of a variety of chips, which increases the chip selection room of the equipment manufacturer.
  • the coupling relationship between the chips is small, and the chip can be increased or decreased as needed.
  • the new business there is no need to replace all the chips, only a new chip can be cascaded to achieve smooth upgrade of the device, shortening the development cycle and reducing development risks and costs.
  • the service chip can be subtracted, and the device cost is reduced. 5. Sharing the business to multiple chips is beneficial to improve the forwarding performance of the chip.
  • the main chip in the system can support port density, it can be effectively expanded by expanding the high-density port chip on the front end.
  • modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices.
  • they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device, or they may be separately fabricated into individual integrated circuit modules, or they may be Multiple modules or steps are made into a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • a packet processing method and a cascading chip provided by an embodiment of the present invention have the following beneficial effects: If the preHeader attribute is not turned on, the original chip process is completely the same, and has good compatibility; Chip cascading method, chip design does not need to implement all business functions on one chip, only need to divide business functions into different chips, which reduces the difficulty of chip design; when new business appears, only need to associate new functions
  • the implementation of the new chip is beneficial to the fast response requirement; the same forwarding system can be composed of a variety of chips, which increases the chip selection room of the equipment manufacturer, and the coupling relationship between the chips is small, and can be increased according to requirements or Reduce the chip.
  • the service chip can be deducted, and the device cost is reduced.
  • the sharing of the service to multiple chips is beneficial to improving the forwarding performance of the chip.
  • the main chip in the system can support the port density, It can be effectively expanded by expanding the high-density port chip at the front end.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

La présente invention porte sur un procédé de traitement de paquet et une puce en cascade. Le procédé comprend les opérations suivantes: une puce d'extrémité avant dans des puces en cascade ajoute des informations d'identification à un paquet dont une puce d'extrémité arrière de la puce d'extrémité avant a besoin pour effectuer un traitement de service, et envoie le paquet auquel les informations d'identification ont été ajoutées à une puce en cascade suivante; et la puce en cascade suivante traite le paquet reçu en fonction des informations d'identification. La présente invention résout un problème, dans l'état antérieur de la technique, de coût de développement élevé causé par un accroissement continu de services, et réduit la complexité de développement et le coût de développement de puces.
PCT/CN2014/075494 2013-05-13 2014-04-16 Procede de traitement de paquet et puce en cascade WO2014183525A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310176754.8A CN104158716A (zh) 2013-05-13 2013-05-13 报文的处理方法和级联芯片
CN201310176754.8 2013-05-13

Publications (1)

Publication Number Publication Date
WO2014183525A1 true WO2014183525A1 (fr) 2014-11-20

Family

ID=51884125

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/075494 WO2014183525A1 (fr) 2013-05-13 2014-04-16 Procede de traitement de paquet et puce en cascade

Country Status (2)

Country Link
CN (1) CN104158716A (fr)
WO (1) WO2014183525A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107612848B (zh) * 2017-10-13 2021-04-09 盛科网络（苏州）有限公司 一种调试方法及装置、以及计算机可读存储介质
CN109617767B (zh) * 2019-02-22 2022-09-23 苏州盛科通信股份有限公司 一种在芯片中报文环回处理的实时调试方法及装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1801771A (zh) * 2005-01-04 2006-07-12 华为技术有限公司 透传虚拟局域网数据的方法
CN101237404A (zh) * 2008-03-11 2008-08-06 华为技术有限公司 报文转发方法和装置
CN102035668A (zh) * 2009-09-29 2011-04-27 中兴通讯股份有限公司 一种交换芯片管理方法和系统
CN102480652A (zh) * 2010-11-29 2012-05-30 中兴通讯股份有限公司 映射业务流的方法和ont

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102281192B (zh) * 2011-07-19 2017-09-29 中兴通讯股份有限公司 交换网络芯片的信元处理方法及装置
CN102624727B (zh) * 2012-03-07 2014-12-24 福建星网锐捷网络有限公司 接口配置方法及装置、主控中央处理器及网络设备
CN102970105B (zh) * 2012-11-09 2015-12-02 深圳市晟碟半导体有限公司 一种led芯片级联信号的传输方法及传输系统

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1801771A (zh) * 2005-01-04 2006-07-12 华为技术有限公司 透传虚拟局域网数据的方法
CN101237404A (zh) * 2008-03-11 2008-08-06 华为技术有限公司 报文转发方法和装置
CN102035668A (zh) * 2009-09-29 2011-04-27 中兴通讯股份有限公司 一种交换芯片管理方法和系统
CN102480652A (zh) * 2010-11-29 2012-05-30 中兴通讯股份有限公司 映射业务流的方法和ont

Also Published As

Publication number Publication date
CN104158716A (zh) 2014-11-19

Similar Documents

Publication Publication Date Title
US9894003B2 (en) Method, apparatus and system for processing data packet
CN105791214B (zh) 一种RapidIO报文和以太网报文之间的转换方法和设备
WO2018032961A1 (fr) Procédé, appareil et système de gestion d'informations
US9973400B2 (en) Network flow information collection method and apparatus
WO2018032962A1 (fr) Procédé, dispositif et système pour la synchronisation d'informations
JP2020508004A (ja) パケット処理方法および装置
RU2661768C2 (ru) Способ воплощения arp, устройство коммутатора и модуль управления
WO2014194677A1 (fr) Procédé de commande de processus de service et dispositif de réseau
CN107948077B (zh) 一种数据报文的转发方法及装置
EP4131870A1 (fr) Procédé et appareil de traitement de service, et dispositif et support de stockage
WO2018161672A1 (fr) Procédé, appareil et système de traitement de paquets
WO2021043232A1 (fr) Procédé par lequel des exigences de performance de réseau hôte peuvent être programmées, dispositif et système
EP3633934A1 (fr) Procédé et appareil de mise en uvre d'arp à base de sdn
CN109936492A (zh) 一种通过隧道传输报文的方法、装置和系统
CN104508651A (zh) 镜像非对称集群多处理器系统中的连接网
EP2953302B1 (fr) Procédé, appareil et système de traitement de paquets de service
WO2023061061A1 (fr) Procédé de traitement de message, attache de câble, dispositif et support d'enregistrement
CN110535812A (zh) 报文传输方法、通信装置和系统
CN112769738A (zh) DetNet数据包处理方法及装置
WO2017206058A1 (fr) Procédé et appareil de configuration de communication destinés à être utilisés dans une communication de partage à large bande
CN107483369B (zh) 一种报文处理方法及虚拟交换机
WO2014183525A1 (fr) Procede de traitement de paquet et puce en cascade
CN102263700A (zh) 一种报文收发方法、装置和系统
CN116095197B (zh) 数据传输方法及相关装置
WO2015154393A1 (fr) Procédé et appareil de traitement de capacité de nœud de service, classificateur de service et contrôleur de service

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14797095

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14797095

Country of ref document: EP

Kind code of ref document: A1