WO2014179809A1 - Gallium nitride field effect transistor - Google Patents
Gallium nitride field effect transistor Download PDFInfo
- Publication number
- WO2014179809A1 WO2014179809A1 PCT/US2014/036842 US2014036842W WO2014179809A1 WO 2014179809 A1 WO2014179809 A1 WO 2014179809A1 US 2014036842 W US2014036842 W US 2014036842W WO 2014179809 A1 WO2014179809 A1 WO 2014179809A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- metal
- layer
- gate
- silicon
- atomic percent
- Prior art date
Links
- 229910002601 GaN Inorganic materials 0.000 title description 16
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title description 10
- 230000005669 field effect Effects 0.000 title description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 114
- 239000002184 metal Substances 0.000 claims abstract description 114
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 50
- 239000010703 silicon Substances 0.000 claims abstract description 50
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 25
- 238000004544 sputter deposition Methods 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 4
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 4
- 230000005641 tunneling Effects 0.000 claims description 4
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 238000002161 passivation Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28264—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
- H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
Definitions
- This relates in general to semiconductor devices, and in particular to gallium nitride field effect transistors.
- a gallium nitride field effect transistor may have an insulated metal gate and tunneling source and drain contacts. Forming reliable source and drain contacts may require annealing at a temperature which causes degradation of the gate dielectric layer.
- a semiconductor device may be formed by forming a metal gate with 2 atomic percent to 10 atomic percent silicon.
- the metal gate is formed over a gate dielectric layer containing silicon.
- a subsequent contact anneal may include heating for at least 30 seconds at a temperature of at least 750 °C.
- FIGS. 1A-1E are cross sections of a semiconductor device depicted in successive stages of fabrication.
- FIGS. 2-4 depict exemplary processes for forming metal gates of GaN FETs with 2 atomic percent to 10 atomic percent silicon.
- a semiconductor device may be formed by forming a silicon-containing gate dielectric layer, such as silicon nitride, over a semiconductor layer.
- a gate metal layer is formed over the gate dielectric layer; the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation.
- the gate metal layer is patterned to form a metal gate.
- Contact metal is formed and possibly patterned to form source and drain contacts.
- a subsequent contact anneal heats the contact metal and gate for at least 30 seconds at a temperature of at least 750 °C.
- Ill-Nitride (III-N) semiconductor materials are materials in which Group III (boron group) elements (boron, aluminum, gallium, indium) provide a portion of the atoms in the semiconductor material and nitrogen atoms provide the remainder.
- Group III-N semiconductor materials are gallium nitride, boron gallium nitride, aluminum gallium nitride, indium nitride, and indium aluminum gallium nitride.
- III-N materials may be written with variable subscripts to denote a range of possible stoichiometries.
- aluminum gallium nitride may be written as Al x Gai_ x N and indium aluminum gallium nitride may be written as In x Al y Gai_ x _ y N.
- GaN FET is an example of a field effect transistor that includes III-N semiconductor materials.
- the sputtered aluminum also includes up to a few percent of copper, silicon, titanium and/or other elements, so as to improve the aluminum's electromigration properties.
- FIGS. 1A-1E are cross sections of a semiconductor device depicted in successive stages of fabrication.
- the semiconductor device 100 is formed on a substrate 102 which may have a low-defect layer of III-N semiconductor material at a top surface, for example, an unintentionally doped layer of gallium nitride.
- a barrier layer 104 of III-N semiconductor material is formed on the top surface of the substrate 102.
- the barrier layer 104 may include Al x Gai_ x N or In x Al y Gai_ x _ y N, 2 to 30 nanometers thick.
- barrier layer 104 Forming the barrier layer 104 on the low-defect layer of III-N semiconductor material at the top surface of the substrate 102 generates a two-dimensional electron gas in the low-defect layer just below the barrier layer 104 with an electron density of, for example, l x lO 12 to 2> ⁇ 10 13 cm 2 .
- An optional cap layer 106 of 2 to 5 nanometers of gallium nitride may be formed over the barrier layer 104.
- a silicon-containing gate dielectric layer 108 is formed over the barrier layer 104, and over the cap layer 106 if present.
- the gate dielectric layer 108 may be, for example, 10 to 20 nanometers of silicon nitride formed by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).
- LPCVD low pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- the gate dielectric layer 108 may include one or more layers of silicon nitride, silicon dioxide and/or silicon oxynitride.
- a layer of field dielectric 110 is formed on the gate dielectric layer 108 and patterned to have sloped edges adjacent to a channel region of the semiconductor device 100.
- the field dielectric 110 may include, for example, 100 to 300 nanometers of silicon nitride, formed by LPCVD or PECVD.
- a metal gate 112 is formed on the gate dielectric layer 108 over the channel region and overlapping the sloped edge of the field dielectric 110.
- the metal gate 112 may include at least 10 percent titanium, for example titanium tungsten alloy.
- the metal gate 112 further includes 2 atomic percent to 10 atomic percent silicon.
- the metal gate 112 may be formed, for example by an etch process or a liftoff process.
- a passivation dielectric layer 114 is formed over the metal gate 112, the field dielectric 110 and the gate dielectric layer 108.
- the passivation dielectric layer 114 may include, for example, 200 to 300 nanometers of silicon nitride, formed by PECVD.
- Source and drain contact holes 116 are etched through the passivation dielectric layer 114, the gate dielectric layer 108 and the cap layer 106, and into the barrier layer 104 proximate to the two-dimensional electron gas.
- the source and drain contact holes 116 may be 1 to 10 microns wide.
- contact metal 118 is formed in the source and drain contact holes 116 and patterned.
- the contact metal 118 may include, for example, a layer of titanium 120 40 to 100 nanometers thick sputtered in the source and drain contact holes 116, a layer of sputtered aluminum 122 50 to 200 nanometers thick formed on the titanium layer 120, and a layer of titanium nitride 124 30 to 80 nanometers thick formed on the sputtered aluminum layer 122 by reactive sputtering, also known as physical vapor deposition (PVD).
- PVD physical vapor deposition
- the contact metal 118 is formed so as to provide an open cavity in each of the source and drain contact holes 116.
- Forming the metal gate 112 and the passivation dielectric layer 114 prior to forming the source and drain contact holes 116 and the contact metal 118 advantageously allows closer gate-source spacing and more fabrication process latitude, because the contact metal 118 may overlap a top surface of the passivation dielectric layer 114 without interfering with the metal gate 112.
- formation of the source and drain contact holes 116 may be omitted so that the contact metal 118 is formed on an existing top surface of the III-N semiconductor material.
- a contact anneal process 126 heats the contact metal 118 to at least 750 °C for at least 30 seconds.
- the contact anneal process 126 improves an electrical connection between the contact metal 118 and the two-dimensional electron gas by reducing an impedance of the electrical connection and making the electrical connection more ohmic, that is, making a current voltage relationship of the electrical connection more linear. Increasing the temperature of the contact anneal process 126 further improves the electrical connection.
- the contact anneal process 126 heats the contact metal 118 to at least 800 °C for at least 30 seconds.
- the contact anneal process 126 heats the contact metal 118 to at least 850 °C for at least 30 seconds. In a further version, the contact anneal process 126 heats the contact metal 118 to at least 900 °C for at least 30 seconds.
- the contact anneal process 126 may be performed, for example, in a rapid thermal processor (RTP) tool which heats the semiconductor device 100 using incandescent lamps.
- RTP rapid thermal processor
- a first metallization layer 128 is formed on the contact metal 118.
- the first metallization layer 128 may include, for example, an adhesion layer 130 of 50 to 150 nanometers of sputtered titanium tungsten, a main metal layer 132 of 200 to 500 nanometers of sputtered aluminum formed on the adhesion layer 130, and an anti-refection layer 134 of 20 to 40 nanometers of titanium nitride formed on the main metal layer 132.
- the first metallization layer 128 is patterned so as to overlap the source and drain contact holes 116.
- FIGS. 2-4 depict exemplary processes for forming metal gates of GaN FETs with 2 atomic percent to 10 atomic percent silicon.
- a substrate 202 of a semiconductor device 200 is positioned in a sputtering tool 236.
- the sputtering tool 236 includes a metal target 238 which has silicon incorporated in the metal target 238.
- Sputtering gas 240 such as argon is introduced into the sputtering tool 236 between the metal target 238 and the substrate 202.
- a plasma is formed in the sputtering gas 240 and electrical bias is applied to the metal target 238 so that metal and silicon are sputtered from the metal target 238 onto the substrate 202 to form a metal gate layer 242 incorporating silicon on the substrate 202.
- a concentration of silicon in the metal target 238 is selected so that the metal gate layer 242 has 2 atomic percent to 10 atomic percent silicon.
- the metal gate layer 242 may be patterned to form a metal gate such as the metal gate 112 depicted in FIGS. 1A-1E.
- a substrate 302 of a semiconductor device 300 is positioned in a sputtering tool 336.
- the sputtering tool 336 includes a metal target 338 which has less than 1 atomic percent silicon.
- Sputtering gas 340 which includes an inert gas such as argon and a silicon species 344 such as silane, is introduced into the sputtering tool 336 between the metal target 338 and the substrate 302.
- a plasma is formed in the sputtering gas 340 and electrical bias is applied to the metal target 338 so that metal is sputtered from the metal target 338 onto the substrate 302 and silicon from the silicon species 344 is incorporated in the sputtered metal to form a metal gate layer 342 incorporating silicon on the substrate 302.
- a pressure and a flow rate of the silicon species 344 is selected so that the metal gate layer 342 has 2 atomic percent to 10 atomic percent silicon.
- the metal gate layer 342 may be patterned to form a metal gate such as the metal gate 112 depicted in FIGS. 1A-1E.
- a substrate 402 of a semiconductor device 400 is positioned in a sputtering tool 436.
- the sputtering tool 436 includes a metal target 438 and a separate silicon target 446.
- Sputtering gas 440 such as argon is introduced into the sputtering tool 436 between the metal target 438 and the silicon target 446 and the substrate 402.
- a plasma is formed in the sputtering gas 440 and electrical bias is applied to the metal target 438 and to the silicon target 446 so that metal and silicon are sputtered from the metal target 438 and the silicon target 446, respectively, onto the substrate 402 to form a metal gate layer 442 incorporating silicon on the substrate 402.
- the substrate 402 may remain stationary with respect to the metal target 438 and the silicon target 446 during formation of the metal gate layer 442 while sputtering occurs concurrently at both targets 438 and 446.
- the substrate 402 may move alternately between a first position under the metal target 438 in which predominantly metal is sputtered onto the substrate 402, and a second position under the silicon target 446 in which predominantly silicon is sputtered onto the substrate 402.
- Process parameters such as sputter rates from the metal target 438 and the silicon target 446 are selected so that the metal gate layer 442 has 2 atomic percent to 10 atomic percent silicon.
- the metal gate layer 442 may be patterned to form a metal gate such as the metal gate 112 depicted in FIGS. 1A-1E.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016512994A JP6562559B2 (en) | 2013-05-03 | 2014-05-05 | Gallium nitride field effect transistor |
CN201480024438.1A CN105164810B (en) | 2013-05-03 | 2014-05-05 | gallium nitride field effect transistor |
EP14792233.0A EP2992557A4 (en) | 2013-05-03 | 2014-05-05 | Gallium nitride field effect transistor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/886,744 US8916427B2 (en) | 2013-05-03 | 2013-05-03 | FET dielectric reliability enhancement |
US13/886,744 | 2013-05-03 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2014179809A1 true WO2014179809A1 (en) | 2014-11-06 |
Family
ID=51841004
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2014/036842 WO2014179809A1 (en) | 2013-05-03 | 2014-05-05 | Gallium nitride field effect transistor |
Country Status (5)
Country | Link |
---|---|
US (2) | US8916427B2 (en) |
EP (1) | EP2992557A4 (en) |
JP (2) | JP6562559B2 (en) |
CN (1) | CN105164810B (en) |
WO (1) | WO2014179809A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11682720B2 (en) | 2018-04-27 | 2023-06-20 | Sony Semiconductor Solutions Corporation | Switching transistor and semiconductor module to suppress signal distortion |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8916427B2 (en) * | 2013-05-03 | 2014-12-23 | Texas Instruments Incorporated | FET dielectric reliability enhancement |
US9941384B2 (en) | 2015-08-29 | 2018-04-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method for fabricating the same |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070010060A1 (en) * | 2005-07-07 | 2007-01-11 | Micron Technology, Inc. | Metal-substituted transistor gates |
US20080157220A1 (en) * | 2006-12-27 | 2008-07-03 | Sung Joong Joo | Semiconductor Device and Manufacturing Method Thereof |
EP2037491A1 (en) | 2006-06-21 | 2009-03-18 | Tokyo Electron Limited | METHOD OF FORMING TaSiN FILM |
US20110195569A1 (en) * | 2010-02-10 | 2011-08-11 | Kwangjin Moon | Semiconductor Device and Method for Forming the Same |
US20140042452A1 (en) | 2012-08-09 | 2014-02-13 | Texas Instruments Incorporated | Iii-nitride enhancement mode transistors with tunable and high gate-source voltage rating |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG116443A1 (en) | 2001-03-27 | 2005-11-28 | Semiconductor Energy Lab | Wiring and method of manufacturing the same, and wiring board and method of manufacturing the same. |
US7323376B2 (en) * | 2003-01-22 | 2008-01-29 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating a semiconductor device including a group III nitride semiconductor |
US20060151846A1 (en) * | 2005-01-13 | 2006-07-13 | International Business Machines Corporation | Method of forming HfSiN metal for n-FET applications |
JP4333652B2 (en) | 2005-08-17 | 2009-09-16 | 沖電気工業株式会社 | Ohmic electrode, ohmic electrode manufacturing method, field effect transistor, field effect transistor manufacturing method, and semiconductor device |
JP2007088342A (en) * | 2005-09-26 | 2007-04-05 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for manufacturing the same |
JP5386785B2 (en) | 2007-03-26 | 2014-01-15 | サンケン電気株式会社 | Semiconductor device and manufacturing method thereof |
JP2008270521A (en) * | 2007-04-20 | 2008-11-06 | Matsushita Electric Ind Co Ltd | Field-effect transistor |
WO2009012536A1 (en) * | 2007-07-20 | 2009-01-29 | Interuniversitair Microelektronica Centrum | Damascene contacts on iii-v cmos devices |
WO2009084376A1 (en) * | 2007-12-28 | 2009-07-09 | Nec Corporation | Semiconductor device and process for producing the semiconductor device |
KR101666910B1 (en) * | 2009-04-08 | 2016-10-17 | 이피션트 파워 컨버젼 코퍼레이션 | ENHANCEMENT MODE GaN HEMT DEVICE AND METHOD FOR FABRICATING THE SAME |
US9306050B2 (en) * | 2009-06-26 | 2016-04-05 | Cornell University | III-V semiconductor structures including aluminum-silicon nitride passivation |
US8105889B2 (en) | 2009-07-27 | 2012-01-31 | Cree, Inc. | Methods of fabricating transistors including self-aligned gate electrodes and source/drain regions |
JP5604087B2 (en) | 2009-11-27 | 2014-10-08 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
JP5626010B2 (en) | 2011-02-25 | 2014-11-19 | 富士通株式会社 | Semiconductor device, manufacturing method thereof, and power supply device |
US9070758B2 (en) | 2011-06-20 | 2015-06-30 | Imec | CMOS compatible method for manufacturing a HEMT device and the HEMT device thereof |
US8633094B2 (en) * | 2011-12-01 | 2014-01-21 | Power Integrations, Inc. | GaN high voltage HFET with passivation plus gate dielectric multilayer structure |
US9525054B2 (en) * | 2013-01-04 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | High electron mobility transistor and method of forming the same |
US8916427B2 (en) | 2013-05-03 | 2014-12-23 | Texas Instruments Incorporated | FET dielectric reliability enhancement |
-
2013
- 2013-05-03 US US13/886,744 patent/US8916427B2/en active Active
-
2014
- 2014-05-05 WO PCT/US2014/036842 patent/WO2014179809A1/en active Application Filing
- 2014-05-05 JP JP2016512994A patent/JP6562559B2/en active Active
- 2014-05-05 CN CN201480024438.1A patent/CN105164810B/en active Active
- 2014-05-05 EP EP14792233.0A patent/EP2992557A4/en not_active Ceased
- 2014-11-10 US US14/537,455 patent/US9112011B2/en active Active
-
2019
- 2019-03-12 JP JP2019044822A patent/JP7000641B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070010060A1 (en) * | 2005-07-07 | 2007-01-11 | Micron Technology, Inc. | Metal-substituted transistor gates |
EP2037491A1 (en) | 2006-06-21 | 2009-03-18 | Tokyo Electron Limited | METHOD OF FORMING TaSiN FILM |
US20080157220A1 (en) * | 2006-12-27 | 2008-07-03 | Sung Joong Joo | Semiconductor Device and Manufacturing Method Thereof |
US20110195569A1 (en) * | 2010-02-10 | 2011-08-11 | Kwangjin Moon | Semiconductor Device and Method for Forming the Same |
US20140042452A1 (en) | 2012-08-09 | 2014-02-13 | Texas Instruments Incorporated | Iii-nitride enhancement mode transistors with tunable and high gate-source voltage rating |
Non-Patent Citations (1)
Title |
---|
See also references of EP2992557A4 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11682720B2 (en) | 2018-04-27 | 2023-06-20 | Sony Semiconductor Solutions Corporation | Switching transistor and semiconductor module to suppress signal distortion |
Also Published As
Publication number | Publication date |
---|---|
US9112011B2 (en) | 2015-08-18 |
JP2016522991A (en) | 2016-08-04 |
US8916427B2 (en) | 2014-12-23 |
CN105164810B (en) | 2019-01-01 |
EP2992557A4 (en) | 2017-07-12 |
JP2019125802A (en) | 2019-07-25 |
EP2992557A1 (en) | 2016-03-09 |
US20140327047A1 (en) | 2014-11-06 |
CN105164810A (en) | 2015-12-16 |
US20150060949A1 (en) | 2015-03-05 |
JP7000641B2 (en) | 2022-01-19 |
JP6562559B2 (en) | 2019-08-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8766321B2 (en) | Self-aligned sidewall gate GaN HEMT | |
JP5491869B2 (en) | Group III nitride semiconductor devices | |
US20110140173A1 (en) | Low OHMIC contacts containing germanium for gallium nitride or other nitride-based power devices | |
CN100449784C (en) | Semiconductor device and its making method | |
WO2011156650A3 (en) | Low resistivity tungsten pvd with enhanced ionization and rf power coupling | |
US8698201B1 (en) | Gate metallization methods for self-aligned sidewall gate GaN HEMT | |
Ao et al. | Thermally stable TiN Schottky contact on AlGaN/GaN heterostructure | |
US8952421B2 (en) | RF power HEMT grown on a silicon or SiC substrate with a front-side plug connection | |
US20190067436A1 (en) | Silicide implants | |
EP2662884B1 (en) | Group 13 nitride semiconductor device and method of its manufacture | |
JP7000641B2 (en) | Gallium Nitride Field Effect Transistor | |
US20160284827A1 (en) | High electron mobility transistor with indium nitride layer | |
CA2829245A1 (en) | Systems and methods for ohmic contacts in silicon carbide devices | |
Xu et al. | Significant roles of low-temperature post-metallization annealing in solution-processed oxide thin-film transistors | |
CN109804458B (en) | Method and apparatus using PVD ruthenium | |
US20140124837A1 (en) | Nitride semiconductor device and method for manufacturing same | |
US9741578B2 (en) | Manufacturing method of semiconductor device | |
JP2024042046A (en) | Enhancement mode metal-insulator-semiconductor high electron mobility transistor | |
US20190148152A1 (en) | Method of forming semiconductor device using titanium-containing layer and device formed | |
US20080093631A1 (en) | Contact structure for semiconductor devices | |
CN105097900A (en) | Semiconductor device and manufacturing method | |
US20180076324A1 (en) | Method of contact formation between metal and semiconductor | |
TWI692804B (en) | Semiconductor device and methods for manufacturing the same | |
CN102867749A (en) | Method for forming MOS (metal oxide semiconductor) transistor | |
US6642133B2 (en) | Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201480024438.1 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 14792233 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
ENP | Entry into the national phase |
Ref document number: 2016512994 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2014792233 Country of ref document: EP |