WO2014174862A1 - Demodulator, demodulation method, and recording medium - Google Patents

Demodulator, demodulation method, and recording medium Download PDF

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Publication number
WO2014174862A1
WO2014174862A1 PCT/JP2014/051383 JP2014051383W WO2014174862A1 WO 2014174862 A1 WO2014174862 A1 WO 2014174862A1 JP 2014051383 W JP2014051383 W JP 2014051383W WO 2014174862 A1 WO2014174862 A1 WO 2014174862A1
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value
bit
signal
signal point
bits
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PCT/JP2014/051383
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French (fr)
Japanese (ja)
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勝 若杉
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日本電気株式会社
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Priority to JP2015513578A priority Critical patent/JP6075446B2/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/067—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing soft decisions, i.e. decisions together with an estimate of reliability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/45—Soft decoding, i.e. using symbol reliability information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
    • H04L1/0003—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate by switching between different modulation schemes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/38—Demodulator circuits; Receiver circuits

Definitions

  • the present invention relates to a demodulation device, a demodulation method, and a program, and more particularly, to a demodulation device, a demodulation method, and a program that demodulates a multi-level modulated signal.
  • a multilevel modulation method such as a 32QAM (Quadrature Amplitude ⁇ ⁇ ⁇ Modulation) method or a 64QAM method is known (see Patent Document 1).
  • FIG. 1 is a diagram showing a multi-level QAM transmission / reception circuit 100 of related technology.
  • the 16 QAM scheme is used as the multi-level QAM scheme will be described.
  • transmission data is 4-bit data, it represents one of 16 values.
  • 16 values are used as symbols.
  • FIG. 2 is a diagram showing the correspondence between 4-bit transmission data and symbols.
  • the 16 types of symbols (0) to (15) shown in FIG. 2 correspond in advance to 16 signal points (hereinafter referred to as “modulation signal points”) that are uniquely arranged on the IQ plane. It is attached.
  • the IQ plane is a signal plane (signal space) defined by the I axis and the Q axis.
  • the xy plane is used instead of the IQ plane.
  • the xy plane is defined by the x axis and the y axis.
  • FIG. 3 is a diagram showing an example of 16 modulation signal points arranged on the xy plane.
  • FIG. 4 is a diagram showing an example of the correspondence between the 16 modulation signal points shown in FIG. 3 and the 16 types of symbols shown in FIG. Note that the correspondence between modulation signal points and symbols as shown in FIG. 4 is also referred to as “QAM symbol arrangement”.
  • the signal point conversion circuit 101b converts the symbol from the channel coding circuit 101a to the coordinates (x, y) of the modulation signal point (hereinafter referred to as “corresponding modulation signal point”) corresponding to the symbol. Convert.
  • the signal point conversion circuit 101b outputs the coordinates (x, y) of the corresponding modulation signal point to the digital modulation circuit 101c.
  • the received signal point is affected by noise and waveform distortion mixed in the transmission path. For this reason, there is a high possibility that the reception signal point is shifted from the position of the modulation signal point shown in FIG.
  • the signal point inverse conversion circuit 102b determines a modulation signal point (symbol) corresponding to the reception signal point represented by the demodulated signal from the modulation signal points indicated in the QAM symbol arrangement.
  • this determination is also referred to as “symbol determination”.
  • the symbol judgment method includes hard judgment and soft judgment.
  • the symbol corresponding to the received signal is only judged as “+10” or “ ⁇ 10”.
  • the soft decision the symbol corresponding to the received signal is decided using a value in the range of ⁇ 10 to +10.
  • the soft decision result represents the hard decision result of the symbol and the likelihood of the hard decision result. For example, when the result of the hard decision is “+10”, the soft decision result is a positive value, and the soft decision result is closer to 0 as the likelihood of the hard decision result is lower. On the other hand, when the result of the hard decision is “ ⁇ 10”, the soft decision result is a negative value, and the soft decision result becomes a value closer to 0 as the likelihood of the hard decision result is lower.
  • the signal point inverse transform circuit 102b outputs the soft decision value of each of the 4 bits corresponding to the modulation signal point (symbol) determined by the symbol determination to the communication path decoding circuit 102c as a soft determination signal.
  • the channel decoding circuit 102c performs channel decoding (specifically, soft decision error correction decoding) using the soft decision signal to generate received data 100b.
  • the number of bits for which soft decision is performed is not m + n but n. For this reason, the method described in Patent Document 2 can simplify the determination process as compared with the case where soft determination is performed on m + n bits constituting a symbol, and thus the determination circuit for symbol determination can be simplified. become.
  • Patent Document 3 describes a log likelihood ratio calculation circuit that facilitates the calculation of a soft decision value (log likelihood ratio).
  • the log likelihood ratio calculation method for the one-dimensional dependent bit is the calculation of the log likelihood ratio of the two-dimensional dependent bit. It is simpler than the method. In other words, the log likelihood ratio calculation method for the two-dimensional dependent bits requires more complicated calculation than the log likelihood ratio calculation method for the one-dimensional dependent bits.
  • Patent Document 2 does not describe a specific method for simplifying the soft decision itself.
  • the demodulator of the present invention is Receiving signal point specifying means for receiving a multi-level modulated signal and specifying a receiving signal point on a signal plane based on the signal; Among the plurality of bits constituting the data specified from the received signal point, the specific bit whose boundary where the value of the bit changes in the signal plane is parallel to one of the two axes defining the signal plane is specified. Likelihood specifying means for specifying the likelihood of the value of the bit based on the distance between the received signal point and the boundary of the specific bit; Decoding means for soft decision decoding using the likelihood for the value of the specific bit; Among the data associated with each of a plurality of modulation signal points used in the multi-level modulation, a plurality of candidate data are specified using a value of the specific bit subjected to the soft decision decoding, and the plurality of modulations Among signal points, identify a plurality of candidate signal points corresponding to the plurality of candidate data, identify the corresponding signal point having the shortest distance to the received signal point from
  • the demodulation method of the present invention includes: A demodulation method performed by a demodulation device, Receiving a multi-level modulated signal, identifying a received signal point in the signal plane based on the signal, Among the plurality of bits constituting the data specified from the received signal point, the specific bit whose boundary where the value of the bit changes in the signal plane is parallel to one of the two axes defining the signal plane is specified Specifying the likelihood of the value of the bit based on the distance between the received signal point and the boundary of the specific bit; Soft-decision decoding using the likelihood for the value of the specific bit, Among the data associated with each of a plurality of modulation signal points used in the multi-level modulation, a plurality of candidate data are specified using a value of the specific bit subjected to the soft decision decoding, and the plurality of modulations Among signal points, identify a plurality of candidate signal points corresponding to the plurality of candidate data, identify the corresponding signal point having the shortest distance to the received signal point from the pluralit
  • the soft decision in the symbol determination process, it is possible to facilitate the soft decision to be executed while reducing the number of bits for executing the soft decision.
  • FIG. 1 is a diagram illustrating a multilevel QAM transmission / reception circuit 1 including a demodulation device according to a first embodiment of the present invention. It is the figure which showed the format of the transmission data used by this embodiment. It is the figure which showed the 5-bit data (symbol) input into the signal point conversion circuit 1a3.
  • FIG. 5 is a diagram showing a multilevel QAM transmission / reception circuit 1 including the demodulator according to the first embodiment of the present invention.
  • the multi-level QAM transmission / reception circuit 1 adopts the 32QAM system as the multi-level QAM system.
  • the multilevel QAM scheme employed by the multilevel QAM transceiver circuit 1 is not limited to the 32QAM scheme.
  • the multilevel QAM scheme may be a multilevel modulation scheme in which the number of modulation signal points is an odd power of 2, or a multilevel modulation scheme in which the number of modulation signal points is an even power of 2.
  • the multi-level QAM transmission / reception circuit 1 includes a transmission circuit 1a and a reception circuit 1b.
  • the transmission circuit 1a includes a communication path encoding circuit 1a1, a delay matching circuit 1a2, a signal point conversion circuit 1a3, and a digital modulation circuit 101c.
  • the communication path encoding circuit 1a1 receives bit data (hereinafter referred to as “first data”) for which soft decision is performed among transmission data, and performs communication path encoding on the data.
  • first data bit data
  • the channel coding circuit 1a1 uses an arbitrary block code as the channel code and outputs 2-bit data.
  • FIG. 6 is a diagram showing a format of transmission data used in the present embodiment.
  • the transmission data is 5-bit data.
  • the lower 2 bits (4SB (4th Significant Bit) and 5SB (5th Significant Bit)) data are used as the first data.
  • the upper 3 bits (MSB (Most (Significant Bit), 2SB (2nd Significant Bit)) and 3SB (3rd Significant Bit) data are used as bit data (hereinafter referred to as "second data") for which hard decision is performed. .
  • a check bit section into which check bits generated by block coding are inserted is set in advance.
  • the communication path encoding circuit 1a1 executes a block code on the first data.
  • the communication path encoding circuit 1a1 inserts a check bit in the check bit period of the first data.
  • the communication path encoding circuit 1a1 outputs the 2-bit data with the check bit inserted to the signal point conversion circuit 1a3.
  • the delay matching circuit 1a2 accepts second data (upper 3 bits of data) in the transmission data.
  • the delay matching circuit 1a2 delays the second data by the same time as the processing delay time generated in the communication path encoding circuit 1a1.
  • the delay matching circuit 1a2 outputs the delayed second data to the signal point conversion circuit 1a3.
  • FIG. 7 is a diagram showing 5-bit data (symbol) input to the signal point conversion circuit 1a3.
  • FIG. 8 is a diagram showing an example of 32 modulation signal points 4 arranged on the xy plane.
  • FIG. 9A is a diagram showing an example in which the MSB value of 5-bit data corresponding to each modulation signal point is arranged at each modulation signal point.
  • the value of 4SB changes depending on only the x coordinate of the x coordinate and the y coordinate. Therefore, the likelihood of the value of 4SB changes according to only the x coordinate of the x coordinate and the y coordinate. Therefore, the calculation of the likelihood of the 4SB value is easier than the calculation of the likelihood that the value changes depending on both the x coordinate and the y coordinate, such as MSB, 2SB, and 3SB.
  • the value of 5SB changes depending on only the y coordinate of the x coordinate and the y coordinate. Therefore, the likelihood of the value of 5SB changes according to only the y coordinate of the x coordinate and the y coordinate. Therefore, the calculation of the likelihood of the value of 5SB is similar to the calculation of the likelihood of the value of 4SB, and the likelihood that the value changes depending on both the x coordinate and the y coordinate such as MSB, 2SB, and 3SB. It becomes easier than calculation.
  • soft-decision decoding is performed on bits (4SB and 5SB) for which a soft-decision value representing the likelihood necessary for soft-decision decoding can be easily calculated.
  • Soft-decision decoding is not performed for bits (MSB, 2SB, 3SB) that make it difficult to calculate a soft-decision value that represents the likelihood required for soft-decision decoding.
  • the signal point conversion circuit 1a3 is represented by the 2-bit data from the communication path coding circuit 1a1 and the 3-bit data from the delay matching circuit 1a2 among the 32 modulation signal points.
  • a modulation signal point (corresponding modulation signal point) corresponding to 5-bit data (symbol) is specified.
  • the signal point conversion circuit 1a3 converts 5-bit data (symbol) into the coordinates (x, y) of the corresponding modulation signal point.
  • the signal point conversion circuit 1a3 outputs the coordinates (x, y) of the corresponding modulation signal point to the digital modulation circuit 101c.
  • the digital modulation circuit 101c modulates the amplitude of one of the two waves whose phases are orthogonal according to the x coordinate of the corresponding modulation signal point, and the amplitude of the other wave according to the y coordinate of the corresponding modulation signal point. To modulate.
  • the digital modulation circuit 101c combines two waves whose amplitudes are modulated to generate a modulation signal (multilevel modulation signal).
  • the modulation signal (multilevel modulation signal) is converted from a digital signal to an analog signal by the D / A converter 200 and transmitted from an antenna (not shown).
  • the receiving circuit 1b is an example of a demodulator.
  • the receiving circuit 1b performs soft-decision decoding on the bits (4SB and 5SB) for which the likelihood (soft-decision value representing the likelihood) necessary for soft-decision decoding is easy, and the likelihood necessary for the soft-decision decoding.
  • the bits (MSB, 2SB, 3SB) for which the calculation of the degree (soft decision value representing likelihood) is complicated the value is specified without performing soft decision decoding.
  • the digital demodulation circuit 102a receives the modulation signal (multilevel modulation signal) from the A / D conversion unit 300.
  • the digital demodulator circuit 102a demodulates the modulated signal to obtain a reception signal point (x coordinate, y coordinate).
  • the digital demodulation circuit 102a generates a demodulated signal that represents a reception signal point.
  • the digital demodulation circuit 102a outputs the demodulated signal to the signal point inverse conversion circuit 1b1 and the delay matching circuit 1b3.
  • the signal point inverse conversion circuit 1b1 is an example of likelihood specifying means.
  • the signal point reverse conversion circuit 1b1 specifies 5-bit data from the received signal point by hard decision. *
  • the signal point inverse transform circuit 1b1 includes an x-axis in which a boundary (a hard decision boundary) whose value changes in the xy plane defines the xy plane among five bits constituting data specified (hard decision) from the received signal point For each of 4SB and 5SB parallel to one of the y-axes, the likelihood of the value of the bit is specified based on the distance between the received signal point and the bit boundary.
  • the signal inverse conversion circuit 1b1 outputs the 4SB and 5SB values and the soft decision signal representing the likelihood to the communication path decoding circuit 1b2.
  • the communication path decoding circuit 1b2 is an example of a decoding unit.
  • the communication path decoding circuit 1b2 receives the soft decision signal and performs soft decision decoding on the 4SB and 5SB values using the likelihood of the 4SB and 5SB values.
  • the channel decoding circuit 1b2 performs soft decision block decoding as soft decision decoding.
  • the channel decoding circuit 1b2 uses the data representing the 4SB and 5SB values (for example, corresponding to the transmission data of the lower 2 bits shown in FIG. 7) whose errors are corrected by the soft decision block decoding, and the hard decision circuit 1b4. Output to.
  • the delay matching circuit 1b3 receives the demodulated signal from the digital demodulating circuit 102a and delays the demodulated signal by the same time as the total processing delay time generated in each of the signal point inverse transform circuit 1b1 and the communication path decoding circuit 1b2. To the hard decision circuit 1b4.
  • the hard decision circuit 1b4 is an example of a predetermined bit value specifying unit.
  • the hard decision circuit 1b4 has 8 types of data (hereinafter referred to as 4SB and 5SB) having 2 bits of data from the channel decoding circuit 1b2 among 32 types of data corresponding to 32 modulation signal points. (Referred to as “candidate data”).
  • the hard decision circuit 1b4 specifies eight modulation signal points corresponding to eight types of candidate data from among the 32 modulation signal points as a plurality of candidate point signals.
  • the hard decision circuit 1b4 uses the MSB, 2SB, and 3SB values of the data associated with the corresponding signal point as the 5-bit MSB, 2SB, and data constituting the data specified from the received signal point. It is specified as each value of 3SB.
  • the digital demodulation circuit 102a generates a demodulated signal representing a received signal point, and outputs the demodulated signal to the signal point inverse conversion circuit 1b1 and the delay matching circuit 1b3.
  • the signal point inverse transform circuit 1b1 When receiving the demodulated signal, the signal point inverse transform circuit 1b1 first performs a hard decision on the 5-bit value corresponding to the received signal point represented by the demodulated signal.
  • the signal point inverse transform circuit 1b1 performs soft decision decoding.
  • “00101” is specified as a symbol determination value (a hard determination value of 5-bit data) at the stage before the operation.
  • the signal point inverse conversion circuit 1b1 sets the 4SB value “0” and the 5SB value “1” to the reception signal point among the plurality of boundaries 50 (see FIGS. 9D and 9E) for the bit.
  • the distance between the nearest boundary and the received signal point is calculated, and the likelihood is calculated based on this distance.
  • This calculated distance becomes smaller as the received signal point is closer to the boundary. Also, the closer the received signal point is to the boundary, the lower the likelihood of the bit value specified from the received signal point. In other words, the smaller the calculated distance, the lower the likelihood of the bit value specified from the received signal point.
  • the signal point inverse conversion circuit 1b1 calculates the likelihood of the binary symbol “+” or “ ⁇ ” in each 1-bit shown in FIG. 9D and FIG. “+” Corresponds to the bit value “0”, and “ ⁇ ” corresponds to the bit value “1”.
  • the likelihood expression method will be described.
  • the symbol “+” is represented by a numerical value 1.000
  • the symbol “ ⁇ ” is represented by a numerical value 1.000
  • the likelihood of a certain bit value is included in a range from -1.000 to 1.000. It is expressed using a value that can be In this case, the likelihood of the bit value becomes smaller as the likelihood is closer to 0.000.
  • the signal point inverse transform circuit 1b1 brings the likelihood of the bit value closer to 0.000 as the distance between the boundary closest to the received signal point and the received signal point is smaller for 4SB and 5SB.
  • the signal point inverse transform circuit 1b1 determines the bit value of 4SB and 5SB as the distance between the boundary closest to the reception signal point and the reception signal point is closer to 1 ⁇ 2 of the shortest distance between the boundaries 50. The likelihood of is approaching 1.000 or -1.000.
  • the signal point inverse transform circuit 1b1 determines that the boundary between the reception signal point and the reception signal point is the closest.
  • the likelihood decreases from 1.000 to 0.000 as the distance decreases, and the likelihood decreases to 1.000 as the distance between the boundary closest to the reception signal point and the reception signal point approaches 1 ⁇ 2 of the shortest distance between the boundaries 50. Move closer.
  • the signal point inverse transform circuit 1b1 determines the boundary between the reception signal point and the boundary closest to the reception signal point. As the distance becomes smaller, the likelihood is made closer to 1.000 to 0.000, and as the distance between the boundary closest to the reception signal point and the reception signal point approaches 1 ⁇ 2 of the shortest distance between the boundaries 50, the likelihood becomes ⁇ Move closer to 1.000.
  • this likelihood also represents the hard decision result of the symbol. For example, if the hard decision result is “1” (ie, “ ⁇ ”), the likelihood is a negative value, whereas if the hard decision result is “0” (ie, “+”), the likelihood is Is a positive value.
  • the accuracy of the resolution of likelihood is set to the third decimal place, but the accuracy of the resolution of likelihood is not limited to this and can be changed as appropriate.
  • the signal point inverse transform circuit 1b1 calculates the likelihood for each value of 4SB and 5SB, it generates a soft decision signal representing each value of 4SB and 5SB and the likelihood.
  • the signal point inverse transform circuit 1b1 since the likelihood also represents each value (hard decision result) of 4SB and 5SB, the signal point inverse transform circuit 1b1 generates a soft decision signal representing the likelihood of 4SB and 5SB.
  • the signal point inverse transformation circuit 1b1 may include a log likelihood ratio calculation circuit described in Patent Document 3. In this case, the signal point inverse transformation circuit 1b1 outputs the output of the log likelihood ratio calculation circuit to the soft Used as a determination signal.
  • the communication path decoding circuit 1b2 When receiving the soft decision signal, the communication path decoding circuit 1b2 performs soft decision block decoding on the values of 4SB and 5SB using the likelihood of the values of 4SB and 5SB. By the soft decision block decoding in the communication path decoding circuit 1b2, the estimation of the values of 4SB and 5SB is completed.
  • the communication path decoding circuit 1b2 outputs data representing the values of 4SB and 5SB whose errors are corrected by the soft decision block decoding to the hard decision circuit 1b4.
  • the hard decision circuit 1b4 receives the data from the communication path decoding circuit 1b2 (data representing the values of 4SB and 5SB) and the signal from the delay alignment circuit 1b3 (signal representing the reception signal point), Used to identify MSB, 2SB and 3SB values.
  • FIG. 11 is a diagram showing an example of the hard decision circuit 1b4.
  • the hard decision circuit 1b4 includes eight upper 3 bits and lower 2 bit combination circuits 1b41, eight signal point conversion circuits 1b42, eight distance comparison circuits 1b43, and an output circuit 1b44. Circuit 1b45.
  • the eight upper 3-bit lower 2-bit combination circuits 1b41, the eight signal point conversion circuits 1b42, and the eight distance comparison circuits 1b43 correspond to each other individually.
  • the eight signal point conversion circuits 1b42 have the same configuration as the signal point conversion circuit 1a3 shown in FIG. 5, and correspond to the 5-bit data (candidate data) from the corresponding upper 3-bit lower 2-bit combination circuit 1b41.
  • the coordinates (x, y) of the corresponding modulation signal point (candidate signal point) are output.
  • FIG. 13 is a diagram showing eight candidate signal points when the value composed of 4SB and 5SB is “11”. The candidate signal points are indicated by hatching.
  • FIG. 14 is a diagram showing eight candidate signal points when the value composed of 4SB and 5SB is “00”. The candidate signal points are indicated by hatching.
  • FIG. 15 is a diagram showing eight candidate signal points when the value composed of 4SB and 5SB is “10”. The candidate signal points are indicated by hatching.
  • the eight distance comparison circuits 1b43 calculate the distance between the corresponding modulation signal point (candidate signal point) from the corresponding signal point conversion circuit 1b42 and the reception signal point.
  • the output circuit 1b44 identifies the distance comparison circuit 1b43 that has calculated the smallest distance among the eight distance comparison circuits 1b43, and supplies the upper 3 bits and the lower 2 bits combination circuit 1b41 corresponding to the identified distance comparison circuit 1b43.
  • the input upper 3 bits are output as MSB, 2SB and 3SB values.
  • the delay matching circuit 1b45 outputs the values of 4SB and 5SB indicated in the data from the communication path decoding circuit 1b2, and outputs the upper 3 bits and lower 2 bits combination circuit 1b41, the signal point conversion circuit 1b42, and the distance comparison circuit 1b43.
  • the processing delay time generated in each of the circuits 1b44 is delayed by the same time as the total time and output.
  • 5-bit data from the hard decision circuit 1b4 is treated as received data.
  • the signal point inverse transformation circuit 1b1 is a specific bit (4SB, 5SB) whose boundary whose value changes in the xy plane is parallel to one of the x axis and the y axis among a plurality of bits constituting the data specified from the received signal point. ), The likelihood of the value of the specific bit is specified based on the distance between the reception signal point and the boundary of the specific bit.
  • the communication path decoding circuit 1b2 performs soft decision decoding on the value of the specific bit using the likelihood of the value of the specific bit.
  • soft decision decoding is performed on specific bits (4SB and 5SB) for which the likelihood (soft decision result) necessary for soft decision decoding can be easily calculated, and the likelihood (soft decision result) necessary for soft decision decoding. ) Can be specified without performing soft-decision decoding for predetermined bits (MSB, 2SB, 3SB) that complicate calculation.
  • the soft decision to be executed can be facilitated while reducing the number of bits for executing the soft decision.
  • the QAM method (modulation signal point arrangement is a cross type) in which the number of modulation signal points is 2 (2n + 1) (where n is an integer of 2 or more ) , such as 32QAM, 128QAM, 512QAM, and 2048QAM. Since it can be applied in common, for example, it can also be applied to an adaptive modulation scheme in which n defining a modulation signal point is changed within an integer of 2 or more during data communication.
  • the present embodiment is applied to an adaptive modulation scheme in which n that defines a modulation signal point changes within an integer of 2 or more, it is desirable that the number of predetermined bits be constant regardless of the value of n.
  • the positions of the plurality of modulation signal points and the data corresponding to the plurality of modulation signal points are set so that the specific bit is the lower 2n-2 bits of the 2n + 1 bits of the data corresponding to the modulation signal points.
  • the number of predetermined bits is fixed to 3.
  • the present embodiment is particularly effective for a cross type, that is, a modulation method with the number of modulation signal points being an odd power of 2.
  • this embodiment is used for a square type, that is, a modulation method with an even power of 2 modulation signal points. Also good.
  • the configuration of the second embodiment is basically the same as the configuration of the first embodiment (the configuration shown in FIG. 5), but various functions are different as shown below due to the difference in modulation scheme.
  • the transmission data and the reception data are 7-bit data
  • the modulation signal point arrangement shape includes four modulation signal point areas in 32QAM shown in FIGS. 9A to 9D and FIG.
  • the signal is divided into signal point areas, and the number of modulation signal points and the number of areas are 128.
  • the bit having the complicated hard decision boundary 50a is the upper 3 bits of the MSB, 2SB, and 3SB, and the lower 4 bits are any bits, and the hard decision boundary 50 is either the x coordinate or the y coordinate. It becomes parallel with the kana.
  • the lower 4 bits are used as the specific bits, and the upper 3 bits are used as the predetermined bits.
  • FIG. 17 is a diagram showing eight candidate signal points when the value represented by the lower 4 bits is “0100”.
  • the hard decision circuit 1b4 executes the estimation of the upper 3 bits using the limit distance decoding method.
  • the hard decision circuit 1b4 executes the estimation of the upper 3 bits using the limit distance decoding method.
  • the basic 32QAM symbol arrangement (symbol arrangement shown in FIGS. 9A to 9D and FIG. 10) is adopted, and the specific bits are made the lower 6 bits and the lower 8 bits to make it complicated. It is possible to use a soft decision method that does not. In any case, the upper 3 bits are estimated in the same way as 32QAM and 128QAM.
  • the modulation method is a square type, that is, a modulation method in which the number of modulation signal points is an even power of 2 will be described focusing on differences from the first embodiment.
  • the 64QAM system will be described as an example of a modulation system whose number of modulation signal points is an even power of 2.
  • the configuration of the third embodiment is basically the same as the configuration of the first embodiment (configuration shown in FIG. 5), but various functions are different as shown below due to the difference in the modulation method.
  • transmission data and reception data are 6-bit data.
  • FIG. 18 is a diagram showing the arrangement of modulation signal points used in the third embodiment.
  • the lower 4 bits are used as the specific bits and the upper 2 bits are used as the predetermined bits.
  • four candidate signal points are generated for one value represented by the estimated lower 4 bits.
  • the transmission circuit 1a or the reception circuit 1b may be realized by a computer.
  • the computer reads and executes a program recorded on a recording medium such as a CD-ROM (Compact Disk Read Only Memory) that can be read by the computer, and has the functions of the transmission circuit 1a or the reception circuit 1b. Execute.
  • a recording medium such as a CD-ROM (Compact Disk Read Only Memory) that can be read by the computer, and has the functions of the transmission circuit 1a or the reception circuit 1b. Execute.
  • the recording medium is not limited to the CD-ROM and can be changed as appropriate.

Abstract

A demodulator includes: a first specification unit for specifying a received signal point on the basis of a multi-level modulation signal; a second specification unit for specifying a likelihood of the value of a specific bit, the hard decision boundary on a signal plane of the bit being parallel to one of two axes of the plane among a plurality of data bits specified from the received signal point, on the basis of a distance between the received signal point and the boundary of the specific bit; a decoding unit for performing soft-decision decoding using the likelihood with regard to the value of the specific bit; and a third specification unit for specifying, from among a plurality of modulation signal points, a plurality of candidate signal points corresponding to candidate data having the value of the decoded specific bit among data corresponding to each of modulation signal points, and specifying the value of a bit other than the specific bit by using data correlated with a candidate signal point from which the distance to the received signal point is shortest.

Description

復調装置、復調方法および記録媒体Demodulator, demodulation method and recording medium
　本発明は、復調装置、復調方法およびプログラムに関し、特には、多値変調された信号を復調する復調装置、復調方法およびプログラムに関する。 The present invention relates to a demodulation device, a demodulation method, and a program, and more particularly, to a demodulation device, a demodulation method, and a program that demodulates a multi-level modulated signal.
　無線通信用の多重伝送方式として、３２ＱＡＭ（Quadrature Amplitude Modulation：直交振幅変調）方式や６４ＱＡＭ方式等の多値変調方式が知られている（特許文献１参照）。 As a multiplex transmission method for wireless communication, a multilevel modulation method such as a 32QAM (Quadrature Amplitude と し て Modulation) method or a 64QAM method is known (see Patent Document 1).
　図１は、関連技術の多値ＱＡＭ送受信回路１００を示した図である。以下では、多値ＱＡＭ方式として１６ＱＡＭ方式が用いられた場合の例を説明する。 FIG. 1 is a diagram showing a multi-level QAM transmission / reception circuit 100 of related technology. In the following, an example in which the 16 QAM scheme is used as the multi-level QAM scheme will be described.
　多値ＱＡＭ送受信回路１００は、送信回路１０１と、受信回路１０２と、を含む。 The multi-level QAM transmission / reception circuit 100 includes a transmission circuit 101 and a reception circuit 102.
　送信回路１０１では、通信路符号化回路１０１ａは、送信データ１００ａを通信路符号化して４ビットを１組とする伝送データ（シンボル）を生成する。通信路符号化回路１０１ａは、伝送データ（シンボル）を信号点変換回路１０１ｂに出力する。 In the transmission circuit 101, the communication path encoding circuit 101a generates transmission data (symbols) that includes 4 bits as a set by performing communication path encoding on the transmission data 100a. The communication path encoding circuit 101a outputs the transmission data (symbol) to the signal point conversion circuit 101b.
　伝送データは、４ビットのデータであるので１６通りの値のいずれかを表す。１６ＱＡＭ方式では、１６通りの値がそれぞれシンボルとして用いられる。 Since transmission data is 4-bit data, it represents one of 16 values. In the 16QAM system, 16 values are used as symbols.
　図２は、４ビットの伝送データとシンボルとの対応を示した図である。 FIG. 2 is a diagram showing the correspondence between 4-bit transmission data and symbols.
　１６ＱＡＭ方式では、図２に示された１６種類のシンボル（０）～（１５）は、ＩＱ平面上にユニークに配置された１６個の信号点（以下「変調信号点」と称する）と予め対応づけられている。ＩＱ平面は、Ｉ軸とＱ軸にて規定された信号平面（信号空間）である。以下では、ＩＱ平面の代わりにｘｙ平面が用いられる。ｘｙ平面はｘ軸とｙ軸にて規定される。 In the 16QAM system, the 16 types of symbols (0) to (15) shown in FIG. 2 correspond in advance to 16 signal points (hereinafter referred to as “modulation signal points”) that are uniquely arranged on the IQ plane. It is attached. The IQ plane is a signal plane (signal space) defined by the I axis and the Q axis. In the following, the xy plane is used instead of the IQ plane. The xy plane is defined by the x axis and the y axis.
　図３は、ｘｙ平面上に配置された１６個の変調信号点の一例を示した図である。図４は、図３に示された１６個の変調信号点と図２に示された１６種類のシンボルとの対応の一例を示した図である。なお、図４に示されたような変調信号点とシンボルとの対応関係は「ＱＡＭシンボル配置」とも称される。 FIG. 3 is a diagram showing an example of 16 modulation signal points arranged on the xy plane. FIG. 4 is a diagram showing an example of the correspondence between the 16 modulation signal points shown in FIG. 3 and the 16 types of symbols shown in FIG. Note that the correspondence between modulation signal points and symbols as shown in FIG. 4 is also referred to as “QAM symbol arrangement”.
　送信回路１０１内の信号点変換回路１０１ｂは、ＱＡＭシンボル配置を記憶している。 The signal point conversion circuit 101b in the transmission circuit 101 stores the QAM symbol arrangement.
　信号点変換回路１０１ｂは、ＱＡＭシンボル配置に従って、通信路符号化回路１０１ａからのシンボルを、そのシンボルに対応する変調信号点（以下「対応変調信号点」と称する）の座標（ｘ、ｙ）に変換する。信号点変換回路１０１ｂは、対応変調信号点の座標（ｘ、ｙ）をディジタル変調回路１０１ｃに出力する。 In accordance with the QAM symbol arrangement, the signal point conversion circuit 101b converts the symbol from the channel coding circuit 101a to the coordinates (x, y) of the modulation signal point (hereinafter referred to as “corresponding modulation signal point”) corresponding to the symbol. Convert. The signal point conversion circuit 101b outputs the coordinates (x, y) of the corresponding modulation signal point to the digital modulation circuit 101c.
　ディジタル変調回路１０１ｃは、位相が直交する２つの波の一方の波の振幅を、対応変調信号点のｘ座標に応じて変調し、他方の波の振幅を、対応変調信号点のｙ座標に応じて変調する。ディジタル変調回路１０１ｃは、振幅が変調された２つの波を合成して変調信号（多値変調信号）を生成する。 The digital modulation circuit 101c modulates the amplitude of one of the two waves whose phases are orthogonal according to the x coordinate of the corresponding modulation signal point, and the amplitude of the other wave according to the y coordinate of the corresponding modulation signal point. To modulate. The digital modulation circuit 101c combines two waves whose amplitudes are modulated to generate a modulation signal (multilevel modulation signal).
　変調信号は、Ｄ／Ａ変換部２００にてディジタル信号からアナログ信号に変換され、不図示のアンテナから送信される。 The modulated signal is converted from a digital signal to an analog signal by the D / A converter 200 and transmitted from an antenna (not shown).
　受信回路１０２では、不図示のアンテナが、不図示の他の多値ＱＡＭ送受信回路から送信された変調信号を受信する。Ａ／Ｄ変換部３００は、受信された変調信号をアナログ信号からディジタル信号に変換する。 In the receiving circuit 102, an antenna (not shown) receives a modulated signal transmitted from another multilevel QAM transmission / reception circuit (not shown). The A / D converter 300 converts the received modulation signal from an analog signal to a digital signal.
　ディジタル復調回路１０２ａは、Ａ／Ｄ変換部３００からの変調信号を復調して、変調信号にて特定されるｘｙ平面上の座標（以下「受信信号点」と称する）を求める。ディジタル復調回路１０２ａは、受信信号点を表す復調信号を生成する。ディジタル復調回路１０２ａは、復調信号を信号点逆変換回路１０２ｂに出力する。 The digital demodulation circuit 102a demodulates the modulation signal from the A / D conversion unit 300 to obtain coordinates on the xy plane (hereinafter referred to as “reception signal point”) specified by the modulation signal. The digital demodulation circuit 102a generates a demodulated signal that represents a reception signal point. The digital demodulation circuit 102a outputs the demodulated signal to the signal point inverse conversion circuit 102b.
　なお、受信信号点は、伝送路等で混入する雑音や波形歪みの影響を受ける。このため、受信信号点は、図４に示した変調信号点の位置からずれる可能性が高い。 The received signal point is affected by noise and waveform distortion mixed in the transmission path. For this reason, there is a high possibility that the reception signal point is shifted from the position of the modulation signal point shown in FIG.
　信号点逆変換回路１０２ｂは、信号点変換回路１０１ｂが記憶しているＱＡＭシンボル配置と同一内容のＱＡＭシンボル配置を記憶している。 The signal point reverse conversion circuit 102b stores a QAM symbol arrangement having the same contents as the QAM symbol arrangement stored in the signal point conversion circuit 101b.
　信号点逆変換回路１０２ｂは、ＱＡＭシンボル配置に示された変調信号点の中から、復調信号が表す受信信号点に対応する変調信号点（シンボル）を判定する。以下、この判定を「シンボル判定」とも称する。 The signal point inverse conversion circuit 102b determines a modulation signal point (symbol) corresponding to the reception signal point represented by the demodulated signal from the modulation signal points indicated in the QAM symbol arrangement. Hereinafter, this determination is also referred to as “symbol determination”.
　シンボル判定の方式としては、硬判定と軟判定がある。 The symbol judgment method includes hard judgment and soft judgment.
　ここで、２値シンボルの要素を数値“＋１０”、“－１０”で定義している場合での硬判定と軟判定について説明する。 Here, the hard decision and the soft decision when the elements of the binary symbol are defined by numerical values “+10” and “−10” will be described.
　硬判定では、受信信号に対応するシンボルは“＋１０”または“－１０”としか判定されない。 In the hard decision, the symbol corresponding to the received signal is only judged as “+10” or “−10”.
　一方、軟判定では、受信信号に対応するシンボルは、－１０～＋１０の範囲の値を用いて判定される。さらに言えば、軟判定の結果は、シンボルの硬判定結果とその硬判定結果の尤度とを表す。例えば、硬判定の結果が“＋１０”である場合、軟判定結果は正の値となり、硬判定の結果の尤度が低いほど、軟判定結果は０に近い値となる。一方、硬判定の結果が“－１０”である場合、軟判定結果は負の値となり、硬判定の結果の尤度が低いほど、軟判定結果は０に近い値となる。 On the other hand, in the soft decision, the symbol corresponding to the received signal is decided using a value in the range of −10 to +10. Furthermore, the soft decision result represents the hard decision result of the symbol and the likelihood of the hard decision result. For example, when the result of the hard decision is “+10”, the soft decision result is a positive value, and the soft decision result is closer to 0 as the likelihood of the hard decision result is lower. On the other hand, when the result of the hard decision is “−10”, the soft decision result is a negative value, and the soft decision result becomes a value closer to 0 as the likelihood of the hard decision result is lower.
　軟判定は、硬判定よりも複雑な方式となるが、硬判定よりも高度な誤り訂正（軟判定誤り訂正復号）を採用できる。このため、多くの通信装置は、目標とする誤り率特性を達成するために、軟判定方式を採用している。 Soft decision is a more complicated method than hard decision, but advanced error correction (soft decision error correction decoding) can be adopted than hard decision. For this reason, many communication apparatuses employ a soft decision method in order to achieve a target error rate characteristic.
　以下、信号点逆変換回路１０２ｂでも軟判定方式が採用されているとする。 Hereinafter, it is assumed that the soft decision method is also adopted in the signal point inverse transformation circuit 102b.
　信号点逆変換回路１０２ｂは、シンボル判定にて判定された変調信号点（シンボル）に対応する４ビットの各ビットの軟判定値を、軟判定信号として通信路復号化回路１０２ｃに出力する。通信路復号化回路１０２ｃは、軟判定信号を用いて通信路復号（具体的には、軟判定誤り訂正復号）を実行して受信データ１００ｂを生成する。 The signal point inverse transform circuit 102b outputs the soft decision value of each of the 4 bits corresponding to the modulation signal point (symbol) determined by the symbol determination to the communication path decoding circuit 102c as a soft determination signal. The channel decoding circuit 102c performs channel decoding (specifically, soft decision error correction decoding) using the soft decision signal to generate received data 100b.
　特許文献２には、シンボル判定用の判定回路を簡略化するための手法が記載されている。 Patent Document 2 describes a technique for simplifying a determination circuit for symbol determination.
　特許文献２に記載の手法では、シンボルを構成するｍ＋ｎビットのデータが、硬判定が行われるビット（ｍビット）と軟判定が行われるビット（ｎビット）とに分けられる。ｎビットについては軟判定が実行され、残りのｍビットについては硬判定が実行される。 In the method described in Patent Document 2, m + n-bit data constituting a symbol is divided into a bit for which a hard decision is made (m bits) and a bit for which a soft decision is made (n bits). A soft decision is performed for n bits, and a hard decision is performed for the remaining m bits.
　特許文献２に記載の手法では、軟判定が実行されるビット数がｍ＋ｎではなくｎとなる。このため、特許文献２に記載の手法は、シンボルを構成するｍ＋ｎビットについて軟判定を行う場合に比べて、判定処理を簡略化でき、よって、シンボル判定用の判定回路を簡略化することが可能になる。 In the method described in Patent Document 2, the number of bits for which soft decision is performed is not m + n but n. For this reason, the method described in Patent Document 2 can simplify the determination process as compared with the case where soft determination is performed on m + n bits constituting a symbol, and thus the determination circuit for symbol determination can be simplified. become.
　また、特許文献３には、軟判定値（対数尤度比）の算出を容易にする対数尤度比演算回路が記載されている。 Patent Document 3 describes a log likelihood ratio calculation circuit that facilitates the calculation of a soft decision value (log likelihood ratio).
　この対数尤度比演算回路は、グレイ符号化による配置が実現されていないＱＡＭ変調方式の場合（例えば、シンボル数が２の奇数乗となるＱＡＭ変調方式の場合）、複数のビットを、ビット値の変化がｘ座標またはｙ座標のいずれか一方のみに依存するビット（以下「一次元依存ビット」と称する）と、ビットの値の変化がｘ座標とｙ座標の両方に依存するビット（以下「二次元依存ビット」と称する）と、に分ける。この対数尤度比演算回路は、一次元依存ビットと二次元依存ビットとで、対数尤度比の算出手法を切り替える。 This log-likelihood ratio calculation circuit is configured to convert a plurality of bits into bit values in the case of a QAM modulation method in which an arrangement by Gray coding is not realized (for example, in the case of a QAM modulation method in which the number of symbols is an odd power of 2). A bit whose change depends on only one of the x coordinate and the y coordinate (hereinafter referred to as “one-dimensional dependent bit”), and a bit whose change in the bit value depends on both the x coordinate and the y coordinate (hereinafter “ This is referred to as a “two-dimensional dependent bit”. This log likelihood ratio calculation circuit switches the method of calculating the log likelihood ratio between the one-dimensional dependent bit and the two-dimensional dependent bit.
　一次元依存ビットの値の変化は、二次元依存ビットの値の変化よりも複雑ではないので、一次元依存ビットの対数尤度比の算出手法は、二次元依存ビットの対数尤度比の算出手法よりも簡略化されている。換言すると、二次元依存ビットについての対数尤度比の算出手法は、一次元依存ビットについての対数尤度比の算出手法よりも、複雑な計算を必要とする。 Since the change in the value of the one-dimensional dependent bit is less complicated than the change in the value of the two-dimensional dependent bit, the log likelihood ratio calculation method for the one-dimensional dependent bit is the calculation of the log likelihood ratio of the two-dimensional dependent bit. It is simpler than the method. In other words, the log likelihood ratio calculation method for the two-dimensional dependent bits requires more complicated calculation than the log likelihood ratio calculation method for the one-dimensional dependent bits.
特開２００３－１７９６５７号公報JP 2003-179657 A 特開２００６－７４８１７号公報JP 2006-74817 A 国際公開２００８／０３８７４９号International Publication No. 2008/038749
　特許文献２に記載の手法は、軟判定を実行するビット数を少なくすることによって、シンボル判定処理を簡略化している。 The technique described in Patent Document 2 simplifies symbol determination processing by reducing the number of bits for executing soft determination.
　しかしながら、特許文献２には、軟判定自体を簡略化する具体的な手法は記載されていない。 However, Patent Document 2 does not describe a specific method for simplifying the soft decision itself.
　特許文献２に記載の軟判定を簡略化するために、特許文献３に記載の手法を用いることが考えられるが、この場合、二次元依存ビットの軟判定については複雑な計算が必要となるという課題があった。 In order to simplify the soft decision described in Patent Document 2, it is conceivable to use the method described in Patent Document 3, but in this case, a complicated calculation is required for the soft decision of two-dimensional dependent bits. There was a problem.
　本発明の目的は、上記課題を解決可能な復調装置、復調方法およびプログラムを提供することである。 An object of the present invention is to provide a demodulation device, a demodulation method, and a program that can solve the above-described problems.
　本発明の復調装置は、
　多値変調された信号を受信し、当該信号に基づいて信号平面での受信信号点を特定する受信信号点特定手段と、
　前記受信信号点から特定されるデータを構成する複数のビットのうち、前記信号平面において前記ビットの値が変化する境界が前記信号平面を規定する２軸の一方と平行な特定ビットについて、当該特定ビットの値の尤度を、前記受信信号点と当該特定ビットの前記境界との距離に基づいて特定する尤度特定手段と、
　前記特定ビットの値について前記尤度を用いて軟判定復号する復号手段と、
　前記多値変調で使用される複数の変調信号点の各々に対応づけられたデータの中から、前記軟判定復号された特定ビットの値を用いて複数の候補データを特定し、前記複数の変調信号点の中から、前記複数の候補データに対応する複数の候補信号点を特定し、前記複数の候補信号点の中から、前記受信信号点までの距離が最も短い該当信号点を特定し、前記該当信号点に対応づけられたデータを用いて、前記複数のビットのうち前記特定ビット以外のビットである所定ビットの値を特定する所定ビット値特定手段と、を含む。 The demodulator of the present invention is
Receiving signal point specifying means for receiving a multi-level modulated signal and specifying a receiving signal point on a signal plane based on the signal;
Among the plurality of bits constituting the data specified from the received signal point, the specific bit whose boundary where the value of the bit changes in the signal plane is parallel to one of the two axes defining the signal plane is specified Likelihood specifying means for specifying the likelihood of the value of the bit based on the distance between the received signal point and the boundary of the specific bit;
Decoding means for soft decision decoding using the likelihood for the value of the specific bit;
Among the data associated with each of a plurality of modulation signal points used in the multi-level modulation, a plurality of candidate data are specified using a value of the specific bit subjected to the soft decision decoding, and the plurality of modulations Among signal points, identify a plurality of candidate signal points corresponding to the plurality of candidate data, identify the corresponding signal point having the shortest distance to the received signal point from the plurality of candidate signal points, And predetermined bit value specifying means for specifying a value of a predetermined bit that is a bit other than the specific bit among the plurality of bits using data associated with the corresponding signal point.
　本発明の復調方法は、
　復調装置が行う復調方法であって、
　多値変調された信号を受信し、当該信号に基づいて信号平面での受信信号点を特定し、
　前記受信信号点から特定されるデータを構成する複数のビットのうち、前記信号平面において前記ビットの値が変化する境界が前記信号平面を規定する２軸の一方と平行な特定ビットについて、当該特定ビットの値の尤度を、前記受信信号点と当該特定ビットの前記境界との距離に基づいて特定し、
　前記特定ビットの値について前記尤度を用いて軟判定復号し、
　前記多値変調で使用される複数の変調信号点の各々に対応づけられたデータの中から、前記軟判定復号された特定ビットの値を用いて複数の候補データを特定し、前記複数の変調信号点の中から、前記複数の候補データに対応する複数の候補信号点を特定し、前記複数の候補信号点の中から、前記受信信号点までの距離が最も短い該当信号点を特定し、前記該当信号点に対応づけられたデータを用いて、前記複数のビットのうち前記特定ビット以外のビットである所定ビットの値を特定する。 The demodulation method of the present invention includes:
A demodulation method performed by a demodulation device,
Receiving a multi-level modulated signal, identifying a received signal point in the signal plane based on the signal,
Among the plurality of bits constituting the data specified from the received signal point, the specific bit whose boundary where the value of the bit changes in the signal plane is parallel to one of the two axes defining the signal plane is specified Specifying the likelihood of the value of the bit based on the distance between the received signal point and the boundary of the specific bit;
Soft-decision decoding using the likelihood for the value of the specific bit,
Among the data associated with each of a plurality of modulation signal points used in the multi-level modulation, a plurality of candidate data are specified using a value of the specific bit subjected to the soft decision decoding, and the plurality of modulations Among signal points, identify a plurality of candidate signal points corresponding to the plurality of candidate data, identify the corresponding signal point having the shortest distance to the received signal point from the plurality of candidate signal points, A value of a predetermined bit that is a bit other than the specific bit among the plurality of bits is specified using data associated with the signal point.
　本発明の記録媒体は、
　コンピュータに、
　多値変調された信号を受信し、当該信号に基づいて信号平面での受信信号点を特定する受信信号点特定手順と、
　前記受信信号点から特定されるデータを構成する複数のビットのうち、前記信号平面において前記ビットの値が変化する境界が前記信号平面を規定する２軸の一方と平行な特定ビットについて、当該特定ビットの値の尤度を、前記受信信号点と当該特定ビットの前記境界との距離に基づいて特定する尤度特定手順と、
　前記特定ビットの値について前記尤度を用いて軟判定復号する復号手順と、
　前記多値変調で使用される複数の変調信号点の各々に対応づけられたデータの中から、前記軟判定復号された特定ビットの値を用いて複数の候補データを特定し、前記複数の変調信号点の中から、前記複数の候補データに対応する複数の候補信号点を特定し、前記複数の候補信号点の中から、前記受信信号点までの距離が最も短い該当信号点を特定し、前記該当信号点に対応づけられたデータを用いて、前記複数のビットのうち前記特定ビット以外のビットである所定ビットの値を特定する所定ビット値特定手順と、を実行させるプログラムを記録したコンピュータ読み取り可能な記録媒体である。 The recording medium of the present invention is
On the computer,
A received signal point specifying procedure for receiving a multi-level modulated signal and specifying a received signal point on a signal plane based on the signal;
Among the plurality of bits constituting the data specified from the received signal point, the specific bit whose boundary where the value of the bit changes in the signal plane is parallel to one of the two axes defining the signal plane is specified A likelihood specifying procedure for specifying the likelihood of the value of a bit based on the distance between the received signal point and the boundary of the specific bit;
A decoding procedure for soft decision decoding using the likelihood for the value of the specific bit;
Among the data associated with each of a plurality of modulation signal points used in the multi-level modulation, a plurality of candidate data are specified using a value of the specific bit subjected to the soft decision decoding, and the plurality of modulations Among signal points, identify a plurality of candidate signal points corresponding to the plurality of candidate data, identify the corresponding signal point having the shortest distance to the received signal point from the plurality of candidate signal points, A computer recording a program for executing a predetermined bit value specifying procedure for specifying a value of a predetermined bit that is a bit other than the specific bit among the plurality of bits using data associated with the corresponding signal point It is a readable recording medium.
　本発明によれば、シンボル判定処理において、軟判定を実行するビット数を少なくしつつ、実行される軟判定を容易にすることが可能になる。 According to the present invention, in the symbol determination process, it is possible to facilitate the soft decision to be executed while reducing the number of bits for executing the soft decision.
関連技術の多値ＱＡＭ送受信回路１００を示した図である。It is the figure which showed the multi-value QAM transmission / reception circuit 100 of related technology. ４ビットの伝送データとシンボルとの対応を示した図である。It is the figure which showed the response | compatibility with 4-bit transmission data and a symbol. ｘｙ平面上に配置された１６個の変調信号点の一例を示した図である。It is the figure which showed an example of 16 modulation signal points arrange | positioned on xy plane. 変調信号点とシンボルとの対応関係の一例を示した図である。It is the figure which showed an example of the correspondence of a modulation signal point and a symbol. 本発明の第１実施形態の復調装置を含む多値ＱＡＭ送受信回路１を示した図である。1 is a diagram illustrating a multilevel QAM transmission / reception circuit 1 including a demodulation device according to a first embodiment of the present invention. 本実施形態で用いられる送信データのフォーマットを示した図である。It is the figure which showed the format of the transmission data used by this embodiment. 信号点変換回路１ａ３に入力される５ビットのデータ（シンボル）を示した図である。It is the figure which showed the 5-bit data (symbol) input into the signal point conversion circuit 1a3. ｘｙ平面上に配置された３２個の変調信号点４の一例を示した図である。It is the figure which showed an example of the 32 modulation signal points 4 arrange | positioned on xy plane. 各変調信号点に、その変調信号点に対応する５ビットのデータのうち、ＭＳＢの値を配置した例を示した図である。It is the figure which showed the example which has arrange | positioned the value of MSB among 5-bit data corresponding to the modulation signal point to each modulation signal point. 各変調信号点に、その変調信号点に対応する５ビットのデータのうち、２ＳＢの値を配置した例を示した図である。It is the figure which showed the example which has arrange | positioned the value of 2SB among the 5-bit data corresponding to the modulation signal point to each modulation signal point. 各変調信号点に、その変調信号点に対応する５ビットのデータのうち、３ＳＢの値を配置した例を示した図である。It is the figure which showed the example which has arrange | positioned the value of 3SB among the 5-bit data corresponding to the modulation signal point to each modulation signal point. 各変調信号点に、その変調信号点に対応する５ビットのデータのうち、４ＳＢの値を配置した例を示した図である。It is the figure which showed the example which has arrange | positioned the value of 4SB among the 5-bit data corresponding to the modulation signal point to each modulation signal point. 各変調信号点に、その変調信号点に対応する５ビットのデータのうち、５ＳＢの値を配置した例を示した図である。It is the figure which showed the example which has arrange | positioned the value of 5SB among the 5-bit data corresponding to the modulation signal point to each modulation signal point. ３２ＱＡＭ受信コンスタレーションの一例を示した図である。It is the figure which showed an example of 32QAM reception constellation. 硬判定回路１ｂ４の一例を示した図である。It is the figure which showed an example of the hard decision circuit 1b4. ４ＳＢ、５ＳＢにて構成される値が“01”であった場合の候補信号点を示した図である。It is the figure which showed the candidate signal point when the value comprised by 4SB and 5SB is "01". ４ＳＢ、５ＳＢにて構成される値が“11”であった場合の候補信号点を示した図である。It is the figure which showed the candidate signal point when the value comprised by 4SB and 5SB was "11". ４ＳＢ、５ＳＢにて構成される値が“00”であった場合の候補信号点を示した図である。It is the figure which showed the candidate signal point when the value comprised by 4SB and 5SB was "00". ４ＳＢ、５ＳＢにて構成される値が“10”であった場合の候補信号点を示した図である。It is the figure which showed the candidate signal point when the value comprised by 4SB and 5SB is "10". １２８ＱＡＭ受信コンスタレーションの一例を示した図である。It is the figure which showed an example of 128QAM reception constellation. 下位の４ビットが表す値が“0100”であった場合の候補信号点を示した図である。It is the figure which showed the candidate signal point when the value which the low-order 4 bits represent is “0100”. ６４ＱＡＭでの変調信号点とシンボルとの対応関係の一例を示した図である。It is the figure which showed an example of the correspondence of the modulation signal point and symbol in 64QAM.
　以下、本発明の実施形態について図面を参照して説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　（第１実施形態）
　図５は、本発明の第１実施形態の復調装置を含む多値ＱＡＭ送受信回路１を示した図である。なお、図５において、図１に示したものと同一構成のものには同一符号を付してある。 (First embodiment)
FIG. 5 is a diagram showing a multilevel QAM transmission / reception circuit 1 including the demodulator according to the first embodiment of the present invention. In FIG. 5, the same components as those shown in FIG.
　多値ＱＡＭ送受信回路１は、多値ＱＡＭ方式として３２ＱＡＭ方式を採用する。なお、多値ＱＡＭ送受信回路１が採用する多値ＱＡＭ方式は、３２ＱＡＭ方式に限らない。多値ＱＡＭ方式は、変調信号点の数が２の奇数乗である多値変調方式であってもよく、変調信号点の数が２の偶数乗である多値変調方式であってもよい。 The multi-level QAM transmission / reception circuit 1 adopts the 32QAM system as the multi-level QAM system. Note that the multilevel QAM scheme employed by the multilevel QAM transceiver circuit 1 is not limited to the 32QAM scheme. The multilevel QAM scheme may be a multilevel modulation scheme in which the number of modulation signal points is an odd power of 2, or a multilevel modulation scheme in which the number of modulation signal points is an even power of 2.
　多値ＱＡＭ送受信回路１は、送信回路１ａと、受信回路１ｂと、を含む。 The multi-level QAM transmission / reception circuit 1 includes a transmission circuit 1a and a reception circuit 1b.
　送信回路１ａは、通信路符号化回路１ａ１と、遅延合わせ回路１ａ２と、信号点変換回路１ａ３と、ディジタル変調回路１０１ｃと、を含む。 The transmission circuit 1a includes a communication path encoding circuit 1a1, a delay matching circuit 1a2, a signal point conversion circuit 1a3, and a digital modulation circuit 101c.
　受信回路１ｂは、ディジタル復調回路１０２ａと、信号点逆変換回路１ｂ１と、通信路復号化回路１ｂ２と、遅延合わせ回路１ｂ３と、硬判定回路１ｂ４と、を含む。 The reception circuit 1b includes a digital demodulation circuit 102a, a signal point inverse conversion circuit 1b1, a communication path decoding circuit 1b2, a delay matching circuit 1b3, and a hard decision circuit 1b4.
　まず、送信回路１ａについて説明する。 First, the transmission circuit 1a will be described.
　通信路符号化回路１ａ１は、送信データのうち、軟判定が行われるビットのデータ（以下「第１データ」と称する）を受け付け、そのデータについて通信路符号化を行う。本実施形態では、通信路符号化回路１ａ１は、通信路符号として任意のブロック符号を用い、２ビットのデータを出力する。 The communication path encoding circuit 1a1 receives bit data (hereinafter referred to as “first data”) for which soft decision is performed among transmission data, and performs communication path encoding on the data. In the present embodiment, the channel coding circuit 1a1 uses an arbitrary block code as the channel code and outputs 2-bit data.
　図６は、本実施形態で用いられる送信データのフォーマットを示した図である。 FIG. 6 is a diagram showing a format of transmission data used in the present embodiment.
　図６に示すように、送信データは５ビットのデータである。下位２ビット（４ＳＢ（4th Significant Bit）と５ＳＢ（5th Significant Bit））のデータが、第１データとして用いられる。上位３ビット（ＭＳＢ（Most Significant Bit）と２ＳＢ（2nd Significant Bit）と３ＳＢ（3rd Significant Bit））のデータが、硬判定が行われるビットのデータ（以下「第２データ」と称する）として用いられる。 As shown in FIG. 6, the transmission data is 5-bit data. The lower 2 bits (4SB (4th Significant Bit) and 5SB (5th Significant Bit)) data are used as the first data. The upper 3 bits (MSB (Most （Significant Bit), 2SB (2nd Significant Bit)) and 3SB (3rd Significant Bit) data are used as bit data (hereinafter referred to as "second data") for which hard decision is performed. .
　第１データには、ブロック符号化にて生成される検査ビットが挿入される検査ビット区間が予め設定されている。 In the first data, a check bit section into which check bits generated by block coding are inserted is set in advance.
　通信路符号化回路１ａ１は、第１データに対してブロック符号を実行する。通信路符号化回路１ａ１は、第１データの検査ビット期間に検査ビットを挿入する。通信路符号化回路１ａ１は、検査ビットが挿入された２ビットのデータを信号点変換回路１ａ３に出力する。 The communication path encoding circuit 1a1 executes a block code on the first data. The communication path encoding circuit 1a1 inserts a check bit in the check bit period of the first data. The communication path encoding circuit 1a1 outputs the 2-bit data with the check bit inserted to the signal point conversion circuit 1a3.
　遅延合わせ回路１ａ２は、送信データのうち、第２データ（上位３ビットのデータ）を受け付ける。遅延合わせ回路１ａ２は、第２データを、通信路符号化回路１ａ１で発生する処理遅延時間と同じ時間遅延させる。遅延合わせ回路１ａ２は、遅延された第２データを信号点変換回路１ａ３に出力する。 The delay matching circuit 1a2 accepts second data (upper 3 bits of data) in the transmission data. The delay matching circuit 1a2 delays the second data by the same time as the processing delay time generated in the communication path encoding circuit 1a1. The delay matching circuit 1a2 outputs the delayed second data to the signal point conversion circuit 1a3.
　信号点変換回路１ａ３は、通信路符号化回路１ａ１から出力された２ビットのデータと遅延合わせ回路１ａ２から出力された３ビットのデータとで表される５ビットのデータを、シンボルとして受け付ける。 The signal point conversion circuit 1a3 accepts, as a symbol, 5-bit data represented by 2-bit data output from the communication path encoding circuit 1a1 and 3-bit data output from the delay alignment circuit 1a2.
　図７は、信号点変換回路１ａ３に入力される５ビットのデータ（シンボル）を示した図である。 FIG. 7 is a diagram showing 5-bit data (symbol) input to the signal point conversion circuit 1a3.
　図７において、信号点変換回路１ａ３に入力される５ビットのデータでは、検査ビット区間に検査ビットが挿入されている。 In FIG. 7, in the 5-bit data input to the signal point conversion circuit 1a3, a check bit is inserted in the check bit section.
　信号点変換回路１ａ３は、５ビットのデータにて表される３２通りのデータと、ｘｙ平面に予め設定された３２個の変調信号点と、の１対１の対応関係（ＱＡＭシンボル配置）を予め記憶している。 The signal point conversion circuit 1a3 has a one-to-one correspondence (QAM symbol arrangement) between 32 types of data represented by 5-bit data and 32 modulation signal points preset on the xy plane. Pre-stored.
　図８は、ｘｙ平面上に配置された３２個の変調信号点４の一例を示した図である。 FIG. 8 is a diagram showing an example of 32 modulation signal points 4 arranged on the xy plane.
　図９Ａ～図９Ｅは、３２個の変調信号点と５ビットのデータ（シンボル）との対応関係を示した図である。なお、図９Ａ～図９Ｅにおいて、「＋」はビット値が「０」であることを示し、「－」はビット値が「１」であることを示す。 FIGS. 9A to 9E are diagrams showing the correspondence between 32 modulation signal points and 5-bit data (symbols). 9A to 9E, “+” indicates that the bit value is “0”, and “−” indicates that the bit value is “1”.
　図９Ａは、各変調信号点に、その変調信号点に対応する５ビットのデータのうち、ＭＳＢの値を配置した例を示した図である。 FIG. 9A is a diagram showing an example in which the MSB value of 5-bit data corresponding to each modulation signal point is arranged at each modulation signal point.
　図９Ｂ、図９Ｃ、図９Ｄおよび図９Ｅは、それぞれ、各変調信号点に、その変調信号点に対応する５ビットのデータのうち、２ＳＢの値、３ＳＢの値、４ＳＢの値、５ＳＢの値を配置した例を示した図である。 9B, FIG. 9C, FIG. 9D, and FIG. 9E show, for each modulation signal point, 2SB value, 3SB value, 4SB value, and 5SB value among 5-bit data corresponding to the modulation signal point, respectively. It is the figure which showed the example which has arrange | positioned.
　ここで、本実施形態でのＱＡＭシンボル配置について説明する。 Here, the QAM symbol arrangement in this embodiment will be described.
　図９Ａ、図９Ｂおよび図９Ｃに示したように、ＭＳＢ、２ＳＢ、３ＳＢでは、ｘｙ平面においてビット値が変化する境界（硬判定境界）として、ｘ座標とｙ座標の両方に依存して傾きが変化する境界５０ａが含まれる。 As shown in FIG. 9A, FIG. 9B, and FIG. 9C, in MSB, 2SB, and 3SB, as the boundary where the bit value changes in the xy plane (hard decision boundary), the inclination depends on both the x coordinate and the y coordinate. A changing boundary 50a is included.
　これに対して、図９Ｄに示したように、４ＳＢでは、ｘ座標とｙ座標の両方に依存して傾きが変化する境界５０ａはなく、境界（硬判定境界）５０ａがｙ軸と平行になっている。 On the other hand, as shown in FIG. 9D, in 4SB, there is no boundary 50a whose inclination changes depending on both the x coordinate and the y coordinate, and the boundary (hard decision boundary) 50a is parallel to the y axis. ing.
　このため、４ＳＢの値は、ｘ座標とｙ座標のうちｘ座標にのみ依存して変化する。よって、４ＳＢの値の尤度は、ｘ座標とｙ座標のうちｘ座標のみに応じて変化することになる。したがって、４ＳＢの値の尤度の算出は、ＭＳＢ、２ＳＢ、３ＳＢのようにｘ座標とｙ座標の両方に依存して値が変化する尤度の算出よりも容易になる。 For this reason, the value of 4SB changes depending on only the x coordinate of the x coordinate and the y coordinate. Therefore, the likelihood of the value of 4SB changes according to only the x coordinate of the x coordinate and the y coordinate. Therefore, the calculation of the likelihood of the 4SB value is easier than the calculation of the likelihood that the value changes depending on both the x coordinate and the y coordinate, such as MSB, 2SB, and 3SB.
　また、図９Ｅに示したように、５ＳＢでも、ｘ座標とｙ座標の両方に依存して変化する境界５０ａはなく、境界（硬判定境界）５０ａがｘ軸と平行になっている。 As shown in FIG. 9E, even in 5SB, there is no boundary 50a that changes depending on both the x coordinate and the y coordinate, and the boundary (hard decision boundary) 50a is parallel to the x axis.
　このため、５ＳＢの値は、ｘ座標とｙ座標のうちｙ座標にのみ依存して変化する。よって、５ＳＢの値の尤度は、ｘ座標とｙ座標のうちｙ座標のみに応じて変化することになる。したがって、５ＳＢの値の尤度の算出は、４ＳＢの値の尤度の算出と同様に、ＭＳＢ、２ＳＢ、３ＳＢのようにｘ座標とｙ座標の両方に依存して値が変化する尤度の算出よりも容易になる。 Therefore, the value of 5SB changes depending on only the y coordinate of the x coordinate and the y coordinate. Therefore, the likelihood of the value of 5SB changes according to only the y coordinate of the x coordinate and the y coordinate. Therefore, the calculation of the likelihood of the value of 5SB is similar to the calculation of the likelihood of the value of 4SB, and the likelihood that the value changes depending on both the x coordinate and the y coordinate such as MSB, 2SB, and 3SB. It becomes easier than calculation.
　本実施形態では、軟判定復号に必要となる尤度を表す軟判定値の算出が容易なビット（４ＳＢおよび５ＳＢ）については、軟判定復号が行われる。軟判定復号に必要となる尤度を表す軟判定値の算出が複雑になるビット（ＭＳＢ、２ＳＢ、３ＳＢ）については、軟判定復号が行われない。 In this embodiment, soft-decision decoding is performed on bits (4SB and 5SB) for which a soft-decision value representing the likelihood necessary for soft-decision decoding can be easily calculated. Soft-decision decoding is not performed for bits (MSB, 2SB, 3SB) that make it difficult to calculate a soft-decision value that represents the likelihood required for soft-decision decoding.
　また、３２個の変調信号点のうち、４ＳＢの値と５ＳＢの値とが共通する５ビットのデータ（シンボル）に対応する８個の変調信号点について説明すると、８個の変調信号点間の距離は等しくなっている。 Further, of the 32 modulation signal points, 8 modulation signal points corresponding to 5-bit data (symbol) having a common 4SB value and 5SB value will be described. The distance is equal.
　図５に戻って、信号点変換回路１ａ３は、３２個の変調信号点の中から、通信路符号化回路１ａ１からの２ビットのデータと遅延合わせ回路１ａ２からの３ビットのデータとで表される５ビットのデータ（シンボル）に対応する変調信号点（対応変調信号点）を特定する。 Returning to FIG. 5, the signal point conversion circuit 1a3 is represented by the 2-bit data from the communication path coding circuit 1a1 and the 3-bit data from the delay matching circuit 1a2 among the 32 modulation signal points. A modulation signal point (corresponding modulation signal point) corresponding to 5-bit data (symbol) is specified.
　信号点変換回路１ａ３は、５ビットのデータ（シンボル）を対応変調信号点の座標（ｘ、ｙ）に変換する。信号点変換回路１ａ３は、対応変調信号点の座標（ｘ、ｙ）をディジタル変調回路１０１ｃに出力する。 The signal point conversion circuit 1a3 converts 5-bit data (symbol) into the coordinates (x, y) of the corresponding modulation signal point. The signal point conversion circuit 1a3 outputs the coordinates (x, y) of the corresponding modulation signal point to the digital modulation circuit 101c.
　ディジタル変調回路１０１ｃは、位相が直交する２つの波の一方の波の振幅を、対応変調信号点のｘ座標に応じて変調し、他方の波の振幅を、対応変調信号点のｙ座標に応じて変調する。ディジタル変調回路１０１ｃは、振幅が変調された２つの波を合成して変調信号（多値変調信号）を生成する。 The digital modulation circuit 101c modulates the amplitude of one of the two waves whose phases are orthogonal according to the x coordinate of the corresponding modulation signal point, and the amplitude of the other wave according to the y coordinate of the corresponding modulation signal point. To modulate. The digital modulation circuit 101c combines two waves whose amplitudes are modulated to generate a modulation signal (multilevel modulation signal).
　変調信号（多値変調信号）は、Ｄ／Ａ変換部２００にてディジタル信号からアナログ信号に変換され、不図示のアンテナから送信される。 The modulation signal (multilevel modulation signal) is converted from a digital signal to an analog signal by the D / A converter 200 and transmitted from an antenna (not shown).
　次に、受信回路１ｂについて説明する。 Next, the receiving circuit 1b will be described.
　受信回路１ｂは復調装置の一例である。受信回路１ｂは、軟判定復号に必要となる尤度（尤度を表す軟判定値）の算出が容易なビット（４ＳＢおよび５ＳＢ）については軟判定復号を行い、軟判定復号に必要となる尤度（尤度を表す軟判定値）の算出が複雑になるビット（ＭＳＢ、２ＳＢ、３ＳＢ）については、軟判定復号を行わずに値を特定する。 The receiving circuit 1b is an example of a demodulator. The receiving circuit 1b performs soft-decision decoding on the bits (4SB and 5SB) for which the likelihood (soft-decision value representing the likelihood) necessary for soft-decision decoding is easy, and the likelihood necessary for the soft-decision decoding. For the bits (MSB, 2SB, 3SB) for which the calculation of the degree (soft decision value representing likelihood) is complicated, the value is specified without performing soft decision decoding.
　不図示のアンテナが、不図示の他の多値ＱＡＭ送受信回路から送信された変調信号（多値変調信号）を受信する。Ａ／Ｄ変換部３００が、受信された変調信号（多値変調信号）をアナログ信号からディジタル信号に変換する。 An antenna (not shown) receives a modulated signal (multilevel modulated signal) transmitted from another not shown multilevel QAM transmission / reception circuit. The A / D conversion unit 300 converts the received modulation signal (multilevel modulation signal) from an analog signal to a digital signal.
　ディジタル復調回路１０２ａは、受信信号点特定手段の一例である。 The digital demodulation circuit 102a is an example of a reception signal point specifying unit.
　ディジタル復調回路１０２ａは、Ａ／Ｄ変換部３００からの変調信号（多値変調信号）を受信する。ディジタル復調回路１０２ａは、その変調信号を復調して受信信号点（ｘ座標、ｙ座標）を求める。ディジタル復調回路１０２ａは、受信信号点を表す復調信号を生成する。ディジタル復調回路１０２ａは、復調信号を、信号点逆変換回路１ｂ１と遅延合わせ回路１ｂ３に出力する。 The digital demodulation circuit 102a receives the modulation signal (multilevel modulation signal) from the A / D conversion unit 300. The digital demodulator circuit 102a demodulates the modulated signal to obtain a reception signal point (x coordinate, y coordinate). The digital demodulation circuit 102a generates a demodulated signal that represents a reception signal point. The digital demodulation circuit 102a outputs the demodulated signal to the signal point inverse conversion circuit 1b1 and the delay matching circuit 1b3.
　信号点逆変換回路１ｂ１は、尤度特定手段の一例である。 The signal point inverse conversion circuit 1b1 is an example of likelihood specifying means.
　信号点逆変換回路１ｂ１は、受信信号点から硬判定にて５ビットのデータを特定する。　　　 The signal point reverse conversion circuit 1b1 specifies 5-bit data from the received signal point by hard decision. *
　信号点逆変換回路１ｂ１は、受信信号点から特定（硬判定）されるデータを構成する５ビットのうち、ｘｙ平面において値が変化する境界（硬判定境界）がｘｙ平面を規定するｘ軸およびｙ軸の一方と平行な４ＳＢおよび５ＳＢの各々について、該ビットの値の尤度を、受信信号点と該ビットの境界との距離に基づいて特定する。 The signal point inverse transform circuit 1b1 includes an x-axis in which a boundary (a hard decision boundary) whose value changes in the xy plane defines the xy plane among five bits constituting data specified (hard decision) from the received signal point For each of 4SB and 5SB parallel to one of the y-axes, the likelihood of the value of the bit is specified based on the distance between the received signal point and the bit boundary.
　信号逆変換回路１ｂ１は、４ＳＢおよび５ＳＢの各値およびその尤度を表す軟判定信号を通信路復号化回路１ｂ２に出力する。 The signal inverse conversion circuit 1b1 outputs the 4SB and 5SB values and the soft decision signal representing the likelihood to the communication path decoding circuit 1b2.
　通信路復号化回路１ｂ２は、復号手段の一例である。 The communication path decoding circuit 1b2 is an example of a decoding unit.
　通信路復号化回路１ｂ２は、軟判定信号を受け付け、４ＳＢおよび５ＳＢの値について、４ＳＢおよび５ＳＢの値の尤度を用いて軟判定復号する。本実施形態では、通信路復号化回路１ｂ２は、軟判定復号として、軟判定ブロック復号を実行する。 The communication path decoding circuit 1b2 receives the soft decision signal and performs soft decision decoding on the 4SB and 5SB values using the likelihood of the 4SB and 5SB values. In the present embodiment, the channel decoding circuit 1b2 performs soft decision block decoding as soft decision decoding.
　通信路復号化回路１ｂ２は、軟判定ブロック復号にて誤りが訂正された４ＳＢおよび５ＳＢの値を表すデータ（例えば、図７に示した下位２ビットの伝送データに対応）を、硬判定回路１ｂ４に出力する。 The channel decoding circuit 1b2 uses the data representing the 4SB and 5SB values (for example, corresponding to the transmission data of the lower 2 bits shown in FIG. 7) whose errors are corrected by the soft decision block decoding, and the hard decision circuit 1b4. Output to.
　遅延合わせ回路１ｂ３は、ディジタル復調回路１０２ａから復調信号を受け付け、復調信号を、信号点逆変換回路１ｂ１および通信路復号化回路１ｂ２の各々で発生する処理遅延時間を合計した時間と同じ時間遅延させて硬判定回路１ｂ４に出力する。 The delay matching circuit 1b3 receives the demodulated signal from the digital demodulating circuit 102a and delays the demodulated signal by the same time as the total processing delay time generated in each of the signal point inverse transform circuit 1b1 and the communication path decoding circuit 1b2. To the hard decision circuit 1b4.
　硬判定回路１ｂ４は、所定ビット値特定手段の一例である。 The hard decision circuit 1b4 is an example of a predetermined bit value specifying unit.
　硬判定回路１ｂ４は、３２個の変調信号点に対応する３２種類のデータの中から、通信路復号化回路１ｂ２からの２ビットのデータを、４ＳＢと５ＳＢのデータとして有する８種類のデータ（以下「候補データ」と称する）を特定する。 The hard decision circuit 1b4 has 8 types of data (hereinafter referred to as 4SB and 5SB) having 2 bits of data from the channel decoding circuit 1b2 among 32 types of data corresponding to 32 modulation signal points. (Referred to as “candidate data”).
　硬判定回路１ｂ４は、３２個の変調信号点の中から、８種類の候補データに対応する８個の変調信号点を、複数の候補点信号として特定する。 The hard decision circuit 1b4 specifies eight modulation signal points corresponding to eight types of candidate data from among the 32 modulation signal points as a plurality of candidate point signals.
　硬判定回路１ｂ４は、８個の候補信号点のうち受信信号点までの距離が最も短い信号点（以下「該当信号点」と称する）を特定する。硬判定回路１ｂ４は、該当信号点に対応づけられたデータを用いて、受信信号点から特定されるデータを構成する５ビットのうちＭＳＢ、２ＳＢおよび３ＳＢの各々の値を特定する。なお、ＭＳＢ、２ＳＢおよび３ＳＢは所定ビットの一例である。 The hard decision circuit 1b4 specifies a signal point (hereinafter referred to as “corresponding signal point”) having the shortest distance to the reception signal point among the eight candidate signal points. The hard decision circuit 1b4 specifies the values of MSB, 2SB, and 3SB among the 5 bits that constitute the data specified from the received signal point, using the data associated with the corresponding signal point. MSB, 2SB, and 3SB are examples of predetermined bits.
　本実施形態では、硬判定回路１ｂ４は、該当信号点に対応づけられたデータのＭＳＢ、２ＳＢおよび３ＳＢの各々の値を、受信信号点から特定されるデータを構成する５ビットのＭＳＢ、２ＳＢおよび３ＳＢの各々の値として特定する。 In the present embodiment, the hard decision circuit 1b4 uses the MSB, 2SB, and 3SB values of the data associated with the corresponding signal point as the 5-bit MSB, 2SB, and data constituting the data specified from the received signal point. It is specified as each value of 3SB.
　次に、受信回路１ｂの動作について説明する。 Next, the operation of the receiving circuit 1b will be described.
　ディジタル復調回路１０２ａは、変調信号（多値変調信号）を受信すると、変調信号（多値変調信号）を復調して受信信号点を求める。 When receiving the modulation signal (multilevel modulation signal), the digital demodulation circuit 102a demodulates the modulation signal (multilevel modulation signal) to obtain a reception signal point.
　続いて、ディジタル復調回路１０２ａは、受信信号点を表す復調信号を生成し、復調信号を、信号点逆変換回路１ｂ１と遅延合わせ回路１ｂ３に出力する。 Subsequently, the digital demodulation circuit 102a generates a demodulated signal representing a received signal point, and outputs the demodulated signal to the signal point inverse conversion circuit 1b1 and the delay matching circuit 1b3.
　信号点逆変換回路１ｂ１は、復調信号を受け付けると、復調信号が表す受信信号点に対応する５ビットの値について、まず、硬判定を行う。 When receiving the demodulated signal, the signal point inverse transform circuit 1b1 first performs a hard decision on the 5-bit value corresponding to the received signal point represented by the demodulated signal.
　例えば、受信信号点の位置（ｘ座標、ｙ座標）が、図１０に示した位置Ｘ（“00101”シンボル領域内の位置）であった場合、信号点逆変換回路１ｂ１は、軟判定復号化を行う前の段階でのシンボル判定値（５ビットのデータの硬判定値）として、“00101”を特定する。 For example, when the position of the received signal point (x coordinate, y coordinate) is the position X shown in FIG. 10 (position in the “00101” symbol area), the signal point inverse transform circuit 1b1 performs soft decision decoding. “00101” is specified as a symbol determination value (a hard determination value of 5-bit data) at the stage before the operation.
　続いて、信号点逆変換回路１ｂ１は、“00101”の４ＳＢの値“0”と、“00101”の５ＳＢの値“1”と、の各々について尤度を算出する。 Subsequently, the signal point inverse transform circuit 1b1 calculates the likelihood for each of the 4SB value “0” of “00101” and the 5SB value “1” of “00101”.
　ここで、尤度の算出手法の一例を説明する。 Here, an example of a likelihood calculation method will be described.
　例えば、信号点逆変換回路１ｂ１は、４ＳＢの値“0”と５ＳＢの値“1”との各々について、該ビットについての複数の境界５０（図９Ｄ、図９Ｅ参照）のうち受信信号点に最も近い境界と受信信号点との距離を算出し、この距離に基づいて尤度を算出する。 For example, the signal point inverse conversion circuit 1b1 sets the 4SB value “0” and the 5SB value “1” to the reception signal point among the plurality of boundaries 50 (see FIGS. 9D and 9E) for the bit. The distance between the nearest boundary and the received signal point is calculated, and the likelihood is calculated based on this distance.
　この算出された距離は、受信信号点が境界に近いほど小さくなる。また、受信信号点が境界に近いほど、受信信号点から特定されるビットの値の尤もらしさは低くなる。つまり、この算出された距離が小さくなるほど、受信信号点から特定されるビットの値の尤もらしさは低くなる。 This calculated distance becomes smaller as the received signal point is closer to the boundary. Also, the closer the received signal point is to the boundary, the lower the likelihood of the bit value specified from the received signal point. In other words, the smaller the calculated distance, the lower the likelihood of the bit value specified from the received signal point.
　本実施形態では、信号点逆変換回路１ｂ１は、図９Ｄ、図９Ｅに示した各１ビットにおける２値シンボル“＋”または“－”の尤度を多値レベルで算出する。なお、“＋”はビット値“0”に対応し、“－”はビット値“1”に対応する。 In this embodiment, the signal point inverse conversion circuit 1b1 calculates the likelihood of the binary symbol “+” or “−” in each 1-bit shown in FIG. 9D and FIG. “+” Corresponds to the bit value “0”, and “−” corresponds to the bit value “1”.
　尤度の表現方法について説明すると、例えば、シンボル“＋”を数値1.000、シンボル“－”を数値-1.000で表すとし、あるビットの値についての尤度が、-1.000から1.000までの範囲に含まれる値を用いて表現される。この場合、尤度が0.000に近いほど、ビット値の尤もらしさが小さくなる。 The likelihood expression method will be described. For example, the symbol “+” is represented by a numerical value 1.000, the symbol “−” is represented by a numerical value 1.000, and the likelihood of a certain bit value is included in a range from -1.000 to 1.000. It is expressed using a value that can be In this case, the likelihood of the bit value becomes smaller as the likelihood is closer to 0.000.
　信号点逆変換回路１ｂ１は、４ＳＢ、５ＳＢについて、受信信号点に最も近い境界と受信信号点との距離が小さいほど、そのビットの値についての尤度を0.000に近づけていく。 The signal point inverse transform circuit 1b1 brings the likelihood of the bit value closer to 0.000 as the distance between the boundary closest to the received signal point and the received signal point is smaller for 4SB and 5SB.
　また、信号点逆変換回路１ｂ１は、４ＳＢ、５ＳＢについて、受信信号点に最も近い境界と受信信号点との距離が、境界５０間の最短距離の１／２に近いほど、そのビットの値についての尤度を1.000または-1.000に近づけていく。 In addition, the signal point inverse transform circuit 1b1 determines the bit value of 4SB and 5SB as the distance between the boundary closest to the reception signal point and the reception signal point is closer to ½ of the shortest distance between the boundaries 50. The likelihood of is approaching 1.000 or -1.000.
　例えば、あるビット（４ＳＢまたは５ＳＢ）の硬判定結果の値が“0”（つまり“＋”）の状況では、信号点逆変換回路１ｂ１は、受信信号点に最も近い境界と受信信号点との距離が小さくなるほど、尤度を1.000から0.000に近づけていき、受信信号点に最も近い境界と受信信号点との距離が境界５０間の最短距離の１／２に近づくほど、尤度を1.000に近づけていく。 For example, in a situation where the value of the hard decision result of a certain bit (4SB or 5SB) is “0” (that is, “+”), the signal point inverse transform circuit 1b1 determines that the boundary between the reception signal point and the reception signal point is the closest. The likelihood decreases from 1.000 to 0.000 as the distance decreases, and the likelihood decreases to 1.000 as the distance between the boundary closest to the reception signal point and the reception signal point approaches ½ of the shortest distance between the boundaries 50. Move closer.
　また、あるビット（４ＳＢまたは５ＳＢ）の硬判定結果の値が“1”（つまり“－”）の状況では、信号点逆変換回路１ｂ１は、受信信号点に最も近い境界と受信信号点との距離が小さくなるほど、尤度を-1.000から0.000に近づけていき、受信信号点に最も近い境界と受信信号点との距離が境界５０間の最短距離の１／２に近づくほど、尤度を-1.000に近づけていく。 In addition, in the situation where the value of the hard decision result of a certain bit (4SB or 5SB) is “1” (that is, “−”), the signal point inverse transform circuit 1b1 determines the boundary between the reception signal point and the boundary closest to the reception signal point. As the distance becomes smaller, the likelihood is made closer to 1.000 to 0.000, and as the distance between the boundary closest to the reception signal point and the reception signal point approaches ½ of the shortest distance between the boundaries 50, the likelihood becomes − Move closer to 1.000.
　さらに言えば、この尤度は、シンボルの硬判定結果も表す。例えば、硬判定の結果が“1”（つまり“－”）である場合、尤度は負の値となり、一方、硬判定の結果が“0”（つまり“＋”）である場合、尤度は正の値となる。 Furthermore, this likelihood also represents the hard decision result of the symbol. For example, if the hard decision result is “1” (ie, “−”), the likelihood is a negative value, whereas if the hard decision result is “0” (ie, “+”), the likelihood is Is a positive value.
　なお、本実施形態では、尤度の分解能の精度を少数第３位としているが、尤度の分解能の精度は、これに限らず適宜変更可能である。 In this embodiment, the accuracy of the resolution of likelihood is set to the third decimal place, but the accuracy of the resolution of likelihood is not limited to this and can be changed as appropriate.
　信号点逆変換回路１ｂ１は、４ＳＢと５ＳＢの各々の値についての尤度を算出すると、４ＳＢと５ＳＢの各々の値とその尤度を表す軟判定信号を生成する。 When the signal point inverse transform circuit 1b1 calculates the likelihood for each value of 4SB and 5SB, it generates a soft decision signal representing each value of 4SB and 5SB and the likelihood.
　本実施形態では、尤度は、４ＳＢと５ＳＢの各々の値（硬判定結果）も表すので、信号点逆変換回路１ｂ１は、４ＳＢと５ＳＢの尤度を表す軟判定信号を生成する。 In this embodiment, since the likelihood also represents each value (hard decision result) of 4SB and 5SB, the signal point inverse transform circuit 1b1 generates a soft decision signal representing the likelihood of 4SB and 5SB.
　なお、信号点逆変換回路１ｂ１が、特許文献３に記載の対数尤度比演算回路を含んでもよく、この場合、信号点逆変換回路１ｂ１は、この対数尤度比演算回路の出力を、軟判定信号として用いる。 The signal point inverse transformation circuit 1b1 may include a log likelihood ratio calculation circuit described in Patent Document 3. In this case, the signal point inverse transformation circuit 1b1 outputs the output of the log likelihood ratio calculation circuit to the soft Used as a determination signal.
　続いて、信号点逆変換回路１ｂ１は、軟判定信号を通信路復号化回路１ｂ２に出力する。 Subsequently, the signal point inverse transform circuit 1b1 outputs the soft decision signal to the communication path decoding circuit 1b2.
　通信路復号化回路１ｂ２は、軟判定信号を受け付けると、４ＳＢおよび５ＳＢの値を、４ＳＢおよび５ＳＢの値の尤度を用いて軟判定ブロック復号する。通信路復号化回路１ｂ２での軟判定ブロック復号にて、４ＳＢおよび５ＳＢの値の推定は完了する。 When receiving the soft decision signal, the communication path decoding circuit 1b2 performs soft decision block decoding on the values of 4SB and 5SB using the likelihood of the values of 4SB and 5SB. By the soft decision block decoding in the communication path decoding circuit 1b2, the estimation of the values of 4SB and 5SB is completed.
　続いて、通信路復号化回路１ｂ２は、軟判定ブロック復号にて誤りが訂正された４ＳＢおよび５ＳＢの値を表すデータを、硬判定回路１ｂ４に出力する。 Subsequently, the communication path decoding circuit 1b2 outputs data representing the values of 4SB and 5SB whose errors are corrected by the soft decision block decoding to the hard decision circuit 1b4.
　硬判定回路１ｂ４は、通信路復号化回路１ｂ２からのデータ（４ＳＢおよび５ＳＢの値を表すデータ）と、遅延合わせ回路１ｂ３からの信号（受信信号点を表す信号）と、を受け付けると、それらを用いて、ＭＳＢ、２ＳＢおよび３ＳＢの値を特定する。 When the hard decision circuit 1b4 receives the data from the communication path decoding circuit 1b2 (data representing the values of 4SB and 5SB) and the signal from the delay alignment circuit 1b3 (signal representing the reception signal point), Used to identify MSB, 2SB and 3SB values.
　以下、硬判定回路１ｂ４について説明する。 Hereinafter, the hard decision circuit 1b4 will be described.
　図１１は、硬判定回路１ｂ４の一例を示した図である。 FIG. 11 is a diagram showing an example of the hard decision circuit 1b4.
　図１１において、硬判定回路１ｂ４は、８個の上位３ビット下位２ビット結合回路１ｂ４１と、８個の信号点変換回路１ｂ４２と、８個の距離比較回路１ｂ４３と、出力回路１ｂ４４と、遅延合わせ回路１ｂ４５と、を含む。８個の上位３ビット下位２ビット結合回路１ｂ４１と、８個の信号点変換回路１ｂ４２と、８個の距離比較回路１ｂ４３とは、それぞれ個別に対応している。 In FIG. 11, the hard decision circuit 1b4 includes eight upper 3 bits and lower 2 bit combination circuits 1b41, eight signal point conversion circuits 1b42, eight distance comparison circuits 1b43, and an output circuit 1b44. Circuit 1b45. The eight upper 3-bit lower 2-bit combination circuits 1b41, the eight signal point conversion circuits 1b42, and the eight distance comparison circuits 1b43 correspond to each other individually.
　８個の上位３ビット下位２ビット結合回路１ｂ４１は、それぞれ、上位３ビットの値として、“000”、“001”、“010”、“011”、“100”、“101”、“110”、“111”を受け付け、下位２ビットの値として、通信路復号化回路１ｂ２からのデータに示された４ＳＢおよび５ＳＢの値を受け付け、上位３ビットの値と下位２ビットの値とを結合する。 The eight upper 3 bits and lower 2 bits combining circuits 1b41 respectively have “000”, “001”, “010”, “011”, “100”, “101”, “110” as the upper 3 bits. , "111" is received, and the 4SB and 5SB values indicated in the data from the channel decoding circuit 1b2 are received as the lower 2 bits, and the upper 3 bits and the lower 2 bits are combined. .
　８個の信号点変換回路１ｂ４２は、図５に示した信号点変換回路１ａ３と同一構成であり、対応する上位３ビット下位２ビット結合回路１ｂ４１からの５ビットのデータ（候補データ）に応じた対応変調信号点（候補信号点）の座標（ｘ、ｙ）を出力する。 The eight signal point conversion circuits 1b42 have the same configuration as the signal point conversion circuit 1a3 shown in FIG. 5, and correspond to the 5-bit data (candidate data) from the corresponding upper 3-bit lower 2-bit combination circuit 1b41. The coordinates (x, y) of the corresponding modulation signal point (candidate signal point) are output.
　図１２は、４ＳＢ、５ＳＢにて構成される値が“01”であった場合の８通りの候補信号点を示した図である。なお、候補信号点は、斜線にて示されている。 FIG. 12 is a diagram showing eight candidate signal points when the value composed of 4SB and 5SB is “01”. The candidate signal points are indicated by hatching.
　図１３は、４ＳＢ、５ＳＢにて構成される値が“11”であった場合の８通りの候補信号点を示した図である。なお、候補信号点は、斜線にて示されている。 FIG. 13 is a diagram showing eight candidate signal points when the value composed of 4SB and 5SB is “11”. The candidate signal points are indicated by hatching.
　図１４は、４ＳＢ、５ＳＢにて構成される値が“00”であった場合の８通りの候補信号点を示した図である。なお、候補信号点は、斜線にて示されている。 FIG. 14 is a diagram showing eight candidate signal points when the value composed of 4SB and 5SB is “00”. The candidate signal points are indicated by hatching.
　図１５は、４ＳＢ、５ＳＢにて構成される値が“10”であった場合の８通りの候補信号点を示した図である。なお、候補信号点は、斜線にて示されている。 FIG. 15 is a diagram showing eight candidate signal points when the value composed of 4SB and 5SB is “10”. The candidate signal points are indicated by hatching.
　４ＳＢ、５ＳＢにて構成される値は、図１２～図１５に示したように、“01”、“11”、“00”、“10”の４通りとなるが、いずれの場合も、候補信号点同士の間隔は等間隔となる。 As shown in FIGS. 12 to 15, there are four values of 4SB and 5SB, which are “01”, “11”, “00”, and “10”. The intervals between the signal points are equal.
　このため、受信信号点に最も近い候補信号点を探すことによって、上位３ビットの値を推定することが可能になる。これは限界距離復号法を適用していることに近い。 Therefore, it is possible to estimate the value of the upper 3 bits by searching for the candidate signal point closest to the received signal point. This is close to applying the limit distance decoding method.
　８個の距離比較回路１ｂ４３は、対応する信号点変換回路１ｂ４２からの対応変調信号点（候補信号点）と受信信号点との距離を算出する。 The eight distance comparison circuits 1b43 calculate the distance between the corresponding modulation signal point (candidate signal point) from the corresponding signal point conversion circuit 1b42 and the reception signal point.
　出力回路１ｂ４４は、８個の距離比較回路１ｂ４３のうち、最も小さい距離を算出した距離比較回路１ｂ４３を特定し、その特定された距離比較回路１ｂ４３に対応する上位３ビット下位２ビット結合回路１ｂ４１に入力された上位３ビットの値を、ＭＳＢ、２ＳＢおよび３ＳＢの値として出力する。 The output circuit 1b44 identifies the distance comparison circuit 1b43 that has calculated the smallest distance among the eight distance comparison circuits 1b43, and supplies the upper 3 bits and the lower 2 bits combination circuit 1b41 corresponding to the identified distance comparison circuit 1b43. The input upper 3 bits are output as MSB, 2SB and 3SB values.
　また、遅延合わせ回路１ｂ４５は、通信路復号化回路１ｂ２からのデータに示された４ＳＢおよび５ＳＢの値を、上位３ビット下位２ビット結合回路１ｂ４１と信号点変換回路１ｂ４２と距離比較回路１ｂ４３と出力回路１ｂ４４の各々で発生する処理遅延時間を合計した時間と同じ時間遅延させて出力する。 The delay matching circuit 1b45 outputs the values of 4SB and 5SB indicated in the data from the communication path decoding circuit 1b2, and outputs the upper 3 bits and lower 2 bits combination circuit 1b41, the signal point conversion circuit 1b42, and the distance comparison circuit 1b43. The processing delay time generated in each of the circuits 1b44 is delayed by the same time as the total time and output.
　硬判定回路１ｂ４からの５ビットのデータは、受信データとして扱われる。 5-bit data from the hard decision circuit 1b4 is treated as received data.
　次に、本実施形態の効果について説明する。 Next, the effect of this embodiment will be described.
　本実施形態によれば、ディジタル復調回路１０２ａは、多値変調された信号を受信し、その信号に基づいてｘｙ平面での受信信号点を特定する。 According to the present embodiment, the digital demodulation circuit 102a receives a multi-level modulated signal and specifies a reception signal point on the xy plane based on the signal.
　信号点逆変換回路１ｂ１は、受信信号点から特定されるデータを構成する複数のビットのうち、ｘｙ平面において値が変化する境界がｘ軸とｙ軸の一方と平行な特定ビット（４ＳＢ、５ＳＢ）について、特定ビットの値の尤度を、受信信号点と特定ビットの境界との距離に基づいて特定する。 The signal point inverse transformation circuit 1b1 is a specific bit (4SB, 5SB) whose boundary whose value changes in the xy plane is parallel to one of the x axis and the y axis among a plurality of bits constituting the data specified from the received signal point. ), The likelihood of the value of the specific bit is specified based on the distance between the reception signal point and the boundary of the specific bit.
　通信路復号化回路１ｂ２は、特定ビットの値について特定ビットの値の尤度を用いて軟判定復号する。 The communication path decoding circuit 1b2 performs soft decision decoding on the value of the specific bit using the likelihood of the value of the specific bit.
　硬判定回路１ｂ４は、多値変調で使用される複数の変調信号点の中から、複数の変調信号点の各々に対応づけられたデータ（シンボル）のうち軟判定復号された特定ビットの値を有する候補データに対応する複数の候補信号点を特定する。そして、硬判定回路１ｂ４は、複数の候補信号点のうち受信信号点までの距離が最も短い該当信号点に対応づけられたデータを用いて、複数のビットのうち特定ビット以外のビットである所定ビットの値を特定する。 The hard decision circuit 1b4 selects a value of a specific bit subjected to soft decision decoding from data (symbols) associated with each of a plurality of modulation signal points from a plurality of modulation signal points used in multilevel modulation. A plurality of candidate signal points corresponding to the candidate data possessed are specified. Then, the hard decision circuit 1b4 uses data associated with the corresponding signal point having the shortest distance to the reception signal point among the plurality of candidate signal points, and is a predetermined bit that is a bit other than the specific bit among the plurality of bits. Specifies the value of the bit.
　このため、軟判定復号に必要となる尤度（軟判定結果）の算出が容易な特定ビット（４ＳＢおよび５ＳＢ）については軟判定復号を行い、軟判定復号に必要となる尤度（軟判定結果）の算出が複雑になる所定ビット（ＭＳＢ、２ＳＢ、３ＳＢ）については軟判定復号を行わずに値を特定することが可能になる。 Therefore, soft decision decoding is performed on specific bits (4SB and 5SB) for which the likelihood (soft decision result) necessary for soft decision decoding can be easily calculated, and the likelihood (soft decision result) necessary for soft decision decoding. ) Can be specified without performing soft-decision decoding for predetermined bits (MSB, 2SB, 3SB) that complicate calculation.
　よって、シンボル判定処理において、軟判定を実行するビット数を少なくしつつ、実行される軟判定を容易にすることが可能になる。 Therefore, in the symbol determination process, the soft decision to be executed can be facilitated while reducing the number of bits for executing the soft decision.
　また、本実施形態では、特定ビットが、複数のビットのうち下位の偶数個のビットとなるように、複数の変調信号点の位置と、複数の変調信号点に対応するデータとが、設定されている。 Further, in the present embodiment, the positions of the plurality of modulation signal points and the data corresponding to the plurality of modulation signal points are set so that the specific bit is the lower even number of bits among the plurality of bits. ing.
　本実施形態は、３２ＱＡＭ、１２８ＱＡＭ、５１２ＱＡＭ、２０４８ＱＡＭのように変調信号点の数が２(2n+1)（ただしｎは２以上の整数）であるＱＡＭ方式（変調信号点配置がクロス型）に共通に適用できるので、例えば、データ通信を行っている際に、変調信号点を規定するｎが２以上の整数の中で変更される適応変調方式にも適用可能である。 In the present embodiment, the QAM method (modulation signal point arrangement is a cross type) in which the number of modulation signal points is 2 (2n + 1) (where n is an integer of 2 or more ) , such as 32QAM, 128QAM, 512QAM, and 2048QAM. Since it can be applied in common, for example, it can also be applied to an adaptive modulation scheme in which n defining a modulation signal point is changed within an integer of 2 or more during data communication.
　本実施形態が、変調信号点を規定するｎが２以上の整数の中で変化する適応変調方式に適用された場合、所定ビットの数は、ｎの値に関わらず一定にすることが望ましい。例えば、特定ビットが、変調信号点に対応するデータの２ｎ＋１ビットのうち下位の２ｎ－２ビットとなるように、複数の変調信号点の位置と複数の変調信号点に対応するデータとが設定され、所定ビットの数を３に固定する。 When the present embodiment is applied to an adaptive modulation scheme in which n that defines a modulation signal point changes within an integer of 2 or more, it is desirable that the number of predetermined bits be constant regardless of the value of n. For example, the positions of the plurality of modulation signal points and the data corresponding to the plurality of modulation signal points are set so that the specific bit is the lower 2n-2 bits of the 2n + 1 bits of the data corresponding to the modulation signal points. The number of predetermined bits is fixed to 3.
　なお、本実施形態は、クロス型つまり変調信号点の数が２の奇数乗の変調方式に特に有効であるが、正方形型つまり変調信号点の数が２の偶数乗の変調方式に用いられてもよい。 The present embodiment is particularly effective for a cross type, that is, a modulation method with the number of modulation signal points being an odd power of 2. However, this embodiment is used for a square type, that is, a modulation method with an even power of 2 modulation signal points. Also good.
　（第２実施形態）
　次に、第２実施形態として、変調方式が１２８ＱＡＭである場合について、第１実施形態と異なる点を中心に説明する。 (Second Embodiment)
Next, as a second embodiment, a case where the modulation scheme is 128QAM will be described focusing on differences from the first embodiment.
　第２実施形態の構成は、基本的に第１実施形態の構成（図５に示した構成）と同様であるが、変調方式の違いにより、以下に示すように種々の機能が異なっている。 The configuration of the second embodiment is basically the same as the configuration of the first embodiment (the configuration shown in FIG. 5), but various functions are different as shown below due to the difference in modulation scheme.
　第２実施形態では、送信データおよび受信データは７ビットのデータとなり、変調信号点の配置形状としては、図９Ａ～図９Ｄおよび図１０に示した３２ＱＡＭでのひとつの変調信号点領域が４つの信号点領域に分割され、変調信号点の数およびその領域の数は、１２８となる。 In the second embodiment, the transmission data and the reception data are 7-bit data, and the modulation signal point arrangement shape includes four modulation signal point areas in 32QAM shown in FIGS. 9A to 9D and FIG. The signal is divided into signal point areas, and the number of modulation signal points and the number of areas are 128.
　このため、１２８ＱＡＭの場合でも、入り組んだ硬判定境界５０ａを持つビットは、ＭＳＢ、２ＳＢおよび３ＳＢの上位３ビットとなり、下位の４ビットはどのビットも硬判定境界５０はｘ座標またはｙ座標のいずれかと平行になる。 Therefore, even in the case of 128QAM, the bit having the complicated hard decision boundary 50a is the upper 3 bits of the MSB, 2SB, and 3SB, and the lower 4 bits are any bits, and the hard decision boundary 50 is either the x coordinate or the y coordinate. It becomes parallel with the kana.
　よって、第２実施形態では、特定ビットとして下位の４ビットが用いられ、所定ビットとして上位３ビットが用いられる。 Therefore, in the second embodiment, the lower 4 bits are used as the specific bits, and the upper 3 bits are used as the predetermined bits.
　例えば、受信コンスタレーションが図１６に示す状態であったとすると、信号点逆変換回路１ｂ１は、下位の４ビットだけ各々のビットの値につきシンボル軟判定を行い、シンボル“＋”またはシンボル“－”の尤度を数値1.000～-1.000で表現する。そして、通信路復号化回路１ｂ２が、下位の４ビットの各々のビットの値について、その尤度を用いて軟判定復号を実行して、下位の４ビットの各値を推定する。 For example, if the reception constellation is in the state shown in FIG. 16, the signal point inverse conversion circuit 1b1 performs symbol soft decision for each bit value by the lower 4 bits, and performs symbol “+” or symbol “−”. Is expressed as a numerical value 1.000 to -1.000. Then, the channel decoding circuit 1b2 performs soft decision decoding on the value of each of the lower 4 bits, using the likelihood, and estimates each value of the lower 4 bits.
　推定された下位の４ビットが表す値としては１６通りが存在する。 There are 16 possible values represented by the estimated lower 4 bits.
　以下では、下位の４ビットが表す値が“0100”であった場合の例を説明する。 In the following, an example where the value represented by the lower 4 bits is “0100” will be described.
　図１７は、下位の４ビットが表す値が“0100”であった場合の８個の候補信号点を示した図である。 FIG. 17 is a diagram showing eight candidate signal points when the value represented by the lower 4 bits is “0100”.
　８個の候補信号点同士の間隔は、等間隔であり、離れているので、硬判定回路１ｂ４は、上位３ビットの値の推定を、限界距離復号法を用いて実行する。 Since the interval between the eight candidate signal points is equal and separated, the hard decision circuit 1b4 executes the estimation of the upper 3 bits using the limit distance decoding method.
　なお、下位４ビットの値が残りの１５通りのいずれかであっても、８つの候補信号点同士の間隔は、下位の４ビットが表す値が“0100”であった場合の間隔と等しくなり、この場合も、硬判定回路１ｂ４は、上位３ビットの値の推定を、限界距離復号法を用いて実行する。 Even if the value of the lower 4 bits is any of the remaining 15 values, the interval between the 8 candidate signal points is equal to the interval when the value represented by the lower 4 bits is “0100”. In this case as well, the hard decision circuit 1b4 executes the estimation of the upper 3 bits using the limit distance decoding method.
　また、５１２ＱＡＭ、２０４８ＱＡＭでも、基本となる３２ＱＡＭシンボル配置（図９Ａ～図９Ｄおよび図１０に示したシンボル配置）を採用し、特定ビットを、下位６ビット、下位８ビットとすることによって、複雑化しない軟判定方法を用いることが可能になる。なお、いずれの場合も、上位３ビットの推定方法は、３２ＱＡＭ・１２８ＱＡＭと同様である。 Also in 512QAM and 2048QAM, the basic 32QAM symbol arrangement (symbol arrangement shown in FIGS. 9A to 9D and FIG. 10) is adopted, and the specific bits are made the lower 6 bits and the lower 8 bits to make it complicated. It is possible to use a soft decision method that does not. In any case, the upper 3 bits are estimated in the same way as 32QAM and 128QAM.
　（第３実施形態）
　次に、第３実施形態として、変調方式が、正方形型つまり変調信号点の数が２の偶数乗の変調方式である場合について、第１実施形態と異なる点を中心に説明する。以下では、変調信号点の数が２の偶数乗の変調方式の一例として６４ＱＡＭ方式を説明する。 (Third embodiment)
Next, as a third embodiment, a case where the modulation method is a square type, that is, a modulation method in which the number of modulation signal points is an even power of 2 will be described focusing on differences from the first embodiment. In the following, the 64QAM system will be described as an example of a modulation system whose number of modulation signal points is an even power of 2.
　第３実施形態の構成は、基本的に第１実施形態の構成（図５に示した構成）と同様であるが、変調方式の違いにより、以下に示すように種々の機能が異なっている。 The configuration of the third embodiment is basically the same as the configuration of the first embodiment (configuration shown in FIG. 5), but various functions are different as shown below due to the difference in the modulation method.
　第３実施形態では、送信データおよび受信データは６ビットのデータとなる。 In the third embodiment, transmission data and reception data are 6-bit data.
　図１８は、第３実施形態で用いる変調信号点の配置を示した図である。 FIG. 18 is a diagram showing the arrangement of modulation signal points used in the third embodiment.
　図１８に示した例では、６ビットのデータのうち、下位４ビットが特定ビットとして用いられ、上位２ビットが所定ビットとして用いられる。 In the example shown in FIG. 18, among the 6-bit data, the lower 4 bits are used as the specific bits and the upper 2 bits are used as the predetermined bits.
　特定ビットで示されるシンボルは１６通りで、その１６個のシンボルの配置（変調信号点との対応）は、図４に示した１６ＱＡＭの例と全く同じである。 There are 16 symbols indicated by specific bits, and the arrangement of 16 symbols (corresponding to modulation signal points) is exactly the same as the 16QAM example shown in FIG.
　図１８に示した例では、特定ビットで示される１６個のシンボルの配置が、所定ビット（２ビット）で示される４通り分設けられ、その４つがｘｙ平面に並べられている。 In the example shown in FIG. 18, fourteen arrangements of 16 symbols indicated by specific bits are provided for predetermined bits (2 bits), and four of them are arranged on the xy plane.
　本実施形態では、信号点逆変換回路１ｂ１は、下位の４ビットだけ各々のビットの値につきシンボル軟判定を行い、シンボル“＋”またはシンボル“－”の尤度を数値1.000～-1.000で表現する。そして、通信路復号化回路１ｂ２が、下位の４ビットの各々のビットの値について、その尤度を用いて軟判定復号を実行して、下位の４ビットの各値を推定する。 In the present embodiment, the signal point inverse transform circuit 1b1 performs symbol soft decision on the value of each lower 4 bits, and expresses the likelihood of the symbol “+” or the symbol “−” as numerical values 1.000 to -1.000. To do. Then, the channel decoding circuit 1b2 performs soft decision decoding on the value of each of the lower 4 bits, using the likelihood, and estimates each value of the lower 4 bits.
　推定された下位の４ビットが表す値としては１６通りが存在する。 There are 16 possible values represented by the estimated lower 4 bits.
　本実施形態では、推定された下位の４ビットにて表される１つの値について、４個の候補信号点が生じる。 In this embodiment, four candidate signal points are generated for one value represented by the estimated lower 4 bits.
　図１８から明らかなように、４個の候補信号点同士の間隔は、等間隔であるので、硬判定回路１ｂ４は、上位２ビットの値の推定を、３２ＱＡＭ・１２８ＱＡＭと同様と方式で実行する。 As can be seen from FIG. 18, since the interval between the four candidate signal points is equal, the hard decision circuit 1b4 executes the estimation of the upper 2 bits in the same manner as in 32QAM / 128QAM. .
　上記各実施形態において、送信回路１ａまたは受信回路１ｂは、コンピュータにて実現されてもよい。この場合、このコンピュータは、コンピュータにて読み取り可能なＣＤ－ＲＯＭ（Compact Disk Read Only Memory）のような記録媒体に記録されたプログラムを読込み実行して、送信回路１ａまたは受信回路１ｂが有する機能を実行する。記録媒体は、ＣＤ－ＲＯＭに限らず適宜変更可能である。 In each of the above embodiments, the transmission circuit 1a or the reception circuit 1b may be realized by a computer. In this case, the computer reads and executes a program recorded on a recording medium such as a CD-ROM (Compact Disk Read Only Memory) that can be read by the computer, and has the functions of the transmission circuit 1a or the reception circuit 1b. Execute. The recording medium is not limited to the CD-ROM and can be changed as appropriate.
　以上説明した各実施形態において、図示した構成は単なる一例であって、本発明はその構成に限定されるものではない。 In each of the embodiments described above, the illustrated configuration is merely an example, and the present invention is not limited to the configuration.
　実施形態を参照して本願発明を説明したが、本願発明は上記実施形態に限定されるものではない。本願発明の構成や詳細には、本願発明のスコープ内で当業者が理解し得る様々な変更をすることができる。この出願は、２０１３年４月２３日に出願された日本出願特願２０１３－９０３３３を基礎とする優先権を主張し、その開示の全てをここに取り込む。 Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above-described embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2013-90333 for which it applied on April 23, 2013, and takes in those the indications of all here.
　　　１　　　　多値ＱＡＭ送受信回路
　　　１ａ　　　送信回路
　　　１ａ１　　通信路符号化回路
　　　１ａ２　　遅延合わせ回路
　　　１ａ３　　信号点変換回路
　　　１０１ｃ　ディジタル変調回路
　　　１ｂ　　　受信回路
　　　１０２ａ　ディジタル復調回路
　　　１ｂ１　　信号点逆変換回路
　　　１ｂ２　　通信路復号化回路
　　　１ｂ３　　遅延合わせ回路
　　　１ｂ４　　硬判定回路
　　　１ｂ４１　上位３ビット下位２ビット結合回路
　　　１ｂ４２　信号点変換回路
　　　１ｂ４３　距離比較回路
　　　１ｂ４４　出力回路
　　　２００　　Ｄ／Ａ変換部
　　　３００　　Ａ／Ｄ変換部 DESCRIPTION OF SYMBOLS 1 Multi-value QAM transmission / reception circuit 1a Transmission circuit 1a1 Communication path coding circuit 1a2 Delay adjustment circuit 1a3 Signal point conversion circuit 101c Digital modulation circuit 1b Reception circuit 102a Digital demodulation circuit 1b1 Signal point reverse conversion circuit 1b2 Communication path decoding circuit 1b3 Delay adjustment Circuit 1b4 Hard decision circuit 1b41 Upper 3 bits and lower 2 bits combination circuit 1b42 Signal point conversion circuit 1b43 Distance comparison circuit 1b44 Output circuit 200 D / A conversion unit 300 A / D conversion unit

Claims (8)

  1. 　多値変調された信号を受信し、当該信号に基づいて信号平面での受信信号点を特定する受信信号点特定手段と、
    　前記受信信号点から特定されるデータを構成する複数のビットのうち、前記信号平面において前記ビットの値が変化する境界が前記信号平面を規定する２軸の一方と平行な特定ビットについて、当該特定ビットの値の尤度を、前記受信信号点と当該特定ビットの前記境界との距離に基づいて特定する尤度特定手段と、
    　前記特定ビットの値について前記尤度を用いて軟判定復号する復号手段と、
    　前記多値変調で使用される複数の変調信号点の各々に対応づけられたデータの中から、前記軟判定復号された特定ビットの値を用いて複数の候補データを特定し、前記複数の変調信号点の中から、前記複数の候補データに対応する複数の候補信号点を特定し、前記複数の候補信号点の中から、前記受信信号点までの距離が最も短い該当信号点を特定し、前記該当信号点に対応づけられたデータを用いて、前記複数のビットのうち前記特定ビット以外のビットである所定ビットの値を特定する所定ビット値特定手段と、を含む復調装置。     Receiving signal point specifying means for receiving a multi-level modulated signal and specifying a receiving signal point on a signal plane based on the signal;
    Among the plurality of bits constituting the data specified from the received signal point, the specific bit whose boundary where the value of the bit changes in the signal plane is parallel to one of the two axes defining the signal plane is specified Likelihood specifying means for specifying the likelihood of the value of the bit based on the distance between the received signal point and the boundary of the specific bit;
    Decoding means for soft decision decoding using the likelihood for the value of the specific bit;
    Among the data associated with each of a plurality of modulation signal points used in the multi-level modulation, a plurality of candidate data are specified using a value of the specific bit subjected to the soft decision decoding, and the plurality of modulations Among signal points, identify a plurality of candidate signal points corresponding to the plurality of candidate data, identify the corresponding signal point having the shortest distance to the received signal point from the plurality of candidate signal points, And a predetermined bit value specifying means for specifying a value of a predetermined bit which is a bit other than the specific bit among the plurality of bits using data associated with the signal point.
  2. 　前記特定ビットが、前記複数のビットのうち下位の偶数個のビットとなるように、前記複数の変調信号点の位置と、前記複数の変調信号点に対応するデータとが、設定されている、請求項１に記載の復調装置。 The positions of the plurality of modulation signal points and the data corresponding to the plurality of modulation signal points are set so that the specific bit is an even number of lower bits of the plurality of bits. The demodulation device according to claim 1.
  3. 　前記複数の候補信号点間の距離が等しくなるように、前記複数の変調信号点の配置および前記複数の変調信号点の各々に対応づけられたデータが設定されている、請求項１または２に記載の復調装置。 The arrangement of the plurality of modulation signal points and data associated with each of the plurality of modulation signal points are set so that the distances between the plurality of candidate signal points are equal to each other. The demodulator described.
  4. 　前記変調信号点の数は、２(2n+1)（ただしｎは２以上の整数）であり、
    　前記変調信号点に対応するデータのビット数は、２ｎ＋１である、請求項１から３のいずれか１項に記載の復調装置。     The number of modulation signal points is 2 (2n + 1) (where n is an integer of 2 or more),
    The demodulator according to any one of claims 1 to 3, wherein the number of data bits corresponding to the modulation signal point is 2n + 1.
  5. 　前記ｎは、２以上の整数であり、かつ、変化する値であり、
    　前記所定ビットの数は、前記ｎの値に関わらず一定である、請求項４に記載の復調装置。     N is an integer of 2 or more and a variable value;
    The demodulator according to claim 4, wherein the number of the predetermined bits is constant regardless of the value of n.
  6. 　前記特定ビットが、前記変調信号点に対応するデータの２ｎ＋１ビットのうち下位の２ｎ－２ビットとなるように、前記複数の変調信号点の位置と、前記複数の変調信号点に対応するデータとが、設定されている、請求項５に記載の復調装置。 The position of the plurality of modulation signal points, the data corresponding to the plurality of modulation signal points, and the specific bits are lower 2n-2 bits of 2n + 1 bits of the data corresponding to the modulation signal points 6. The demodulator according to claim 5, wherein is set.
  7. 　復調装置が行う復調方法であって、
    　多値変調された信号を受信し、当該信号に基づいて信号平面での受信信号点を特定し、
    　前記受信信号点から特定されるデータを構成する複数のビットのうち、前記信号平面において前記ビットの値が変化する境界が前記信号平面を規定する２軸の一方と平行な特定ビットについて、当該特定ビットの値の尤度を、前記受信信号点と当該特定ビットの前記境界との距離に基づいて特定し、
    　前記特定ビットの値について前記尤度を用いて軟判定復号し、
    　前記多値変調で使用される複数の変調信号点の各々に対応づけられたデータの中から、前記軟判定復号された特定ビットの値を用いて複数の候補データを特定し、前記複数の変調信号点の中から、前記複数の候補データに対応する複数の候補信号点を特定し、前記複数の候補信号点の中から、前記受信信号点までの距離が最も短い該当信号点を特定し、前記該当信号点に対応づけられたデータを用いて、前記複数のビットのうち前記特定ビット以外のビットである所定ビットの値を特定する、復調方法。     A demodulation method performed by a demodulation device,
    Receiving a multi-level modulated signal, identifying a received signal point in the signal plane based on the signal,
    Among the plurality of bits constituting the data specified from the received signal point, the specific bit whose boundary where the value of the bit changes in the signal plane is parallel to one of the two axes defining the signal plane is specified Specifying the likelihood of the value of the bit based on the distance between the received signal point and the boundary of the specific bit;
    Soft-decision decoding using the likelihood for the value of the specific bit,
    Among the data associated with each of a plurality of modulation signal points used in the multi-level modulation, a plurality of candidate data are specified using a value of the specific bit subjected to the soft decision decoding, and the plurality of modulations Among signal points, identify a plurality of candidate signal points corresponding to the plurality of candidate data, identify the corresponding signal point having the shortest distance to the received signal point from the plurality of candidate signal points, A demodulation method for specifying a value of a predetermined bit that is a bit other than the specific bit among the plurality of bits using data associated with the signal point.
  8. 　コンピュータに、
    　多値変調された信号を受信し、当該信号に基づいて信号平面での受信信号点を特定する受信信号点特定手順と、
    　前記受信信号点から特定されるデータを構成する複数のビットのうち、前記信号平面において前記ビットの値が変化する境界が前記信号平面を規定する２軸の一方と平行な特定ビットについて、当該特定ビットの値の尤度を、前記受信信号点と当該特定ビットの前記境界との距離に基づいて特定する尤度特定手順と、
    　前記特定ビットの値について前記尤度を用いて軟判定復号する復号手順と、
    　前記多値変調で使用される複数の変調信号点の各々に対応づけられたデータの中から、前記軟判定復号された特定ビットの値を用いて複数の候補データを特定し、前記複数の変調信号点の中から、前記複数の候補データに対応する複数の候補信号点を特定し、前記複数の候補信号点の中から、前記受信信号点までの距離が最も短い該当信号点を特定し、前記該当信号点に対応づけられたデータを用いて、前記複数のビットのうち前記特定ビット以外のビットである所定ビットの値を特定する所定ビット値特定手順と、を実行させるためのプログラムを記録したコンピュータ読み取り可能な記録媒体。     On the computer,
    A received signal point specifying procedure for receiving a multi-level modulated signal and specifying a received signal point on a signal plane based on the signal;
    Among the plurality of bits constituting the data specified from the received signal point, the specific bit whose boundary where the value of the bit changes in the signal plane is parallel to one of the two axes defining the signal plane is specified A likelihood specifying procedure for specifying the likelihood of the value of a bit based on the distance between the received signal point and the boundary of the specific bit;
    A decoding procedure for soft decision decoding using the likelihood for the value of the specific bit;
    Among the data associated with each of a plurality of modulation signal points used in the multi-level modulation, a plurality of candidate data are specified using a value of the specific bit subjected to the soft decision decoding, and the plurality of modulations Among signal points, identify a plurality of candidate signal points corresponding to the plurality of candidate data, identify the corresponding signal point having the shortest distance to the received signal point from the plurality of candidate signal points, A program for executing a predetermined bit value specifying procedure for specifying a value of a predetermined bit that is a bit other than the specific bit among the plurality of bits using data associated with the corresponding signal point is recorded. Computer-readable recording medium.
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