WO2014173218A1 - 一种基于低维半导体结构的倍频器 - Google Patents

一种基于低维半导体结构的倍频器 Download PDF

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WO2014173218A1
WO2014173218A1 PCT/CN2014/073996 CN2014073996W WO2014173218A1 WO 2014173218 A1 WO2014173218 A1 WO 2014173218A1 CN 2014073996 W CN2014073996 W CN 2014073996W WO 2014173218 A1 WO2014173218 A1 WO 2014173218A1
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layer
insulating
conductive layer
semiconductor
dimensional
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PCT/CN2014/073996
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French (fr)
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许坤远
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华南师范大学
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Priority to US14/767,301 priority Critical patent/US9530845B2/en
Publication of WO2014173218A1 publication Critical patent/WO2014173218A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
    • H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
    • H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device

Definitions

  • Frequency multiplier based on low-dimensional semiconductor structure
  • the present invention relates to a frequency multiplier based on a low dimensional semiconductor structure, and more particularly to a frequency multiplier that does not require the addition of an additional filtering circuit and can operate in the terahertz band at normal temperature. Background technique
  • the device's feature size continues to shrink, from the micron level to the current nanoscale; and the corresponding material architecture used also ranges from traditional high latitude (3D) to low dimensional (2D, Quasi-one-dimensional and one-dimensional) transformation.
  • Devices based on low-dimensional semiconductor structures are generally considered to be ideal for high-frequency devices because of their simple process, ease of integration, and low parasitic capacitance.
  • the shielding effect of the low-dimensional conductive structure on the electric field is greatly weakened, which results in a strong electric field distribution around the conductive structure, and the electric field coupling between the conductive structures is greatly enhanced.
  • a physical phenomenon called “self-gate effect” has appeared in "Y"-type planar nano-switching devices (J. Jan-olof and J. Wesstrom, “Self- Gating Effect in the Electron Y-Branch Switch” , Phys. Rev. Lett. 82, 2564 (1999) . ) 0
  • Multiplier technology has long been an integral part of wireless communication and broadcast technology. With the rapid development of technology, the reliance on frequency doubling technology is increasing day by day. Currently, digital communication, analog communication, radio astronomy and terahertz science and technology have great demand for frequency doubling technology.
  • the nonlinear component will distort the waveform of the input signal.
  • the frequency component of the output signal will change. This is the physical basis for the familiar frequency multiplication.
  • the current nonlinear multipliers mainly include two categories: one is a diode-based frequency multiplier; the other is a FET-based frequency multiplier. A common feature of these multipliers is that the output signal contains multiple frequency components, so additional filtering circuitry is required.
  • the frequency multiplier is also based on the nonlinear characteristics of the FET, but the material for the FET is not a traditional material, but a new material with unique electrical properties - graphene.
  • the field effect transistor made of this new material has a special "V" type current-voltage characteristic, which makes the output signal only contain the second harmonic of the input signal, so it can be fabricated by using a single graphene field effect transistor.
  • the frequency multiplier is out and no additional filtering circuit is required.
  • a frequency multiplier based on a low-dimensional semiconductor structure comprising an insulating substrate layer, a semiconductor conductive layer disposed on a surface of the insulating substrate layer, an insulating protective layer disposed on a surface of the semiconductor conductive layer, and an insulating groove penetrating the semiconductor conductive layer, An access electrode on a surface of one side of the semiconductor conductive layer and an output electrode disposed on a surface corresponding to the side of the access pole, the semiconductor conductive layer comprising two two-dimensional, one-dimensional or one-dimensional ones that are close to each other and arranged in parallel Carrier channel.
  • the gap between the two carrier channels is less than 1 micron.
  • the dielectric constant of the insulating protective layer is higher than the dielectric constant of the semiconductor conductive layer.
  • the insulating groove when the carrier channel is in a one-dimensional dimension, includes a first insulating groove symmetrically disposed, a second insulating groove, and a first insulating groove and a second insulating groove a third insulating groove; one end of the first insulating groove, one end of the second insulating groove, and one end of the third insulating groove extend to the side surface of the conductive layer respectively; the access electrode and the extraction electrode are respectively disposed On the opposite side surface of the conductive layer, the access electrode includes a first access electrode, a second insulating groove and a third, respectively disposed on a side surface of the conductive layer region formed by the first insulating groove and the third insulating groove The insulating groove encloses the formed second conductive electrode of the conductive layer region and the same side surface as the first access electrode.
  • the semiconductor conductive layer is an AlGaN/GaN heterojunction comprising an AlGaN layer, a GaN layer, and a two-dimensional electron gas layer formed between the AlGaN layer and the GaN layer.
  • the semiconductor conductive layer is an AlGaAs/InGaAs heterojunction comprising an InGaAs layer, an AlGaAs layer, and a doped region formed in the AlGaN layer to form a two-dimensional electron gas layer between the AlGaN layer and the GaN layer.
  • the dielectric constant of the third insulating groove is higher than the dielectric constant of the semiconductor conductive layer.
  • an insulating spacer layer and a second semiconductor conductive layer are sequentially included between the insulating protective layer and the semiconductor conductive layer; the semiconductor structure of the frequency multiplier is from the bottom layer
  • the surface to the surface includes an insulating substrate layer, a semiconductor conductive layer, an insulating spacer layer, a second semiconductor conductive layer, and an insulating protective layer, respectively.
  • the access electrode includes a first access electrode disposed on a bottom surface of the insulating substrate layer and connected to the curved portion of the semiconductor conductive layer, and a second access electrode disposed on the surface of the insulating protective layer and connected to the curved portion of the second semiconductor conductive layer;
  • the output end is connected to the insulating protective layer, the second semiconductor conductive layer, the insulating spacer layer, the semiconductor conductive layer and the insulating protective layer.
  • the invention has simple structure and easy process, and no additional filter circuit is needed.
  • the material properties are small, so the material can choose a wide range, including various inorganic, organic semiconductors and new nano-semiconductor materials carbon nanotubes and graphene.
  • 1 is a schematic view showing the surface of a frequency multiplier in which a carrier channel is one-dimensional in the first embodiment
  • Figure 2 is a cross-sectional view taken along line A-A of Figure 1;
  • Fig. 3 is a graph showing the output characteristics of the carrier channel obtained by Monte Carlo simulation as a quasi-one-dimensional under the action of two high-frequency signals;
  • FIG. 4 is a diagram showing the change of the input characteristic signal of the carrier characteristic of the carrier channel obtained by Monte Carlo simulation with frequency;
  • FIG. 5 is a multi-frequency multiplier of the carrier channel in the second embodiment;
  • Figure 6 is a cross-sectional view taken along line B-B of Figure 5;
  • 3 two-dimensional conductive layer
  • 31 AlGaN layer
  • 32 GaN layer
  • 33 two-dimensional electron gas layer
  • 311 doped region
  • 61 insulation substrate layer
  • 62 semiconductor conductive layer
  • 63 insulation spacer layer
  • 64 second semiconductor conductive layer
  • 65 insulating protective layer.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • FIG. 1 is a top view of a frequency multiplier based on a low-dimensional semiconductor structure according to the embodiment, which omits insulation
  • the protective layer from which the first insulating groove 11, the second insulating groove 12, the third insulating groove 13, the first access electrode 21, the second access electrode 22 and the extraction electrode 23 can be seen.
  • the third insulating groove 13 is inserted between the oppositely disposed first insulating notches 11 and the second insulating notches 12.
  • the gap between the first insulating groove 11 and the third insulating groove 13 constitutes the first carrier channel 14; the gap between the second insulating groove 12 and the third insulating groove 13 constitutes the second load Stream channel 15.
  • a region surrounded by the first insulating groove 11 and the third insulating groove 13 is a first low resistance region 16; a region surrounded by the second insulating groove 12 and the third insulating groove 13 is a second low resistance region 17;
  • the low resistance region 16, the second low resistance region 17, and the semiconductor conductive layers other than the first carrier channel 14 and the second carrier channel 15 are the third low resistance regions 18.
  • the insulating groove can be obtained by dry etching, and the depth of the insulating groove is required to penetrate the two-dimensional conductive layer 3 to the shallowest depth.
  • the first access electrode 21 is disposed on a side surface of the first low resistance region 16 at a surface perpendicular to the plane of the first carrier channel 14.
  • the second access electrode 22 is disposed on a side surface of the second low resistance region 17 at a surface perpendicular to the plane of the second carrier channel 15.
  • the take-off electrode 23 is disposed on the side surface of the third low-resistance region 18 in a plane perpendicular to the plane of the first carrier channel 14 or the second carrier channel 15. That is, the first access electrode 21, the second access electrode 22, and the extraction electrode 23 are respectively disposed on opposite sides of the semiconductor conductive layer. Input signals are input from the first access electrode 21 and the second access electrode 22, respectively, through the first low resistance region 16 and the second low resistance region 17, the first carrier channel 14 and the second carrier trench The track 15, the third low resistance region 18, is output from the take-off electrode 23.
  • the carrier channel is made of a semiconductor material. Further, in order to realize the coupling between the carrier channels by the "self-gate effect", the carrier channel adopts a two-dimensional, quasi-one-dimensional or one-dimensional low-dimensional structure.
  • the semiconductor material of this embodiment employs a one-dimensional low-dimensional structure.
  • the first carrier channel 14 and the second carrier channel 15 are arranged in parallel with a gap of ⁇ ! ⁇ ⁇ . ⁇ ⁇ ⁇ between.
  • the self-gate effect is an effect on the nanometer scale, which means that when the carrier channels are close together, the lateral electric field caused by the potential difference between the carrier channels can change the transport properties of carriers in the channel.
  • the effect is similar to the effect of the gate of the FET, but in fact there is no gate, the English is Self-gating ef f ect.
  • the frequency multiplier of this embodiment includes an insulating substrate layer 35, a semiconductor conductive layer 3 disposed on the surface of the insulating substrate layer, and an insulating protective layer 34 disposed on the surface of the semiconductor conductive layer.
  • the first insulating groove 11, the second insulating groove 12, and the third insulating groove 13 penetrate the semiconductor conductive layer 3. Further, the high dielectric constant of the third insulating groove 13 is higher than the dielectric constant of the semiconductor semiconductor conductive layer 3.
  • the insulating protective layer 18 has a high dielectric constant and a dielectric constant higher than that of the semiconductor conductive layer 3.
  • the high dielectric constant insulating material can achieve the effect of enhancing the mutual coupling of the carrier channels, so that a good signal output curve can be obtained when the carrier channel spacing is greater than 1 micron.
  • the semiconductor conductive layer is an AlGaN/GaN heterojunction comprising an AlGaN layer, a GaN layer, and a two-dimensional electron gas layer formed between the AlGaN layer and the GaN layer. Since GAN has a self-polarization effect, it can form a two-dimensional electron gas layer. Further, the semiconductor conductive layer is an AlGaAs/InGaAs heterojunction comprising an InGaAs layer, an AlGaAs layer, and a doped region formed in the AlGaN layer to form a two-dimensional electron gas layer between the AlGaN layer and the GaN layer. The doped region here functions to introduce a two-dimensional electron gas.
  • the semiconductor conductive layer is the working characteristic of the AlGaN/GaN heterojunction structure at normal temperature.
  • the semiconductor conductive layer in the simulation uses a structure having the following characteristics:
  • the carrier channel length is 400 nm
  • the width is 50 nm
  • the insulating groove width between the carrier channels is 200 nm
  • the dielectric constant is 12.
  • Figure 3 shows the multiplier output characteristics under the action of two high frequency signals. At t ⁇ 20 ps, both the first access electrode 21 and the second access electrode 22 have no signal input, and the output current of the output electrode 23 is zero. In this simulation, a sinusoidal AC signal having an amplitude of _5 V and a period of 2.
  • FIG. 3 shows the time average of the output AC signal is no longer zero, which means that the structure of the embodiment can also be used for rectifying the high frequency signal.
  • Figure 4 shows the amplitude of the output multiplying oscillating current as a function of the input signal frequency.
  • the output signal with an input frequency of 0. ITHz is used as the normalized denominator. From the simulation results, the operating cutoff frequency of the present invention at normal temperature, that is, the frequency of the input signal, is about 2. 5 THz. Since the output signal is twice the input signal, the cutoff frequency of the output signal is approximately 5 THz.
  • the semiconductor conductive layer is a two-dimensional semiconductor material.
  • FIG. 5 is a schematic diagram of a surface of a frequency multiplier with a carrier channel in the embodiment.
  • the first insulating notch 41 and the second insulating notch 42 are oppositely disposed, and a gap between the first insulating notch 41 and the second insulating notch 42 forms a carrier channel.
  • On the first insulating groove 41, the carrier channel and the second insulating groove 42 one side is the first low resistance region 45, and the other side is the second low resistance region 46.
  • the first low resistance region 45 is in communication with the second low resistance region 46 through the carrier channel.
  • the semiconductor structure of the frequency multiplier when the carrier channel is two-dimensional, includes an insulating substrate layer 61, a semiconductor conductive layer 62, an insulating spacer layer 63, and a second semiconductor, respectively, from the bottom layer to the surface.
  • the insulating protective layer 65 or the insulating spacer 63 is made of a high dielectric constant insulating material which enhances the mutual coupling of the carrier channels so that the channel pitch can be larger than 1 ⁇ m and the output signal is not affected.
  • FIG. 6 is a schematic structural view of a frequency multiplier with a carrier channel in the present invention.
  • the longitudinal structure of the frequency multiplier of this embodiment includes, in order from bottom to top, a second access electrode 52, an insulating substrate layer 61, a semiconductor conductive layer 62, an insulating spacer layer 63, a second semiconductor conductive layer 64, an insulating protective layer 65, and An access electrode 51 is provided. Further, on the right side, there is an output end 53 connected to the second semiconductor conductive layer 64 and the semiconductor conductive layer 62. In the dotted portion of the second semiconductor conductive layer 64 of FIG.
  • the domain is the first carrier channel 43, and the dotted portion of the semiconductor conductive layer 62 is the second carrier channel 44, and the width of the insulating spacer between the two carrier channels is less than 1 micron.
  • the left ends of the semiconductor conductive layer 62 and the second semiconductor conductive layer 64 are respectively bent toward the substrate and the device surface.
  • the top view structure of the device includes a first access electrode 51 from left to right, and connects the first access electrode 51 and the second input terminal 52 and the first low resistance region 45 of the carrier channel, the first carrier channel 43.
  • a second low resistance region 46 connecting the carrier channel and the output terminal 53 to the output electrode 26.
  • the depth of the first insulating groove 41 must be able to penetrate the second semiconductor conductive layer 64, and the depth of the second insulating groove 42 must be able to penetrate the semiconductor conductive layer 62.

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Abstract

本发明公开了一种基于低维半导体结构的倍频器，包括绝缘衬底层、设置在绝缘衬底层表面的半导体导电层，设置在半导体导电层表面的绝缘保护层，穿透半导体导电层的绝缘刻槽，设置在半导体导电层一侧表面的接入电极和设置在接入极对应一侧表面的接出电极，所述半导体导电层包括两条相互靠近且平行设置的二维、准一维或一维的载流子沟道。本发明的倍频器结构简单，工艺容易实现，无需额外添加滤波电路，还有对材料特性依赖小，材料可选择范围宽等优点。

Description

一种基于低维半导体结构的倍频器
技术领域
本发明涉及一种基于低维半导体结构的倍频器， 尤其涉及无需添加额外滤波电路且能在 常温下工作于太赫兹频段的倍频器。 背景技术
随着半导体技术的持续发展， 器件的特征尺寸不断缩小， 从微米量级一直到现在的纳米 量级； 而且所用对应的材料体系结构也从传统的高纬度 （三维） 向低维 （二维、 准一维和一 维） 转变。 基于低维半导体结构的器件一般工艺简单、 易于集成而且寄生电容小， 因此被认 为是高频器件的理想选择。
此外， 相比于三维的导电结构， 低维导电结构对电场的屏蔽效应大为减弱， 这就导致导 电结构的周围将存在很强的电场分布， 导电结构间的电场耦合大大增强。 由于低维导电结构 的这种特性导致了 "Y"型平面纳米开关器件中出现了一种被称之为 "自栅效应"的物理现象 ( J. Jan-olof and J. Wesstrom, " Self-Gating Effect in the Electron Y-Branch Switch" , Phys. Rev. Lett. 82, 2564 (1999) . ) 0
倍频技术一直以来就是无线通信和广播技术不可或缺的组成部分。随着科技的迅猛发展， 对倍频技术的依赖更是与日俱增， 目前数字通信、 模拟通信、 射电天文学以及太赫兹科学技 术等多个领域都对倍频技术有很大的需求。
非线性元件会使得输入信号的波形产生畸变， 根据傅立叶变换理论， 输出信号的频率成 份将发生变化。 这便是大家熟知的倍频产生的物理基础。 目前的非线性倍频器主要包括了两 大类： 一类为基于二极管的倍频器； 另一类为基于场效应管的倍频器。 这些倍频器有一个共 同的特点就是输出信号包含多种频率成份， 因此需要增加额外的滤波电路。
最近 MIT的研究者们发明了首个由单个场效应管构成的无需外加滤波电路的倍频器 （H. Wang, D. Nezich, J. Kong and T. Palacios, "Graphene frequency multipl iers "， IEEE Electron Device Letters 30, 547 (2009) )。 该倍频器同样也是基于场效应管的非线性特性， 但制作场效应管的材料却不是传统的材料， 而是具有独特电学性质的新型材料——石墨烯。 由这种新材料制成的场效应管具有特殊的 "V"型电流电压特性， 这使得输出的信号只含有输 入信号的二次谐波， 因此只需采用单个石墨烯场效应管就能够制作出倍频器且无需再外加滤 波电路。
MIT研究者们的上述发明大大简化了倍频器电路，但该发明是基于制作材料的独特电学性 质， 也就是说该发明具有很强的材料依赖性， 不能采用其它材料体系来实现。 发明内容
本发明的目的， 就是克服现有技术的不足， 提供一种对材料特性依赖性小而且无需额外 滤波电路的基于低维半导体结构的倍频器。
为了达到上述目的， 采用如下技术方案：
一种基于低维半导体结构的倍频器， 包括绝缘衬底层、 设置在绝缘衬底层表面的半导体 导电层， 设置在半导体导电层表面的绝缘保护层， 穿透半导体导电层的绝缘刻槽， 设置在半 导体导电层一侧表面的接入电极和设置在接入极对应一侧表面的接出电极， 所述半导体导电 层包括两条相互靠近且平行设置的二维、 准一维或一维的载流子沟道。
进一步地， 所述两条载流子沟道之间的间隙小于 1微米。
进一步地， 所述绝缘保护层的介电常数高于半导体导电层的介电常数。
进一步地， 所述载流子沟道为准一维时， 所述绝缘刻槽包括对称设置的第一绝缘刻槽、 第二绝缘刻槽和设置在第一绝缘刻槽及第二绝缘刻槽之间的第三绝缘刻槽； 所述第一绝缘刻 槽一端、 第二绝缘刻槽一端、 第三绝缘刻槽一端分别延伸至导电层侧表面； 所述接入电极和 接出电极分别设置在导电层相对侧表面， 所述接入电极包括分别设置在第一绝缘刻槽与第三 绝缘刻槽包围形成的导电层区域侧表面的第一接入电极， 第二绝缘刻槽与第三绝缘刻槽包围 形成的导电层区域、 并与第一接入电极相同侧表面的第二接入电极。
进一步地，所述半导体导电层为 AlGaN/GaN异质结，其包括 AlGaN层、 GaN层以及在 AlGaN 层和 GaN层之间形成二维电子气层。
进一步地， 所述半导体导电层为 AlGaAs/InGaAs异质结， 其包括 InGaAs层、 AlGaAs层、 以及在 AlGaN层设置的在 AlGaN层和 GaN层之间形成二维电子气层的 掺杂区。
进一步地， 所述第三绝缘刻槽的介电常数高于半导体导电层的介电常数。
进一步地， 所述载流子沟道为二维时， 在绝缘保护层和半导体导电层之间还依次包括一 绝缘间隔层和一第二半导体导电层； 所述倍频器的半导体结构从底层到表面分别依次包括绝 缘衬底层、 半导体导电层、 绝缘间隔层、 第二半导体导电层和绝缘保护层。
进一步地， 所述半导体导电层一端弯曲延伸至绝缘衬底层底部表面， 第二半导体导电层 一端弯曲延伸至绝缘保护层表面， 所述半导体导电层的弯曲部分和第二半导体导电层弯曲部 分相对； 所述接入电极包括设于绝缘衬底层底部表面并连接半导体导电层弯曲部分的第一接 入电极， 设于绝缘保护层表面并与第二半导体导电层弯曲部分连接的第二接入电极； 所述输 出端与绝缘保护层、 第二半导体导电层、 绝缘间隔层、 半导体导电层和绝缘保护层连接。 与现有技术相比， 本发明的有益效果在于：
1、 本发明结构简单， 工艺容易实现， 无需额外添加滤波电路。
2、 对材料特性依赖小， 因此材料可选择范围宽， 包括各类无机、 有机半导体以及新型的纳 米半导体材料碳纳米管和石墨烯。
3、 能常温工作且工作频率高。 选择恰当的材料可在常温工作于太赫兹频段。 附图说明
图 1是第一实施例中载流子沟道为准一维的倍频器的表面示意图；
图 2是图 1的 A-A剖视图；
图 3由蒙特卡罗模拟获得的载流子沟道为准一维的在两个高频信号的作用下的输出特性 曲线图；
图 4由蒙特卡罗模拟获得的载流子沟道为准一维的工作特性输入信号随频率的变化图； 图 5是第二实施例中载流子沟道为二维的倍频器的表面示意图；
图 6是图 5的 B-B剖视图。
图示： 11一第一绝缘刻槽； 12—第二绝缘刻槽； 13—第三绝缘刻槽；
14一第一载流子沟道； 15—第二载流子沟道； 16—第一低电阻区；
17—第二低电阻区； 18—第三低电阻区；
21—第一接入电极； 22—第二接入电极； 23—接出电极；
3—二维导电层； 31— AlGaN层； 32— GaN层； 33—二维电子气层； 311—掺杂区；
34—绝缘保护层； 35—绝缘衬底层；
41一第一绝缘刻槽； 42—第二绝缘刻槽； 43—第一载流子沟道； 44一第二载流子沟道；
45—第一低电阻区； 46—第二低电阻区；
51—第一接入电极； 52—第二接入电极； 53—接出电极；
61—绝缘衬底层； 62—半导体导电层； 63—绝缘间隔层； 64—第二半导体导电层； 65—绝缘保护层。 具体实施方式 下面将结合附图以及具体实施方法来详细说明本发明， 在本发明的示意性实施及说明用 来解释本发明， 但并不作为对本发明的限定。
实施例一：
请参阅图 1， 其为本实施例所述基于低维半导体结构的倍频器的俯视图， 其省略了绝缘 保护层， 由此可以看见第一绝缘刻槽 11， 第二绝缘刻槽 12， 第三绝缘刻槽 13， 第一接入电 极 21， 第二接入电极 22和接出电极 23。 第三绝缘刻槽 13插入相对设置的第一绝缘刻槽 11 和第二绝缘刻槽 12之间。第一绝缘刻槽 11和第三绝缘刻槽 13之间的空隙构成了第一载流子 沟道 14; 第二绝缘刻槽 12和第三绝缘刻槽 13之间的空隙构成了第二载流子沟道 15。第一绝 缘刻槽 11与第三绝缘刻槽 13包围的区域为第一低电阻区 16; 第二绝缘刻槽 12与第三绝缘 刻槽 13包围的区域为第二低电阻区 17; 第一低电阻区 16、第二低电阻区 17以及第一载流子 沟道 14、 第二载流子沟道 15之外的半导体导电层为第三低电阻区 18。 绝缘刻槽可以通过干 法刻蚀获得， 绝缘沟槽的深度以能够穿透二维导电层 3为最浅深度要求。
第一接入电极 21设置在第一低电阻区 16的侧表面，其所在表面与第一载流子沟道 14所 在平面垂直。 第二接入电极 22设置在第二低电阻区 17的侧表面， 其所在表面与第二载流子 沟道 15所在平面垂直。接出电极 23设置在第三低电阻区 18的侧表面， 其所在平面与第一载 流子沟道 14或第二载流子沟道 15所在平面垂直。 即第一接入电极 21、 第二接入电极 22和 接出电极 23分别设置在半导体导电层的相对侧面。 输入信号分别从第一接入电极 21、 第二 接入电极 22输入， 分别经过第一低电阻区 16和第二低电阻区 17， 第一载流子沟道 14和第 二载流子沟道 15， 第三低电阻区 18， 从接出电极 23输出。
为了使倍频器的电特性能为外电场所调控， 载流子沟道采用半导体材料。 进一步， 为了 利用 "自栅效应"实现载流子沟道间的耦合， 载流子沟道采用二维、 准一维或一维的低维结 构。 本实施例半导体材料采用一维的低维结构。 其中第一载流子沟道 14 和第二载流子沟道 15平行设置， 其间隙在 ΙΟΟηπ！〜 Ι. Ο μ πι之间。 自栅效应是纳米尺度的一种效应， 指的是当 载流子沟道靠得很近时， 载流子沟道间电势差引起的侧向电场能够改变沟道中载流子的输运 性质，其效果类似于场效应管的栅的作用，但实际上并没有栅的存在，其英文为 Self-gating ef f ect。
请参阅图 2， 其为图 1的 A-A截面图。 本实施例的倍频器包括绝缘衬底层 35、 设置在绝 缘衬底层表面的半导体导电层 3， 设置在半导体导电层表面的绝缘保护层 34。 所述第一绝缘 刻槽 11、 第二绝缘刻槽 12和第三绝缘刻槽 13穿透半导体导电层 3。 进一步地， 所述第三绝 缘刻槽 13的高介电常数高于半导体半导体导电层 3的介电常数。 所述绝缘保护层 18为高介 电常数， 其介电常数高于半导体导电层 3介电常数。 高介电常数的绝缘材料可以达到增强载 流子沟道的相互耦合的效果， 使得载流子沟道间距大于 1微米时， 也能获得良好的信号输出 曲线。
进一步地，所述半导体导电层为 AlGaN/GaN异质结，其包括 AlGaN层、 GaN层以及在 AlGaN 层和 GaN层之间形成二维电子气层。 由于 GAN具有自极化作用， 其能形成二维电子气层。 进一步地， 所述半导体导电层为 AlGaAs/InGaAs异质结， 其包括 InGaAs层、 AlGaAs层、 以及在 AlGaN层设置的在 AlGaN层和 GaN层之间形成二维电子气层的 掺杂区。 此处的掺杂 区起到引入二维电子气的作用。
参阅图 3和图 4， 利用系宗蒙特卡罗模拟可获得： 半导体导电层为 AlGaN/GaN异质结结 构在常温下的工作特性。 模拟时半导体导电层采用了具如下特征的结构： 载流子沟道长度为 400nm, 宽度为 50纳米， 载流子沟道间的绝缘刻槽宽度为 200nm、 介电常数为 12。 图 3展示 出了在两个高频信号作用下的倍频器输出特性。 在 t〈20ps的时候， 第一接入电极 21和第二 接入电极 22均无信号输入， 接出电极 23的输出电流为零。 在本次模拟中， 采用幅度为 _5V、 周期为 2. 5ps,对应频率 0. 4THz的正弦交流信号作为第一接入电极 21的输入信号。在 t=20ps 时施加于第一接入电极 21上， 此后接出电极 23输出周期等于 2. 5ps的振荡电流。 使用幅度 为 _5V、周期为 2. 5ps的正弦交流信号在 t=26. 25ps时施加于第二接入电极 22上，此时输出端 23输出周期等于 1. 25ps, 对应于频率为 0. 8THz的振荡电流。可见在两个频率均为 0. 4THz的 信号作用下， 输出频率为 O. STHz的信号， 实现了倍频的效果。 此外由图 3可见输出交流信号 的时间平均值不再为零， 这说明本实施例结构也可以用于对高频信号进行整流。 图 4给出了 输出倍频振荡电流幅度随输入信号频率的变化情况，其中采用输入频率为 0. ITHz时的输出信 号作为归一化的分母。 由模拟结果可见本发明在常温下的工作截止频率， 即输入信号的频率， 约为 2. 5THz。 由于输出信号为输入信号的两倍， 因此输出信号的截止频率约为 5THz。
实施例二
本实施例中， 半导体导电层采用二维半导体材料。
请参阅图 5， 其为本实施例中载流子沟道为二维的倍频器的表面示意图。所述第一绝缘刻 槽 41、 第二绝缘刻槽 42相对设置， 第一绝缘刻槽 41和第二绝缘刻槽 42之间的间隙形成了 载流子沟道。在第一绝缘刻槽 41、载流子沟道和第二绝缘刻槽 42的一侧为第一低电阻区 45， 另一侧为第二低电阻区 46。 第一低电阻区 45通过载流子沟道与第二低电阻区 46连通。
请参阅图 6， 所述载流子沟道为二维时， 所述倍频器的半导体结构从底层到表面分别依次 包括绝缘衬底层 61、 半导体导电层 62、 绝缘间隔层 63、 第二半导体导电层 64和绝缘保护层 65。 绝缘保护层 65或绝缘间隔层 63采用高介电常数的绝缘材料， 其可以增强载流子沟道的 相互耦合， 使得沟道间距可以大于 1微米而输出信号不受影响。
参看图 6， 为本发明中载流子沟道为二维的倍频器的结构示意图。本实施例倍频器的纵向 结构由下往上依次包括第二接入电极 52、 绝缘衬底层 61、 半导体导电层 62、 绝缘间隔层 63、 第二半导体导电层 64、 绝缘保护层 65以及第一接入电极 51。 此外右侧还有与第二半导体导 电层 64和半导体导电层 62相连的输出端 53。 在图 6的第二半导体导电层 64的虚线部分区 域为第一载流子沟道 43， 半导体导电层 62的虚线部分区域为第二载流子沟道 44， 两载流子 沟道之间的绝缘间隔层宽度为小于 1微米。 为了便于制作电极并减小极间电容， 半导体导电 层 62和第二半导体导电层 64的左端分别向衬底和器件表面弯曲。 器件的俯视结构从左到右 包括第一接入电极 51， 连接第一接入电极 51及第二输入端 52和载流子沟道的第一低电阻区 45， 第一载流子沟道 43， 连接载流子沟道和输出端 53的第二低电阻区 46， 输出电极 26。 第 一绝缘刻槽 41的深度必须能够穿透第二半导体导电层 64， 第二绝缘刻槽 42的深度必须能够 穿透半导体导电层 62。
以上对本发明实施例所提供的技术方案进行了详细介绍， 本文中应用了具体个例对本发 明实施例的原理以及实施方式进行了阐述， 以上实施例的说明只适用于帮助理解本发明实施 例的原理； 同时， 对于本领域的一般技术人员， 依据本发明实施例， 在具体实施方式以及应 用范围上均会有改变之处， 综上所述， 本说明书内容不应理解为对本发明的限制。

Claims

1、 一种基于低维半导体结构的倍频器， 包括绝缘衬底层、设置在绝缘衬底层表面的半导 体导电层， 设置在半导体导电层表面的绝缘保护层， 穿透半导体导电层的绝缘刻槽， 设置在 半导体导电层一侧表面的接入电极和设置在接入极对应一侧表面的接出电极， 其特征在于： 所述半导体导电层包括两条相互靠近且平行设置的二维、 准一维或一维的载流子沟道。
2、 根据权利要求 1所述的基于低维半导体结构的倍频器， 其特征在于： 所述两条载流子 沟道之间的间隙小于 1微米。
3、 根据权利要求 1所述的基于低维半导体结构的倍频器， 其特征在于： 所述绝缘保护层 的介电常数高于半导体导电层的介电常数。
4、 根据权利要求 1或 2或 3所述的基于低维半导体结构的倍频器， 其特征在于： 所述载 流子沟道为准一维时， 所述绝缘刻槽包括对称设置的第一绝缘刻槽、 第二绝缘刻槽和设置在 第一绝缘刻槽及第二绝缘刻槽之间的第三绝缘刻槽； 所述第一绝缘刻槽一端、 第二绝缘刻槽 一端、 第三绝缘刻槽一端分别延伸至导电层侧表面； 所述接入电极和接出电极分别设置在导 电层相对侧表面， 所述接入电极包括分别设置在第一绝缘刻槽与第三绝缘刻槽包围形成的导 电层区域侧表面的第一接入电极， 第二绝缘刻槽与第三绝缘刻槽包围形成的导电层区域、 并 与第一接入电极相同侧表面的第二接入电极。
5、 根据权利要求 4所述的基于低维半导体结构的倍频器， 其特征在于： 所述半导体导电 层为 AlGaN/GaN异质结， 其包括 AlGaN层、 GaN层以及在 AlGaN层和 GaN层之间形成二维电 子气层。
6、 根据权利要求 4所述的基于低维半导体结构的倍频器， 其特征在于： 所述半导体导电 层为 AlGaAs/InGaAs异质结， 其包括 InGaAs层、 AlGaAs层、 以及在 AlGaN层设置的在 AlGaN 层和 GaN层之间形成二维电子气层的 掺杂区。
7、 根据权利要求 4所述的基于低维半导体结构的倍频器， 其特征在于： 所述第三绝缘刻 槽的介电常数高于半导体导电层的介电常数。
8、 根据权利要求 1所述的基于低维半导体结构的倍频器， 其特征在于： 所述载流子沟道 为二维时， 在绝缘保护层和半导体导电层之间还依次包括一绝缘间隔层和一第二半导体导电 层； 所述倍频器的半导体结构从底层到表面分别依次包括绝缘衬底层、 半导体导电层、 绝缘 间隔层、 第二半导体导电层和绝缘保护层。
9、 根据权利要求 8所述的基于低维半导体结构的倍频器， 其特征在于： 所述半导体导电 层一端弯曲延伸至绝缘衬底层底部表面，第二半导体导电层一端弯曲延伸至绝缘保护层表面， 所述半导体导电层的弯曲部分和第二半导体导电层弯曲部分相对； 所述接入电极包括设于绝 缘衬底层底部表面并连接半导体导电层弯曲部分的第一接入电极， 设于绝缘保护层表面并与 第二半导体导电层弯曲部分连接的第二接入电极； 所述输出端与绝缘保护层、 第二半导体导 电层、 绝缘间隔层、 半导体导电层和绝缘保护层连接。
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