WO2014166126A1 - 显示信号处理系统、电路板及液晶显示装置 - Google Patents

显示信号处理系统、电路板及液晶显示装置 Download PDF

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Publication number
WO2014166126A1
WO2014166126A1 PCT/CN2013/074331 CN2013074331W WO2014166126A1 WO 2014166126 A1 WO2014166126 A1 WO 2014166126A1 CN 2013074331 W CN2013074331 W CN 2013074331W WO 2014166126 A1 WO2014166126 A1 WO 2014166126A1
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Prior art keywords
signal
circuit
resistor
port
selection
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English (en)
French (fr)
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吴东光
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/884,290 priority Critical patent/US8964118B2/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units

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  • the present invention relates to the field of communication interface transmission technologies, and in particular, to a display signal processing system, a circuit board, and a liquid crystal display device.
  • the high-frequency signal transmission currently set between the two uses LVDS with ultra-high speed, low power consumption and low electromagnetic radiation characteristics. (Low-Voltage Differential Signaling, low voltage differential) signal.
  • FIG. 1 is a schematic block diagram of a prior art display signal processing system 100.
  • the acquisition of the LVDS signal must be performed by means of the V-by-One circuit 120, and the acquisition process is: the image processing circuit 110 inputs the format-converted display signal from the signal source, The V-by-One circuit 120 converts this display signal into a corresponding LVDS signal.
  • the mapping of LVDS signals mainly includes JEIDA (Japan). Electronic Industry Development Association, Japan Electronics Industry Development Association) mode and VESA (Video Electronics Standards Association, Video Electronics Standards Association) model.
  • JEIDA Joint Imaging Association
  • VESA Video Electronics Standards Association, Video Electronics Standards Association
  • the current V-by-One circuit 120 internally defaults to the JEIDA mode. If the user needs to switch to the VESA mode, the driving capability of the circuit must be controlled by the image processing circuit 110 through the I2C bus 130 from high to low to change the data mapping. The sequence is such that the V-by-One circuit 130 outputs the VESA mode, which is cumbersome to operate and relatively expensive.
  • the technical problem to be solved by the present invention is to provide a display signal processing system, a circuit board and a liquid crystal display device, and realize V-by-One with a more simplified circuit system.
  • the selective switching of the VESA mode and the JEIDA mode of the circuit is simple in operation and low in cost.
  • a technical solution adopted by the present invention is to provide a display signal processing system including an image processing circuit and a V-by-One circuit having a JEIDA mode and a VESA mode selection;
  • the image processing circuit is configured to format convert the display signal from the signal source, and output the formatted display signal to the V-by-One circuit;
  • the V-by-One circuit includes a signal input port, a GPIO port, and a signal output port.
  • the signal input port is connected to the image processing circuit to input the formatted display signal
  • the GPIO port is used to selectively input the first selection signal, so that
  • the V-by-One circuit converts the formatted display signal into a first LVDS signal in JEIDA mode, and then outputs it through a signal output port; or selectively inputs a second selection signal to make the V-by-One circuit In the VESA mode, the format converted display signal is converted into a second LVDS signal, and then output through the signal output port.
  • the first selection signal and the second selection signal are both voltage signals, and the voltage value of the first selection signal is greater than the voltage value of the second selection signal.
  • the display signal processing system includes a first resistor and a second resistor. One end of the first resistor is grounded, the other end of the first resistor, one end of the second resistor and the GPIO port are connected, and the other end of the second resistor is connected to the voltage source.
  • the first selection signal or the second selection signal is generated at the GPIO port under the control of the voltage source.
  • the V-by-One circuit, the first resistor, and the second resistor are all disposed on the same printed circuit board.
  • the signal input port of the V-by-One circuit is connected to the image processing circuit through the I2C bus.
  • another technical solution adopted by the present invention is to provide a circuit board including a V-by-One chip having a JEIDA mode and a VESA mode selection; and a V-by-One chip including a signal input port.
  • the signal input port is for connecting to the image processing circuit, and the GPIO port is for selectively inputting the first selection signal, so that the V-by-One chip processes the signal in the JEIDA mode to obtain the first LVDS.
  • the signal is then output through the signal output port; or the second selection signal is selectively input to cause the V-by-One chip to process the signal in the JEIDA mode to obtain the second LVDS signal, and then output through the signal output port.
  • the first selection signal and the second selection signal are both voltage signals, and the voltage value of the first selection signal is greater than the voltage value of the second selection signal.
  • the circuit board includes a first resistor and a second resistor. One end of the first resistor is grounded, the other end of the first resistor, one end of the second resistor and the GPIO port are connected, and the other end of the second resistor is connected to the voltage source. A first selection signal or a second selection signal is generated at the GPIO port under the control of the voltage source.
  • a liquid crystal display device including a display panel, a timing control circuit, a V-by-One circuit, and an image processing circuit which are sequentially connected;
  • the image processing circuit is configured to format convert the display signal from the signal source, and output the formatted display signal to the V-by-One circuit;
  • the V-by-One circuit is a display signal processing circuit with JEIDA mode and VESA mode selection, including a signal input port, a GPIO port, and a signal output port.
  • the signal input port is connected to the image processing circuit to input the formatted display signal, GPIO.
  • the port is configured to selectively input the first selection signal, so that the V-by-One circuit converts the formatted display signal into a first LVDS signal in the JEIDA mode, and outputs the signal to the timing control circuit through the signal output port; Or selectively inputting the second selection signal, so that the V-by-One circuit converts the format converted display signal into a second LVDS signal in the VESA mode, and outputs the signal to the timing control circuit through the signal output port.
  • first selection signal and the second selection signal are both voltage signals, and the voltage value of the first selection signal is greater than the voltage value of the second selection signal;
  • the display signal processing circuit further includes a first resistor and a second resistor. One end of the first resistor is grounded, the other end of the first resistor, one end of the second resistor and the GPIO port are connected, and the other end of the second resistor is connected to the voltage source. A first selection signal or a second selection signal is generated at the GPIO port under control of the voltage source.
  • the timing control circuit, the V-by-One circuit, the first resistor and the second resistor are grouped together, and the image processing circuit belongs to different printed circuit boards.
  • the display panel includes a driving circuit connected to the timing control circuit for driving the display panel to display an image according to the first LVDS signal or the second LVDS signal received by the timing control circuit.
  • the signal input port of the V-by-One circuit is connected to the image processing circuit through the I2C bus.
  • the present invention provides a display signal processing system including an image processing circuit and a V-by-One circuit having a JEIDA mode and a VESA mode selection, and a signal passing through the V-by-One circuit.
  • the input port is connected to the image processing circuit to input the formatted display signal, and the GPIO port selectively inputs the first selection signal or the second selection signal, so that the V-by-One circuit corresponds to the JEIDA mode or the VESA mode.
  • the format converted display signal is converted into a corresponding first LVDS signal or a second LVDS signal, and then output through the signal output port.
  • the invention can realize selective switching of the VESA mode and the JEIDA mode of the V-by-One circuit in the LVDS signal transmission process with a more simplified circuit system, and the operation is simple and the cost is low.
  • FIG. 1 is a schematic block diagram of a display signal processing system in the prior art
  • FIG. 2 is a schematic block diagram of an embodiment of a display signal processing system of the present invention.
  • FIG. 3 is a schematic block diagram of an embodiment of a circuit board of the present invention.
  • Fig. 4 is a view showing the configuration of an embodiment of a liquid crystal display device of the present invention.
  • the invention mainly provides a display signal processing system, a circuit board and a liquid crystal display device, and the main purpose thereof is to realize the selectivity of the VESA mode and the JEIDA mode of the V-by-One circuit in the LVDS signal transmission process with a more simplified circuit system. Switching, simple operation and low cost.
  • the display signal processing system 200 of the present embodiment includes an image processing circuit 210 and a V-by-One circuit 220 having a JEIDA mode and a VESA mode selection.
  • the V-by-One circuit 220 includes a signal input port 221, a signal output port 222, and a GPIO port 223. And the first resistor R1 and the second resistor R2 are electrically connected to the GPIO port 223. One end of the first resistor R1 is grounded, the other end is connected to one end of the second resistor R2 and the GPIO port 223, and the other end of the second resistor R2 is connected.
  • the voltage source 224 is connected to the voltage source 224.
  • the voltage source 224 can be an external voltage source for displaying the signal processing system 200, or can be a voltage source that the signal processing system 200 itself has and is disposed on the circuit board 225. It should be noted that the first resistor R1, the second resistor R2, and the V-by-One circuit 220 of the embodiment are all disposed on the same printed circuit board 225.
  • the image processing circuit 210 is configured to format convert the display signal from the signal source, and output the format converted display signal to the V-by-One circuit 220.
  • the signal input port 221 of the V-by-One circuit 220 is connected to the image processing circuit 210 to input the format-converted display signal.
  • the GPIO port 223 enters the input state, and the display signal processing system 200 controls the voltage source 224 so that the GPIO port 223 is under the control of the voltage source 224.
  • the first selection signal is generated, the current output is increased, and the high level is connected, so that the GPIO port 223 is a pull-up resistor.
  • the V-by-One circuit 220 receives the format-converted display signal received from the image processing circuit 210.
  • the high driving capability provided by the pull-up resistor of the GPIO port 223 is converted into a first LVDS signal, and then output through the signal output port 222 for the display panel to receive and corresponding display images.
  • the GPIO port 223 enters the input state, and the display signal processing system 200 controls the voltage source 224 to cause the GPIO port 223 to be under the control of the voltage source 224.
  • a second selection signal is generated, the current output is reduced, and the low level is connected, so that the GPIO port 223 is a pull-down resistor.
  • the V-by-One circuit 220 receives the format converted display signal from the image processing circuit 210 at the GPIO.
  • the low driving capability provided by the pull-down resistor of the port 223 is converted into a second LVDS signal, which is then output through the signal output port 222 for the display panel to receive and display the corresponding image.
  • the first selection signal and the second selection signal are both voltage signals, and the voltage value of the first selection signal is greater than the voltage value of the second selection signal.
  • the first selection signal and the second selection signal may also be power signals, or both are current output signals, and correspondingly, the power value or current value of the first selection signal corresponds to a power value greater than the second selection signal. Or current value.
  • the display signal processing system 200 of the present embodiment can realize not only the selective switching of the VESA mode and the JEIDA mode of the V-by-One circuit 220 with a more simplified circuit system, but also the operation is simple and the cost is low.
  • the present invention also provides a circuit board.
  • the circuit board 300 of the present embodiment mainly includes a V-by-One chip 310 having a JEIDA mode and a VESA mode selection.
  • the V-by-One chip 310 includes a signal input port 311, a signal output port 312, and a GPIO port 313. And a first resistor R3 and a second resistor R4 are electrically connected to the GPIO port 313. One end of the first resistor R3 is grounded, the other end is connected to one end of the second resistor R4 and the GPIO port 313, and the other end of the second resistor R4 is connected. Connected to a voltage source 314.
  • the signal input port 311 is used to connect the image processing circuit, and the GPIO port 313 is used to selectively input the first selection signal under the control of the voltage source 314, so that the V-by-One chip 310 is in the JEIDA mode.
  • the first LVDS signal is obtained by processing the signal, and then outputted through the signal output port 312; or the second selection signal is selectively input under the control of the voltage source 314, so that the V-by-One chip 310 processes the signal in the VESA mode.
  • the second LVDS signal is obtained and output through the signal output port 312.
  • the first selection signal and the second selection signal are both voltage signals, and the voltage value of the first selection signal is greater than the voltage value of the second selection signal.
  • the first selection signal and the second selection signal may also be power signals, or both are current output signals, and correspondingly, the power value or current value of the first selection signal corresponds to a power value greater than the second selection signal. Or current value.
  • Fig. 4 is a view showing the configuration of an embodiment of a liquid crystal display device of the present invention.
  • the liquid crystal display device 400 of the present embodiment mainly includes a display panel 410, a timing control circuit 420, a V-by-One circuit 430, and an image processing circuit 440 which are sequentially connected.
  • the image processing circuit 440 is configured to format convert the display signal from the signal source, and output the format converted display signal to the V-by-One circuit 430.
  • the image processing circuit 440 mainly performs display update rate conversion and conversion color conversion to a multi-bit format scaling conversion.
  • the V-by-One circuit 430 is a display signal processing circuit having a JEIDA mode and a VESA mode selection, and includes a signal input port 431, a signal output port 432, and a GPIO port 433. And a first resistor R5 and a second resistor R6 are electrically connected to the GPIO port 433. One end of the first resistor R5 is grounded, the other end is connected to one end of the second resistor R6 and the GPIO port 433, and the other end of the second resistor R6 is connected.
  • the voltage source 434 is connected to the voltage source 434.
  • the voltage source 434 can be an external voltage source of the liquid crystal display device 400 or a voltage source disposed on the printed circuit board A. It should be noted that the first resistor R5 and the second resistor R6 of the embodiment are combined with the timing control circuit 420 and the V-by-One circuit 430, and belong to different printed circuit boards A, and the image processing circuit 440. B.
  • the signal input port 431 and the image processing circuit 440 are connected through the I2C bus to input the formatted display signal.
  • the GPIO port 433 enters the input state, and the built-in processing unit of the liquid crystal display device 400 controls the voltage source 434 so that the GPIO port 433 is at the voltage source 434.
  • the first selection signal is generated under the control, the current output is increased, and the high level is connected, so that the GPIO port 433 is a pull-up resistor, and the V-by-One circuit 430 will receive the format converted from the image processing circuit 440.
  • the display signal is converted into a first LVDS signal and then output through the signal output port 432 for display and corresponding display images by the display panel 410.
  • the GPIO port 433 enters the input state, and the built-in processing unit of the liquid crystal display device 400 controls the voltage source 434 such that the GPIO port 433 is at the voltage source 434.
  • the second selection signal is generated under control, the current output is reduced, and the low level is connected, so that the GPIO port 433 is a pull-down resistor, and the V-by-One circuit 430 will receive the format converted display from the image processing circuit 440.
  • the signal is converted to a second LVDS signal and then output through the signal output port 432 for the display panel 410 to receive and display the corresponding image.
  • the first selection signal and the second selection signal are both voltage signals, and the voltage value of the first selection signal is greater than the voltage value of the second selection signal.
  • the first selection signal and the second selection signal may also be power signals, or both are current output signals, and correspondingly, the power value or current value of the first selection signal corresponds to a power value greater than the second selection signal. Or current value.
  • the first LVDS signal or the second LVDS signal output by the signal output port 432 is first received by the timing control circuit 420 and processed for output, and then received by the driving circuit 411 disposed in the display panel 410, and finally the driving circuit 411 is The driving principle drives the display panel 410 to display a corresponding image.
  • the liquid crystal display device 400 of the present embodiment not only has an efficient high-frequency signal transmission rate, but also can realize V-by-One during LVDS signal transmission in a more simplified circuit system.
  • the selective switching of the VESA mode and the JEIDA mode of the circuit is simple in operation and low in cost.
  • the disclosed display signal processing system, circuit board, and liquid crystal display device can also be implemented in other manners.
  • the embodiments described above are merely illustrative, and the schematic division of the circuit modules described is only a logical function and a schematic division, and may be further divided in actual implementation.
  • the coupling or communication connection between the circuit modules may be through some interfaces, or may be electrical or other forms.

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Abstract

本发明提供了一种显示信号处理系统、电路板及液晶显示装置。本发明的显示信号处理系统包括影像处理电路和具备JEIDA模式、VESA模式选择的V-by-One电路，V-by-One电路的GPIO端口用于选择性地输入第一选择信号或第二选择信号，以使得V-by-One电路对应在JEIDA模式或VESA模式下将经格式转换后的显示信号转换为对应的第一LVDS信号或第二LVDS信号，再通过信号输出端口输出。本发明能够以更加简化的电路系统实现V-by-One电路的VESA模式和JEIDA模式的选择性切换，操作简单且成本较低。

Description

显示信号处理系统、电路板及液晶显示装置
【技术领域】
本发明涉及通信接口传输技术领域，具体而言涉及一种显示信号处理系统、电路板及液晶显示装置。
【背景技术】
由于显示面板和显示信号处理系统之间的讯号通讯量非常庞大且频率非常高，因此目前设置于两者之间的高频讯号传输是采用具有超高速、低功耗以及低电磁辐射特性的LVDS（Low-Voltage Differential Signaling，低电压差分）信号。
图1是现有技术中显示信号处理系统100的原理框图。如图1所示，在现有技术中LVDS信号的获取必须要借助于V-by-One电路120，其获取过程为：影像处理电路110输入来自信号源的且经格式转换后的显示信号，V-by-One电路120将此显示信号转换为对应的LVDS信号。
由于在液晶显示装置中需要输出到显示面板的显示信号是并行的图像信号和控制信号，而LVDS信号是串行传输的，因此在发送时需要将串行数据转换为并行数据，并且由于在发送和接收时采用的像素映射顺序不同，LVDS信号的映射主要有JEIDA（Japan Electronic Industry Development Association，日本电子行业开发协会）模式和VESA（Video Electronics Standards Association，视频电子标准协会）模式。然而，目前的V-by-One电路120内部默认为JEIDA模式，如果用户需要切换为VESA模式，则必须由影像处理电路110通过I2C总线130控制电路的驱动能力由高变低，以改变数据映射的顺序以使V-by-One电路130输出VESA模式，此种电路系统操作繁琐且成本也相对较高。
综上所述，有必要提供一种显示信号处理系统、电路板及液晶显示装置，以解决上述问题。
【发明内容】
本发明主要解决的技术问题是提供一种显示信号处理系统、电路板及液晶显示装置，以更加简化的电路系统实现V-by-One 电路的VESA模式和JEIDA模式的选择性切换，操作简单且成本较低。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种显示信号处理系统，包括影像处理电路和具备JEIDA模式、VESA模式选择的V-by-One电路；
影像处理电路用于将来自信号源的显示信号进行格式转换，并将格式转换后的显示信号输出至V-by-One电路；
V-by-One电路包括信号输入端口、GPIO端口以及信号输出端口，信号输入端口连接影像处理电路以输入经格式转换后的显示信号，GPIO端口用于选择性地输入第一选择信号，以使得V-by-One电路在JEIDA模式下将经格式转换后的显示信号转换为第一LVDS信号，再通过信号输出端口输出；或选择性地输入第二选择信号，以使得V-by-One电路在VESA模式下将经格式转换后的显示信号转换为第二LVDS信号，再通过信号输出端口输出。
其中，第一选择信号和第二选择信号均是电压信号，并且第一选择信号的电压值大于第二选择信号的电压值。
其中，显示信号处理系统包括第一电阻和第二电阻，第一电阻的一端接地，第一电阻的另一端、第二电阻的一端以及GPIO端口相接，第二电阻的另一端接电压源，以在电压源的控制下在GPIO端口产生第一选择信号或第二选择信号。
其中，V-by-One电路、第一电阻以及第二电阻均设置于同一印刷电路板上。
其中，V-by-One电路的信号输入端口与影像处理电路通过I2C总线相连接。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种电路板，电路板包括具备JEIDA模式、VESA模式选择的V-by-One芯片；V-by-One芯片包括信号输入端口、GPIO端口以及信号输出端口，信号输入端口用于连接影像处理电路，GPIO端口用于选择性地输入第一选择信号，以使得V-by-One芯片在JEIDA模式下处理信号而得到第一LVDS信号，再通过信号输出端口输出；或选择性地输入第二选择信号，以使得V-by-One芯片在JEIDA模式下处理信号而得到第二LVDS信号，再通过信号输出端口输出。
其中，第一选择信号和第二选择信号均是电压信号，并且第一选择信号的电压值大于第二选择信号的电压值。
其中，电路板包括第一电阻和第二电阻，第一电阻的一端接地，第一电阻的另一端、第二电阻的一端以及GPIO端口相接，第二电阻的另一端接电压源，以在电压源的控制下在GPIO端口产生第一选择信号或第二选择信号。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示装置，包括依次连接的显示面板、时序控制电路、V-by-One电路以及影像处理电路；
影像处理电路用于将来自信号源的显示信号进行格式转换，并将格式转换后的显示信号输出至V-by-One电路；
V-by-One电路为具备JEIDA模式、VESA模式选择的显示信号处理电路，包括信号输入端口、GPIO端口以及信号输出端口，信号输入端口连接影像处理电路以输入经格式转换后的显示信号，GPIO端口用于选择性地输入第一选择信号，以使得V-by-One电路在JEIDA模式下将经格式转换后的显示信号转换为第一LVDS信号，再通过信号输出端口输出至时序控制电路；或选择性地输入第二选择信号，以使得V-by-One电路在VESA模式下将经格式转换后的显示信号转换为第二LVDS信号，再通过信号输出端口输出至时序控制电路。
其中，第一选择信号和第二选择信号均是电压信号，并且第一选择信号的电压值大于第二选择信号的电压值；
显示信号处理电路还包括第一电阻和第二电阻，第一电阻的一端接地，第一电阻的另一端、第二电阻的一端以及GPIO端口相接，第二电阻的另一端接电压源，以在电压源的控制下在GPIO端口产生第一选择信号或第二选择信号。
其中，时序控制电路、V-by-One电路、第一电阻以及第二电阻作为一组，与影像处理电路之间分属于不同印刷电路板。
其中，显示面板包括与时序控制电路连接的驱动电路，用于根据时序控制电路接收的第一LVDS信号或第二LVDS信号驱动显示面板显示图像。
其中，V-by-One电路的信号输入端口与影像处理电路通过I2C总线相连接。
本发明的有益效果是：区别于现有技术，本发明设置包括影像处理电路和具备JEIDA模式、VESA模式选择的V-by-One电路的显示信号处理系统，通过V-by-One电路的信号输入端口连接影像处理电路以输入经格式转换后的显示信号、GPIO端口选择性地输入第一选择信号或第二选择信号，以使得V-by-One电路对应在JEIDA模式或VESA模式下将经格式转换后的显示信号转换为对应的第一LVDS信号或第二LVDS信号，再通过信号输出端口输出。本发明能够以更加简化的电路系统实现LVDS信号传输过程中V-by-One电路的VESA模式和JEIDA模式的选择性切换，操作简单且成本较低。
【附图说明】
图1是现有技术中显示信号处理系统的原理框图；
图2是本发明的显示信号处理系统一实施例的原理框图；
图3是本发明的电路板一实施例的原理框图；
图4是本发明的液晶显示装置一实施例的结构示意图。
【具体实施方式】
本发明主要提供了一种显示信号处理系统、电路板及液晶显示装置，主要目的是能够以更加简化的电路系统实现LVDS信号传输过程中V-by-One电路的VESA模式和JEIDA模式的选择性切换，操作简单且成本较低。
下面结合附图2~4和实施例对本发明进行详细说明。
图2是本发明的显示信号处理系统一实施例的原理框图。如图2所示，本实施例的显示信号处理系统200包括影像处理电路210以及具备JEIDA模式、VESA模式选择的V-by-One电路220。
其中，V-by-One电路220包括信号输入端口221、信号输出端口222以及GPIO端口223。并且在GPIO端口223还电连接有第一电阻R1和第二电阻R2，第一电阻R1的一端接地，另一端与第二电阻R2的一端以及GPIO端口223相接，第二电阻R2的另一端接电压源224，其中电压源224可以是显示信号处理系统200的外接电压源，也可以是显示信号处理系统200自身具有且设置于电路板225上的电压源。需要说明的是，本实施例的第一电阻R1、第二电阻R2与V-by-One电路220均设置于同一印刷电路板225上。
在本实施例中，影像处理电路210用于将来自信号源的显示信号进行格式转换，并将格式转换后的显示信号输出至V-by-One电路220。
V-by-One电路220的信号输入端口221与影像处理电路210连接，以输入经格式转换后的显示信号。
当用户需要V-by-One电路220在JEIDA模式下输出第一LVDS信号时：GPIO端口223进入输入状态，显示信号处理系统200控制电压源224，以使GPIO端口223在电压源224的控制下产生第一选择信号，增大电流输出，连接高电平，使得GPIO端口223为上拉电阻，此时V-by-One电路220将接收自影像处理电路210的经格式转换后的显示信号在GPIO端口223的上拉电阻提供的高驱动能力下转换为第一LVDS信号，再通过信号输出端口222输出，以供显示面板接收并对应的显示图像。
当用户需要V-by-One电路220在VESA模式下输出第二LVDS信号时：GPIO端口223进入输入状态，显示信号处理系统200控制电压源224，以使GPIO端口223在电压源224的控制下产生第二选择信号，减小电流输出，连接低电平，使得GPIO端口223为下拉电阻，此时V-by-One电路220将接收自影像处理电路210的经格式转换后的显示信号在GPIO端口223的下拉电阻提供的低驱动能力下转换为第二LVDS信号，再通过信号输出端口222输出，以供显示面板接收并显示对应的图像。
在本实施例中，第一选择信号和第二选择信号均是电压信号，并且第一选择信号的电压值大于第二选择信号的电压值。在其他实施例中，第一选择信号和第二选择信号也可以均为功率信号，或均为电流输出信号，相应地第一选择信号的功率值或电流值对应大于第二选择信号的功率值或电流值。
基于上述，本实施例的显示信号处理系统200不仅能够以更加简化的电路系统实现V-by-One电路220的VESA模式和JEIDA模式的选择性切换，而且操作简单且成本较低。
本发明还提供了一种电路板，如图3所示，本实施例的电路板300主要包括具备JEIDA模式、VESA模式选择的V-by-One芯片310。
其中，V-by-One芯片310包括信号输入端口311、信号输出端口312以及GPIO端口313。并且在GPIO端口313还电连接有第一电阻R3和第二电阻R4，第一电阻R3的一端接地，另一端与第二电阻R4的一端以及GPIO端口313相接，第二电阻R4的另一端接电压源314。
在本实施例中，信号输入端口311用于连接影像处理电路，GPIO端口313用于在电压源314的控制下选择性地输入第一选择信号，以使得V-by-One芯片310在JEIDA模式下处理信号而得到第一LVDS信号，再通过信号输出端口312输出；或在电压源314的控制下选择性地输入第二选择信号，以使得V-by-One芯片310在VESA模式下处理信号而得到第二LVDS信号，再通过信号输出端口312输出。
在本实施例中，第一选择信号和第二选择信号均是电压信号，并且第一选择信号的电压值大于第二选择信号的电压值。在其他实施例中，第一选择信号和第二选择信号也可以均为功率信号，或均为电流输出信号，相应地第一选择信号的功率值或电流值对应大于第二选择信号的功率值或电流值。
图4是本发明的液晶显示装置一实施例的结构示意图。如图4所示，本实施例的液晶显示装置400主要包括：依次连接的显示面板410、时序控制电路420、V-by-One电路430以及影像处理电路440。
在本实施例中，影像处理电路440用于将来自信号源的显示信号进行格式转换，并将格式转换后的显示信号输出至V-by-One电路430。其中，影像处理电路440主要将显示信号进行画面更新速率转换及转换色彩变异到多位元格式的缩放转换。
V-by-One电路430为具备JEIDA模式、VESA模式选择的显示信号处理电路，且包括信号输入端口431、信号输出端口432以及GPIO端口433。并且在GPIO端口433还电连接有第一电阻R5和第二电阻R6，第一电阻R5的一端接地，另一端与第二电阻R6的一端以及GPIO端口433相接，第二电阻R6的另一端接电压源434，其中电压源434可以是液晶显示装置400的外接电压源，也可以是设置于印刷电路板A上的电压源。需要说明的是，本实施例的第一电阻R5、第二电阻R6与时序控制电路420和V-by-One电路430作为一组，与影像处理电路440之间分属于不同印刷电路板A、B。
其中，信号输入端口431与影像处理电路440通过I2C总线相连接，以输入经格式转换后的显示信号。
当用户需要V-by-One电路430在JEIDA模式下输出第一LVDS信号时：GPIO端口433进入输入状态，液晶显示装置400的内置处理单元控制电压源434，以使GPIO端口433在电压源434的控制下产生第一选择信号，增大电流输出，连接高电平，使得GPIO端口433为上拉电阻，此时V-by-One电路430将接收自影像处理电路440的经格式转换后的显示信号转换为第一LVDS信号，再通过信号输出端口432输出，以供显示面板410接收并对应的显示图像。
当用户需要V-by-One电路430在VESA模式下输出第二LVDS信号时：GPIO端口433进入输入状态，液晶显示装置400的内置处理单元控制电压源434，以使GPIO端口433在电压源434的控制下产生第二选择信号，减小电流输出，连接低电平，使得GPIO端口433为下拉电阻，此时V-by-One电路430将接收自影像处理电路440的经格式转换后的显示信号转换为第二LVDS信号，再通过信号输出端口432输出，以供显示面板410接收并显示对应的图像。
在本实施例中，第一选择信号和第二选择信号均是电压信号，并且第一选择信号的电压值大于第二选择信号的电压值。在其他实施例中，第一选择信号和第二选择信号也可以均为功率信号，或均为电流输出信号，相应地第一选择信号的功率值或电流值对应大于第二选择信号的功率值或电流值。另外，信号输出端口432输出的第一LVDS信号或第二LVDS信号首先被时序控制电路420接收并进行处理后输出，而后被设置于显示面板410内的驱动电路411所接收，最后驱动电路411根据驱动原理驱动显示面板410显示相应的图像。
基于所述，本实施例的液晶显示装置400不仅具有高效的高频讯号传输率，而且能够以更加简化的电路系统实现LVDS信号传输过程中V-by-One 电路的VESA模式和JEIDA模式的选择性切换，操作简单且成本较低。
在本发明所提供的实施方式中，应该理解到，所揭露的显示信号处理系统、电路板及液晶显示装置，也可以通过其它的方式实现。以上所描述的实施方式仅仅是示意性的，所描述电路模块的原理框划分，仅仅为一种逻辑功能和示意性划分，实际实现时可以有另外的划分方式。另外，各电路模块相互之间的耦合或通信连接可以是通过一些接口，也可以是电性或其它的形式。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种显示信号处理系统，其中，所述显示信号处理系统包括影像处理电路和具备JEIDA模式、VESA模式选择的V-by-One电路；
    所述影像处理电路用于将来自信号源的显示信号进行格式转换，并将格式转换后的所述显示信号输出至所述V-by-One电路；
    所述V-by-One电路包括信号输入端口、GPIO端口以及信号输出端口，所述信号输入端口连接影像处理电路以输入所述经格式转换后的显示信号，所述GPIO端口用于选择性地输入第一选择信号，以使得所述V-by-One电路在所述JEIDA模式下将所述经格式转换后的显示信号转换为第一LVDS信号，再通过所述信号输出端口输出；或选择性地输入第二选择信号，以使得所述V-by-One电路在所述VESA模式下将所述经格式转换后的显示信号转换为第二LVDS信号，再通过所述信号输出端口输出。
  2. 根据权利要求1所述的系统，其中，所述第一选择信号和第二选择信号均是电压信号，并且所述第一选择信号的电压值大于所述第二选择信号的电压值。
  3. 根据权利要求2所述的系统，其中，所述系统包括第一电阻和第二电阻，所述第一电阻的一端接地，所述第一电阻的另一端、所述第二电阻的一端以及所述GPIO端口相接，所述第二电阻的另一端接电压源，以在所述电压源的控制下在所述GPIO端口产生第一选择信号或第二选择信号。
  4. 根据权利要求3所述的系统，其中，所述V-by-One电路、第一电阻以及第二电阻均设置于同一印刷电路板上。
  5. 根据权利要求1所述的系统，其中，所述V-by-One电路的信号输入端口与所述影像处理电路通过I2C总线相连接。
  6. 一种电路板，其中，所述电路板包括具备JEIDA模式、VESA模式选择的V-by-One芯片；
    所述V-by-One芯片包括信号输入端口、GPIO端口以及信号输出端口，所述信号输入端口用于连接影像处理电路，所述GPIO端口用于选择性地输入第一选择信号，以使得所述V-by-One芯片在所述JEIDA模式下处理信号而得到第一LVDS信号，再通过所述信号输出端口输出；或选择性地输入第二选择信号，以使得所述V-by-One芯片在所述VESA模式下处理信号而得到第二LVDS信号，再通过所述信号输出端口输出。
  7. 根据权利要求6所述的电路板，其中，所述第一选择信号和第二选择信号均是电压信号，并且所述第一选择信号的电压值大于所述第二选择信号的电压值。
  8. 根据权利要求7所述的电路板，其中，所述电路板包括第一电阻和第二电阻，所述第一电阻的一端接地，所述第一电阻的另一端、所述第二电阻的一端以及所述GPIO端口相接，所述第二电阻的另一端接电压源，以在所述电压源的控制下在所述GPIO端口产生第一选择信号或第二选择信号。
  9. 一种液晶显示装置，其中，所述装置包括依次连接的显示面板、时序控制电路、V-by-One电路以及影像处理电路；
    所述影像处理电路用于将来自信号源的显示信号进行格式转换，并将格式转换后的所述显示信号输出至所述V-by-One电路；
    所述V-by-One电路为具备JEIDA模式、VESA模式选择的显示信号处理电路，包括信号输入端口、GPIO端口以及信号输出端口，所述信号输入端口连接所述影像处理电路以输入所述经格式转换后的显示信号，所述GPIO端口用于选择性地输入第一选择信号，以使得所述V-by-One电路在所述JEIDA模式下将所述经格式转换后的显示信号转换为第一LVDS信号，再通过所述信号输出端口输出至所述时序控制电路；或选择性地输入第二选择信号，以使得所述V-by-One电路在所述VESA模式下将所述经格式转换后的显示信号转换为第二LVDS信号，再通过所述信号输出端口输出至所述时序控制电路。
  10. 根据权利要求9所述的装置，其中，
    所述第一选择信号和第二选择信号均是电压信号，并且所述第一选择信号的电压值大于所述第二选择信号的电压值；
    所述显示信号处理电路还包括第一电阻和第二电阻，所述第一电阻的一端接地，所述第一电阻的另一端、所述第二电阻的一端以及所述GPIO端口相接，所述第二电阻的另一端接电压源，以在所述电压源的控制下在所述GPIO端口产生所述第一选择信号或第二选择信号。
  11. 根据权利要求10所述的装置，其中，所述时序控制电路、V-by-One电路、第一电阻以及第二电阻作为一组，与所述影像处理电路之间分属于不同印刷电路板。
  12. 根据权利要求9所述的装置，其中，所述显示面板包括与所述时序控制电路连接的驱动电路，用于根据所述时序控制电路接收的所述第一LVDS信号或第二LVDS信号驱动所述显示面板显示图像。
  13. 根据权利要求9所述的装置，其中，所述V-by-One电路的信号输入端口与所述影像处理电路通过I2C总线相连接。
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