WO2014145300A2 - Pin photovoltaic cell and process of manufacture - Google Patents

Pin photovoltaic cell and process of manufacture Download PDF

Info

Publication number
WO2014145300A2
WO2014145300A2 PCT/US2014/030038 US2014030038W WO2014145300A2 WO 2014145300 A2 WO2014145300 A2 WO 2014145300A2 US 2014030038 W US2014030038 W US 2014030038W WO 2014145300 A2 WO2014145300 A2 WO 2014145300A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
type semiconductor
electrode
forming
Prior art date
Application number
PCT/US2014/030038
Other languages
French (fr)
Other versions
WO2014145300A3 (en
Inventor
Koji Matsumaru
Jose Briceno
Original Assignee
Nusola Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/844,686 external-priority patent/US20130255774A1/en
Priority claimed from US13/844,428 external-priority patent/US20130255773A1/en
Priority claimed from US13/844,298 external-priority patent/US8952246B2/en
Priority claimed from US13/844,521 external-priority patent/US9099578B2/en
Priority claimed from US13/844,747 external-priority patent/US20130255775A1/en
Application filed by Nusola Inc. filed Critical Nusola Inc.
Publication of WO2014145300A2 publication Critical patent/WO2014145300A2/en
Publication of WO2014145300A3 publication Critical patent/WO2014145300A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/07—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the Schottky type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0725—Multiple junction or tandem solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to photovoltaic devices, and in particular, a PIN photovoltaic device structure with improved photovoltaic properties and a simplified method of manufacture.
  • a solar cell also called a photovoltaic cell
  • a solar cell is an electrical device that converts the energy of light directly into electricity by the photovoltaic effect.
  • Prior art solar cell technology typically utilizes crystalline silicon as a main ingredient, and in some other cases, inexpensive poly-ciy stall ine silicon or other compound semiconductors.
  • other technologies use organic materials for the so-called dye-sensitized solar cells.
  • Prior art crystalline silicon solar ceils are often fabricated by forming a high concentration n-type layer on a p-type silicon substrate.
  • This high concentration n-type layer is generally formed by a process of ion implantation, or diffusion, introducing the n-type dopant phosphorous, to form a PN junction, followed by an annealing process. Once the PN junction is so formed, anode and cathode electrodes are formed to complete the photovoltaic cell.
  • the conventional methods for manufacturing photovoitaic materials also require a multi-step process, or different processes, with each step possibly taking place at a different apparatus and at different times, and requiring its own management and resources. It is highly desirable to have a manufacturing process for photovoltaic materials that reduces the number of necessary processes or steps to reduce costs.
  • Preferred embodiments of the present invention provide a PIN photovoitaic device and a method of manufacturing the device.
  • Embodiments include a method for manufacturing using a heating process to create one or more photovoitaic structures on a bulk semiconductor substrate.
  • the PIN photovoltaic (PIN PV) device is composed of a first electrode iayer, a p- type semiconductor iayer, an intrinsic semiconductor iayer, an n-type semiconductor substrate, and a back surface electrode.
  • the method for manufacturing the PIN PV device of the present invention is preferably a toxic material free process, which lowers the overall manufacturing cost, in a first embodiment, the method begins by cleaning an n-type semiconductor substrate; introducing an inert gas under vacuum and a high temperature to form a high resistivity layer on the top surface of the substrate; depositing a p-type semiconductor Iayer on the high resistivity layer; forming a transparent electrode layer on the p-type semiconductor layer; and forming a metal electrode on the bottom surface of the substrate,
  • the method begins by cleaning an n-type semiconductor substrate; forming an SiC or Si02 isolation layer on the bottom surface of the substrate: introducing an inert gas under vacuum and a high temperature to form a high resistivity layer on the top surface of the substrate; depositing a p-type semiconductor layer on the high resistivity iayer; forming a transparent electrode layer on the p-type semiconductor layer; and forming a metal electrode on the bottom surface of the substrate.
  • FIG. 1 is a cross-sectional view of a PIN PV device during one stage of the manufacturing process after the PV device has been formed according to one embodiment of the present invention
  • FIG, 2 is a cross-sectional view of a PIN PV device during one stage of the manufacturing process after the PV device has been formed according to another embodiment of the present invention.
  • FIG. 3 is a flow diagram illustrating an example of the steps of the process for manufacturing the PV device shown in FIG. 2. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE
  • FIG. 1 is a diagrammatic view of a cross-section of a photovoltaic (PV) device 1 during an initial stage of the manufacturing process according to one embodiment of the present invention.
  • Device 1 includes an n-type semiconductor substrate 12 on the top of which an intrinsic, high resistivity semiconductor layer 9 is formed.
  • a p-type semiconductor layer 7 is formed on top of the high resistivity semiconductor layer 9.
  • the intrinsic semiconductor layer 9 has a resistivity that is at least 10 times higher of that of semiconductor substrate 12.
  • An electrode layer 5 is formed on top of p-type semiconductor layer 7.
  • Electrode layer 5 is typically made of a transparent conductive oxide (TCO). Formation of these layers 5, 7, and 9 may be by any means known in the art including impurity diffusion or doping of the semiconductor substrate.
  • a bottom or back surface electrode is 14 is formed on the bottom surface of substrate 12. Electrode 14 is composed of a single, or multiple metal layer that will have an ohmic contact with the semiconductor substrate. Note that layers 12, 9, and 7 define the P-I-N junction 20 of the device 1.
  • EXAMPLE 1 (top p-type layer by doping (diffusion), implantation)
  • One embodiment of the present invention to fabricate a PV cell as shown at 60 in FIG. 2 uses a process as depicted in a block flow diagram of FIG. 3, which shows the following sequential steps:
  • Wafer cleaning step 30 in which a neutral detergent is used for the n-type silicon substrate (wafer) 32 and an organic neutral detergent is used for removal of the abrading agent.
  • Wafer cleaning step 36 which is substantially the same as step 30.
  • a 6- inch N-type silicon single crystal wafer 12 having a resistivity of 1 to 5 ( ⁇ cm), (300) crystal orientation is cleaned by a typical RCA cleaning method.
  • the substrate cleaning is performed in the following steps: (1 ) removing organic material using sulfuric acid-hydrogen peroxide water cleaning for ten m inutes at 350°K; (2) using a pure water cleaning; (3) drying the resulting substrate with nitrogen, with an infrared treatment, and with ultraviolet light drying; and (4) cleaning the dried substrate with a 0.5% hydrofluoric acid solution.
  • a SiC isolation layer 55 having a 200 nm thickness is placed on the back surface of the resultant cleaned wafer 12 by means of a sputtering method. While the isolation layer in the present example is SiC, an 8102 isolation layer may also be used. In addition, while the isolation layer thickness used in the present example is 200 nm, any other thickness above 100 nm may be used as well.
  • a high resistivity layer 9 is formed on substrate 12 by the following method, inert gas is introduced into a quartz boat containing the substrate 12 which had been previously vacuumed to approximately 1 E-3 Pa.
  • the quartz boat is heated and kept at pre-determined annealing temperature of 800°K or more for 30 minutes. While a vacuum of approximately 1E-3 Pa is used in the present example, the degree of the vacuum is not critical and any vacuum of approximately 20 Pa or lower can be used. Further, while argon gas was used as the inert gas in the present example, another inert gas such as helium gas and the like or a mixture of these inert gases may be used.
  • a variety of heating methods can be used to form intrinsic silicon layer 9, including but not limited to infrared heating, laser heating, and hot-wall furnace heating, in some embodiments, the particular heating methods used for treating the substrate layer have an effect on photovoltaic performance of the photovoltaic cell, in some embodiments, the cooling rate after the heating stage is a crucial factor to photovoltaic ceil fabrication, whereas the heating rate is a less crucial factor to photovoltaic ceil fabrication. Maximum photovoltaic cell performance can be obtained at heating temperatures above 1500°K, at heating times above 5 minutes, at approximately 1x10° Pa.
  • the overall parameters used during heating step include temperatures ranging from 852 1700° Kelvin, heating times from one to 600 min., atmospheres from vacuum, argon, nitrogen or other inert gas at temperatures up to 1 atm.
  • the substrate is transformed into a photovoltaic semiconductor materia! having a high-resistivity layer therein.
  • the resulting substrate was cleaned by the use of a typical RCA cleaning method, similar to the one mentioned above,
  • a p-type silicon layer 7 is formed on top of layer 9 by means of boron (B) doping (diffusion) of the silicon wafer.
  • B boron
  • the quartz boat containing the silicon wafers is placed next to the BN powder and vacuumed to approximately 1 Pa.
  • the heating chamber is heated and kept at a predetermined heating temperature of between 900 and 1200 °K for I to 15 minutes.
  • the amount of B diffusion into the intrinsic silicon layer varies according to heating temperature and time, in this example, the p-type silicon layer thickness was calculated to be 50 to 250 nm, for the temperature and time range mentioned above.
  • p-type silicon layer 7 may be also formed by means of a B ion implantation method.
  • a 150 nm thick ZnO transparent conductive film is formed over the p-type silicon layer 7 by a sputtering method to form top TCO electrode 50.
  • a silver paste bus-bar may be placed on top of the ZnO layer to improve overall electrical properties of top TCO electrode 50. Placement of the bus-bar is performed by a screen printing method.
  • ZnO is used in the present example
  • other transparent conductive oxide films such as ⁇ , AZO, GZO, ⁇ , and Nb02, or a stacked structure thereof; may be used, and the transparent conductive oxide film may be formed by PLD, PvIOCVD, or a coating method, not limited to the sputtering method.
  • a silicon nitride film may be formed consecutively as an anti-reflection film.
  • Aluminum is coated by screen printing on the bottom (back) surface of the wafer 60 and heating is provided at 550°K for removing binder, and to complete the solar cell 60 construction.
  • the face orientation may be (1 10) or ( 1 1 1 ), and solar grade silicon or poly- crystalline silicon may be used.
  • a silicon substrate having a different resistivity it is necessary to change heating temperature and time.
  • EXAMPLE 2 (top p-type layer by deposition: CVD, PVD, PLD)
  • the steps for forming PV cell 60 are the same as in example 1 , described above, except, for process step 38, where the p-type silicon layer 7 is created, in this example 2, the p-type silicon layer 7 is deposited on top of the high resistivity layer by means of chemical vapor deposition (CVD).
  • This p-type silicon layer may be an amorphous structure and of a thickness of approximately 5 to 100 nni.
  • p-type silicon layer may be also formed by PVD, PLD, or some other coating method not limited to a sputtering method.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Sustainable Energy (AREA)
  • Photovoltaic Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

A PIN photovoltaic (PIN PV) device is composed of a first electrode layer, a p-type semiconductor layer, an intrinsic semiconductor layer, an n-type semiconductor substrate, and a back surface electrode. Also described is a method for manufacturing a PIN PV device. In a first embodiment, the method includes cleaning an n-type semiconductor substrate; introducing an inert gas under vacuum and a high temperature to form a high resistivity layer on the top surface of the substrate; forming or depositing a p-type semiconductor layer on the high resistivity layer; forming a transparent electrode layer on the p-type semiconductor layer; and forming a metal electrode on the bottom surface of the substrate. In a second embodiment, an SiC or Si02 isolation layer is formed on the bottom surface of the substrate after initial cleaning of the wafer before the high resistivity Iayer is formed on the top of the substrate.

Description

PIN PHOTOVOLTAIC CELL AND PROCESS OF MANUFACTURE
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Application No. 1 /844,686, filed March 15, 201 3 (Attorney Docket No. 44671-047 (P7)): U.S. Application No. 1 3/844,298, filed March 15, 2013 (Attorney Docket No. 44671 - 033 (P2j); U.S. Application No. 13/844,428, filed March 15, 2013 (Attorney Docket No. 44671 -034 (P3)); U.S. Application No. 13/844,521, filed March 1 5, 2013 (Attorney Docket No. 44671 -035 (P4)); U.S. Application No. 13/844,747, filed March 15, 2013 (Attorney Docket No. 44671-038 (P5)); U.S. Provisional Application No. 61/801,019, entitled Manufacturing Equipment for Photovoltaic Devices, filed 15 March 2013 (Attorney Docket No. 44671 -050 (P 32)}; U.S. Provisional Application No. 61/800,912, entitled Infrared Photovoltaic Device, filed 15 March 2013 (Attorney Docket No. 44671 -049 (P 10}): U.S. Provisional Application No. 61 /800,800, entitled Hybrid Transparent Electrode Assembly for Photovoltaic Ceil Manufacturing, filed 15 March 2013 (Attorney Docket No. 44671 -048 (P2.3)); U .S. Provisional Application No. 61 /801 , 145, entitled ΡΪΝ Photo-voltaic device and Manufacturing Method, filed 15 March 2013 (Attorney Docket No. 44671 -051 (P 17)), and U.S. Provisional Application No, 61/801,244, entitled Infrared Photo-voltaic device and Manufacturing Method, filed 15 March 2013 (Attorney Docket No. 44671-052 (P36)), the entireties of which are incorporated by reference as if fully set forth herein.
[0002] This application is related to copending U.S. Patent Application No. 13/844,686, filed 15 March 2 13 (docket number P7, sub case 003); the entirety of which is incorporated by reference as if fully set forth herein.
FIELD OF THE INVENTION
[0003] The present invention relates to photovoltaic devices, and in particular, a PIN photovoltaic device structure with improved photovoltaic properties and a simplified method of manufacture. BACKGROUND OF THE INVENTION
[0004] A solar cell (also called a photovoltaic cell) is an electrical device that converts the energy of light directly into electricity by the photovoltaic effect. Prior art solar cell technology typically utilizes crystalline silicon as a main ingredient, and in some other cases, inexpensive poly-ciy stall ine silicon or other compound semiconductors. In addition, other technologies use organic materials for the so-called dye-sensitized solar cells. Prior art crystalline silicon solar ceils are often fabricated by forming a high concentration n-type layer on a p-type silicon substrate. This high concentration n-type layer is generally formed by a process of ion implantation, or diffusion, introducing the n-type dopant phosphorous, to form a PN junction, followed by an annealing process. Once the PN junction is so formed, anode and cathode electrodes are formed to complete the photovoltaic cell.
[00051 Recently, an intrinsic layer between the P and N layers to create a so- called PIN junction cell has also been added, to increase cell efficiency. However, in the same mariner as the PN junction solar cell, the manufacturing process for PIN junction cells is based on impurity doping methods that are expensive and use toxic materials. It is highly desirable to have a manufacturing process for photovoltaic materials that reduces or eliminates toxic additives.
[0006] The conventional methods for manufacturing photovoitaic materials also require a multi-step process, or different processes, with each step possibly taking place at a different apparatus and at different times, and requiring its own management and resources. It is highly desirable to have a manufacturing process for photovoltaic materials that reduces the number of necessary processes or steps to reduce costs.
BRIEF SUMMARY OF THE PREFERRED EMBODIMENTS OF THE INVENTION
[0007] Preferred embodiments of the present invention provide a PIN photovoitaic device and a method of manufacturing the device. Embodiments include a method for manufacturing using a heating process to create one or more photovoitaic structures on a bulk semiconductor substrate. [0008] The PIN photovoltaic (PIN PV) device is composed of a first electrode iayer, a p- type semiconductor iayer, an intrinsic semiconductor iayer, an n-type semiconductor substrate, and a back surface electrode.
[Θ009] The method for manufacturing the PIN PV device of the present invention is preferably a toxic material free process, which lowers the overall manufacturing cost, in a first embodiment, the method begins by cleaning an n-type semiconductor substrate; introducing an inert gas under vacuum and a high temperature to form a high resistivity layer on the top surface of the substrate; depositing a p-type semiconductor Iayer on the high resistivity layer; forming a transparent electrode layer on the p-type semiconductor layer; and forming a metal electrode on the bottom surface of the substrate,
[00010] In a second embodiment, the method begins by cleaning an n-type semiconductor substrate; forming an SiC or Si02 isolation layer on the bottom surface of the substrate: introducing an inert gas under vacuum and a high temperature to form a high resistivity layer on the top surface of the substrate; depositing a p-type semiconductor layer on the high resistivity iayer; forming a transparent electrode layer on the p-type semiconductor layer; and forming a metal electrode on the bottom surface of the substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
[00011] Preferred embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
[00012] FIG. 1 is a cross-sectional view of a PIN PV device during one stage of the manufacturing process after the PV device has been formed according to one embodiment of the present invention,
[00013] FIG, 2 is a cross-sectional view of a PIN PV device during one stage of the manufacturing process after the PV device has been formed according to another embodiment of the present invention.
[00014] FIG. 3 is a flow diagram illustrating an example of the steps of the process for manufacturing the PV device shown in FIG. 2. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE
INVENTION
[00015] In the following description numerous specific details have been set forth to provide a more thorough understanding of embodiments of the present invention. It will he appreciated however, by one skilled in the art, that embodiments of the invention may be practiced without such specific details or with different implementations for such details. Additionally some well-known structures have not been shown in detail to avoid unnecessarily obscuring the present invention. 00016] FIG. 1 is a diagrammatic view of a cross-section of a photovoltaic (PV) device 1 during an initial stage of the manufacturing process according to one embodiment of the present invention. Device 1 includes an n-type semiconductor substrate 12 on the top of which an intrinsic, high resistivity semiconductor layer 9 is formed. A p-type semiconductor layer 7 is formed on top of the high resistivity semiconductor layer 9. The intrinsic semiconductor layer 9 has a resistivity that is at least 10 times higher of that of semiconductor substrate 12. An electrode layer 5 is formed on top of p-type semiconductor layer 7. Electrode layer 5 is typically made of a transparent conductive oxide (TCO). Formation of these layers 5, 7, and 9 may be by any means known in the art including impurity diffusion or doping of the semiconductor substrate. Finally, a bottom or back surface electrode is 14 is formed on the bottom surface of substrate 12. Electrode 14 is composed of a single, or multiple metal layer that will have an ohmic contact with the semiconductor substrate. Note that layers 12, 9, and 7 define the P-I-N junction 20 of the device 1.
BEST MODE FOR CARRYiNG OUT THE INVENTION
[00017] EXAMPLE 1 : (top p-type layer by doping (diffusion), implantation)
One embodiment of the present invention to fabricate a PV cell as shown at 60 in FIG. 2 uses a process as depicted in a block flow diagram of FIG. 3, which shows the following sequential steps:
[00018] Wafer cleaning step 30 in which a neutral detergent is used for the n-type silicon substrate (wafer) 32 and an organic neutral detergent is used for removal of the abrading agent.
(000.19] Placing an isolation layer 55 preferably composed of S;C or Si02 on the back or bottom surface of the silicon substrate 32 at step 32.
[00020] Wafer heating step 34 to form intrinsic silicon layer 9 on the top surface of substrate 12.
[00021] Wafer cleaning step 36, which is substantially the same as step 30.
[00022] Formation of a p-type silicon layer 7 on top of layer 9 by a boron (B) diffusion p layer or boron ion implantation at step 38.
(00023] Placement of a top TCO electrode in which ITO (indium tin oxide) as the TCO 5 is deposited on the resulting wafer by sputtering followed by an optional step of applying an anti-reflection coat of Si , at step 40.
[00024] Placement of a bottom (back) electrode on the bottom surface of the resulting wafer below isolation layer 55, in which an aluminum paste 14 is screen-printed onto the wafer followed by firing.
[00025] Cell testing step 44 in which the resultant PV device 60 is run through a series of tests to determine its overall efficiency.
[00026] Now to describe the above steps carried out in Example I in further detail, a 6- inch N-type silicon single crystal wafer 12 having a resistivity of 1 to 5 (Ω cm), (300) crystal orientation is cleaned by a typical RCA cleaning method. [00027] The substrate cleaning is performed in the following steps: (1 ) removing organic material using sulfuric acid-hydrogen peroxide water cleaning for ten m inutes at 350°K; (2) using a pure water cleaning; (3) drying the resulting substrate with nitrogen, with an infrared treatment, and with ultraviolet light drying; and (4) cleaning the dried substrate with a 0.5% hydrofluoric acid solution. Subsequent cleaning by ammonium-hydrogen peroxide water at 350°K for 1 0 minutes, removing heavy metal contamination by 80°C hydrochloric acid- hydrogen peroxide water cleaning solution for ten minutes after a pure water rinsing, and lastly pure water cleaning and nitrogen gas drying followed by paper IPA drying.
[00028] Next a SiC isolation layer 55 having a 200 nm thickness, is placed on the back surface of the resultant cleaned wafer 12 by means of a sputtering method. While the isolation layer in the present example is SiC, an 8102 isolation layer may also be used. In addition, while the isolation layer thickness used in the present example is 200 nm, any other thickness above 100 nm may be used as well.
[00029] Following the previous step, a high resistivity layer 9 is formed on substrate 12 by the following method, inert gas is introduced into a quartz boat containing the substrate 12 which had been previously vacuumed to approximately 1 E-3 Pa. The quartz boat is heated and kept at pre-determined annealing temperature of 800°K or more for 30 minutes. While a vacuum of approximately 1E-3 Pa is used in the present example, the degree of the vacuum is not critical and any vacuum of approximately 20 Pa or lower can be used. Further, while argon gas was used as the inert gas in the present example, another inert gas such as helium gas and the like or a mixture of these inert gases may be used.
[00030] A variety of heating methods can be used to form intrinsic silicon layer 9, including but not limited to infrared heating, laser heating, and hot-wall furnace heating, in some embodiments, the particular heating methods used for treating the substrate layer have an effect on photovoltaic performance of the photovoltaic cell, in some embodiments, the cooling rate after the heating stage is a crucial factor to photovoltaic ceil fabrication, whereas the heating rate is a less crucial factor to photovoltaic ceil fabrication. Maximum photovoltaic cell performance can be obtained at heating temperatures above 1500°K, at heating times above 5 minutes, at approximately 1x10° Pa. The overall parameters used during heating step include temperatures ranging from 852 1700° Kelvin, heating times from one to 600 min., atmospheres from vacuum, argon, nitrogen or other inert gas at temperatures up to 1 atm. After the heating process is completed, the substrate is transformed into a photovoltaic semiconductor materia! having a high-resistivity layer therein.
[00031 | After formation of the intrinsic silicon layer 9, the resulting substrate was cleaned by the use of a typical RCA cleaning method, similar to the one mentioned above,
[00032] After the cleaning step, a p-type silicon layer 7 is formed on top of layer 9 by means of boron (B) doping (diffusion) of the silicon wafer. In this example, boron nitride (BN) powder having a diameter between 2 and 20 microns was introduced in a heating chamber, then the quartz boat containing the silicon wafers is placed next to the BN powder and vacuumed to approximately 1 Pa. Next the heating chamber is heated and kept at a predetermined heating temperature of between 900 and 1200 °K for I to 15 minutes, The amount of B diffusion into the intrinsic silicon layer varies according to heating temperature and time, in this example, the p-type silicon layer thickness was calculated to be 50 to 250 nm, for the temperature and time range mentioned above.
[00033] While B doping was used to create p-type silicon layer 7 in this example, p-type silicon layer 7, may be also formed by means of a B ion implantation method.
[00034} Next, a 150 nm thick ZnO transparent conductive film is formed over the p-type silicon layer 7 by a sputtering method to form top TCO electrode 50.
[00035] In this example, a silver paste bus-bar may be placed on top of the ZnO layer to improve overall electrical properties of top TCO electrode 50. Placement of the bus-bar is performed by a screen printing method.
[00036] While ZnO is used in the present example, other transparent conductive oxide films such as ΠΌ, AZO, GZO, ΪΖΟ, and Nb02, or a stacked structure thereof; may be used, and the transparent conductive oxide film may be formed by PLD, PvIOCVD, or a coating method, not limited to the sputtering method.
[00037] Next, a silicon nitride film may be formed consecutively as an anti-reflection film. [00038] Lastly, Aluminum is coated by screen printing on the bottom (back) surface of the wafer 60 and heating is provided at 550°K for removing binder, and to complete the solar cell 60 construction.
[00039] While, a single crystal of I to 5 (Ω cm) and orientation (100) was used for the silicon substrate 12 in the present example, the face orientation may be (1 10) or ( 1 1 1 ), and solar grade silicon or poly- crystalline silicon may be used. When a silicon substrate having a different resistivity is used, it is necessary to change heating temperature and time.
[00040] EXAMPLE 2: (top p-type layer by deposition: CVD, PVD, PLD)
[00041 ] The following is another method for fabricating a PV cell 60 as shown in FIG, 2 of the present invention according to the process flowchart of FIG. 3.
[00042] In this example the steps for forming PV cell 60 are the same as in example 1 , described above, except, for process step 38, where the p-type silicon layer 7 is created, in this example 2, the p-type silicon layer 7 is deposited on top of the high resistivity layer by means of chemical vapor deposition (CVD). This p-type silicon layer may be an amorphous structure and of a thickness of approximately 5 to 100 nni.
[00043] While a CVD method is used to create a p-type silicon Iayer on top of the intrinsic silicon layer (or high resistivity layer) in this example, p-type silicon layer may be also formed by PVD, PLD, or some other coating method not limited to a sputtering method.
[00044] The foregoing description of preferred embodiments of the present invention has been provided tor the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed, Various additions, deletions and modifications are contemplated as being within its scope. The scope of the invention is, therefore, indicated by the appended claims rather than the foregoing description. Further, all changes which may fall within the meaning and range of equivalency of the claims and elements and features thereof are to be embraced within their scope.

Claims

We claim:
1 . A PIN photovoltaic device comprising a first electrode layer, a p-type semiconductor layer, a high resistivity intrinsic semiconductor layer, an n-type semiconductor substrate; and a bottom electrode.
2. The device of claim 1 wherein said first electrode layer is a transparent conductive oxide (TCO).
3. The device of claim 1 wherein said first electrode layer is selected from the group consisting of ZnO ΓΤΟ, ACO, GZO, IZO, and b02,
4. The device of claim 3 wherein said first electrode layer is ZnO.
5. The device of claim 4 further comprising placing a silver paste bus-bar on top of said first electrode layer.
6. The device of claim 1 further comprising an anti -reflecting coating on lop of said first electrode layer.
7. The device of claim 1 wherein the resistivity of said intrinsic semiconductor layer is at least 10 times that of said n-type semiconductor substrate.
8. The dev ice of claim 1 wherein said semiconductor substrate is an n-type single crystal silicon substrate having a resistivity in the range of about 1 to about five ohm- centimeter (Ω-cm).
9. The device of claim 1 further comprising a silicon carbide isolation layer between the semiconductor substrate and the bottom electrode,
10. The device of claim I wherein said p-type semiconductor layer is a p-type silicon layer.
1 1. The device of claim I wherein aid bottom eiectrode is a metal layer having an ohmic contact with said n-type semiconductor substrate.
12. The device of claim 1 wherein said bottom electrode is aluminum.
13. A method of manufacturing a photovoltaic device having an n-type semiconductor substrate comprising performing the steps of: cleaning the n-type semiconductor substrate; introducing an inert gas under vacuum and a high temperature to form a high resistivity layer on the top surface of the substrate: forming a p-type semiconductor iayer on the high resistivity layer; forming a transparent electrode layer on the p-type semiconductor layer; and forming a metal electrode on the bottom surface of the substrate.
14. The method of claim 13 wherein said n-type silicon substrate has a resistivity in the range of about 1 to about five ohm- centimeter (Ω· η).
1 5. The method of claim 1 3 wherein said intrinsic semiconductor iayer has a thickness of at least 100 nanometers (nm).
16. The method of claim 13 wherein said p-type semiconductor iayer is a p-type silicon !ayer.
17. The method of claim 13 wherein said transparent eiectrode layer is a TCO layer selected from the group consisting ofZnO, iTO, AGO, GZO, IZO, and Nb02.
1 8. The method of claim 33 wherein said TCO layer is ZnO.
19. The method of claim 13 wherein said metal bottom electrode is aluminum.
20. A method of manufacturing a photovoltaic device having an n-type semiconductor substrate comprising performing the steps of: cleaning the n-type semiconductor substrate; forming an SiC or Si()2 isolation layer on the bottom surface of the substrate: introducing an inert gas under vacuum and a high temperature to form a high resistivity layer on the top surface of the substrate; depositing a p-lype semiconductor layer on the high resistivity layer; forming a transparent electrode layer on the p-type semiconductor layer; and forming a metal electrode on the bottom surface of the substrate
21 . The method of claim 20 wherein said transparent electrode layer is ZnO.
22. The method of claim 20 further comprising forming an anil-reflecting coating on the top of said transparent electrode layer, wherein said an ti -reflective film is SiN.
PCT/US2014/030038 2013-03-15 2014-03-15 Pin photovoltaic cell and process of manufacture WO2014145300A2 (en)

Applications Claiming Priority (20)

Application Number Priority Date Filing Date Title
US201361800912P 2013-03-15 2013-03-15
US201361801145P 2013-03-15 2013-03-15
US201361801019P 2013-03-15 2013-03-15
US201361800800P 2013-03-15 2013-03-15
US201361801244P 2013-03-15 2013-03-15
US61/801,019 2013-03-15
US61/800,912 2013-03-15
US13/844,686 2013-03-15
US61/801,244 2013-03-15
US13/844,686 US20130255774A1 (en) 2012-04-02 2013-03-15 Photovoltaic cell and process of manufacture
US13/844,298 2013-03-15
US13/844,747 2013-03-15
US13/844,428 US20130255773A1 (en) 2012-04-02 2013-03-15 Photovoltaic cell and methods for manufacture
US13/844,298 US8952246B2 (en) 2012-04-02 2013-03-15 Single-piece photovoltaic structure
US13/844,428 2013-03-15
US13/844,521 2013-03-15
US13/844,521 US9099578B2 (en) 2012-06-04 2013-03-15 Structure for creating ohmic contact in semiconductor devices and methods for manufacture
US13/844,747 US20130255775A1 (en) 2012-04-02 2013-03-15 Wide band gap photovoltaic device and process of manufacture
US61/801,145 2013-03-15
US61/800,800 2013-03-15

Publications (2)

Publication Number Publication Date
WO2014145300A2 true WO2014145300A2 (en) 2014-09-18
WO2014145300A3 WO2014145300A3 (en) 2014-11-13

Family

ID=51537946

Family Applications (5)

Application Number Title Priority Date Filing Date
PCT/US2014/030044 WO2014145306A1 (en) 2013-03-15 2014-03-15 Infrared photovoltaic device and manufacturing method
PCT/US2014/030038 WO2014145300A2 (en) 2013-03-15 2014-03-15 Pin photovoltaic cell and process of manufacture
PCT/US2014/030089 WO2014145348A1 (en) 2013-03-15 2014-03-15 Infrared photovoltaic device
PCT/US2014/030032 WO2014145294A2 (en) 2013-03-15 2014-03-15 Manufacturing equipment for photovoltaic devices and methods
PCT/US2014/030079 WO2014145339A1 (en) 2012-10-17 2014-03-15 Hybrid-transparent electrode assembly for photovoltaic cell manufacturing

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/US2014/030044 WO2014145306A1 (en) 2013-03-15 2014-03-15 Infrared photovoltaic device and manufacturing method

Family Applications After (3)

Application Number Title Priority Date Filing Date
PCT/US2014/030089 WO2014145348A1 (en) 2013-03-15 2014-03-15 Infrared photovoltaic device
PCT/US2014/030032 WO2014145294A2 (en) 2013-03-15 2014-03-15 Manufacturing equipment for photovoltaic devices and methods
PCT/US2014/030079 WO2014145339A1 (en) 2012-10-17 2014-03-15 Hybrid-transparent electrode assembly for photovoltaic cell manufacturing

Country Status (1)

Country Link
WO (5) WO2014145306A1 (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4072541A (en) * 1975-11-21 1978-02-07 Communications Satellite Corporation Radiation hardened P-I-N and N-I-P solar cells
US4167015A (en) * 1978-04-24 1979-09-04 Rca Corporation Cermet layer for amorphous silicon solar cells
US5286306A (en) * 1992-02-07 1994-02-15 Shalini Menezes Thin film photovoltaic cells from I-III-VI-VII compounds
US20060231802A1 (en) * 2005-04-14 2006-10-19 Takuya Konno Electroconductive thick film composition, electrode, and solar cell formed therefrom
US20110088760A1 (en) * 2009-10-20 2011-04-21 Applied Materials, Inc. Methods of forming an amorphous silicon layer for thin film solar cell application
US20110197960A1 (en) * 2010-02-12 2011-08-18 Heraeus Materials Technology Llc Method for applying full back surface field and silver busbar to solar cell
US20120049242A1 (en) * 2009-04-21 2012-03-01 The Silanna Group Pty Ltd Optoelectronic device with lateral pin or pin junction
US20120318347A1 (en) * 2009-12-04 2012-12-20 Q-Cells Se Antireflection coating as well as solar cell and solar module therewith

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4163677A (en) * 1978-04-28 1979-08-07 Rca Corporation Schottky barrier amorphous silicon solar cell with thin doped region adjacent metal Schottky barrier
DE3135933A1 (en) * 1980-09-26 1982-05-19 Unisearch Ltd., Kensington, New South Wales SOLAR CELL AND METHOD FOR THEIR PRODUCTION
US4417092A (en) * 1981-03-16 1983-11-22 Exxon Research And Engineering Co. Sputtered pin amorphous silicon semi-conductor device and method therefor
JP2859632B2 (en) * 1988-04-14 1999-02-17 キヤノン株式会社 Film forming apparatus and film forming method
US5578520A (en) * 1991-05-28 1996-11-26 Semiconductor Energy Laboratory Co., Ltd. Method for annealing a semiconductor
CN1067155C (en) * 1994-08-06 2001-06-13 彭景尧 Multi-chamber continuous annealing furnace
US6117266A (en) * 1997-12-19 2000-09-12 Interuniversifair Micro-Elektronica Cenirum (Imec Vzw) Furnace for continuous, high throughput diffusion processes from various diffusion sources
US20090111206A1 (en) * 1999-03-30 2009-04-30 Daniel Luch Collector grid, electrode structures and interrconnect structures for photovoltaic arrays and methods of manufacture
US6566685B2 (en) * 2000-04-12 2003-05-20 Casio Computer Co., Ltd. Double gate photo sensor array
MY141175A (en) * 2000-09-08 2010-03-31 Semiconductor Energy Lab Light emitting device, method of manufacturing the same, and thin film forming apparatus
AU2001277779B2 (en) * 2001-08-13 2005-04-07 Sphelar Power Corporation Semiconductor device and method of its manufacture
AU2007346834A1 (en) * 2007-02-08 2008-08-21 Wuxi Suntech-Power Co., Ltd. Hybrid silicon solar cells and method of fabricating same
JP4486135B2 (en) * 2008-01-22 2010-06-23 東京エレクトロン株式会社 Temperature control mechanism and processing apparatus using the same
DE102009007908A1 (en) * 2009-02-06 2010-08-12 Zylum Beteiligungsgesellschaft Mbh & Co. Patente Ii Kg Method for producing a thin-film photovoltaic system and thin-film photovoltaic system
TW201037845A (en) * 2009-04-10 2010-10-16 Ritdisplay Corp Photovoltaic cell structure and manufacturing method
KR101995704B1 (en) * 2009-11-20 2019-07-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Method for manufacturing semiconductor device
US10770323B2 (en) * 2010-02-18 2020-09-08 Brooks Automation Gmbh Stackable substrate carriers
KR20110136180A (en) * 2010-06-14 2011-12-21 삼성전자주식회사 Method of forming electrode and method of manufacturing solar cell using the same
US8410000B2 (en) * 2010-11-17 2013-04-02 Hitachi Chemical Company, Ltd. Method for producing photovoltaic cell
US20120210936A1 (en) * 2011-02-21 2012-08-23 Ji Fu Machinery & Equipment Inc. Systems and methods for mutli-chamber photovoltaic module processing
US20120285517A1 (en) * 2011-05-09 2012-11-15 International Business Machines Corporation Schottky barrier solar cells with high and low work function metal contacts
US20130255774A1 (en) * 2012-04-02 2013-10-03 Nusola, Inc. Photovoltaic cell and process of manufacture

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4072541A (en) * 1975-11-21 1978-02-07 Communications Satellite Corporation Radiation hardened P-I-N and N-I-P solar cells
US4167015A (en) * 1978-04-24 1979-09-04 Rca Corporation Cermet layer for amorphous silicon solar cells
US5286306A (en) * 1992-02-07 1994-02-15 Shalini Menezes Thin film photovoltaic cells from I-III-VI-VII compounds
US20060231802A1 (en) * 2005-04-14 2006-10-19 Takuya Konno Electroconductive thick film composition, electrode, and solar cell formed therefrom
US20120049242A1 (en) * 2009-04-21 2012-03-01 The Silanna Group Pty Ltd Optoelectronic device with lateral pin or pin junction
US20110088760A1 (en) * 2009-10-20 2011-04-21 Applied Materials, Inc. Methods of forming an amorphous silicon layer for thin film solar cell application
US20120318347A1 (en) * 2009-12-04 2012-12-20 Q-Cells Se Antireflection coating as well as solar cell and solar module therewith
US20110197960A1 (en) * 2010-02-12 2011-08-18 Heraeus Materials Technology Llc Method for applying full back surface field and silver busbar to solar cell

Also Published As

Publication number Publication date
WO2014145339A1 (en) 2014-09-18
WO2014145294A3 (en) 2014-11-27
WO2014145348A1 (en) 2014-09-18
WO2014145294A2 (en) 2014-09-18
WO2014145306A1 (en) 2014-09-18
WO2014145300A3 (en) 2014-11-13

Similar Documents

Publication Publication Date Title
Gall et al. Polycrystalline silicon thin-film solar cells on glass
US8518724B2 (en) Method to form a device by constructing a support element on a thin semiconductor lamina
US8101451B1 (en) Method to form a device including an annealed lamina and having amorphous silicon on opposing faces
TWI424582B (en) Method of fabricating solar cell
US20140014169A1 (en) Nanostring mats, multi-junction devices, and methods for making same
Nemeth et al. Low temperature Si/SiO x/pc-Si passivated contacts to n-type Si solar cells
US8536448B2 (en) Zener diode within a diode structure providing shunt protection
Seyhan et al. A hydrogenated amorphous silicon (a-Si: H) thin films for heterojunction solar cells: structural and optical properties
US9842956B2 (en) System and method for mass-production of high-efficiency photovoltaic structures
Bruhat et al. TCO contacts on poly-Si layers: High and low temperature approaches to maintain passivation and contact properties
US11769848B2 (en) Heterojunction structure-based solar cell and manufacturing method thereof
US20120258561A1 (en) Low-Temperature Method for Forming Amorphous Semiconductor Layers
JP6635934B2 (en) Back contact type Si thin film solar cell
US20150007875A1 (en) Pin photovoltaic cell and process of manufacture
WO2014145300A2 (en) Pin photovoltaic cell and process of manufacture
JP5975841B2 (en) Manufacturing method of photovoltaic device and photovoltaic device
JP5398772B2 (en) Photovoltaic device, manufacturing method thereof, and photovoltaic module
KR101673241B1 (en) Method for fabricating tandem solar cell with thin film silicon and bulk crystalline silicon using silicon thin film tunnel junction layer by PECVD and solar cell thereof
Ng et al. Development of p+/n+ polysilicon tunnel junctions compatible for industrial screen printing
US20130255775A1 (en) Wide band gap photovoltaic device and process of manufacture
JP2011243726A (en) Solar cell manufacturing method
US20160043245A1 (en) Hybrid transparent electrode assembly for photovoltaic cell manufacturing
KR20100093291A (en) Method of fabricating solar sell
US20150295117A1 (en) Infrared photovoltaic device
Hernández-Como et al. Hetero-junction (HIT) silicon solar cell model for AMPS-1D simulation

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14763313

Country of ref document: EP

Kind code of ref document: A2

122 Ep: pct application non-entry in european phase

Ref document number: 14763313

Country of ref document: EP

Kind code of ref document: A2