WO2014139345A1 - 超高清显示的控制方法及装置、超高清电视机 - Google Patents

超高清显示的控制方法及装置、超高清电视机 Download PDF

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Publication number
WO2014139345A1
WO2014139345A1 PCT/CN2014/071314 CN2014071314W WO2014139345A1 WO 2014139345 A1 WO2014139345 A1 WO 2014139345A1 CN 2014071314 W CN2014071314 W CN 2014071314W WO 2014139345 A1 WO2014139345 A1 WO 2014139345A1
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Prior art keywords
signal
frame
high definition
ultra high
pixel
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PCT/CN2014/071314
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English (en)
French (fr)
Inventor
徐遥令
李海鹰
侯志龙
郭明海
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Shenzhen Skyworth RGB Electronics Co Ltd
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Shenzhen Skyworth RGB Electronics Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder

Definitions

  • the invention relates to the field of display technology, in particular to a control method and device for ultra high definition display, and an ultra high definition television.
  • Ultra High Definition Television is a TV with a pixel count of 3840 ⁇ 2160 (4K ⁇ 2K) or 7680 ⁇ 4320 (8K ⁇ 4K), compared to 1920 ⁇ 1080 (2K ⁇ 1K) pixels of Full HD TV (FHDTV). The number of pixels is increased by 4 or 16 times, so the image performance is very clear and delicate.
  • the 4K ⁇ 2K standard and the 8K ⁇ 4K standard are included in the ultra-high definition television standard developed by ITU-R, and 4K ⁇ 2K Compared with 8K ⁇ 4K UHDTV, UHDTV is easier to implement and popularize. It is the hotspot and direction of TV industry attention and development.
  • the ultra-high-definition television mainly receives 2K ⁇ 1K signals, and after decoding and image quality processing, it drives the ultra-high-definition screen through amplification processing to realize ultra-high-definition display; and for 4K ⁇ 2K signals, it needs to be converted into special instruments and means.
  • 2K ⁇ 1K high cost, complicated operation, low stability and reliability, and defects such as image distortion and blurring of the displayed image.
  • the existing problems in the prior art are: the existing ultra-high-definition television is designed for the full HD signal because the television chip is designed for the full HD signal.
  • the source of the film is 4K ⁇ 2K, the ultra-high-definition screen cannot realize the super-high-definition signal. HD display.
  • the main object of the present invention is to provide a control method for an ultra high definition display, which aims to enable an ultra high definition screen to realize ultra high definition display on an ultra high definition signal.
  • the embodiment of the invention discloses a control method for ultra high definition display, which comprises the following steps:
  • the specific steps of decomposing the received 4K ⁇ 2K signal into a 2K ⁇ 1K transition signal include:
  • the received 4K ⁇ 2K signal is subjected to frame pixel compression to obtain a 4K ⁇ 1K signal;
  • the method further includes performing a frame extraction step on the received 4K ⁇ 2K signal to receive the received signal. Converting the frequency of the 4K ⁇ 2K signal to the first frequency group;
  • the first frequency group includes 24 Hz, 25 Hz, and 30 Hz
  • the second frequency group includes 50 Hz, 59.94 Hz, and 60 Hz.
  • the manner of frame extraction of the received 4K ⁇ 2K signal whose frequency belongs to the first frequency group is frame-by-frame extraction.
  • the manner of frame pixel compression of the received 4K ⁇ 2K signal is interlaced removal of pixels.
  • the manner of performing frame pixel segmentation on the 4K ⁇ 1K signal is left and right segmentation.
  • the specific steps of converting the 2K ⁇ 1K screen display signal into a 4K ⁇ 2K target signal include:
  • the 2K ⁇ 2K signal is subjected to frame combining processing to acquire a 4K ⁇ 2K target signal.
  • the interpolation formula used for performing the interpolation and amplification processing on the 2K ⁇ 1K screen display signal to obtain the 2K ⁇ 2K signal is:
  • the pixels of the odd frame of the 2K ⁇ 2K signal are E(L/R)’ 'pq
  • the pixel of the current row of the odd frame of the 2K ⁇ 1K screen display signal is E(L/R)'ab
  • the uplink pixel of the odd frame of the 2K ⁇ 1K screen display signal is E(L/R) '(a-1)b
  • the descending pixel of the odd frame of the 2K ⁇ 1K screen display signal is E(L/R)'(a+1)b
  • the odd number of the 2K ⁇ 1K screen display signal
  • the pixel of the current row of the even frame corresponding to the frame is O(L/R)'ab
  • the pixels of the even frames of the 2K x 2K signal are O(L/R)' 'pq
  • the pixel of the current row of the even frame of the 2K ⁇ 1K screen display signal is O(L/R)'ab
  • the uplink pixel of the even frame of the 2K ⁇ 1K screen display signal is O(L/R) '(a-1)b
  • the descending pixel of the even frame of the 2K ⁇ 1K screen display signal is O(L/R)'(a+1)b
  • the pixel of the current line of the odd frame corresponding to the frame is E(L/R)'ab
  • the pixel of the current line of the rear odd frame adjacent to the even frame of the 2K ⁇ 1K screen display signal is E(L/R) +1'ab
  • the embodiment of the invention further discloses a control device for the ultra high definition display, comprising:
  • a frame decomposition module configured to decompose the received 4K ⁇ 2K signal into a 2K ⁇ 1K transition signal
  • a frame decoding module configured to perform decoding processing on the 2K ⁇ 1K transition signal to obtain a 2K ⁇ 1K screen display signal
  • a frame synthesis module configured to convert the 2K ⁇ 1K screen display signal into a 4K ⁇ 2K target signal for providing to the ultra high definition screen display.
  • the frame decomposition module comprises:
  • a frequency identification unit for identifying a frequency of the received 4K ⁇ 2K signal
  • a frame extracting unit configured to perform frame extraction on the received 4K ⁇ 2K signal when the frequency of the received 4K ⁇ 2K signal is recognized by the frequency identifying unit as belonging to the second frequency group, to receive the received 4K ⁇ 2K Converting a frequency of the signal to the first frequency group;
  • a frame pixel compression unit configured to receive the received 4K ⁇ when the frequency of the received 4K ⁇ 2K signal is recognized by the frequency identification unit as belonging to the first frequency group or converted by the frame extraction unit to the first frequency group
  • the 2K signal is subjected to compression of frame pixels to obtain a 4K ⁇ 1K signal
  • a frame pixel dividing unit configured to perform frame pixel segmentation on the 4K ⁇ 1K signal to obtain a 2K ⁇ 1K transition signal
  • the first frequency group includes 24 Hz, 25 Hz, and 30 Hz
  • the second frequency group includes 50 Hz, 59.94 Hz, and 60 Hz.
  • the frame synthesis module includes:
  • a frame pixel amplifying unit configured to perform interpolation and amplification processing on the 2K ⁇ 1K screen display signal to obtain a 2K ⁇ 2K signal;
  • a frame combining unit configured to perform frame combining processing on the 2K ⁇ 2K signal to acquire a 4K ⁇ 2K target signal.
  • the embodiment of the invention also discloses an ultra high definition television, comprising a format judging device, a super high definition display control device and an ultra high definition screen;
  • the format determining device is configured to determine whether the input signal is a 4K ⁇ 2K signal, and if it is determined that the input signal is a 4K ⁇ 2K signal, output the 4K ⁇ 2K signal to the control device of the ultra high definition display. ;
  • the control device for the ultra high definition display is the control device for the ultra high definition display according to any one of the above technical solutions, and is configured to control the ultra high definition television to realize ultra high definition display;
  • the ultra high definition screen is used for displaying a 4K ⁇ 2K signal output by the control device of the ultra high definition display in ultra high definition.
  • the control method of the ultra high definition display disclosed by the invention decomposes the received 4K ⁇ 2K signal into a 2K ⁇ 1K transition signal; and the TV chip designed for the full HD (2K ⁇ 1K) signal can perform the 2K ⁇ 1K transition signal.
  • the decoding process is performed to obtain a 2K ⁇ 1K screen display signal after decoding and image quality processing; finally, the 2K ⁇ 1K screen display signal is converted into a 4K ⁇ 2K target signal.
  • the present invention decomposes it into a 2K ⁇ 1K transition signal to facilitate decoding processing by a conventional television chip to obtain a 2K ⁇ 1K on-screen signal, and by decoding the processed 2K ⁇
  • the 1K screen display signal is combined with the 4K ⁇ 2K target signal to achieve the ultra-high definition screen to achieve ultra-high definition display.
  • FIG. 1 is a schematic flow chart of a method for controlling an ultra high definition display in a preferred embodiment of the present invention
  • FIG. 2 is a schematic flow chart of decomposing a received 4K ⁇ 2K signal into a 2K ⁇ 1K transition signal in a preferred embodiment of the method for controlling an ultra high definition display according to the present invention
  • FIG. 3 is a schematic flow chart of converting a 2K ⁇ 1K screen display signal into a 4K ⁇ 2K target signal in a preferred embodiment of a method for controlling an ultra high definition display according to the present invention
  • FIG. 4 is a schematic structural diagram of a control device for an ultra high definition display in a preferred embodiment of the present invention.
  • 5-1 is a schematic diagram of odd frame pixels (6 ⁇ 6 pixels) in a 4K ⁇ 2K@30Hz signal according to the present invention
  • 5-2 is a schematic diagram of an even frame pixel (6 ⁇ 6 pixels) in a 4K ⁇ 2K@30Hz signal according to the present invention
  • Figure 6-1 is a schematic diagram of an E' frame pixel formed by compressing an E frame pixel shown in Figure 5-1;
  • FIG. 6-2 is a schematic diagram of an O' frame pixel formed by compressing an O frame pixel shown in FIG. 5-2;
  • FIG. 7-1 is a schematic diagram of an E'L frame pixel formed by dividing an E' frame pixel shown in FIG. 6-1;
  • FIG. 7-2 is a schematic diagram of an E'R frame pixel formed by dividing an E' frame pixel shown in FIG. 6-1;
  • FIG. 7-3 is a schematic diagram of an O'L frame pixel formed by dividing the O' frame pixel shown in FIG. 6-2;
  • FIG. 7-4 is a schematic diagram of an O'R frame pixel formed by dividing the O' frame pixel shown in FIG. 6-2;
  • 8-1 is a schematic diagram of an EL' frame pixel formed by image decoding and image processing of the E'L frame pixel shown in FIG. 7-1;
  • 8-2 is a schematic diagram of an ER' frame pixel formed by image decoding and image processing of the E'R frame pixel shown in FIG. 7-2;
  • 8-3 is a schematic diagram of an OL' frame pixel formed by the image decoding and image processing of the O'L frame pixel shown in FIG. 7-3;
  • 8-4 is a schematic diagram of an OR' frame pixel formed by image decoding and image processing of the O'R frame pixel shown in FIG. 7-4;
  • 9-1 is a schematic diagram of an EL'' frame pixel formed by the EL' frame pixel shown in FIG. 8-1 after being enlarged by interpolation;
  • 9-2 is a schematic diagram of an ER'' frame pixel formed by the ER' frame pixel shown in FIG. 8-2 after being enlarged by interpolation;
  • 9-3 is a schematic diagram of an OL'' frame pixel formed by the OL' frame pixel shown in FIG. 8-3 after being enlarged by interpolation;
  • 9-4 is a schematic diagram of an OR'' frame pixel formed by the OR' frame pixel shown in FIG. 8-4 after being enlarged by interpolation;
  • Figure 10-1 shows the EL'' frame pixel shown in Figure 9-1 and the ER'' shown in Figure 9-2.
  • 10-2 is a schematic diagram of an MO frame pixel formed by combining the OL'' frame pixel shown in FIG. 9-3 and the OR'' frame image shown in FIG. 9-4;
  • FIG. 11 is a schematic structural diagram of an ultra high definition television set according to a preferred embodiment of the present invention.
  • the invention discloses a control method for ultra high definition display.
  • the control method of the ultra high definition display in the embodiment comprises the following steps:
  • step S01 the received 4K ⁇ 2K signal is decomposed into a 2K ⁇ 1K transition signal.
  • Step S02 performing decoding processing on the 2K ⁇ 1K transition signal to obtain a 2K ⁇ 1K screen display signal.
  • Step S03 converting the 2K ⁇ 1K screen display signal into a 4K ⁇ 2K target signal to provide an ultra high definition screen for the ultra high definition display.
  • the present invention decomposes it into a 2K ⁇ 1K transition signal to facilitate the decoding process of the conventional television chip to obtain a 2K ⁇ 1K screen display signal, and passes the decoded 2K ⁇ 1K screen.
  • the display signal is synthesized into a 4K ⁇ 2K target signal to achieve the purpose of ultra-high-definition display for ultra-high-definition signals.
  • the specific steps of decomposing the received 4K ⁇ 2K signal into a 2K ⁇ 1K transition signal include:
  • Step S11 identifying the frequency of the received 4K ⁇ 2K signal; when the frequency of the received 4K ⁇ 2K signal is identified as belonging to the first frequency group, performing step S13; when the frequency of the received 4K ⁇ 2K signal is identified as belonging to In the second frequency group, step S12 is performed.
  • the first frequency group includes 24 Hz, 25 Hz, and 30 Hz
  • the second frequency group includes 50 Hz, 59.94 Hz, and 60 Hz.
  • Step S12 performing frame extraction on the received 4K ⁇ 2K signal to convert the frequency of the received 4K ⁇ 2K signal to the first frequency group, and then performing step S13.
  • step S13 frame pixels are compressed on the received 4K ⁇ 2K signal to obtain a 4K ⁇ 1K signal.
  • Step S14 performing segmentation of the frame pixels on the 4K ⁇ 1K signal to obtain a 2K ⁇ 1K transition signal.
  • the manner of frame decimation of the received 4K x 2K signal belonging to the first frequency group is frame-by-frame extraction.
  • the received 4K ⁇ 2K signal is 4K ⁇ 2K@60Hz
  • the odd or even frames of the 4K ⁇ 2K@60Hz signal are extracted to form a 4K ⁇ 2K@30Hz signal for subsequent frame pixel compression.
  • the received 4K ⁇ 2K signal is 4K ⁇ 2K@30Hz
  • no frame deselection is performed, and subsequent frame pixel compression is directly performed.
  • the frame extraction is not limited to the foregoing manner, and may be continuous extraction.
  • the received 4K ⁇ 2K signal is 4K ⁇ 2K@50Hz
  • the number of frames may be continuously extracted to form a 4K ⁇ 2K@30Hz signal or form a 4K ⁇ 2K@25Hz signal.
  • the manner in which the received 4K x 2K signal is frame pixel compressed is interlaced to remove pixels.
  • the 4K ⁇ 2K@30Hz signal is subjected to frame pixel compression processing, the even-numbered lines of the odd-numbered frames (E-frames) are reserved, and the odd-numbered lines are removed to form the E'-frames and the odd-numbered lines (O-frames) are retained to remove the even-numbered lines.
  • each row of pixels of the E' frame is an odd row of pixel values of the E frame
  • the pixel value of each row of the O' frame is an even-numbered pixel value of the O frame, that is, the 4K ⁇ 2K@30 Hz signal is subjected to frame pixel compression processing to form a 4K ⁇ 1K@30 Hz signal.
  • the manner of performing frame pixel compression is not limited to interlace removing pixels. Loss of information in the vertical direction of the image can be avoided by removing pixels in an interlaced manner.
  • the method of performing frame pixel segmentation on the 4K ⁇ 1K signal is left and right segmentation.
  • the 4K ⁇ 1K@30Hz signal is subjected to frame pixel segmentation processing, and the E' frame of the 4K ⁇ 1K@30Hz signal is divided into left and right halves to form a left half odd frame (E'L frame) and a right half odd frame (E'R).
  • the O' frame of the 4K ⁇ 1K@30Hz signal is divided into two left and right halves (O'L frame) and (O'R frame), that is, the 4K ⁇ 1K@30Hz signal is subjected to frame pixel segmentation processing to form 2K.
  • ⁇ 1K@60Hz signal frame pixel segmentation is not limited to the above manner, and may be, for example, up and down segmentation.
  • the decoding process of the 2K ⁇ 1K transition signal specifically includes performing image decoding and image processing steps on the 2K ⁇ 1K transition signal, where the operation of the traditional television chip can be completed, and no longer Narration.
  • the specific steps of converting the 2K ⁇ 1K screen display signal into a 4K ⁇ 2K target signal include:
  • Step S21 performing interpolation processing on the 2K ⁇ 1K screen display signal to obtain a 2K ⁇ 2K signal.
  • Step S22 performing frame combining processing on the 2K ⁇ 2K signal to acquire a 4K ⁇ 2K target signal.
  • the interpolation algorithm used to perform the interpolation and amplification processing on the 2K ⁇ 1K screen display signal to obtain the 2K ⁇ 2K signal is:
  • the pixel of the odd frame of the 2K ⁇ 2K signal is E(L/R)’ 'pq
  • the pixel of the current line of the odd frame of the 2K ⁇ 1K screen display signal is E(L/R)'ab
  • the upside pixel of the odd frame of the 2K ⁇ 1K screen display signal is E(L/R)'(a -1) b
  • the downstream pixel of the odd frame of the 2K ⁇ 1K screen display signal is E(L/R)'(a+1)b
  • the current line of the even frame corresponding to the odd frame of the 2K ⁇ 1K screen display signal The pixel of the current row of the preceding even frame adjacent to the odd frame of the 2K ⁇ 1K screen display signal is O(L/R)-1'ab;
  • the coefficient is k1
  • the second coefficient is k2
  • the similarity correlation value of the E(L/R)' frame and the O(L/R)' frame is K3, E(L/R)' frame and O(L/R).
  • the -1' frame similarity correlation value is k4.
  • the pixel of the even frame of the 2K ⁇ 2K signal is O(L/R)’ 'pq
  • the pixel of the current line of the even frame of the 2K ⁇ 1K screen display signal is O(L/R)'ab
  • the upside pixel of the even frame of the 2K ⁇ 1K screen display signal is O(L/R)'(a -1) b
  • the downstream pixel of the even frame of the 2K ⁇ 1K screen display signal is O(L/R)'(a+1)b
  • the current line of the odd frame corresponding to the even frame of the 2K ⁇ 1K screen display signal
  • the pixel of the last row of the odd-numbered frame adjacent to the even-numbered frame of the 2K ⁇ 1K screen signal is E(L/R)+1'ab;
  • the similarity correlation value of O(L/R)' frame and E(L/R)' frame is K7
  • the similarity correlation value of O(L/R)' frame and E(L/R)+1' frame is K8.
  • the method of performing frame pixel segmentation on the 4K ⁇ 1K signal is left-right segmentation
  • the method of performing frame combining processing on the 2K ⁇ 2K signal to acquire a 4K ⁇ 2K target signal is left-right merge.
  • the present invention discloses a control device for an ultra high definition display, and the control device for the ultra high definition display can correspond to the control method of the ultra high definition display in any of the above embodiments.
  • the control device of the ultra-high definition display includes a frame decomposition module 1, a frame decoding module 2, and a frame synthesis module 3.
  • the frame decomposition module 1 is configured to decompose the received 4K ⁇ 2K signal into a 2K ⁇ 1K transition signal, and decompose the received 4K ⁇ 2K signal into a 2K ⁇ 1K transition signal by the frame decomposition module 1 to satisfy the current television decoding and image processing.
  • the requirements for the signal format are configured to decompose the received 4K ⁇ 2K signal into a 2K ⁇ 1K transition signal.
  • the frame decoding module 2 is configured to perform decoding processing on the 2K ⁇ 1K transition signal to obtain an ultra high definition screen 2K ⁇ 1K screen display signal.
  • the frame synthesis module 3 is configured to convert the 2K ⁇ 1K screen display signal into a 4K ⁇ 2K target signal for providing to the ultra high definition screen display, and convert the 2K ⁇ 1K screen display signal into 4K ⁇ 2K through the frame synthesis module 3.
  • the target signal can drive ultra-high definition (UHD) screen to achieve ultra-high definition display, and avoid image abrupt change, which can prevent image blur and edge aliasing, and effectively improve the image display quality.
  • UHD ultra-high definition
  • the present invention decomposes it into a 2K ⁇ 1K transition signal by the frame decomposition module 1 so that the conventional television chip (corresponding to the frame decoding module 2 in the present invention) performs decoding processing and obtains 2K ⁇ 1K.
  • the screen display signal, and then the framed synthesis module 3 synthesizes the 2K ⁇ 1K screen display signal after the decoding process into a 4K ⁇ 2K target signal, so as to achieve the ultra-high definition screen to achieve ultra high definition display of the ultra high definition signal.
  • the frame decomposition module 1 includes a frequency identification unit 11, a frame extraction unit 12, a frame pixel compression unit 13, and a frame pixel division unit 14.
  • the frequency identifying unit 11 is configured to identify the frequency of the received 4K ⁇ 2K signal
  • the frame extracting unit 12 is configured to: when the frequency of the received 4K ⁇ 2K signal is recognized by the frequency identifying unit as belonging to the second frequency group, Performing frame decimation on the received 4K ⁇ 2K signal to convert the frequency of the received 4K ⁇ 2K signal to the first frequency group; the frame pixel compression unit 13 when the frequency of the received 4K ⁇ 2K signal is described
  • the frequency identification unit is configured to perform compression on the received 4K ⁇ 2K signal to obtain a 4K ⁇ 1K signal when the frequency identification unit belongs to or is converted to the first frequency group by the frame extraction unit; the frame pixel segmentation unit 14 uses Segmentation of the frame pixels is performed on the 4K ⁇ 1K signal to obtain a 2K ⁇ 1K
  • the frame synthesis module 3 includes a frame pixel amplifying unit 31 and a frame merging unit 32, wherein the frame pixel amplifying unit 31 is configured to perform interpolation processing on the 2K ⁇ 1K screen display signal.
  • a frame combining unit 32 is configured to perform frame combining processing on the 2K ⁇ 2K signal to obtain a 4K ⁇ 2K target signal.
  • an independent control module 4 and a storage module 5 can be provided, and the control module 4 is configured to control the frame decomposition module 1, the frame decoding module 2, and the frame.
  • the synthesizing module 3 performs corresponding operations, and the storage module 5 is configured to store various data input or outputted in the frame decomposing module 1, the frame decoding module 2, and the frame synthesizing module 3.
  • the frequency identifying unit 11 When the frequency of the received 4K x 2K signal is recognized by the frequency identifying unit 11 as 4K x 2K@60 Hz, the 4K x 2K@60 Hz signal is transmitted to the frame extracting unit 12; when the frequency of the received 4K x 2K signal is When the frequency identification unit 11 recognizes that it is 4K ⁇ 2K@30 Hz, the 4K ⁇ 2K@30 Hz signal is transmitted to the frame pixel compression unit 13.
  • the frame extracting unit 12 performs frame extraction on the input 4K ⁇ 2K@60 Hz signal in a frame-by-frame manner to obtain a 4K ⁇ 2K@30 Hz signal.
  • the frame extraction method is: when the received 4K ⁇ 2K@60Hz signal is an odd frame, the control frame extraction unit 12 outputs the odd frame to the frame pixel compression unit 13; When the received 4K ⁇ 2K@60Hz signal is an even frame, the control frame extracting unit 12 causes the even frame to be output to the frame pixel compressing unit 13.
  • the odd frame of only 30 frames out of 60 frames of each field of the 4K ⁇ 2K@60Hz signal received by the final frame extracting unit 12 is output to the frame pixel compressing unit 13, that is, the new 4K ⁇ 2K@30Hz received by the frame pixel compressing unit 13. signal.
  • E-frame odd-numbered frame
  • O-frame even-numbered frame
  • the frame pixel compression unit 13 performs frame pixel compression on the input 4K ⁇ 2K@30 Hz signal in an interlaced manner to obtain a 4K ⁇ 1K@30 Hz signal.
  • the frame pixel compression method is:
  • the pixel value of the E frame of the 4K ⁇ 2K@30Hz signal received by the frame pixel compression unit 13 is Eij
  • the pixel value of the O frame is Oij
  • i is 1 to 2160
  • j is 3840.
  • E' The frame is a 4K ⁇ 1K (3840 ⁇ 1080) frame; the frame pixel compression process is performed on the O frame, and the even line pixels of the O frame are reserved while the odd line pixels of the O frame are ignored, forming an O’ frame, O’
  • the frame is a 4K x 1K (3840 x 1080) frame.
  • the pixel value of the E' frame is E'mn
  • the pixel value of the O' frame is O'mn
  • m is 1 to 1080
  • n is 3840.
  • the 4K ⁇ 1K@30Hz signal outputted by the frame pixel compression unit 13 is a series of frames composed of E' frames and O' frames, and the pixel values of the E' frames are the odd-numbered pixel values of the E-frame of the input signal.
  • the pixel values of each row of the O' frame are the even-numbered row pixel values of the O-frame of the input signal.
  • FIG. 6-1 shows a schematic diagram of an E′ frame pixel formed by compressing an E frame pixel shown in FIG. 5-1, and an O′ frame pixel formed by compressing an O frame pixel shown in FIG. 5-2.
  • Figure 6-2 shows.
  • the frame pixel dividing unit 14 performs frame pixel segmentation on the input 4K ⁇ 1K@30 Hz signal in a left-right divided manner to acquire a 2K ⁇ 1K@60 Hz signal, and outputs a 2K ⁇ 1K@60 Hz signal to the frame decoding module 2.
  • the frame pixel segmentation method is: performing frame pixel processing on the E' frame, acquiring the left half of the E' frame to form an E'L frame, and acquiring the right half of the E' frame to form an E'R frame; and also performing frame on the O' frame. Pixel processing, obtaining the left half of the O' frame pixel to form an O'L frame, and acquiring the right half of the O' frame pixel to form an O'R frame.
  • the E'L, E'R, O'L, O'R frames are 2K x 1K (1920 x 1080) frames.
  • the frequency of the E'L, E'R, O'L, O'R series frame signals formed after the division is twice the input frame rate, that is, 60 Hz.
  • the E'L frame pixel formed by dividing the E' frame pixel shown in FIG. 6-1 is shown in Figure 7-1, and the E' frame pixel shown in Figure 6-1 is divided into E'R.
  • Figure 7-2 shows the frame pixel structure.
  • the O'L frame pixel formed by the O' frame pixel shown in Figure 6-2 is shown in Figure 7-3.
  • the O' is shown in Figure 6-2.
  • a schematic diagram of an O'R frame pixel formed by dividing a frame pixel is shown in Figure 7-4.
  • the frame decoding module 2 includes an image decoding unit 21 and an image processing unit 22, and receives the 2K ⁇ 1K@60 Hz signal output by the frame pixel dividing unit 14, performs image decoding and image processing, and outputs the image to the frame synthesis module 3.
  • the frame decoding module 2 performs image decoding and image processing on the input E'L, E'R, O'L, O'R series frames, and forms EL', ER', OL', OR' series frames
  • the frame synthesis module 3 outputs a 2K x 1K@60 Hz signal composed of EL', ER', OL', OR' series frames.
  • Figure 8-1 shows the schematic diagram of the EL' frame pixel formed by the image decoding and image processing of the E'L frame pixel shown in Figure 7-1, and the E'R frame pixel shown in Figure 7-2 is decoded by the image.
  • Figure 8-2 shows the schematic diagram of the ER' frame pixel formed after image processing.
  • Figure 8-3 shows the OL' frame pixel formed by the image decoding and image processing of the O'L frame pixel shown in Figure 7-3.
  • the schematic diagram of the OR' frame pixel formed by the image decoding and image processing of the O'R frame pixel shown in FIG. 7-4 is as shown in FIG. 8-4.
  • the frame pixel amplifying unit 31 performs interpolation and amplification processing on the input 2K ⁇ 1K@60 Hz signal to acquire a 2K ⁇ 2K@60 Hz signal, and outputs the 2K ⁇ 2K@60 Hz signal to the frame combining unit 32.
  • the method of frame interpolation is as follows:
  • the frame pixel amplifying unit 31 receives successive OL-1' frames, OR-1' frames, EL' frames, ER' frames, OL' frames, OR' frames, EL+1' frame, ER+1' frame.
  • the EL' frame is interpolated to form an EL'', that is, the odd line pixels of the EL'' frame are filled with the EL' current line pixel order, and the even line pixels of the EL'' frame and the up and down pixels of the current line of the EL' frame
  • the value, as well as the pixel value of the current line of the OL' and OL-1' frames adjacent to EL', is obtained by comprehensive interpolation.
  • the specific process is:
  • the pixel value of the EL' frame is EL'ab, EL'', and the pixel value is EL''pq, where a is 1 to 1080, b is 1 to 1920, a is p to 2160, and q is 1 to 1920.
  • K1, k2, k3, K4 can be obtained according to the method in the prior art, wherein the first coefficients of EL'(a-1)b and EL'(a+1)b are k1, and the second coefficient thereof is k2,
  • the similarity correlation value of the EL' frame and the OL' frame is K3, and the similarity correlation value of the EL' frame and the OL-1' frame is k4.
  • the process of enlarging the ER' frame to form the ER'' is the same as the process of inserting the EL' frame into the EL'', and will not be described again.
  • the OL' frame is enlarged to form an OL'', that is, the even line pixels of the OL'' frame are filled with the OL' current line pixel order, and the odd line pixels of the OL'' frame and the upstream and downstream pixels of the current line of the OL' frame
  • the value, as well as the pixel value of the current line of the EL' and EL+1' frames adjacent to OL', is obtained by comprehensive interpolation.
  • the specific process is:
  • the pixel value of the OL' frame is OL'ab
  • the pixel value of the OL'' frame is OL''pq, where a is 1 to 1080, b is 1 to 1920, a is p to 2160, and q is 1 to 1920.
  • the values of OL'(a-1)b, OL'(a+1)b, EL'ab, and EL+1'ab are known values.
  • K5, k6, k7, K8 can be obtained according to the method in the prior art, wherein OL' (a-1)b and OL'(a+1)b have a first coefficient of k5 and a second coefficient of k6.
  • the similarity correlation value of the OL' frame and the EL' frame is K7, and the similarity correlation value of the OL' frame and the EL+1' frame is k8.
  • OR'' of the OR' frame is enlarged to form an OR'' and the OL' frame is enlarged and enlarged to form an OL'', which will not be described herein.
  • the EL' of the EL' frame pixel shown in Fig. 8-1 is enlarged by interpolation.
  • the frame pixel diagram is shown in Figure 9-1
  • the ER' frame pixel shown in Figure 8-2 is enlarged by interpolation.
  • the frame pixel diagram is shown in Figure 9-2.
  • the OL' frame pixel shown in Figure 8-3 is enlarged by interpolation.
  • the frame pixel diagram is shown in Figure 9-3.
  • the OR'' frame pixel formed by the OR' frame pixel shown in Figure 8-4 is enlarged as shown in Figure 9-4.
  • the frame merging unit 32 performs frame merging processing on the input 2K ⁇ 2K@60 Hz signal to obtain a 4K ⁇ 2K@30 Hz target signal, and the frame merging method is: setting the odd frame of the 4K ⁇ 2K@30 Hz target signal as the ME frame.
  • the even frame is an MO frame.
  • the frame merging unit 32 fills the pixels of the EL'' frame in the left half of the ME frame and continues to receive the ER'' frame; after receiving the ER'' frame, the ER'' frame is The pixels are filled in the right half of the ME frame; that is, the ME frame is formed.
  • the frame merging unit 32 continues to receive the OL'' frame.
  • the frequency of the ME, MO series frame signals formed by the frame combining unit 32 is half of the input frame rate, that is, 30 Hz.
  • EL'’ shown in Figure 9-1 The frame pixel is shown and the ER’’ shown in Figure 9-2
  • the schematic diagram of the ME frame pixel formed by the combined processing of the frame image is shown in Figure 10-1.
  • the OL'' frame pixel shown in Figure 9-3 and the OR'' frame image shown in Figure 9-4 are combined.
  • a schematic diagram of the formed MO frame pixel is shown in Figure 10-2.
  • 4K ⁇ 2K is 3840 ⁇ 2160, that is, 2160 lines, 3840 pixels per line
  • 4K ⁇ 1K is 3840 ⁇ 1080, ie 1080 lines, 3840 pixels per line
  • 2K ⁇ 1K is 1920 ⁇ 1080, ie 1080 lines, 1920 lines per line.
  • the pixel, 2K ⁇ 2K, is 1920 ⁇ 2160, that is, 2160 lines, and 1920 pixels per line.
  • the present invention also discloses an ultra high definition television set.
  • the ultra high definition television set includes a format judging device 6, a super high definition display control device 7, an ultra high definition screen 8, a storage module 5 and a control module 4.
  • the format determining device 6 is configured to determine whether the input signal is a 4K ⁇ 2K signal, and if it is determined that the input signal is a 4K ⁇ 2K signal, output the 4K ⁇ 2K signal to the control of the ultra high definition display.
  • the control device 7 of the ultra-high-definition display is configured to control the ultra-high-definition television to enable the ultra-high-definition display, and the control device for the ultra-high-definition display in any of the above embodiments may be specifically referred to any of the above embodiments.
  • the description of the control device of the ultra high definition display will not be repeated here;
  • the ultra high definition screen 8 is used for displaying the 4K ⁇ 2K signal output by the control device of the ultra high definition display in the ultra high definition;
  • the storage module 5 is used for the storage format determination device. 6 and various data input and output by the control device 7 such as the ultra high definition display;
  • the control module 4, the control device 7 for controlling the storage format judging device 6, the ultra high definition display, and the ultra high definition screen 8 perform corresponding operations.
  • the ultra high definition television set in this embodiment further includes a frequency multiplication frame insertion device 9 for performing frame insertion and frequency multiplication processing on the 4K ⁇ 2K@30Hz target signal output by the ultra high definition display control device 7 and
  • the ultra high definition screen 8 outputs 4K ⁇ 2K@60Hz signal to drive the ultra high definition screen 8 to realize ultra high definition display.
  • the ultra-high definition television disclosed in the present invention can realize ultra-high definition display on the source of 4K ⁇ 2K signals, and can avoid loss of vertical information of the image and sudden change of images, and can prevent image blurring and edges.
  • the appearance of sawtooth can effectively improve the display quality of the image.

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Abstract

本发明提供了一种超高清显示的控制方法及装置、超高清电视机，其中超高清显示的控制方法包括以下步骤：将接收的4K×2K信号分解成2K×1K过渡信号；对所述2K×1K过渡信号进行解码处理，以获得2K×1K屏显信号；将所述2K×1K屏显信号转换成4K×2K目标信号以提供给超高清屏实现超高清显示。对于4K×2K信号的片源，本发明通过将其分解成2K×1K过渡信号以便于传统的电视芯片进行解码处理以获得2K×1K的屏显信号，并通过将解码处理后的2K×1K屏显信号合成4K×2K目标信号，以达到超高清屏对超高清信号实现超高清显示的目的。

Description

超高清显示的控制方法及装置、超高清电视机
技术领域
　　　本发明涉及显示技术领域，特别涉及到一种超高清显示的控制方法及装置、超高清电视机。　　　
背景技术
　　　超高清电视（UHDTV）即像素数目达3840×2160（4K×2K）或7680×4320（8K×4K）的电视，相比全高清电视（FHDTV）1920×1080（2K×1K）的像素数目，其像素数目提高了4倍或16倍，因此其图像表现非常清晰、细腻。在ITU-R制定的超高清电视标准中包括4K×2K标准和8K×4K标准，而4K×2K UHDTV较8K×4K UHDTV更容易实现和普及，是目前电视行业关注和发展的热点和方向。
　　　目前的超高清电视主要是接收2K×1K信号，经过解码、图像画质处理后通过放大处理来驱动超高清屏，实现超高清显示；而对于4K×2K信号需要通过专门的仪器和手段转换成2K×1K，成本高、操作复杂、稳定可靠性低，且存在显示的图像失真、模糊等缺陷。即现有技术中存在的问题为：现有的超高清电视因其电视芯片是针对全高清信号设计的，当片源是4K×2K的信号时，其超高清屏无法对超高清信号实现超高清显示。　　　
发明内容
　　　本发明的主要目的是提供一种超高清显示的控制方法，旨在使超高清屏对超高清信号实现超高清显示。
　　　本发明实施例公开了一种超高清显示的控制方法，包括以下步骤：
　　　将接收的4K×2K信号分解成2K×1K过渡信号；
　　　对所述2K×1K过渡信号进行解码处理，以获得2K×1K屏显信号；
　　　将所述2K×1K屏显信号转换成4K×2K目标信号以提供给超高清屏实现超高清显示。
　　　优选地，所述将接收的4K×2K信号分解成2K×1K过渡信号的具体步骤包括：
　　　识别所接收的4K×2K信号的频率；
　　　当所接收的4K×2K信号的频率属于第一频率组时，对所接收的4K×2K信号进行帧像素的压缩以获得4K×1K信号；
　　　当所接收的4K×2K信号的频率属于第二频率组时，在对所接收的4K×2K信号进行帧像素的压缩以前还包括对所接收的4K×2K信号进行帧抽取步骤，以将所接收的4K×2K信号的频率转换至所述第一频率组；
　　　对所述4K×1K信号进行帧像素的分割以获得2K×1K过渡信号；
　　　其中第一频率组包括24Hz、25Hz和30Hz，第二频率组包括50Hz、59.94Hz和60Hz。
　　　优选地，对频率属于所述第一频率组的所接收的4K×2K信号进行帧抽取的方式为隔帧抽取。
　　　优选地，对所接收的4K×2K信号进行帧像素压缩的方式为隔行去除像素。
　　　优选地，对所述4K×1K信号进行帧像素分割的方式为左右分割。
　　　优选地，所述将所述2K×1K屏显信号转换成4K×2K目标信号的具体步骤包括：
　　　对所述2K×1K屏显信号进行插行放大处理以获取2K×2K信号；
　　　对所述2K×2K信号进行帧合并处理以获取4K×2K目标信号。
　　　优选地，所述对所述2K×1K屏显信号进行插行放大处理以获取2K×2K信号所采用的插行公式为：
　　　所述2K×2K信号的奇数帧的像素为E（L/R）’ ’pq，所述2K×1K屏显信号的奇数帧的当前行的像素为E（L/R）’ab，所述2K×1K屏显信号的奇数帧的上行的像素为E（L/R）’（a-1）b，所述2K×1K屏显信号的奇数帧的下行的像素为E（L/R）’（a+1）b，与所述2K×1K屏显信号的奇数帧对应的偶数帧的当前行的像素为O（L/R）’ab，与所述2K×1K屏显信号的奇数帧相邻的前偶数帧的当前行的像素为O（L/R）－1’ab；当p为奇数时，E（L/R）’ ’pq=E（L/R）’ab，其中p=2a-1，q=b；当p为偶数时，E（L/R）’ ’pq=k1* E（L/R）’（a-1）b+ k2*E（L/R）’（a+1）b+ K3* O（L/R）’ab+k4* O（L/R）－1’ab；其中p＝2a，q＝b，E（L/R）’（a-1）b和E（L/R）’（a+1）b的第一系数为k1、其第二系数为k2，E（L/R）’帧和O（L/R）’帧的相似度关联值为K3，E（L/R）’帧和O（L/R）－1’帧的相似度关联值为k4；
　　　所述2K×2K信号的偶数帧的像素为O（L/R）’ ’pq，所述2K×1K屏显信号的偶数帧的当前行的像素为O（L/R）’ab，所述2K×1K屏显信号的偶数帧的上行的像素为O（L/R）’（a-1）b，所述2K×1K屏显信号的偶数帧的下行的像素为O（L/R）’（a+1）b，与所述2K×1K屏显信号的偶数帧对应的奇数帧的当前行的像素为E（L/R）’ab，与所述2K×1K屏显信号的偶数帧相邻的后奇数帧的当前行的像素为E（L/R）+1’ab；当p为偶数时，O（L/R）’ ’pq=O（L/R）’ab，其中p=2a，q=b；当p为奇数时，O（L/R）’ ’pq=k5* O（L/R）’（a-1）b+ k6*O（L/R）’（a+1）b+ K7* E（L/R）’ab+k8* E（L/R）+1’ab；其中p＝2a-1，q＝b，O（L/R）’ （a-1）b和O（L/R）’（a+1）b的第一系数为k5、其第二系数为k6， O（L/R）’帧和E（L/R）’帧的相似度关联值为K7，O（L/R）’帧和E（L/R）+1’帧的相似度关联值为k8。　　　
　　　本发明实施例还公开了一种超高清显示的控制装置，包括：
　　　帧分解模块，用于将接收的4K×2K信号分解成2K×1K过渡信号；
　　　帧解码模块，用于对所述2K×1K过渡信号进行解码处理，以获得2K×1K屏显信号；
　　　以及帧合成模块，用于将所述2K×1K屏显信号转换成4K×2K目标信号以提供给超高清屏显示。
　　　优选地，所述帧分解模块包括：
　　　频率识别单元，用于识别所接收的4K×2K信号的频率；
　　　帧抽取单元，当所接收的4K×2K信号的频率被所述频率识别单元识别为属于第二频率组时，用于对所接收的4K×2K信号进行帧抽取，以将所接收的4K×2K信号的频率转换至所述第一频率组；
　　　帧像素压缩单元，当所接收的4K×2K信号的频率被所述频率识别单元识别为属于第一频率组或被所述帧抽取单元转换至第一频率组时，用于对所接收的4K×2K信号进行帧像素的压缩以获得4K×1K信号；
　　　以及帧像素分割单元，用于对所述4K×1K信号进行帧像素的分割以获得2K×1K过渡信号；
　　　其中第一频率组包括24Hz、25Hz和30Hz，第二频率组包括50Hz、59.94Hz和60Hz。
　　　优选地，所述帧合成模块包括：
　　　帧像素放大单元，用于对所述2K×1K屏显信号进行插行放大处理以获取2K×2K信号；
　　　以及帧合并单元，用于对所述2K×2K信号进行帧合并处理以获取4K×2K目标信号。　　　
　　　本发明实施例还公开了一种超高清电视机，包括格式判断装置、超高清显示的控制装置和超高清屏；
　　　所述格式判断装置，用于判断所输入的信号是否为4K×2K信号，若判断所输入的信号是4K×2K信号，则将所述4K×2K信号输出至所述超高清显示的控制装置；
　　　所述超高清显示的控制装置，为上述任一技术方案中的所述的超高清显示的控制装置，用于控制所述超高清电视机能够实现超高清显示；
　　　所述超高清屏，用于超高清显示所述超高清显示的控制装置输出的4K×2K信号。　　　
　　　本发明所公开的超高清显示的控制方法，通过将接收的4K×2K信号分解成2K×1K过渡信号；进而针对全高清（2K×1K）信号设计的电视芯片可对2K×1K过渡信号进行解码处理，以获得解码、画质处理后的2K×1K屏显信号；最后将该2K×1K屏显信号转换成4K×2K目标信号。即对于4K×2K信号的片源，本发明通过将其分解成2K×1K过渡信号以便于传统的电视芯片进行解码处理以获得2K×1K的屏显信号，并通过将解码处理后的2K×1K屏显信号合成4K×2K目标信号，以达到超高清屏对超高清信号实现超高清显示的目的。　　　
附图说明
　　　图1为本发明优选实施方式中超高清显示的控制方法的流程示意图；
　　　图2为本发明超高清显示的控制方法的优选实施例中将接收的4K×2K信号分解成2K×1K过渡信号的流程示意图；
　　　图3为本发明超高清显示的控制方法的优选实施例中将所述2K×1K屏显信号转换成4K×2K目标信号的流程示意图；
　　　图4为本发明优选实施方式中超高清显示的控制装置的结构示意图；
　　　图5-1为本发明中的4K×2K@30Hz信号中奇数帧像素（6×6个像素）示意图；
　　　图5-2为本发明中的4K×2K@30Hz信号中偶数帧像素（6×6个像素）示意图；
　　　图6-1为图5-1所示的E帧像素经压缩后形成的E’帧像素示意图；
　　　图6-2为图5-2所示的O帧像素经压缩后形成的O’帧像素示意图；
　　　图7-1为图6-1所示的E’帧像素经分割后形成的E’L帧像素示意图；
　　　图7-2为图6-1所示的E’帧像素经分割后形成的E’R帧像素示意图；
　　　图7-3为图6-2所示的O’帧像素经分割后形成的O’L帧像素示意图；
　　　图7-4为图6-2所示的O’帧像素经分割后形成的O’R帧像素示意图；
　　　图8-1为图7-1所示的E’L帧像素经图像解码及图像处理后形成的EL’帧像素示意图；
　　　图8-2为图7-2所示的E’R帧像素经图像解码及图像处理后形成的ER’帧像素示意图；
　　　图8-3为图7-3所示的O’L帧像素经图像解码及图像处理后形成的OL’帧像素示意图；
　　　图8-4为图7-4所示的O’R帧像素经图像解码及图像处理后形成的OR’帧像素示意图；
　　　图9-1为图8-1所示的EL’帧像素经插行放大处理后形成的EL’’ 帧像素示意图；
　　　图9-2为图8-2所示的ER’帧像素经插行放大处理后形成的ER’’ 帧像素示意图；
　　　图9-3为图8-3所示的OL’帧像素经插行放大处理后形成的OL’’ 帧像素示意图；
　　　图9-4为图8-4所示的OR’帧像素经插行放大处理后形成的OR’’帧像素示意图；
　　　图10-1为图9-1所示的EL’’ 帧像素示和图9-2所示的ER’’ 帧像经合并处理后形成的ME帧像素示意图；
　　　图10-2为图9-3所示的OL’’帧像素示和图9-4所示的OR’’帧像经合并处理后形成的MO帧像素示意；
　　　图11为本发明优选实施方式中超高清电视机的结构示意图。　　　
　　　本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。　　　
具体实施方式
　　　应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
　　　本发明公开了一种超高清显示的控制方法，参照图1，在该实施方式中超高清显示的控制方法包括以下步骤：
　　　步骤S01，将接收的4K×2K信号分解成2K×1K过渡信号。
　　　通过将接收的4K×2K信号分解成2K×1K过渡信号可满足目前电视解码及图像处理时对信号格式的要求。
　　　步骤S02，对所述2K×1K过渡信号进行解码处理，以获得2K×1K屏显信号。
　　　步骤S03，将所述2K×1K屏显信号转换成4K×2K目标信号以提供给超高清屏实现超高清显示。
　　　通过将所述2K×1K屏显信号转换成4K×2K目标信号，能够驱动超高清（UHD）屏实现超高清显示，且可避免图像的突变，即能够防止图像模糊及边缘锯齿的出现，有效提高了图像的显示质量。
　　　对于4K×2K信号的片源，本发明通过将其分解成2K×1K过渡信号以便于传统的电视芯片进行解码处理以获得2K×1K屏显信号，并通过将解码处理后的2K×1K屏显信号合成4K×2K目标信号，以达到超高清屏对超高清信号实现超高清显示的目的。
　　　在具体实施例中，参照图2，将接收的4K×2K信号分解成2K×1K过渡信号的具体步骤包括：
　　　步骤S11，识别所接收的4K×2K信号的频率；当所接收的4K×2K信号的频率被识别为属于第一频率组时，执行步骤S13；当所接收的4K×2K信号的频率被识别为属于第二频率组时，执行步骤S12。其中第一频率组包括24Hz、25Hz和30Hz，第二频率组包括50Hz、59.94Hz和60Hz。
　　　步骤S12，对所接收的4K×2K信号进行帧抽取，以将所接收的4K×2K信号的频率转换至所述第一频率组，再执行步骤S13。
　　　步骤S13，对所接收的4K×2K信号进行帧像素的压缩以获得4K×1K信号。
　　　步骤S14，对所述4K×1K信号进行帧像素的分割以获得2K×1K过渡信号。
　　　作为优选的实施例，对频率属于所述第一频率组的所接收的4K×2K信号进行帧抽取的方式为隔帧抽取。如：当所接收的4K×2K信号为4K×2K@60Hz时，则抽取4K×2K@60Hz信号的奇数帧或偶数帧，形成4K×2K@30Hz信号以便后续进行帧像素压缩。当所接收的4K×2K信号为4K×2K@30Hz时，则不进行帧抽取，直接进行后续的帧像素压缩。当然进行帧抽取不限于上述方式，如可以是连续抽取，具体地，当所接收的4K×2K信号为4K×2K@50Hz时，可以连续抽取数帧以形成4K×2K@30Hz信号或形成4K×2K@25Hz信号。
　　　作为优选的实施例，对所接收的4K×2K信号进行帧像素压缩的方式为隔行去除像素。如对4K×2K@30Hz信号进行帧像素压缩处理，保留奇数帧（E帧）的偶数行而去除其奇数行形成E’帧及保留偶数帧（O帧）的奇数行而去除其偶数行形成O’帧，其中E’帧的各行像素值为E帧的奇数行像素值， O’帧的各行像素值为O帧的偶数行像素值，即4K×2K@30Hz信号进行帧像素压缩处理后形成了4K×1K@30Hz信号。再如保留奇数帧（E帧）的奇数行而去除其偶数行及保留偶数帧（O帧）的偶数行而去除其奇数行，当然不限于上述两种方式。同时可以理解的是进行帧像素压缩的方式也不限于隔行去除像素。通过采用隔行去除像素的方式可避免图像垂直方向信息的丢失。
　　　作为优选的实施例，对所述4K×1K信号进行帧像素分割的方式为左右分割。如对4K×1K@30Hz信号进行帧像素分割处理，将4K×1K@30Hz信号的E’帧分割成左右两半形成左半奇数帧（E’L帧）和右半奇数帧（E’R帧），将4K×1K@30Hz信号的O’帧分割成左右两半形成（O’L帧）和（O’R帧），即4K×1K@30Hz信号进行帧像素分割处理后形成了2K×1K@60Hz信号。当然进行帧像素分割不限于上述方式，如可以是上下分割。
　　　可以理解的是，对所述2K×1K过渡信号进行解码处理具体包括对所述2K×1K过渡信号进行图像解码和图像处理部分步骤，该处的操作传统电视机芯片可完成，在此不再赘述。
　　　在具体实施例中，参照图3，将所述2K×1K屏显信号转换成4K×2K目标信号的具体步骤包括：
　　　步骤S21，对所述2K×1K屏显信号进行插行放大处理以获取2K×2K信号。
　　　步骤S22，对所述2K×2K信号进行帧合并处理以获取4K×2K目标信号。
　　　作为优选的实施例，对所述2K×1K屏显信号进行插行放大处理以获取2K×2K信号所采用的插行算法为：
　　　作如下定义：2K×2K信号的奇数帧的像素为E（L/R）’ ’pq，2K×1K屏显信号的奇数帧的当前行的像素为E（L/R）’ab，2K×1K屏显信号的奇数帧的上行的像素为E（L/R）’（a-1）b，2K×1K屏显信号的奇数帧的下行的像素为E（L/R）’（a+1）b，与2K×1K屏显信号的奇数帧对应的偶数帧的当前行的像素为O（L/R）’ab，与2K×1K屏显信号的奇数帧相邻的前偶数帧的当前行的像素为O（L/R）－1’ab；
　　　当p为奇数时，E（L/R）’ ’pq=E（L/R）’ab，其中p=2a-1，q=b；
　　　当p为偶数时，E（L/R）’ ’pq=k1* E（L/R）’（a-1）b+ k2*E（L/R）’（a+1）b+ K3* O（L/R）’ab+k4* O（L/R）－1’ab；其中p＝2a，q＝b，E（L/R）’（a-1）b和E（L/R）’（a+1）b的第一系数为k1、其第二系数为k2，E（L/R）’帧和O（L/R）’帧的相似度关联值为K3，E（L/R）’帧和O（L/R）－1’帧的相似度关联值为k4。
　　　并作如下定义：2K×2K信号的偶数帧的像素为O（L/R）’ ’pq，2K×1K屏显信号的偶数帧的当前行的像素为O（L/R）’ab，2K×1K屏显信号的偶数帧的上行的像素为O（L/R）’（a-1）b，2K×1K屏显信号的偶数帧的下行的像素为O（L/R）’（a+1）b，与2K×1K屏显信号的偶数帧对应的奇数帧的当前行的像素为E（L/R）’ab，与2K×1K屏显信号的偶数帧相邻的后奇数帧的当前行的像素为E（L/R）+1’ab；
　　　当p为偶数时，O（L/R）’ ’pq=O（L/R）’ab，其中p=2a，q=b；
　　　当p为奇数时，O（L/R）’ ’pq=k5* O（L/R）’（a-1）b+ k6*O（L/R）’（a+1）b+ K7* E（L/R）’ab+k8* E（L/R）+1’ab；其中p＝2a-1，q＝b，O（L/R）’ （a-1）b和O（L/R）’（a+1）b的第一系数为k5、其第二系数为k6， O（L/R）’帧和E（L/R）’帧的相似度关联值为K7，O（L/R）’帧和E（L/R）+1’帧的相似度关联值为k8。
　　　当上述对所述4K×1K信号进行帧像素分割的方式为左右分割，则对所述2K×2K信号进行帧合并处理以获取4K×2K目标信号的方式为左右合并。　　　
　　　本发明公开了一种超高清显示的控制装置，该超高清显示的控制装置与上述任一实施例中的超高清显示的控制方法均可对应，具体地，可参照图4，在该实施方式中超高清显示的控制装置包括帧分解模块1、帧解码模块2和帧合成模块3。其中帧分解模块1，用于将接收的4K×2K信号分解成2K×1K过渡信号，通过帧分解模块1将接收的4K×2K信号分解成2K×1K过渡信号可满足目前电视解码及图像处理时对信号格式的要求。帧解码模块2，用于对所述2K×1K过渡信号进行解码处理，以获得超高清屏2K×1K屏显信号。帧合成模块3，用于将所述2K×1K屏显信号转换成4K×2K目标信号以提供给超高清屏显示，通过帧合成模块3将所述2K×1K屏显信号转换成4K×2K目标信号，能够驱动超高清（UHD）屏实现超高清显示，且可避免图像的突变，即能够防止图像模糊及边缘锯齿的出现，有效提高了图像的显示质量。
　　　对于4K×2K信号的片源，本发明通过帧分解模块1将其分解成2K×1K过渡信号以便于传统的电视芯片（对应本发明中的帧解码模块2）进行解码处理并获得2K×1K屏显信号，进而通过帧合成模块3将解码处理后的2K×1K屏显信号合成4K×2K目标信号，以达到超高清屏对超高清信号实现超高清显示的目的。
　　　再次参照图4，在具体实施例中，帧分解模块1包括频率识别单元11、帧抽取单元12、帧像素压缩单元13和帧像素分割单元14 。其中频率识别单元11，用于识别所接收的4K×2K信号的频率；帧抽取单元12，当所接收的4K×2K信号的频率被所述频率识别单元识别为属于第二频率组时，用于对所接收的4K×2K信号进行帧抽取，以将所接收的4K×2K信号的频率转换至所述第一频率组；帧像素压缩单元13，当所接收的4K×2K信号的频率被所述频率识别单元识别为属于或被所述帧抽取单元转换至第一频率组时，用于对所接收的4K×2K信号进行帧像素的压缩以获得4K×1K信号；帧像素分割单元14，用于对所述4K×1K信号进行帧像素的分割以获得2K×1K过渡信号；其中第一频率组包括24Hz、25Hz和30Hz，第二频率组包括50Hz、59.94Hz和60Hz。
　　　再次参照图4，在具体实施例中，帧合成模块3包括帧像素放大单元31和帧合并单元32，其中帧像素放大单元31，用于对所述2K×1K屏显信号进行插行放大处理以获取2K×2K信号；帧合并单元32，用于对所述2K×2K信号进行帧合并处理以获取4K×2K目标信号。
　　　可以理解的是，对于上述任一实施例中的超高清显示的控制装置，其可设置独立的控制模块4和存储模块5，控制模块4用于控制帧分解模块1、帧解码模块2和帧合成模块3进行相应操作，存储模块5用于存储帧分解模块1、帧解码模块2和帧合成模块3中所输入或输出的各种数据。　　　
　　　为了使本发明的目的、技术方案及优点更加清楚明白，以下以输入信号4K×2K@30Hz和4K×2K@60Hz为例对本发明中超高清显示的控制方法及装置进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
　　　1、当所接收的4K×2K信号的频率被频率识别单元11识别为4K×2K@60Hz时，该4K×2K@60Hz信号被传输至帧抽取单元12；当所接收的4K×2K信号的频率被频率识别单元11识别为4K×2K@30Hz时，该4K×2K@30Hz信号被传输至帧像素压缩单元13。
　　　2、帧抽取单元12对输入的4K×2K@60Hz信号以隔帧抽取的方式进行帧抽取以获取4K×2K@30Hz信号。以抽取4K×2K@60Hz信号的奇数帧为例，帧抽取方法为：当接收的4K×2K@60Hz信号为奇数帧时，控制帧抽取单元12让奇数帧输出给帧像素压缩单元13；当接收的4K×2K@60Hz信号为偶数帧时，控制帧抽取单元12让偶数帧不能输出给帧像素压缩单元13。最终帧抽取单元12所接收的4K×2K@60Hz信号每一场的60帧中只有30帧的奇数帧输出给帧像素压缩单元13，即帧像素压缩单元13接收的新的4K×2K@30Hz信号。
　　　帧像素压缩单元13所接收的4K×2K@30Hz信号中奇数帧（E帧）像素（以6×6个像素为例）示意图如图5-1所示，其偶数帧（O帧）像素（以6×6个像素为例）示意图如图5-2所示。
　　　3、帧像素压缩单元13对输入的4K×2K@30Hz信号以隔行去除像素的方式进行帧像素压缩以获取4K×1K@30Hz信号。帧像素压缩方法为：
　　　设帧像素压缩单元13接收的4K×2K@30Hz信号的E帧的像素值为Eij、O帧的像素值为Oij，i为1～2160、j为3840。
　　　对E帧进行帧像素压缩处理，保留E帧的奇数行像素而忽略E帧的偶数行像素，形成了E’ 帧，E’ 帧为4K×1K（3840×1080）帧；对O帧进行帧像素压缩处理，保留O帧的偶数行像素而忽略O帧的奇数行像素，形成了O’ 帧，O’ 帧为4K×1K（3840×1080）帧。
　　　再设E’帧的像素值为E’mn、O’帧的像素值为O’mn，m为1～1080、n为3840。则：
　　　E’mn＝Eij，其中n＝j，2m＝i＋1；即E’帧各行像素值为E帧的奇数行像素值。
　　　O’mn＝Oij，其中n＝j，2m＝i；即O’帧各行像素值为O帧的奇数行像素值。
　　　即帧像素压缩单元13处理后输出的4K×1K@30Hz信号是由E’帧和O’帧组成的系列帧，且E’帧各行像素值为输入信号的E帧的奇数行像素值， O’帧各行像素值为输入信号的O帧的偶数行像素值。其中图5-1所示的E帧像素经压缩后形成的E’帧像素示意图如图6-1所示，图5-2所示的O帧像素经压缩后形成的O’帧像素示意图如图6-2所示。
　　　4、帧像素分割单元14对输入的4K×1K@30Hz信号以左右分割的方式进行帧像素分割以获取2K×1K@60Hz信号，并将2K×1K@60Hz信号输出给帧解码模块2。帧像素分割方法为：对E’帧进行帧像素处理，获取E’帧左半部分像素形成E’L帧，获取E’帧右半部分像素形成E’R帧；同样对O’帧进行帧像素处理，获取O’帧左半部分像素形成O’L帧，获取O’帧右半部分像素形成O’R帧。E’L、E’R、O’L、O’R帧为2K×1K（1920×1080）帧。分割后形成的E’L、E’R、O’L、O’R系列帧信号的频率为输入帧频的2倍，即60Hz。其中图6-1所示的E’帧像素经分割后形成的E’L帧像素示意图如图7-1所示，图6-1所示的E’帧像素经分割后形成的E’R帧像素示意图如图7-2所示，图6-2所示的O’帧像素经分割后形成的O’L帧像素示意图如图7-3所示，图6-2所示的O’帧像素经分割后形成的O’R帧像素示意图如图7-4所示。
　　　5、帧解码模块2包括图像解码单元21和图像处理单元22，接收帧像素分割单元14输出的2K×1K@60Hz信号后对其进行图像解码及图像处理后、向帧合成模块3输出经图像解码和处理后的2K×1K@60Hz屏显信号，其中图像处理包括去隔行、降噪、亮度增强等画质处理。
　　　即帧解码模块2对输入的E’L、E’R、O’L、O’R系列帧进行图像解码及图像处理后，形成EL’、ER’、OL’、OR’系列帧，并向帧合成模块3输出由EL’、ER’、OL’、OR’系列帧组成的2K×1K@60Hz信号。其中图7-1所示的E’L帧像素经图像解码及图像处理后形成的EL’帧像素示意图如图8-1所示，图7-2所示的E’R帧像素经图像解码及图像处理后形成的ER’帧像素示意图如图8-2所示，图7-3所示的O’L帧像素经图像解码及图像处理后形成的OL’帧像素示意图如图8-3所示，图7-4所示的O’R帧像素经图像解码及图像处理后形成的OR’帧像素示意图如图8-4所示。
　　　6、帧像素放大单元31对输入的2K×1K@60Hz信号进行插行放大处理以获取2K×2K@60Hz信号，并将2K×2K@60Hz信号输出给帧合并单元32。帧插行放大的方法为：
　　　帧像素放大单元31接收到连续的OL－1’帧、OR－1’帧、EL’帧、ER’帧、OL’帧、OR’帧、 EL+1’帧、ER+1’帧。
　　　对EL’帧插行放大形成EL’’，即EL’’帧的奇数行像素用EL’当前行像素顺序填充，而EL’’帧的偶数行像素与EL’帧当前行的上行和下行像素值、以及和EL’相邻的OL’和OL－1’帧当前行的像素值相关，通过综合插值来得出。具体过程为：
　　　设EL’帧的像素值为EL’ab、EL’’帧的像素值为EL’’pq，其中a为1～1080、b为1～1920，a为p～2160、q为1～1920。
　　　当p为奇数时：EL’’ pq ＝EL’ ab；其中p＝2a－1、q＝b。
　　　当p为偶数时：EL’’ pq=k1* EL’ （a-1）b + k2*EL’(a+1)b+K3* OL’ab+k4* OL－1’ab；其中p＝2a、q＝b。EL’（a-1）b、EL’(a+1)b、OL’ab、OL－1’ab的值为已知值。k1、k2、k3、K4可按照现有技术中的方法得出，其中EL’（a-1）b和EL’（a+1）b的第一系数为k1、其第二系数为k2，EL’帧和OL’帧的相似度关联值为K3，EL’帧和OL－1’帧的相似度关联值为k4。
　　　对ER’帧插行放大形成ER’’与对EL’帧插行放大形成EL’’过程一样，在此不再赘述。
　　　对OL’帧插行放大形成OL’’，即OL’’帧的偶数行像素用OL’当前行像素顺序填充，而OL’’帧的奇数行像素与OL’帧当前行的上行和下行像素值、以及和OL’相邻的EL’和EL+1’帧当前行的像素值相关，通过综合插值来得出。具体过程为：
　　　设OL’帧的像素值为OL’ab、OL’’帧的像素值为OL’’pq，其中a为1～1080、b为1～1920，a为p～2160、q为1～1920。
　　　当p为奇数时：OL’’ pq=k5* OL’ （a-1）b + k6*OL’(a+1)b+K7* EL’ab+k8* EL+1’ab；其中p＝2a－1、q＝b。OL’（a-1）b、OL’(a+1)b、EL’ab、EL+1’ab的值为已知值。k5、k6、k7、K8可按照现有技术中的方法得出，其中OL’ （a-1）b和OL’（a+1）b的第一系数为k5、其第二系数为k6， OL’帧和EL’帧的相似度关联值为K7，OL’帧和EL+1’帧的相似度关联值为k8。
　　　当p为偶数时：OL’’ pq ＝OL’ ab；其中p＝2a、q＝b。
　　　对OR’帧插行放大形成OR’’与对OL’帧插行放大形成OL’’过程一样，在此不再赘述。
　　　其中图8-1所示的EL’帧像素经插行放大处理后形成的EL’’ 帧像素示意图如图9-1所示，图8-2所示的ER’帧像素经插行放大处理后形成的ER’’ 帧像素示意图如图9-2所示，图8-3所示的OL’帧像素经插行放大处理后形成的OL’’ 帧像素示意图如图9-3所示，图8-4所示的OR’帧像素经插行放大处理后形成的OR’’帧像素示意图如图9-4所示。
　　　7、帧合并单元32对输入的2K×2K@60Hz信号进行帧合并处理以获取4K×2K@30Hz目标信号，帧合并的方法为：设4K×2K@30Hz目标信号的奇数帧为ME帧，偶数帧为MO帧。帧合并单元32接收到EL’’帧后，将EL’’帧的像素填充在ME帧的左半部分、并继续接收ER’’帧；接收到ER’’帧后，将ER’’帧的像素填充在ME帧的右半部分；即形成了ME帧。帧合并单元32继续接收OL’’帧，接收到OL’’帧后，将OL’’帧的像素填充在MO帧的左半部分、并继续接收OR’’； 接收到OR’’帧后，将OR’’帧的像素填充在MO帧的右半部分即形成了MO帧。继续循环上述过程直至完成所有帧的合并。帧合并单元32形成的ME、MO系列帧信号的频率为输入帧频的一半，即30Hz。其中，图9-1所示的EL’’ 帧像素示和图9-2所示的ER’’ 帧像经合并处理后形成的ME帧像素示意图如图10-1所示，图9-3所示的OL’’帧像素示和图9-4所示的OR’’帧像经合并处理后形成的MO帧像素示意图如图10-2所示。
　　　上述4K×2K为3840×2160即2160行、每行3840个像素，4K×1K为3840×1080即1080行、每行3840个像素，2K×1K为1920×1080即1080行、每行1920个像素，2K×2K为1920×2160即2160行、每行1920个像素。　　　
　　　本发明还公开了一种超高清电视机，参照图11，在该实施方式中超高清电视机包括格式判断装置6、超高清显示的控制装置7、超高清屏8、存储模块5和控制模块4。其中，格式判断装置6，用于判断所输入的信号是否为4K×2K信号，若判断所输入的信号是4K×2K信号，则将所述4K×2K信号输出至所述超高清显示的控制装置7；超高清显示的控制装置7，用于控制所述超高清电视机能够实现超高清显示，为上述任一实施例中的超高清显示的控制装置，具体可参照上述任一实施例对超高清显示的控制装置的描述，在此不再赘述；超高清屏8，用于超高清显示所述超高清显示的控制装置输出的4K×2K信号；存储模块5，用于存储格式判断装置6和超高清显示的控制装置7等其他装置所输入和输出的各项数据；控制模块4，用于控制存储格式判断装置6、超高清显示的控制装置7和超高清屏8执行相应操作。
　　　进一步地，本实施例中的超高清电视机还包括倍频插帧装置9，用于对超高清显示的控制装置7输出的4K×2K@30Hz目标信号进行插帧、倍频处理，并向超高清屏8输出4K×2K@60Hz信号以驱动超高清屏8实现超高清显示。
　　　综上所述可知，本发明所公开的超高清电视机，能够对4K×2K信号的片源实现超高清显示，且可避免图像垂直方向信息的丢失及图像的突变，能够防止图像模糊及边缘锯齿的出现，可有效提高图像的显示质量。　　　
　　　以上所述仅为本发明的优选实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种超高清显示的控制方法，其特征在于，包括以下步骤：
    　　　将接收的4K×2K信号分解成2K×1K过渡信号；
    　　　对所述2K×1K过渡信号进行解码处理，以获得2K×1K屏显信号；
    　　　将所述2K×1K屏显信号转换成4K×2K目标信号以提供给超高清屏实现超高清显示。
  2. 根据权利要求1所述的超高清显示的控制方法，其特征在于，所述将接收的4K×2K信号分解成2K×1K过渡信号的具体步骤包括：
    　　　识别所接收的4K×2K信号的频率；
    　　　当所接收的4K×2K信号的频率属于第一频率组时，对所接收的4K×2K信号进行帧像素的压缩以获得4K×1K信号；
    　　　当所接收的4K×2K信号的频率属于第二频率组时，在对所接收的4K×2K信号进行帧像素的压缩以前还包括对所接收的4K×2K信号进行帧抽取步骤，以将所接收的4K×2K信号的频率转换至所述第一频率组；
    　　　对所述4K×1K信号进行帧像素的分割以获得2K×1K过渡信号；
    　　　其中第一频率组包括24Hz、25Hz和30Hz，第二频率组包括50Hz、59.94Hz和60Hz。
  3. 根据权利要求2所述的超高清显示的控制方法，其特征在于，对频率属于所述第一频率组的所接收的4K×2K信号进行帧抽取的方式为隔帧抽取。
  4. 根据权利要求2所述的超高清显示的控制方法，其特征在于，对频率属于所述第一频率组的所接收的4K×2K信号进行帧抽取的方式为连续抽取。
  5. 根据权利要求2所述的超高清显示的控制方法，其特征在于，对所接收的4K×2K信号进行帧像素压缩的方式为隔行去除像素。
  6. 根据权利要求2所述的超高清显示的控制方法，其特征在于，对所述4K×1K信号进行帧像素分割的方式为左右分割。
  7. 根据权利要求2所述的超高清显示的控制方法，其特征在于，对所述4K×1K信号进行帧像素分割的方式为上下分割。
  8. 根据权利要求1所述的超高清显示的控制方法，其特征在于，所述对所述2K×1K过渡信号进行解码处理具体包括对所述2K×1K过渡信号进行图像解码和图像处理。
  9. 根据权利要求1所述的超高清显示的控制方法，其特征在于，所述将所述2K×1K屏显信号转换成4K×2K目标信号的具体步骤包括：
    　　　对所述2K×1K屏显信号进行插行放大处理以获取2K×2K信号；
    　　　对所述2K×2K信号进行帧合并处理以获取4K×2K目标信号。
  10. 根据权利要求9所述的超高清显示的控制方法，其特征在于，所述对所述2K×1K屏显信号进行插行放大处理以获取2K×2K信号所采用的插行公式为：
    　　　所述2K×2K信号的奇数帧的像素为E（L/R）’ ’pq，所述2K×1K屏显信号的奇数帧的当前行的像素为E（L/R）’ab，所述2K×1K屏显信号的奇数帧的上行的像素为E（L/R）’（a-1）b，所述2K×1K屏显信号的奇数帧的下行的像素为E（L/R）’（a+1）b，与所述2K×1K屏显信号的奇数帧对应的偶数帧的当前行的像素为O（L/R）’ab，与所述2K×1K屏显信号的奇数帧相邻的前偶数帧的当前行的像素为O（L/R）－1’ab；当p为奇数时，E（L/R）’ ’pq=E（L/R）’ab，其中p=2a-1，q=b；当p为偶数时，E（L/R）’ ’pq=k1* E（L/R）’（a-1）b+ k2*E（L/R）’（a+1）b+ K3* O（L/R）’ab+k4* O（L/R）－1’ab；其中p＝2a，q＝b，E（L/R）’（a-1）b和E（L/R）’（a+1）b的第一系数为k1、其第二系数为k2，E（L/R）’帧和O（L/R）’帧的相似度关联值为K3，E（L/R）’帧和O（L/R）－1’帧的相似度关联值为k4；
    　　　所述2K×2K信号的偶数帧的像素为O（L/R）’ ’pq，所述2K×1K屏显信号的偶数帧的当前行的像素为O（L/R）’ab，所述2K×1K屏显信号的偶数帧的上行的像素为O（L/R）’（a-1）b，所述2K×1K屏显信号的偶数帧的下行的像素为O（L/R）’（a+1）b，与所述2K×1K屏显信号的偶数帧对应的奇数帧的当前行的像素为E（L/R）’ab，与所述2K×1K屏显信号的偶数帧相邻的后奇数帧的当前行的像素为E（L/R）+1’ab；当p为偶数时，O（L/R）’ ’pq=O（L/R）’ab，其中p=2a，q=b；当p为奇数时，O（L/R）’ ’pq=k5* O（L/R）’（a-1）b+ k6*O（L/R）’（a+1）b+ K7* E（L/R）’ab+k8* E（L/R）+1’ab；其中p＝2a-1，q＝b，O（L/R）’ （a-1）b和O（L/R）’（a+1）b的第一系数为k5、其第二系数为k6， O（L/R）’帧和E（L/R）’帧的相似度关联值为K7，O（L/R）’帧和E（L/R）+1’帧的相似度关联值为k8。
  11. 一种超高清显示的控制装置，其特征在于，包括：
    　　　帧分解模块，用于将接收的4K×2K信号分解成2K×1K过渡信号；
    　　　帧解码模块，用于对所述2K×1K过渡信号进行解码处理，以获得2K×1K屏显信号；
    　　　以及帧合成模块，用于将所述2K×1K屏显信号转换成4K×2K目标信号以提供给超高清屏显示。
  12. 根据权利要求11所述的超高清显示的控制装置，其特征在于，所述帧分解模块包括：
    　　　频率识别单元，用于识别所接收的4K×2K信号的频率；
    　　　帧抽取单元，当所接收的4K×2K信号的频率被所述频率识别单元识别为属于第二频率组时，用于对所接收的4K×2K信号进行帧抽取，以将所接收的4K×2K信号的频率转换至所述第一频率组；
    　　　帧像素压缩单元，当所接收的4K×2K信号的频率被所述频率识别单元识别为属于第一频率组或被所述帧抽取单元转换至第一频率组时，用于对所接收的4K×2K信号进行帧像素的压缩以获得4K×1K信号；
    　　　以及帧像素分割单元，用于对所述4K×1K信号进行帧像素的分割以获得2K×1K过渡信号；
    　　　其中第一频率组包括24Hz、25Hz和30Hz，第二频率组包括50Hz、59.94Hz和60Hz。
  13. 根据权利要求12所述的超高清显示的控制装置，其特征在于，所述帧解码模块包括：
    　　　图像解码单元，用于对所述2K×1K过渡信号进行图像解码以获得2K×1K屏显信号；
    　　　图像处理单元，用于对所述2K×1K过渡信号进行图像处理以获得2K×1K屏显信号。
  14. 根据权利要求12所述的超高清显示的控制装置，其特征在于，所述帧合成模块包括：
    　　　帧像素放大单元，用于对所述2K×1K屏显信号进行插行放大处理以获取2K×2K信号；
    　　　以及帧合并单元，用于对所述2K×2K信号进行帧合并处理以获取4K×2K目标信号。
  15. 一种超高清电视机，其特征在于，包括格式判断装置、超高清显示的控制装置和超高清屏；
    　　　所述格式判断装置，用于判断所输入的信号是否为4K×2K信号，若判断所输入的信号是4K×2K信号，则将所述4K×2K信号输出至所述超高清显示的控制装置；
    　　　所述超高清显示的控制装置，用于控制所述超高清电视机能够实现超高清显示；
    　　　所述超高清屏，用于超高清显示所述超高清显示的控制装置输出的4K×2K信号；
    　　　所述超高清显示的控制装置包括：
    　　　帧分解模块，用于将接收的4K×2K信号分解成2K×1K过渡信号；
    　　　帧解码模块，用于对所述2K×1K过渡信号进行解码处理，以获得2K×1K屏显信号；
    　　　以及帧合成模块，用于将所述2K×1K屏显信号转换成4K×2K目标信号以提供给超高清屏显示。
  16. 根据权利要求15所述的超高清电视机，其特征在于，所述帧分解模块包括：
    　　　频率识别单元，用于识别所接收的4K×2K信号的频率；
    　　　帧抽取单元，当所接收的4K×2K信号的频率被所述频率识别单元识别为属于第二频率组时，用于对所接收的4K×2K信号进行帧抽取，以将所接收的4K×2K信号的频率转换至所述第一频率组；
    　　　帧像素压缩单元，当所接收的4K×2K信号的频率被所述频率识别单元识别为属于第一频率组或被所述帧抽取单元转换至第一频率组时，用于对所接收的4K×2K信号进行帧像素的压缩以获得4K×1K信号；
    　　　以及帧像素分割单元，用于对所述4K×1K信号进行帧像素的分割以获得2K×1K过渡信号；
    　　　其中第一频率组包括24Hz、25Hz和30Hz，第二频率组包括50Hz、59.94Hz和60Hz。
  17. 根据权利要求16所述的超高清电视机，其特征在于，所述帧解码模块包括：
    　　　图像解码单元，用于对所述2K×1K过渡信号进行图像解码以获得2K×1K屏显信号；
    　　　图像处理单元，用于对所述2K×1K过渡信号进行图像处理以获得2K×1K屏显信号。
  18. 根据权利要求16所述的超高清电视机，其特征在于，所述帧合成模块包括：
    　　　帧像素放大单元，用于对所述2K×1K屏显信号进行插行放大处理以获取2K×2K信号；
    　　　以及帧合并单元，用于对所述2K×2K信号进行帧合并处理以获取4K×2K目标信号。
  19. 根据权利要求15所述的超高清电视机，其特征在于，所述超高清电视机还包括：
    　　　存储模块，用于存储所述格式判断装置和所述超高清显示的控制装置所输入和输出的数据；
    　　　控制模块，用于控制存所述储格式判断装置、所述超高清显示的控制装置和所述超高清屏执行相应操作。
  20. 根据权利要求15所述的超高清电视机，其特征在于，所述超高清电视机还包括：
    　　　倍频插帧装置，用于对所述超高清显示的控制装置输出的4K×2K@30Hz目标信号进行插帧、倍频处理，并向所述超高清屏输出4K×2K@60Hz信号以驱动所述超高清屏实现超高清显示。
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