WO2014139077A1

WO2014139077A1 - Source follower based on deep n-well nmos transistor

Info

Publication number: WO2014139077A1
Application number: PCT/CN2013/072418
Authority: WO
Inventors: 刘松; 杨飞琴; 吴柯
Original assignee: 香港中国模拟技术有限公司
Priority date: 2013-03-11
Filing date: 2013-03-11
Publication date: 2014-09-18

Abstract

A source follower based on a deep N-well NMOS transistor comprises a current source and a deep N-well NMOS transistor which is used as an input component. A bulk of the deep N-well NMOS transistor is connected with an input end of the source follower, so that a voltage between a source and the bulk of the deep N-well NMOS transistor is basically maintained constant in a condition that an input signal changes. The source follower has small distortion and good linearity, and is especially suitable for being used in a high-speed heavy-load scenario.

Description

Source follower based on deep N-well NMOS transistor

The invention belongs to the field of source follower technology, and relates to a source follower based on a deep N-well NMOS transistor. Background technique

Source followers based on MOS devices (i.e., MOSFETs, i.e., MOS transistors) are widely used in various functional circuits. For example, a source follower can typically be used as a high-speed input buffer with a simple circuit structure. The source follower provides high input impedance, low output impedance, and wide signal bandwidth. Compared to closed-loop-based op amps, sources There is no stability issue with the follower. Therefore, the source follower is ideal for buffers and driver circuits.

Figure 1 shows a schematic diagram of a standard NMOS transistor, where (a) is a schematic diagram of its cross-section and (b) is an equivalent circuit diagram. Figure 2 shows a circuit diagram based on the conventional source i formed by the standard N M 0 S transistor shown in Figure 1.

As shown in FIG. 1, a standard NMOS transistor ^ is formed directly on the P-type substrate 1H, patterned on the substrate 111 to form an N-type doped source region 113, and patterned N-doped to form a drain region 114, forming a gate. After the dielectric layer 112, a source (Source, hereinafter abbreviated as S) 115 and a drain (Drain, hereinafter abbreviated as D) 117 are formed from the source region 113 and the drain region 114, and a gate is patterned on the gate dielectric layer 112. A pole 116 (Gate, hereinafter abbreviated as G), and a body terminal (Bulk, hereinafter abbreviated as B) 118 which forms a bias ground signal (GND) is taken out from the substrate 111. Therefore, the parasitic capacitances C _sb and C _db are usually formed in the standard NMOS transistor, wherein C _sb is the junction of the diode formed between the source region 113 and the P-type substrate 111 (as shown in FIG. 1(a)). Capacitor, C _db is the junction capacitance of the diode formed between drain region 1M and P-type substrate 111 (as shown in Figure 1 (a)).

Based on the standard of the NMOS transistor shown in FIG. FIG. 2 ^ source forming a source follower, the standard NMOS transistor is used as an input device as an input terminal of a gate ^ V _in, input signal level of the NMOS transistor (e.g., before An 'output signal' is input from the gate, and the source of the standard NMOS transistor is used as the output terminal V. _Ut ; the drain is connected to the power signal V _DD , the body is biased to the ground signal GND; the current source is placed between the source and ground, which provides a constant bias current for the input device; therefore, C _{db is} placed at the drain Between D and body B, C _sb Placed between source S and body B. The output signal of the source follower shown in Figure 2 can follow the input signal change, and its gain can be calculated by the following formula (1):

Gain = (1) where ro is the output impedance of the input device (here the standard 1^3⁄4103 transistor), which is in parallel with the current source; Gw is the transconductance of the standard NMOS transistor. Usually r. 〉>l/G _W , therefore, the gain of the source follower is approximately equal to, ie the output signal substantially follows the input signal.

However, in fact, the input device (including the device under the current source) r. It varies with the voltage level of the output signal, so that its gain Gain also changes with the voltage of the output signal. This characteristic is usually called voltage dependence. This voltage dependency causes the source follower to exhibit a nonlinear characteristic when the input signal swings at a high amplitude, that is, large distortion is likely to occur when the input signal swing is large. Therefore, the source follower shown in Fig. 2 is easily linearly distorted due to its voltage dependency, and the linearity is poor.

Applicants have discovered that the fundamental cause of linear distortion in the source follower is an important factor that causes voltage dependence: body effects. This is because r ₀ varies with the bias voltage between the source and the substrate (B), that is, with V _sb ; when the bottom is grounded, the source is the voltage of the output signal (approximately equal to the voltage of the input signal). ) , .y varies with the voltage of the input signal, and w and the gain of the source follower Ga in vary with the input voltage.

In order to avoid linear distortion caused by voltage-dependent bulk effects, a source follower based on deep N-well NMOS transistors is further proposed, but this source follower does not consider the parasitic capacitance in deep N-well NMOS transistors at high frequencies. The effect of its application on its high-frequency dynamic distortion performance is usually prone to dynamic distortion in high-frequency or high-speed applications.

In view of this, it is necessary to propose a new type of source follower. Summary of the invention

One of the objects of the present invention is to improve the linearity of the source follower.

It is still another object of the present invention to reduce the linear distortion and dynamic distortion of the output signal of the source follower.

To achieve the above or other objects, the present invention provides a source follower based on a deep N-well NMOS transistor, including an electrical and a deep N-well used as an input device. The NMOS transistor, the deep N-well NMOS transistor includes:

P-type substrate,

Patterning a deep N-well formed by doping in the P-type substrate,

Patterning a P-well formed by doping in the deep N well,

The body end (B) drawn from the P-well,

Patterning the source and drain regions formed by doping in the P well,

a deep N-well extraction pole drawn from the deep N-well,

a source (S) drawn from the drain region,

a drain (D) drawn from the drain region, and

Gate (G);

Wherein the gate is defined as an input end (V _in ) of the source follower, the source is defined as an output ^ (V _ut ) of the source follower, the drain and The deep N-well terminal is connected to the high-level signal (V _DD ), and the two ends of the current source are respectively connected to the source and the ground;

Wherein the body end (B) is connected to the input end (V _in ) such that the voltage (V _sb ) between the source and the body end is substantially constant in the case where the input signal changes. .

A source follower according to an embodiment of the invention, wherein the P well is surrounded by the deep N well.

Wherein, in the deep N-well NMOS transistor, there is a first parasitic capacitance (C _sb ) caused by a diode formed between the source region and the P well, and a formation between the drain region and the P well The second parasitic capacitance (C _db ) caused by the diode, the diode generated by the diode formed between the P well and the deep N well, and the capacitance (C _b ).

According to an embodiment of the invention, the source follows H:, the high level signal (V _DD ) is biased on the deep N well to isolate the P well from the P-type substrate .

Specifically, the P-type substrate is grounded.

The technical effect of the present invention is that by connecting the body end of the P-well with the input terminal, on the one hand, the gain of the source follower can be affected by the receptor effect, the linearity is improved, and the linear distortion is greatly reduced; In this respect, the parasitic capacitance at the output of the source follower can be skillfully reduced, and the dynamic distortion is small when the frequency of the input signal at the input terminal V _in is changed, and the dynamic distortion in the case of the high frequency input signal is solved. The problem. Therefore, the source follower of the present invention is very suitable for high speed and large load applications. DRAWINGS

The above and other objects and advantages of the present invention will be more fully understood from the aspects of the appended claims.

Figure 1 is a schematic diagram of a standard NMOS transistor, in which (a) is a cross-sectional structure and (b) is an equivalent circuit diagram.

2 is a circuit diagram of a conventional source follower formed based on the standard NMOS transistor shown in FIG. 1.

Figure 3 is a schematic diagram of a deep N-well NMOS transistor, in which a cross-sectional structure of the channel direction is shown, and (b) is an equivalent circuit diagram.

4 is a circuit diagram of a source follower formed based on the deep N-well NMOS transistor shown in FIG.

Figure 5 is a circuit diagram of a source follower in accordance with an embodiment of the present invention formed by a deep N-well NMOS transistor shown in Figure 3. detailed description

The following is a description of some of the various possible embodiments of the invention, which are intended to provide a basic understanding of the invention and are not intended to identify key or critical elements of the invention. It is to be understood that, in accordance with the technical scope of the present invention, those skilled in the art can suggest other alternatives that can be interchanged without departing from the spirit of the invention. Therefore, the following detailed description and the annexed drawings are only to be construed as limiting or limiting the technical aspects of the invention.

It will be understood that when a component is said to be "connected" to another component, it can be directly connected to the other component or the intermediate component can be present. Conversely, when a nickname "directly connects" a component to another component, it means that there is no intermediate component.

Figure 3 shows the deep N-well NMOS transistor ^! , intent, where) is a schematic diagram of the cross-sectional structure of its channel direction, (b) its schematic diagram of the government;

As shown in FIG. 3, in this embodiment, a deep well NMOS transistor is selected to be formed on a P-type substrate or substrate 211, and a deep N-well NMOS transistor includes a deep N well 212, a P well 213, and a source. A region 221, a drain region 222, a deep N-well extinction pole 231, a body terminal (B) 232, a source (S) 233, a gate (G) 234, a drain (D) 235, and a gate dielectric Mass layer 240. The deep N well 212 may be of the N conductivity type, which may be formed by patterning the P type substrate 21 1 by N-type doping, the specific depth and doping concentration of which are not limited; the P well 213 is of the P conductivity type, For forming an NMOS transistor, specifically, a P-type doping may be patterned in the deep N-well 212; in the P-well 213, patterning doping forms a source region 221 and a drain region 222, which may be simultaneously doped or divided. The step doping is formed, and both of them are of the N conductivity type, and the specific doping concentration is not 艮's, and between the source region 221 and the drain region 222, the channel can be controlled under the gate bias; 233, the metal electrode may be formed from the source region 221, the drain electrode 235 may be formed by drawing the metal electrode from the drain region 222, and the body terminal 232 may be formed from the P-well 213. The gate dielectric layer 240 may specifically but not limited to Si0 ₂ , which may The gate electrode 234 is formed between the source electrode 233 and the drain electrode 235 by patterning the surface of the substrate 21 1 of the silicon material. Since the P well 213 is patterned by doping in the deep N well 212, the deep N well 212 surrounds the P well 213 to be isolated from the P type substrate 21 1 , thus forming each on the P type substrate 21 1 A deep N-well NMOS transistor is similar to an "island" on it. The deep N-well 212, here also drawn through the deep N-well extraction pole 23 1 , biases the voltage signal thereto, for example, by biasing the high-level power supply signal V _DD .

Continuing with Figure 3, similar to the standard NMOS transistor of Figure 1, the parasitic capacitances C _sb and C _db are typically formed, and C _sb is the diode formed between the source region 221 and the P well 213 (Fig. 3(a) The junction capacitance shown in )): C^ _b is the diode formed between drain region 222 and P well 213 (as shown in Figure 3 (a)). Also, the junction capacitance of the diode between the P well 213 and the deep N well 212 at the periphery thereof also introduces the parasitic capacitance C _b , and therefore, an equivalent circuit diagram as shown in FIG. 3( b ) is formed. In this embodiment, in order to prevent the diode corresponding to C _b from being forward biased, the deep N-well extracting pole 231 biases the power supply signal V _DD , and the P-type substrate 21 1 biases the ground signal GND. At this time, the P well 213 has been isolated from the P type substrate 21 1 , and the P well 213 no longer needs to be grounded to ensure the reverse bias of its parasitic diode, which is completely different from the standard NMOS transistor shown in FIG. 1 .

4 is a circuit diagram showing a source follower formed based on the deep N-well NMOS transistor shown in FIG. In the embodiment shown in FIG. 4, in order to solve the problem of the source follower shown in FIG. 2, a deep N-well NMOS transistor is used, and the P-well 213 does not have to be grounded, but the body terminal 232 of the P-well 213 is used. It is directly connected to its own source 233. Thus, the voltage V _sb between the source and the body terminal is substantially constant to zero, thus substantially eliminating the body effect in the embodiment shown in FIG. 2, and the gain Gain of the follower is not followed by the source follower. The input signal (ie, the gate) changes in the voltage of the sense signal (Figure The gain Gain of the embodiment shown in Fig. 3 is similarly calculated according to the formula (1), and the voltage dependency is also eliminated. Compared to the source follower shown in Figure 2, the source follower shown in Figure 4 greatly reduces linear distortion and provides relatively better linearity.

However, Applicant has found that in the source follower of the embodiment of Figure 4, the output terminal V _{QUt is} connected to the parasitic capacitances C _db and C _b (C _sb is short-circuited due to substrate connection and is not present at the output); When the frequency rises, part of the output current through the deep N-well NMOS transistor is shunted to the capacitor channel (load capacitance or parasitic capacitance) at the output. Since this dynamic current varies with the input signal frequency, this will result in the output impedance of the input device. r. It also has a voltage dependence, so the gain of the source follower varies with the signal voltage, causing dynamic distortion. The higher the frequency of the input signal, the larger the output capacitance (including parasitic capacitance) and the more severe the dynamic distortion. "

FIG. 5 is a circuit diagram of a source follower formed in accordance with an embodiment of the present invention based on the deep N-well NMOS transistor shown in FIG. In the embodiment shown in FIG. 5, the deep N-well NMOS transistor of the embodiment shown in FIG. 3 is also selected as an input device, and a current source is placed between the source and the ground (GND) for providing basic input devices. Constant bias current; the input signal of the source follower is input from the gate G of the deep N-well NMOS transistor, and the gate G is defined as the input terminal V _in of the source follower; the signal is sourced from the deep N-well NMOS transistor The pole S output, the source S is defined as the output terminal V _out of the source follower; further, the drain D is connected to the high level power supply signal V _DD ; the deep N well deep N well out pole 231 is also biased A high level power supply signal V _DD is used to reverse bias the diode formed between the P-type substrate 21 1 and the deep N well 212 and reverse bias the diode formed between the N well 212 and the P well 213. In particular, the body end or ^ V _in the gate terminal G is connected, for example, in FIG. 3, the end member 232 may be directly connected to the gate 234. Thus, the source follower of the embodiment of Figure 5 will have both of the following advantages.

First, the body effect problem of a source follower based on a standard NMOS transistor is considered. It can be noted that in the embodiment shown in FIG. 5, since the body terminal B is connected to the input terminal Vi^ gate G, the body terminal B is equal to the potential of the gate G, so V _sb = V _sg ; and because of the source follower The medium source S voltage follows the input gate G, so V _sg will be a constant that does not change with the voltage of the input signal, ie, there is no voltage dependency problem. The gain of the source follower shown in Figure 5 (α " can be calculated similarly by equation (1), where is the output impedance of the input device, which is the transconductance of the deep-sink NMOS transistor) and the receptor effect. Effect, compared to the source follower of the embodiment shown in Figure 2 The linearity is good and the linear distortion is greatly reduced.

Second, consider the effect of the parasitic capacitance at the output on the distortion. It can be noted that in the embodiment shown in FIG. 5, by connecting the body terminal 8 with the 'input terminal V _in or the gate G, C _db and C _b are placed in parallel between the V _DD and the body end, C _db and C _b no longer appears at the output V. _Ut ; and for 亍C _sb , although it is placed between body B and source S, as mentioned above, v _sb =v _sg , v _sb voltage value is also a constant (not with the input signal voltage The change varies, so that the parasitic capacitance C _sb does not increase the output terminal V. The total amount of capacitance of _ut . Thus, the parasitic capacitance at the output is significantly reduced compared to the source follower structure shown in Figure 4, at the input.

When the frequency of the input signal of V _in changes, the voltage dependency problem and the dynamic distortion problem of the source follower shown in FIG. 4 above do not occur.

In summary, the source follower of the embodiment shown in FIG. 5 not only reduces the linear distortion caused by the hibernation effect, but also eliminates the problem of dynamic distortion caused by the parasitic capacitance of the deep N-well NMOS transistor, so that it can be maintained It has good low-frequency linear characteristics and reduces dynamic distortion. It has good high-frequency characteristics and is very suitable for high-speed and large-load applications.

It is to be understood that the input terminal V _in is the input number ^ 'for the output of the previous stage circuit, for example, the front-stage circuit may be an operational amplifier. The specific type of input signal is not limiting.

It will also be appreciated that the source follower of the embodiment of Figure 5 is not only suitable for fabrication in an integrated circuit, but is also suitable for formation by a deep N-well NMOS transistor separation device through a line connection.

The above examples mainly illustrate the source follower of the deep N-well NMOS transistor of the present invention. Although only a few of the embodiments of the present invention have been described, it will be understood by those skilled in the art that the present invention may be embodied in many other forms without departing from the spirit and scope of the invention. Accordingly, the present invention is to be construed as illustrative and not restrictive, and the invention may cover various modifications without departing from the spirit and scope of the invention as defined by the appended claims With replacement.

Claims

Rights request

A source follower based on a deep N-well NMOS transistor, comprising a current source and a deep N-well NMOS transistor used as an input device, the deep N-well NMOS transistor comprising:

P-type substrate,

Patterning a deep N-well formed by doping in the P-type substrate,

Patterning a P-well formed by doping in the deep N well,

a body end (B) drawn from the P well,

Patterning the source and drain regions formed by doping in the P well,

a deep N-well extraction pole drawn from the deep N-well,

a source (S) drawn from the drain region,

a drain (D) drawn from the drain region, and

Gate (G);

Wherein the gate is defined as an input end (V _in ) of the source follower, and the source is defined as an output end of the source follower ('V. _ut ), the drain And a deep N-well terminal is connected to a high-level signal (V _DD ), and the two ends of the source are respectively connected to the source and the ground;

Wherein the body terminal (B) is connected to the input ^ (V _in ) such that a voltage (V _sb ) between the source and the body terminal is substantially constant in the case where the input signal changes. .

2. The source follower of claim 1 wherein the P-well is surrounded by the deep N-well.

3. The source follower according to claim 1, wherein in the deep N-well NMOS transistor, there is a first parasitic capacitance caused by a diode formed between the source region and the P well ( C _sb ), a second parasitic capacitance (C _db ) caused by a diode formed between the drain region and the P well, and a third parasitic caused by a diode formed between the P well and the deep N well Capacitance (C _b :).

4. The source follower of claim 1 wherein said high level signal (V _DD ) is biased on said deep N-well to cause said P-well and said P-type lining The bottom phase is isolated.

5. The source follower of claim 4, wherein the P-type ground is grounded