WO2014132619A1 - Information processing device, information processing method, and memory medium - Google Patents

Information processing device, information processing method, and memory medium Download PDF

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Publication number
WO2014132619A1
WO2014132619A1 PCT/JP2014/000965 JP2014000965W WO2014132619A1 WO 2014132619 A1 WO2014132619 A1 WO 2014132619A1 JP 2014000965 W JP2014000965 W JP 2014000965W WO 2014132619 A1 WO2014132619 A1 WO 2014132619A1
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memory
data
memory area
information processing
virtual
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PCT/JP2014/000965
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French (fr)
Japanese (ja)
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岳生 細見
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日本電気株式会社
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Priority to JP2015502767A priority Critical patent/JP6142916B2/en
Publication of WO2014132619A1 publication Critical patent/WO2014132619A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor

Definitions

  • the present invention relates to a technical field of appropriately controlling data saved in a memory area in order to realize smooth processing in an information processing apparatus having a host processor and a hardware accelerator.
  • main memory main memory
  • accelerator memory is connected to the hardware accelerator.
  • Such an information processing system performs a virtual storage operation using the main memory and the accelerator memory, and can also allocate a virtual memory area (swap area) to a storage device such as a hard disk.
  • a virtual memory area a storage device such as a hard disk.
  • the hardware accelerator can secure a memory area larger than the physical capacity of the accelerator memory.
  • the above-described effects can be obtained by a technique of paging and swapping of the memory area.
  • Such paging is one of virtual storage methods.
  • Such paging is a technique in which a physical memory area and a virtual memory area are divided into areas of a certain size called pages, and data is transferred between the main memory and a storage device such as a hard disk in units of the pages. is there.
  • Such swap is a technique mainly related to paging data transfer. Specifically, the swap is a technique for exchanging data by writing and reading contents between a main memory and a storage device such as a hard disk.
  • paging out in paging is a technique for erasing an unnecessary page in a memory area from a physical memory by writing the page in a virtual area allocated to a storage device such as a hard disk.
  • the paging out described here is a swap-out in a swap.
  • Paging-in in paging is a technique for reading a necessary page from a virtual area allocated to a hard disk or the like and arranging data corresponding to the read page in a physical memory, contrary to the above-described paging-out. is there.
  • the paging-in described here is a swap-in in a swap.
  • a new usable storage area can be secured in the physical memory by moving the data in the physical memory to a virtual area. That is, according to the above technique, a high-speed memory can be used for other processing.
  • FIG. 10 is a block diagram illustrating an information processing system 5 including a host processor and a hardware accelerator using a virtual memory management method.
  • the information processing system 5 has the following configuration. That is, A host processor 502, A main memory 504 accessed by the host processor 502, ⁇ Hardware accelerator 506, An accelerator memory 508 accessed by the hardware accelerator 506, The virtual memory management unit 112 included in the hardware accelerator 506.
  • the information processing system 5 has a swap area 514.
  • the virtual storage management unit 112 uses a swap area in the storage device 514 as a save destination of data in the accelerator memory 508.
  • the virtual memory management unit 512 As a function of the virtual memory management unit 512, a technique is known in which the area of the accelerator memory 508 is managed in units of pages and operates by a demand paging method.
  • the virtual memory management unit 512 when the virtual memory management unit 512 cannot secure a page required by the accelerator memory 508, the virtual memory management unit 512 selects several pages from the group of pages secured in the accelerator memory 508. Next, the virtual storage management unit 512 saves the selected page in the swap area. When a page to be accessed by the hardware accelerator 506 is saved in the swap area, the virtual storage management unit 512 controls to read the page saved in the swap area into the accelerator memory 508.
  • FIG. 11 is a flowchart showing the flow of processing in the information processing system 5.
  • a task is input to the information processing system 5, and the host processor 502 executes processing (step S502).
  • the host processor 502 transfers data to be processed in the hardware accelerator 506 from the main memory 504 to the accelerator memory 508 (step S504).
  • the hardware accelerator 506 executes processing using the data transferred from the host processor 502 (step S506).
  • the host processor 502 transfers the result processed by the hardware accelerator 506 from the accelerator memory 508 to the main memory 504 (step S508).
  • the host processor 502 processes the next task (step S502 or step S504).
  • the information processing system 5 completes the task processing in the host processor 502 by repeating the processing in steps S502 to S508 several times.
  • Patent Document 1 discloses a device having a general-purpose processor and a hardware accelerator. That is, Patent Document 1 discloses a memory system that executes memory operations such as paging in and paging out between a main memory and a hard disk drive.
  • Patent Document 2 discloses a technique for selecting a swap-out suppression target page based on the operation characteristics of a program immediately after a task can be executed in a swap process. At that time, in the technique disclosed in Patent Document 2, prioritization of pages for suppressing swap-out processing is performed by a page replacement algorithm.
  • Patent Document 3 discloses a system in which a plurality of information processing apparatuses share data recorded in the same logical volume. That is, Patent Document 3 describes a technique for exclusively controlling a plurality of areas of the logical volume when the logical volume is configured by a plurality of areas. Specifically, in the technology disclosed in Patent Document 3, when there is an unused area in the logical volume composed of a plurality of areas, the unused area can be accessed from another information processing apparatus. This technology is open to the public.
  • Patent Document 1 performs processing such as paging in and paging out between the main memory and the hard disk drive. For this reason, in the technique described in Patent Document 1, the performance of the system deteriorates when paging-in and paging-out are performed.
  • Patent Document 2 selects pages that suppress swap-out processing by a page replacement algorithm based on the operation characteristics of the program. In other words, the technique described in Patent Document 2 makes a selection that suppresses swap-out of recently used pages. For this reason, the technique described in Patent Document 2 may suppress the swap-out of a page that is not used at a later time even if it is a recently used page.
  • the present invention has been made in view of the above problems. That is, it is an object of the present invention to prevent performance degradation associated with data transfer during execution of processing in an information processing apparatus having a host processor and a hardware accelerator.
  • an information processing apparatus provides: Virtual memory management means for managing virtual memory processing performed using a first memory area connected to the host processor and a second memory area connected to the hardware accelerator; Data for controlling the virtual memory management means to set and release the data saving in the second memory area based on data transferred between the first memory area and the second memory area Transfer control means.
  • an information processing method includes: Computer Managing virtual memory processing performed using the first memory area connected to the host processor and the second memory area connected to the hardware accelerator by the virtual memory managing means; Based on the data transferred between the first memory area and the second memory area, the operation of the virtual memory management means is controlled so as to set and release the data saving in the second memory area. To do.
  • a computer program manages virtual memory processing performed using a first memory area connected to a host processor and a second memory area connected to a hardware accelerator. Based on the virtual memory management process and data transferred between the first memory area and the second memory area, the virtual memory is configured to set and release the data save in the second memory area. Data transfer control processing for controlling management processing is executed by a computer.
  • the same object can be achieved by a computer-readable storage medium storing the computer program.
  • the information processing apparatus of the present invention in an information processing apparatus having a host processor and a hardware accelerator, it is possible to prevent performance deterioration due to data transfer during processing execution.
  • FIG. 1 It is a figure which shows the hardware structural example of the information processing apparatus (computer) which can implement
  • FIG. 1 It is a block diagram which illustrates functional composition of information processor 1 concerning a 1st embodiment. It is a flowchart which shows the flow of the process in the information processing apparatus 1 which concerns on 1st Embodiment. It is a block diagram which illustrates functional composition of information processor 2 concerning a 2nd embodiment. It is a flowchart which shows the flow of a process in the information processing apparatus 2 which concerns on 2nd Embodiment. It is a block diagram which illustrates functional composition of information processor 3 concerning a 3rd embodiment.
  • FIG. 1 is a diagram illustrating a hardware configuration example of an information processing apparatus (computer) capable of realizing the information processing apparatus 1 according to the first embodiment of the present invention.
  • the information processing apparatus 1 has a configuration illustrated in FIG. That is, CPU (Central Processing Unit) 10, -Memory 12, HDD (hard disk drive) 14, A communication IF (interface) 16 for performing communication via a network (not shown), ⁇ Input device 18, -Output device 20, A reader / writer 22 that can read information stored in a computer-readable storage medium 24 such as a CD (compact disk).
  • the above-described components are connected to each other through the bus 26 and can input / output data to / from each other.
  • the CPU 10 executes a computer program (hereinafter referred to as “program”) stored in the memory 12 or the HDD 14.
  • the CPU 10 executes a program stored in the storage medium 24.
  • the program executed in the CPU 10 may be acquired from the outside via the communication IF 16, the input device 18, or the reader / writer 22.
  • the CPU 10 displays the output result on the output device 20.
  • the hardware configuration example of the information processing apparatus 1 illustrated in FIG. 1 can also be applied to embodiments described later.
  • FIG. 2 is a block diagram illustrating the functional configuration of the information processing apparatus 1 according to the first embodiment of the invention.
  • an information processing apparatus according to an embodiment of the present invention described later is a server or the like.
  • the information processing apparatus 1 according to the first embodiment has the following configuration, for example. That is, A host processor 102, A main memory 104 (first memory area) accessed by the host processor 102, Hardware accelerator 106, An accelerator memory 108 (second memory area) accessed by the hardware accelerator 106; Data transfer control unit 110.
  • the hardware accelerator 106 includes a menicore accelerator, a graphic accelerator, and the like.
  • the hardware accelerator 106 includes a virtual memory management unit 112.
  • the host processor 102 and the hardware accelerator 106 have a virtual memory management function (not shown) different from the virtual memory management unit 112 described below.
  • the virtual storage management function itself itself can employ a generally known technique, the description in this embodiment will be omitted.
  • the hardware accelerator 106 includes the virtual memory management unit 112
  • the virtual memory management unit 112 may not include the hardware accelerator 106.
  • the host processor 102 or an external device may have a virtual memory management unit 112.
  • the information processing apparatus 1 can read / write data from / to the storage device (hard disk drive or the like) 114.
  • the storage device 114 may be included in the information processing apparatus 1 or may be installed as an external device.
  • the host processor 102 executes process A according to the program.
  • the process A represents the entire process to be executed by the host processor 102, and includes a plurality of processes including a process B executed by a hardware accelerator 106 to be described later.
  • the host processor 102 completes a series of processes A including a plurality of processes such as the process B, the host processor 102 ends the operation.
  • the host processor 102 performs control related to the hardware accelerator 106. Specifically, the host processor 102 transfers data necessary for processing in the hardware accelerator 106 from the main memory 104 to the accelerator memory 108.
  • the hardware accelerator 106 executes the process B using the data transferred from the main memory 104 to the accelerator memory 108.
  • the process B executed by the hardware accelerator 106 is a process distributed to the hardware accelerator 106 among a plurality of processes included in the process A executed by the host processor 102.
  • the distribution method of the process B since a general technique can be adopted at present, the description in this embodiment is omitted.
  • the hardware accelerator 106 transfers the processing result from the accelerator memory 108 to the main memory 104.
  • the virtual memory management unit 112 manages the memory area of the accelerator memory 108. When the necessary memory area cannot be secured in the memory area of the accelerator memory 108, the virtual storage management unit 112 selects a part of the memory area secured in the accelerator memory 108. Then, the virtual storage management unit 112 saves the data described in the selected partial memory area to the swap area in the storage device 114 (swap out).
  • the data transfer control unit 110 controls data transfer between the main memory 104 and the accelerator memory 108 in cooperation with the virtual memory management unit 112. Specifically, the data transfer control unit 110 cooperates with the virtual memory management unit 112 to perform setting so as to save the data stored in the memory area in the accelerator memory 108. For example, the data transfer control unit 110 performs non-target setting for data saving (non-swap setting) in a specific memory area of the accelerator memory 108 and cancels the setting.
  • the non-swap setting is a procedure for excluding the memory area from the target area for saving data.
  • Such a non-swap setting may be any setting that reduces the frequency with which a specific memory area in the accelerator memory 108 is swapped.
  • the data transfer control unit 110 may be set so that a specific memory area in the accelerator memory 108 is not completely swapped, or may be set to reduce (reduce) the frequency of swapping.
  • FIG. 3 is a flowchart showing the flow of processing in the information processing apparatus 1 according to the first embodiment of the present invention.
  • step S102 the host processor 102 starts executing the process A according to the program.
  • step S104 the data transfer control unit 110 cooperates with the virtual memory management unit 112 to set the memory area of the accelerator memory 108 as a non-swap target. Specifically, the data transfer control unit 110 cooperates with the virtual memory management unit 112. Then, the data transfer control unit 110 performs a process of reading all data saved in the swap area in the storage device 114 from the swap area in the storage device 114 into the accelerator memory 108 for a specific memory area.
  • the specific memory area is a memory area included in the accelerator memory 108 used by the hardware accelerator 106 for processing B. Then, the hardware accelerator 106 sets the memory area of the accelerator memory 108 used for the process B to be excluded from swapping.
  • step S106 the host processor 102 transfers the data used by the hardware accelerator 106 for processing B from the main memory 104 to the accelerator memory 108.
  • step S108 the hardware accelerator 106 executes a process B that is a part of a specified process among a series of processes (process A) described in the program. Specifically, the hardware accelerator 106 executes process B using the data transferred from the host processor 102 in step S106.
  • step S110 for example, the host processor 102 transfers the processing result in the hardware accelerator 106 from the accelerator memory 108 to the main memory 104.
  • step S112 the data transfer control unit 110 cooperates with the virtual memory management unit 112 to cancel the setting not to be swapped in the accelerator memory 108 set in step S104.
  • step S102 to step S112 is repeatedly performed.
  • the host processor 102 outputs the process result of the process A, whereby the operation of the information processing apparatus 1 ends.
  • the information processing apparatus according to an embodiment to be described later also ends the operation when the processing result of the processing A is output.
  • step S104 and step S106 may be reversed. That is, after the data is transferred from the main memory 104 to the accelerator memory 108, the memory area of the accelerator memory 108 may be set as a data saving target.
  • step S110 and step S112 may be reversed. That is, the processing result may be transferred from the accelerator memory 108 to the main memory 104 after canceling the setting to be excluded from data transfer set in the memory area of the accelerator memory 112.
  • the information processing apparatus 1 can prevent performance degradation due to data transfer during processing execution in an information processing apparatus having a host processor and a hardware accelerator. it can.
  • the reason is that in the phase in which the hardware accelerator 106 is executing the process B (step S108), the data described in the memory area of the accelerator memory 108 used when executing the process B is not swapped out. It is because it becomes difficult to be done.
  • a page miss does not occur or the frequency of page misses is low in the phase (step S108) in which the hardware accelerator 106 executes the process B.
  • FIG. 4 is a block diagram illustrating the functional configuration of the information processing apparatus 2 according to the second embodiment of the invention.
  • the information processing apparatus 2 according to the second embodiment has a configuration in which the data transfer control unit 110 is replaced with a data transfer control unit 210, as compared with the information processing apparatus 1 according to the first embodiment. Different. Other than that, since it is the same as that of the information processing apparatus 1 according to the first embodiment, the same drawing number is given, and a duplicate description is omitted.
  • the host processor 102 starts execution of the process A according to the program, and transfers data from the main memory 104 to the accelerator memory 108.
  • the hardware accelerator 106 executes the process B using the data transferred to the accelerator memory 108 and transfers the processing result from the accelerator memory 108 to the main memory 104.
  • the virtual memory management unit 112 manages the memory area of the accelerator memory 108, and saves (swaps out) the data in the accelerator memory 108 to the swap area in the storage device 114.
  • the data transfer control unit 210 controls data transfer between the main memory 104 and the accelerator memory 108 in cooperation with the virtual memory management unit 112. Specifically, the data transfer control unit 210 cooperates with the virtual memory management unit 112 to swap out a specific memory area in the accelerator memory 108.
  • the specific memory area in the accelerator memory 108 may be a memory area that is not reused in the subsequent process B executed by the hardware accelerator 106.
  • the data transfer control unit 210 may decide to swap out the memory area of the data transferred from the accelerator memory 108 to the main memory 104 (data processed in the hardware accelerator 106).
  • the specific memory area swapped out may be a memory area of data transferred from the main memory 104 to the accelerator memory 108.
  • the specific memory area to be swapped out may be a memory area specified by a program written by the user.
  • the specific memory area to be swapped out may be specified by a combination of the specific methods described above.
  • FIG. 5 is a flowchart showing the flow of processing in the information processing apparatus 2 according to the second embodiment of the present invention.
  • step S102 the host processor 102 starts executing the process A according to the program.
  • step S106 the host processor 102 transfers data used by the hardware accelerator 106 for processing B from the main memory 104 to the accelerator memory 108.
  • step S108 the hardware accelerator 106 executes process B.
  • step S ⁇ b> 110 for example, the host processor 102 transfers the processing result in the hardware accelerator 106 from the accelerator memory 108 to the main memory 104.
  • step S220 the data transfer control unit 210 cooperates with the virtual memory management unit 112 to swap out a specific memory area in the accelerator memory 112.
  • the method for determining a specific memory area is as described above.
  • the information processing apparatus 2 reduces the frequency of occurrence of swap in the phase in which the hardware accelerator 106 executes the process B (step S108). Performance degradation can be suppressed. The reason is that the virtual storage management unit 112 frees a memory area that does not actively hold data.
  • FIG. 6 is a block diagram illustrating the functional configuration of the information processing apparatus 3 according to the third embodiment of the invention.
  • the information processing apparatus 3 according to the third embodiment has a configuration in which the data transfer control unit 110 is replaced with a data transfer control unit 310 and the host processor 102 includes a data replication unit 316. This is different from the information processing apparatus 1 according to the second embodiment and the second embodiment.
  • the same drawing number is given, and a duplicate description is omitted.
  • the host processor 102 starts execution of the process A according to the program, and transfers data from the main memory 104 to the accelerator memory 108.
  • the hardware accelerator 106 executes process B using the data transferred to the accelerator memory 108, and transfers the processing result from the accelerator memory 108 to the data replication unit 316.
  • the virtual memory management unit 112 sets the memory area of the processing result transferred to the data replication unit 316 as swapped out.
  • the data transfer control unit 310 controls data transfer by cooperating with the virtual memory management unit 112. Specifically, the data transfer control unit 310 controls to transfer the result processed in the hardware accelerator 106 to the data replication unit 316.
  • the data replication unit 316 writes the processing result transferred from the accelerator memory 108 to the designated memory area of the main memory. Further, the data duplication unit 316 duplicates the processing result transferred from the accelerator memory 108 and saves the duplicated processing result in the swap area in the storage device 114.
  • FIG. 7 is a flowchart showing the flow of processing in the information processing apparatus 3 according to the third embodiment of the present invention.
  • step S102 the host processor 102 starts executing the process A according to the program.
  • step S106 the host processor 102 transfers data used by the hardware accelerator 106 for processing B from the main memory 104 to the accelerator memory 108.
  • step S108 the hardware accelerator 106 executes process B.
  • step S332 the data transfer control unit 310 transfers the result processed in the hardware accelerator 106 from the accelerator memory 108 to the data replication unit 316.
  • step S334 the virtual memory management unit 112 sets the memory area transferred in the accelerator memory 108 as swapped out.
  • step S336 the data replication unit 316 writes the processing result transferred from the accelerator memory 108 into a specific memory area of the main memory 104.
  • step S3308 the data copying unit 316 copies the processing result transferred from the accelerator memory 108, and saves the copied processing result in the swap area in the storage device 114.
  • the information processing apparatus 3 can avoid performance degradation due to swap-out.
  • the reason is that swap-out can be executed in accordance with the data transfer without increasing the data transfer between the hardware accelerator 106 and the host processor 102.
  • FIG. 8 is a block diagram illustrating the functional configuration of the information processing apparatus 4 according to the fourth embodiment of the invention.
  • the information processing device 4 according to the fourth embodiment has a configuration in which the data transfer control unit 110 is replaced with a data transfer control unit 410, as compared with the information processing device 1 according to the first embodiment. Different. Other than that, since it is the same as that of the information processing apparatus 1 according to the first embodiment, the same drawing number is given, and a duplicate description is omitted.
  • the host processor 102 starts executing the process A according to the program. Further, the host processor 102 transfers the designated area from the main memory 104 to the accelerator memory 108.
  • the data transfer control unit 410 controls data transfer between the main memory 104 and the accelerator memory 108 in cooperation with the virtual memory management unit 112. Specifically, the data transfer control unit 410 controls the virtual memory management unit 112 so as to secure data used for the process B executed by the hardware accelerator 106.
  • the virtual storage management unit 112 sets the data swapped out in the accelerator memory 108 as being swapped in by allocating the physical area without reading the data from the swap area in the storage device 114.
  • the hardware accelerator 106 executes the process B using the data set as swapped in by the virtual memory management unit 112 and transfers the processing result from the accelerator memory 108 to the main memory 104.
  • FIG. 9 is a flowchart showing the flow of processing in the information processing apparatus 4 according to the fourth embodiment of the present invention.
  • step S102 the host processor 102 starts executing the process A according to the program.
  • step S442 the virtual memory management unit 112 allocates a physical area on the virtual memory and sets the data used for the process B executed by the hardware accelerator 106 to be swapped in. Specifically, the virtual memory management unit 112 allocates a physical area to the data on the virtual memory swapped out from the accelerator memory 108.
  • step S444 for example, the host processor 102 transfers the data in the designated area from the main memory 104 to the accelerator memory 108.
  • step S108 the hardware accelerator 106 executes process B.
  • step S ⁇ b> 110 for example, the host processor 102 transfers the processing result in the hardware accelerator 106 from the accelerator memory 108 to the main memory 104.
  • the information processing apparatus 4 can avoid performance degradation due to swap-in.
  • the reason is that the swap-in can be executed in accordance with the data transfer without increasing the data transfer between the hardware accelerator 106 and the host processor 102.
  • Information processing device 1 Information processing system 10 CPU 12 Memory 14 HDD 16 Communication IF 18 Input device 20 Output device 22 Reader / writer 24 Storage medium 26 Bus 102, 502 Host processor 104, 504 Main memory 106, 506 Hardware accelerator 108, 508 Accelerator memory 110, 210, 310, 410 Data transfer control unit 112, 512 Virtual Storage management unit 114, 514 Storage device (swap area) 316 Data replication unit

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Abstract

Provided is an information processing device, and the like, having a host processor and a hardware accelerator, wherein a drop in performance that accompanies data transfer during processing can be prevented. An information processing device (1) has the following: a virtual memory management section (112) for managing virtual memory processing carried out using a first memory region connected to a host processor (102) and a second memory region connected to a hardware accelerator (106); and a data transfer control section (110) for controlling, on the basis of data transferred between the first memory region and the second memory region, the virtual memory management section (112) so that data backup in the second memory region is set or such setting is cancelled.

Description

情報処理装置、情報処理方法及び記憶媒体Information processing apparatus, information processing method, and storage medium
　本発明は、ホストプロセッサとハードウェアアクセラレータとを有する情報処理装置において、円滑な処理を実現すべく、メモリ領域に退避するデータを適宜制御する技術分野に関する。 The present invention relates to a technical field of appropriately controlling data saved in a memory area in order to realize smooth processing in an information processing apparatus having a host processor and a hardware accelerator.
　近年、ホストプロセッサとハードウェアアクセラレータとを有する情報処理システムが知られている。このような情報処理システムにおいて、そのホストプロセッサには主記憶装置（主メモリ、メモリ、以降「主メモリ」と表現する）が更に接続される。そして、そのハードウェアアクセラレータには、アクセラレータメモリが接続される。 In recent years, an information processing system having a host processor and a hardware accelerator is known. In such an information processing system, a main storage device (main memory, memory, hereinafter referred to as “main memory”) is further connected to the host processor. An accelerator memory is connected to the hardware accelerator.
　係る情報処理システムは、主メモリとアクセラレータメモリとを用いて仮想記憶動作を実行し、さらにハードディスク等の記憶装置にも仮想的なメモリ領域（スワップ領域）を割り当てることができる。この仮想記憶動作により、ハードウェアアクセラレータは、アクセラレータメモリの物理的な容量以上のメモリ領域を確保することが可能になる。 Such an information processing system performs a virtual storage operation using the main memory and the accelerator memory, and can also allocate a virtual memory area (swap area) to a storage device such as a hard disk. With this virtual storage operation, the hardware accelerator can secure a memory area larger than the physical capacity of the accelerator memory.
　具体的には、メモリ領域のページング及びスワップという技術により、上述した効果を得ることができる。 Specifically, the above-described effects can be obtained by a technique of paging and swapping of the memory area.
　係るページングとは、仮想記憶方式の１つである。係るページングは、物理メモリ領域及び仮想メモリ領域をページと呼ばれる一定の大きさの領域に分割し、このページを単位として主メモリと、ハードディスク等の記憶装置との間において、データを転送する技術である。係るスワップとは、主にページングのデータ転送に関する技術である。具体的には、係るスワップとは、主メモリと、ハードディスク等の記憶装置との間において、内容を書き出したり読み込んだりすることによりデータを交換する技術である。 Such paging is one of virtual storage methods. Such paging is a technique in which a physical memory area and a virtual memory area are divided into areas of a certain size called pages, and data is transferred between the main memory and a storage device such as a hard disk in units of the pages. is there. Such swap is a technique mainly related to paging data transfer. Specifically, the swap is a technique for exchanging data by writing and reading contents between a main memory and a storage device such as a hard disk.
　次に、ページングにおけるページングアウトとは、メモリ領域の不要なページを、ハードディスク等の記憶装置に割り当てられた仮想的な領域に書き出すことにより、物理メモリから当該ページを消去する技術である。尚、ここで説明したページングアウトは、スワップにおけるスワップアウトである。
また、ページングにおけるページングインとは、上述したページングアウトとは逆に、必要なページをハードディスク等に割り当てられた仮想的な領域から読み出し、読み出したページに相当するデータを物理メモリに配置する技術である。尚、ここで説明したページングインは、スワップにおけるスワップインである。 Next, paging out in paging is a technique for erasing an unnecessary page in a memory area from a physical memory by writing the page in a virtual area allocated to a storage device such as a hard disk. Note that the paging out described here is a swap-out in a swap.
Paging-in in paging is a technique for reading a necessary page from a virtual area allocated to a hard disk or the like and arranging data corresponding to the read page in a physical memory, contrary to the above-described paging-out. is there. The paging-in described here is a swap-in in a swap.
　上記技術によれば、係る物理メモリのデータを仮想的な領域へ移すことにより、新たに使用可能な記憶領域を物理メモリに確保することができる。即ち、上記技術によれば、高速なメモリを他の処理のために用いることが可能になる。 According to the above technique, a new usable storage area can be secured in the physical memory by moving the data in the physical memory to a virtual area. That is, according to the above technique, a high-speed memory can be used for other processing.
　上記技術について、図１０及び図１１を参照して説明する。図１０は、仮想記憶管理方式を用いたホストプロセッサとハードウェアアクセラレータから構成される情報処理システム５を例示するブロック図である。 The above technique will be described with reference to FIGS. FIG. 10 is a block diagram illustrating an information processing system 5 including a host processor and a hardware accelerator using a virtual memory management method.
　図１０に示すように、情報処理システム５は、以下の構成を有する。即ち、
　　・ホストプロセッサ５０２、
　　・ホストプロセッサ５０２がアクセスする主メモリ５０４、
　　・ハードウェアアクセラレータ５０６、
　　・ハードウェアアクセラレータ５０６がアクセスするアクセラレータメモリ５０８、
　　・ハードウェアアクセラレータ５０６が有する仮想記憶管理部１１２。 As shown in FIG. 10, the information processing system 5 has the following configuration. That is,
A host processor 502,
A main memory 504 accessed by the host processor 502,
・ Hardware accelerator 506,
An accelerator memory 508 accessed by the hardware accelerator 506,
The virtual memory management unit 112 included in the hardware accelerator 506.
　更に、情報処理システム５は、スワップ領域５１４を有する。仮想記憶管理部１１２は、アクセラレータメモリ５０８のデータの退避先として、記憶装置５１４におけるスワップ領域を用いる。 Furthermore, the information processing system 5 has a swap area 514. The virtual storage management unit 112 uses a swap area in the storage device 514 as a save destination of data in the accelerator memory 508.
　仮想記憶管理部５１２の機能としては、アクセラレータメモリ５０８の領域をページ単位で管理し、デマンドページング方式により動作する技術が知られている。 As a function of the virtual memory management unit 512, a technique is known in which the area of the accelerator memory 508 is managed in units of pages and operates by a demand paging method.
　具体的に、仮想記憶管理部５１２は、アクセラレータメモリ５０８が必要とするページが確保できなくなると、アクセラレータメモリ５０８に確保されているページ群から、いくつかのページを選択する。次に、仮想記憶管理部５１２は、選択したページを、スワップ領域に退避させる。そして、ハードウェアアクセラレータ５０６がアクセスしようとするページが当該スワップ領域に退避されている場合、仮想記憶管理部５１２は、係るスワップ領域に退避されたページを、アクセラレータメモリ５０８に読み込むよう制御する。 Specifically, when the virtual memory management unit 512 cannot secure a page required by the accelerator memory 508, the virtual memory management unit 512 selects several pages from the group of pages secured in the accelerator memory 508. Next, the virtual storage management unit 512 saves the selected page in the swap area. When a page to be accessed by the hardware accelerator 506 is saved in the swap area, the virtual storage management unit 512 controls to read the page saved in the swap area into the accelerator memory 508.
　次に、図１１を参照して、情報処理システム５の動作について説明する。図１１は、情報処理システム５における処理の流れを示すフローチャートである。図１１に示すように、まず情報処理システム５にタスクが投入され、ホストプロセッサ５０２は、処理を実行する（ステップＳ５０２）。次いで、ホストプロセッサ５０２は、ハードウェアアクセラレータ５０６において処理するデータを、主メモリ５０４からアクセラレータメモリ５０８に転送する（ステップＳ５０４）。ハードウェアアクセラレータ５０６は、ホストプロセッサ５０２から転送されたデータを用いて処理を実行する（ステップＳ５０６）。その後、ホストプロセッサ５０２は、ハードウェアアクセラレータ５０６が処理した結果を、アクセラレータメモリ５０８から主メモリ５０４に転送する（ステップＳ５０８）。次に、ホストプロセッサ５０２は、次のタスクを処理する（ステップＳ５０２、あるいはステップＳ５０４）。情報処理システム５は、ステップＳ５０２乃至ステップＳ５０８における処理を何回か繰り返すことにより、ホストプロセッサ５０２におけるタスクの処理を完了する。 Next, the operation of the information processing system 5 will be described with reference to FIG. FIG. 11 is a flowchart showing the flow of processing in the information processing system 5. As shown in FIG. 11, first, a task is input to the information processing system 5, and the host processor 502 executes processing (step S502). Next, the host processor 502 transfers data to be processed in the hardware accelerator 506 from the main memory 504 to the accelerator memory 508 (step S504). The hardware accelerator 506 executes processing using the data transferred from the host processor 502 (step S506). Thereafter, the host processor 502 transfers the result processed by the hardware accelerator 506 from the accelerator memory 508 to the main memory 504 (step S508). Next, the host processor 502 processes the next task (step S502 or step S504). The information processing system 5 completes the task processing in the host processor 502 by repeating the processing in steps S502 to S508 several times.
　例えば、特許文献１は、汎用プロセッサとハードウェアアクセラレータとを有する装置を開示する。即ち、特許文献１は、主メモリとハードディスクドライブとの間のページングイン及びページングアウト等のメモリオペレーションを実行するメモリシステムについて開示する。 For example, Patent Document 1 discloses a device having a general-purpose processor and a hardware accelerator. That is, Patent Document 1 discloses a memory system that executes memory operations such as paging in and paging out between a main memory and a hard disk drive.
　特許文献２は、スワップ処理において、あるタスクを実行可能な状態になった直後のプログラムの動作特性を踏まえて、スワップアウト抑制対象のページを選択する技術を開示する。その際、特許文献２に開示された技術では、ページ置換アルゴリズムによりスワップアウト処理を抑制するページの優先順位付けを行う。 Patent Document 2 discloses a technique for selecting a swap-out suppression target page based on the operation characteristics of a program immediately after a task can be executed in a swap process. At that time, in the technique disclosed in Patent Document 2, prioritization of pages for suppressing swap-out processing is performed by a page replacement algorithm.
　特許文献３は、複数の情報処理装置が同一の論理ボリュームに記録されたデータを共有するシステムを開示する。即ち、特許文献３は、係る論理ボリュームが複数の区域により構成されている場合、係る論理ボリュームの複数の区域を排他的に制御する技術を記載する。具体的に、特許文献３に開示された技術は、複数の区域から構成される当該論理ボリュームにおいて、未使用の区域がある場合、その未使用の区域を、他の情報処理装置からアクセスできるように開放する技術である。 Patent Document 3 discloses a system in which a plurality of information processing apparatuses share data recorded in the same logical volume. That is, Patent Document 3 describes a technique for exclusively controlling a plurality of areas of the logical volume when the logical volume is configured by a plurality of areas. Specifically, in the technology disclosed in Patent Document 3, when there is an unused area in the logical volume composed of a plurality of areas, the unused area can be accessed from another information processing apparatus. This technology is open to the public.
特開２００９－１４０４７９号公報JP 2009-140479 A 特開２０１０－００９２６５号公報JP 2010-009265 A 特開平１０－１６１９１９号公報Japanese Patent Laid-Open No. 10-161919
　しかしながら、特許文献１に記載された技術は、主メモリとハードディスクドライブとの間において、ページングイン及びページングアウト等の処理を実行する。このため、特許文献１に記載された技術は、係るページングイン及びページングアウトの実行時に、システムの性能が劣化する。 However, the technique described in Patent Document 1 performs processing such as paging in and paging out between the main memory and the hard disk drive. For this reason, in the technique described in Patent Document 1, the performance of the system deteriorates when paging-in and paging-out are performed.
　特許文献２に記載された技術は、プログラムの動作特性を踏まえて、ページ置換アルゴリズムによりスワップアウト処理を抑制するページの選択を行う。即ち、特許文献２に記載された技術は、最近使われたページのスワップアウトを抑制するような選択をすることになる。このため、特許文献２に記載された技術は、最近使われたページであっても、その後、いつ使うかわからないページのスワップアウトを抑制するおそれがある。 The technology described in Patent Document 2 selects pages that suppress swap-out processing by a page replacement algorithm based on the operation characteristics of the program. In other words, the technique described in Patent Document 2 makes a selection that suppresses swap-out of recently used pages. For this reason, the technique described in Patent Document 2 may suppress the swap-out of a page that is not used at a later time even if it is a recently used page.
　特許文献３に記載された技術は、論理ボリュームの未使用の区域を開放するため、開放する区域を選択する際に、その区域のデータが今後使われないのか否かが考慮されていない。 In the technique described in Patent Document 3, an unused area of a logical volume is released. Therefore, when selecting an area to be released, it is not considered whether or not data in that area will not be used in the future.
　本発明は、上記課題を鑑みなされた。即ち、本発明は、ホストプロセッサとハードウェアアクセラレータとを有する情報処理装置において、処理実行中のデータ転送に伴う性能劣化を防ぐことを１つの目的とする。 The present invention has been made in view of the above problems. That is, it is an object of the present invention to prevent performance degradation associated with data transfer during execution of processing in an information processing apparatus having a host processor and a hardware accelerator.
　上記目的を達成するために、本発明に係る情報処理装置は、
　ホストプロセッサに接続された第１メモリ領域とハードウェアアクセラレータに接続された第２メモリ領域とを用いて行われる仮想記憶処理を管理する仮想記憶管理手段と、
　前記第１メモリ領域と前記第２メモリ領域との間において転送されるデータに基づいて、前記第２メモリ領域におけるデータ退避の設定及び該設定の解除を行うよう前記仮想記憶管理手段を制御するデータ転送制御手段と、を備える。 In order to achieve the above object, an information processing apparatus according to the present invention provides:
Virtual memory management means for managing virtual memory processing performed using a first memory area connected to the host processor and a second memory area connected to the hardware accelerator;
Data for controlling the virtual memory management means to set and release the data saving in the second memory area based on data transferred between the first memory area and the second memory area Transfer control means.
　上記目的を達成するために、本発明に係る情報処理方法は、
　コンピュータが、
　　ホストプロセッサに接続された第１メモリ領域とハードウェアアクセラレータに接続された第２メモリ領域とを用いて行われる仮想記憶処理を仮想記憶管理手段によって管理し、
　　前記第１メモリ領域と前記第２メモリ領域との間において転送されるデータに基づいて、前記第２メモリ領域におけるデータ退避の設定及び該設定の解除を行うよう前記仮想記憶管理手段の動作を制御する。 In order to achieve the above object, an information processing method according to the present invention includes:
Computer
Managing virtual memory processing performed using the first memory area connected to the host processor and the second memory area connected to the hardware accelerator by the virtual memory managing means;
Based on the data transferred between the first memory area and the second memory area, the operation of the virtual memory management means is controlled so as to set and release the data saving in the second memory area. To do.
　上記目的を達成するために、本発明に係るコンピュータプログラムは、ホストプロセッサに接続された第１メモリ領域とハードウェアアクセラレータに接続された第２メモリ領域とを用いて行われる仮想記憶処理を管理する仮想記憶管理処理と、前記第１メモリ領域と前記第２メモリ領域との間において転送されるデータに基づいて、前記第２メモリ領域におけるデータ退避の設定及び該設定の解除を行うよう前記仮想記憶管理処理を制御するデータ転送制御処理と、をコンピュータに実行させる。 In order to achieve the above object, a computer program according to the present invention manages virtual memory processing performed using a first memory area connected to a host processor and a second memory area connected to a hardware accelerator. Based on the virtual memory management process and data transferred between the first memory area and the second memory area, the virtual memory is configured to set and release the data save in the second memory area. Data transfer control processing for controlling management processing is executed by a computer.
　尚、係る同目的は、当該コンピュータプログラムを格納したコンピュータ読み取り可能な記憶媒体によっても達成することができる。 The same object can be achieved by a computer-readable storage medium storing the computer program.
　本発明の情報処理装置によれば、ホストプロセッサとハードウェアアクセラレータとを有する情報処理装置において、処理実行中のデータ転送に伴う性能劣化を防ぐことができる。 According to the information processing apparatus of the present invention, in an information processing apparatus having a host processor and a hardware accelerator, it is possible to prevent performance deterioration due to data transfer during processing execution.
本実施形態に係る情報処理装置１を実現可能な情報処理装置（コンピュータ）のハードウェア構成例を示す図である。It is a figure which shows the hardware structural example of the information processing apparatus (computer) which can implement | achieve the information processing apparatus 1 which concerns on this embodiment. 第１の実施形態に係る情報処理装置１の機能構成を例示するブロック図である。It is a block diagram which illustrates functional composition of information processor 1 concerning a 1st embodiment. 第１の実施形態に係る情報処理装置１における処理の流れを示すフローチャートである。It is a flowchart which shows the flow of the process in the information processing apparatus 1 which concerns on 1st Embodiment. 第２の実施形態に係る情報処理装置２の機能構成を例示するブロック図である。It is a block diagram which illustrates functional composition of information processor 2 concerning a 2nd embodiment. 第２の実施形態に係る情報処理装置２における処理の流れを示すフローチャートである。It is a flowchart which shows the flow of a process in the information processing apparatus 2 which concerns on 2nd Embodiment. 第３の実施形態に係る情報処理装置３の機能構成を例示するブロック図である。It is a block diagram which illustrates functional composition of information processor 3 concerning a 3rd embodiment. 第３の実施形態に係る情報処理装置３における処理の流れを示すフローチャートである。It is a flowchart which shows the flow of a process in the information processing apparatus 3 which concerns on 3rd Embodiment. 第４の実施形態に係る情報処理装置４の機能構成を例示するブロック図である。It is a block diagram which illustrates functional composition of information processor 4 concerning a 4th embodiment. 第４の実施形態に係る情報処理装置４における処理の流れを示すフローチャートである。It is a flowchart which shows the flow of a process in the information processing apparatus 4 which concerns on 4th Embodiment. 本発明に関連する仮想記憶管理方式を用いた情報処理システム５の機能構成を例示するブロック図である。It is a block diagram which illustrates the function structure of the information processing system 5 using the virtual memory management system relevant to this invention. 本発明に関連する仮想記憶管理方式を用いた情報処理システム５における処理の流れを示すフローチャートである。It is a flowchart which shows the flow of a process in the information processing system 5 using the virtual memory management system relevant to this invention.
　本発明の実施形態について、図面を参照して詳細に説明する。 Embodiments of the present invention will be described in detail with reference to the drawings.
　＜第１の実施形態＞
　はじめに、本発明の第１の実施形態に係る情報処理装置１について説明する。 <First Embodiment>
First, the information processing apparatus 1 according to the first embodiment of the present invention will be described.
　図１は、本発明の第１の実施形態に係る情報処理装置１を実現可能な情報処理装置（コンピュータ）のハードウェア構成例を示す図である。情報処理装置１は、図１に例示する構成を有する。即ち、
　　・ＣＰＵ（Central Processing Unit）１０、
　　・メモリ１２、
　　・ＨＤＤ（ハードディスクドライブ）１４、
　　・図示しないネットワークを介して通信を行う通信ＩＦ（インタフェース）１６、
　　・入力装置１８、
　　・出力装置２０、
　　・ＣＤ（コンパクトディスク）等のコンピュータ読み取り可能な記憶媒体２４に記憶された情報を読み取り可能なリーダーライター２２。 FIG. 1 is a diagram illustrating a hardware configuration example of an information processing apparatus (computer) capable of realizing the information processing apparatus 1 according to the first embodiment of the present invention. The information processing apparatus 1 has a configuration illustrated in FIG. That is,
CPU (Central Processing Unit) 10,
-Memory 12,
HDD (hard disk drive) 14,
A communication IF (interface) 16 for performing communication via a network (not shown),
・ Input device 18,
-Output device 20,
A reader / writer 22 that can read information stored in a computer-readable storage medium 24 such as a CD (compact disk).
　そして、上記の各構成要素は、バス２６を通して互いに接続されており、互いにデータの入出力を行うことができる。 The above-described components are connected to each other through the bus 26 and can input / output data to / from each other.
　本実施形態に係る情報処理装置１は、メモリ１２又はＨＤＤ１４に記憶されているコンピュータプログラム（以下、「プログラム」と称する）をＣＰＵ１０が実行する。または、情報処理装置１は、ＣＰＵ１０が記憶媒体２４に記憶されているプログラムを実行する。ＣＰＵ１０において実行するプログラムは、通信ＩＦ１６、入力装置１８あるいはリーダーライター２２を介して外部から取得してもよい。また、表示が必要な場合、ＣＰＵ１０は出力装置２０に出力結果を表示する。図１に示す情報処理装置１のハードウェア構成例は、後述する実施形態にも適用可能である。 In the information processing apparatus 1 according to the present embodiment, the CPU 10 executes a computer program (hereinafter referred to as “program”) stored in the memory 12 or the HDD 14. Alternatively, in the information processing apparatus 1, the CPU 10 executes a program stored in the storage medium 24. The program executed in the CPU 10 may be acquired from the outside via the communication IF 16, the input device 18, or the reader / writer 22. When display is necessary, the CPU 10 displays the output result on the output device 20. The hardware configuration example of the information processing apparatus 1 illustrated in FIG. 1 can also be applied to embodiments described later.
　図２は、本発明の第１の実施形態に係る情報処理装置１の機能構成を例示するブロック図である。例えば、後述する本発明の実施形態に係る情報処理装置は、サーバ等である。図２に示すように、第１の実施形態に係る情報処理装置１は、例えば以下の構成を有する。即ち、
　　・ホストプロセッサ１０２、
　　・ホストプロセッサ１０２がアクセスする主メモリ１０４（第１のメモリ領域）、
　　・ハードウェアアクセラレータ１０６、
　　・ハードウェアアクセラレータ１０６がアクセスするアクセラレータメモリ１０８（第２のメモリ領域）、
　　・データ転送制御部１１０。 FIG. 2 is a block diagram illustrating the functional configuration of the information processing apparatus 1 according to the first embodiment of the invention. For example, an information processing apparatus according to an embodiment of the present invention described later is a server or the like. As illustrated in FIG. 2, the information processing apparatus 1 according to the first embodiment has the following configuration, for example. That is,
A host processor 102,
A main memory 104 (first memory area) accessed by the host processor 102,
Hardware accelerator 106,
An accelerator memory 108 (second memory area) accessed by the hardware accelerator 106;
Data transfer control unit 110.
　例えば、ハードウェアアクセラレータ１０６には、メニコアアクセラレータやグラフィックアクセラレータ等が含まれる。 For example, the hardware accelerator 106 includes a menicore accelerator, a graphic accelerator, and the like.
　ハードウェアアクセラレータ１０６は、仮想記憶管理部１１２を有する。また、ホストプロセッサ１０２及びハードウェアアクセラレータ１０６は、以下に説明する仮想記憶管理部１１２とは異なる不図示の仮想記憶管理機能を有することとする。但し、係る不図示の仮想記憶管理機能自体現在では、一般的に知られた技術を採用することができるので、本実施形態における説明は省略する。 The hardware accelerator 106 includes a virtual memory management unit 112. The host processor 102 and the hardware accelerator 106 have a virtual memory management function (not shown) different from the virtual memory management unit 112 described below. However, since the virtual storage management function itself (not shown) itself can employ a generally known technique, the description in this embodiment will be omitted.
　本実施形態においては、ハードウェアアクセラレータ１０６が、仮想記憶管理部１１２を有する構成について説明するが、仮想記憶管理部１１２は、ハードウェアアクセラレータ１０６が有していなくてもよい。例えば、ホストプロセッサ１０２あるいは外部装置等は、仮想記憶管理部１１２を有していてもよい。 In the present embodiment, a configuration in which the hardware accelerator 106 includes the virtual memory management unit 112 will be described. However, the virtual memory management unit 112 may not include the hardware accelerator 106. For example, the host processor 102 or an external device may have a virtual memory management unit 112.
　さらに、情報処理装置１は、記憶装置（ハードディスクドライブ等）１１４にデータを読み書き可能である。例えば、記憶装置１１４は、情報処理装置１が備えていてもよいし、外部装置として設置されていてもよい。 Furthermore, the information processing apparatus 1 can read / write data from / to the storage device (hard disk drive or the like) 114. For example, the storage device 114 may be included in the information processing apparatus 1 or may be installed as an external device.
　ホストプロセッサ１０２は、プログラムに従って処理Ａを実行する。処理Ａは、ホストプロセッサ１０２が実行すべき処理全体を表わし、後述するハードウェアアクセラレータ１０６が実行する処理Ｂ等を含む複数の処理からなる。ホストプロセッサ１０２は、処理Ｂ等の複数の処理を含む一連の処理Ａを完了した場合、動作を終了する。また、ホストプロセッサ１０２は、ハードウェアアクセラレータ１０６に関する制御を行う。具体的には、ホストプロセッサ１０２は、ハードウェアアクセラレータ１０６における処理に必要なデータを、主メモリ１０４からアクセラレータメモリ１０８に転送する。 The host processor 102 executes process A according to the program. The process A represents the entire process to be executed by the host processor 102, and includes a plurality of processes including a process B executed by a hardware accelerator 106 to be described later. When the host processor 102 completes a series of processes A including a plurality of processes such as the process B, the host processor 102 ends the operation. In addition, the host processor 102 performs control related to the hardware accelerator 106. Specifically, the host processor 102 transfers data necessary for processing in the hardware accelerator 106 from the main memory 104 to the accelerator memory 108.
　ハードウェアアクセラレータ１０６は、主メモリ１０４からアクセラレータメモリ１０８に転送されたデータを用いて処理Ｂを実行する。ハードウェアアクセラレータ１０６が実行する処理Ｂは、ホストプロセッサ１０２が実行する処理Ａに含まれる複数の処理のうち、ハードウェアアクセラレータ１０６に振り分けられた処理である。処理Ｂの振り分け手法については、現在では一般的な技術を採用できるので、本実施例における説明を省略する。係る処理Ｂが完了した場合、ハードウェアアクセラレータ１０６は、処理結果をアクセラレータメモリ１０８から主メモリ１０４に転送する。 The hardware accelerator 106 executes the process B using the data transferred from the main memory 104 to the accelerator memory 108. The process B executed by the hardware accelerator 106 is a process distributed to the hardware accelerator 106 among a plurality of processes included in the process A executed by the host processor 102. As for the distribution method of the process B, since a general technique can be adopted at present, the description in this embodiment is omitted. When the processing B is completed, the hardware accelerator 106 transfers the processing result from the accelerator memory 108 to the main memory 104.
　仮想記憶管理部１１２は、アクセラレータメモリ１０８のメモリ領域を管理する。仮想記憶管理部１１２は、アクセラレータメモリ１０８のメモリ領域において、必要とするメモリ領域が確保できなくなると、アクセラレータメモリ１０８に確保されているメモリ領域の一部を選択する。そして、仮想記憶管理部１１２は、選択した当該一部のメモリ領域に記載されているデータを、記憶装置１１４におけるスワップ領域に退避させる（スワップアウト）。 The virtual memory management unit 112 manages the memory area of the accelerator memory 108. When the necessary memory area cannot be secured in the memory area of the accelerator memory 108, the virtual storage management unit 112 selects a part of the memory area secured in the accelerator memory 108. Then, the virtual storage management unit 112 saves the data described in the selected partial memory area to the swap area in the storage device 114 (swap out).
　データ転送制御部１１０は、仮想記憶管理部１１２と連携することにより、主メモリ１０４とアクセラレータメモリ１０８との間におけるデータの転送を制御する。具体的には、データ転送制御部１１０は、仮想記憶管理部１１２と連携し、アクセラレータメモリ１０８におけるメモリ領域に格納されているデータを退避するよう設定を行う。例えば、データ転送制御部１１０は、アクセラレータメモリ１０８の特定のメモリ領域におけるデータ退避の対象外設定（スワップ対象外設定）及びその設定の解除を行う。スワップ対象外設定とは、当該メモリ領域をデータ退避のための対象領域から除外する手続である。係るスワップ対象外設定は、アクセラレータメモリ１０８における特定のメモリ領域がスワップされる頻度を減らす設定であればよい。例えば、データ転送制御部１１０は、アクセラレータメモリ１０８における特定のメモリ領域が完全にスワップされないよう設定してもよいし、スワップされる頻度を少なくする（小さくする）よう設定してもよい。 The data transfer control unit 110 controls data transfer between the main memory 104 and the accelerator memory 108 in cooperation with the virtual memory management unit 112. Specifically, the data transfer control unit 110 cooperates with the virtual memory management unit 112 to perform setting so as to save the data stored in the memory area in the accelerator memory 108. For example, the data transfer control unit 110 performs non-target setting for data saving (non-swap setting) in a specific memory area of the accelerator memory 108 and cancels the setting. The non-swap setting is a procedure for excluding the memory area from the target area for saving data. Such a non-swap setting may be any setting that reduces the frequency with which a specific memory area in the accelerator memory 108 is swapped. For example, the data transfer control unit 110 may be set so that a specific memory area in the accelerator memory 108 is not completely swapped, or may be set to reduce (reduce) the frequency of swapping.
　次に、情報処理装置１における処理の流れを説明する。 Next, the flow of processing in the information processing apparatus 1 will be described.
　図３は、本発明の第１の実施形態に係る情報処理装置１における処理の流れを示すフローチャートである。 FIG. 3 is a flowchart showing the flow of processing in the information processing apparatus 1 according to the first embodiment of the present invention.
　ステップＳ１０２において、ホストプロセッサ１０２は、当該プログラムに従って処理Ａの実行を開始する。 In step S102, the host processor 102 starts executing the process A according to the program.
　ステップＳ１０４において、データ転送制御部１１０は、仮想記憶管理部１１２と連携し、アクセラレータメモリ１０８のメモリ領域をスワップの対象外として設定する。具体的に、データ転送制御部１１０は、仮想記憶管理部１１２と連携する。そして、データ転送制御部１１０は、特定のメモリ領域に対して、記憶装置１１４におけるスワップ領域に退避されているデータを、記憶装置１１４におけるスワップ領域からアクセラレータメモリ１０８に全て読み込む処理を実施する。ここで、当該特定のメモリ領域とは、ハードウェアアクセラレータ１０６が処理Ｂに用いるアクセラレータメモリ１０８が有するメモリ領域である。そして、ハードウェアアクセラレータ１０６は、処理Ｂに用いるアクセラレータメモリ１０８のメモリ領域をスワップ対象外に設定する。 In step S104, the data transfer control unit 110 cooperates with the virtual memory management unit 112 to set the memory area of the accelerator memory 108 as a non-swap target. Specifically, the data transfer control unit 110 cooperates with the virtual memory management unit 112. Then, the data transfer control unit 110 performs a process of reading all data saved in the swap area in the storage device 114 from the swap area in the storage device 114 into the accelerator memory 108 for a specific memory area. Here, the specific memory area is a memory area included in the accelerator memory 108 used by the hardware accelerator 106 for processing B. Then, the hardware accelerator 106 sets the memory area of the accelerator memory 108 used for the process B to be excluded from swapping.
　ステップＳ１０６において、ホストプロセッサ１０２は、ハードウェアアクセラレータ１０６が処理Ｂに用いるデータを、主メモリ１０４からアクセラレータメモリ１０８に転送する。 In step S106, the host processor 102 transfers the data used by the hardware accelerator 106 for processing B from the main memory 104 to the accelerator memory 108.
　ステップＳ１０８において、ハードウェアアクセラレータ１０６は、当該プログラムに記述された一連の処理（処理Ａ）のうち、指定された一部の処理である処理Ｂを実行する。具体的には、ハードウェアアクセラレータ１０６は、ステップＳ１０６において、ホストプロセッサ１０２から転送されたデータを用いて処理Ｂを実行する。 In step S108, the hardware accelerator 106 executes a process B that is a part of a specified process among a series of processes (process A) described in the program. Specifically, the hardware accelerator 106 executes process B using the data transferred from the host processor 102 in step S106.
　ステップＳ１１０において、例えばホストプロセッサ１０２は、ハードウェアアクセラレータ１０６における処理結果を、アクセラレータメモリ１０８から主メモリ１０４に転送する。 In step S110, for example, the host processor 102 transfers the processing result in the hardware accelerator 106 from the accelerator memory 108 to the main memory 104.
　ステップＳ１１２において、データ転送制御部１１０は、仮想記憶管理部１１２と連携し、ステップＳ１０４において設定されたアクセラレータメモリ１０８におけるスワップ対象外の設定を解除する。 In step S112, the data transfer control unit 110 cooperates with the virtual memory management unit 112 to cancel the setting not to be swapped in the accelerator memory 108 set in step S104.
　尚、図示していないが、ステップＳ１０２からステップＳ１１２の処理は、繰り返し行われる。処理Ａに含まれる複数の処理が完了した場合に、ホストプロセッサ１０２は、処理Ａの処理結果を出力することにより、情報処理装置１の動作は終了する。後述する実施形態に係る情報処理装置も、処理Ａの処理結果が出力された場合に、動作を終了する。 Although not shown, the processing from step S102 to step S112 is repeatedly performed. When a plurality of processes included in the process A are completed, the host processor 102 outputs the process result of the process A, whereby the operation of the information processing apparatus 1 ends. The information processing apparatus according to an embodiment to be described later also ends the operation when the processing result of the processing A is output.
　なお、上述した処理の流れの変形例として、ステップＳ１０４とステップＳ１０６の実行順序は、逆であってもよい。即ち、主メモリ１０４からアクセラレータメモリ１０８にデータを転送した後に、アクセラレータメモリ１０８のメモリ領域をデータ退避の対象外として設定してもよい。 As a modification of the above-described process flow, the execution order of step S104 and step S106 may be reversed. That is, after the data is transferred from the main memory 104 to the accelerator memory 108, the memory area of the accelerator memory 108 may be set as a data saving target.
　また、ステップＳ１１０とステップＳ１１２の実行順序は、逆であってもよい。即ち、アクセラレータメモリ１１２のメモリ領域に設定されたデータ転送の対象外とする設定を解除した後に、アクセラレータメモリ１０８から主メモリ１０４に処理結果を転送してもよい。 Further, the execution order of step S110 and step S112 may be reversed. That is, the processing result may be transferred from the accelerator memory 108 to the main memory 104 after canceling the setting to be excluded from data transfer set in the memory area of the accelerator memory 112.
　以上説明したように、本発明の第１の実施形態に係る情報処理装置１は、ホストプロセッサとハードウェアアクセラレータとを有する情報処理装置において、処理実行中のデータ転送に伴う性能劣化を防ぐことができる。その理由は、ハードウェアアクセラレータ１０６が処理Ｂを実行しているフェーズ（ステップＳ１０８）においては、処理Ｂを実行する際に用いているアクセラレータメモリ１０８のメモリ領域に記載されているデータがスワップアウトされない、あるいはされにくくなっているためである。 As described above, the information processing apparatus 1 according to the first embodiment of the present invention can prevent performance degradation due to data transfer during processing execution in an information processing apparatus having a host processor and a hardware accelerator. it can. The reason is that in the phase in which the hardware accelerator 106 is executing the process B (step S108), the data described in the memory area of the accelerator memory 108 used when executing the process B is not swapped out. It is because it becomes difficult to be done.
　従って、本実施形態によれば、ハードウェアアクセラレータ１０６が処理Ｂを実行しているフェーズ（ステップＳ１０８）において、ページミスが発生しない、あるいはページミスの頻度が低くなる。 Therefore, according to the present embodiment, a page miss does not occur or the frequency of page misses is low in the phase (step S108) in which the hardware accelerator 106 executes the process B.
　＜第２の実施形態＞
　次に、上述した本発明の第１の実施形態に係る情報処理装置１を基本とする第２の実施形態に係る情報処理装置２について説明する。 <Second Embodiment>
Next, an information processing apparatus 2 according to a second embodiment based on the information processing apparatus 1 according to the first embodiment of the present invention described above will be described.
　図４は、本発明の第２の実施形態に係る情報処理装置２の機能構成を例示するブロック図である。図４に示すように、第２の実施形態に係る情報処理装置２は、データ転送制御部１１０がデータ転送制御部２１０に置き換えられた構成が、第１の実施形態に係る情報処理装置１と異なる。それ以外については、第１の実施形態に係る情報処理装置１と同様のため、同一の図面番号を付与すると共に、重複する説明は省略する。 FIG. 4 is a block diagram illustrating the functional configuration of the information processing apparatus 2 according to the second embodiment of the invention. As illustrated in FIG. 4, the information processing apparatus 2 according to the second embodiment has a configuration in which the data transfer control unit 110 is replaced with a data transfer control unit 210, as compared with the information processing apparatus 1 according to the first embodiment. Different. Other than that, since it is the same as that of the information processing apparatus 1 according to the first embodiment, the same drawing number is given, and a duplicate description is omitted.
　ホストプロセッサ１０２は、当該プログラムに従って処理Ａの実行を開始し、データを主メモリ１０４からアクセラレータメモリ１０８に転送する。 The host processor 102 starts execution of the process A according to the program, and transfers data from the main memory 104 to the accelerator memory 108.
　ハードウェアアクセラレータ１０６は、アクセラレータメモリ１０８に転送されたデータを用いて処理Ｂを実行し、処理結果をアクセラレータメモリ１０８から主メモリ１０４に転送する。 The hardware accelerator 106 executes the process B using the data transferred to the accelerator memory 108 and transfers the processing result from the accelerator memory 108 to the main memory 104.
　仮想記憶管理部１１２は、アクセラレータメモリ１０８のメモリ領域を管理し、アクセラレータメモリ１０８のデータを、記憶装置１１４におけるスワップ領域に退避（スワップアウト）させる。 The virtual memory management unit 112 manages the memory area of the accelerator memory 108, and saves (swaps out) the data in the accelerator memory 108 to the swap area in the storage device 114.
　データ転送制御部２１０は、仮想記憶管理部１１２と連携することにより、主メモリ１０４とアクセラレータメモリ１０８との間におけるデータの転送を制御する。具体的には、データ転送制御部２１０は、仮想記憶管理部１１２と連携し、アクセラレータメモリ１０８における特定のメモリ領域をスワップアウトする。例えば、アクセラレータメモリ１０８における特定のメモリ領域は、以降のハードウェアアクセラレータ１０６が実行する処理Ｂにおいて、再利用されないメモリ領域でもよい。 The data transfer control unit 210 controls data transfer between the main memory 104 and the accelerator memory 108 in cooperation with the virtual memory management unit 112. Specifically, the data transfer control unit 210 cooperates with the virtual memory management unit 112 to swap out a specific memory area in the accelerator memory 108. For example, the specific memory area in the accelerator memory 108 may be a memory area that is not reused in the subsequent process B executed by the hardware accelerator 106.
　例えば、データ転送制御部２１０は、アクセラレータメモリ１０８から主メモリ１０４に転送されたデータ（ハードウェアアクセラレータ１０６において処理されたデータ）のメモリ領域をスワップアウトするよう決定してもよい。また、スワップアウトされる特定のメモリ領域は、主メモリ１０４からアクセラレータメモリ１０８に転送されたデータのメモリ領域としてもよい。また、スワップアウトされる特定のメモリ領域は、ユーザによって記述されたプログラムによって指定されたメモリ領域としてもよい。また、スワップアウトされる特定のメモリ領域は、上記説明した特定手法の組み合わせにより指定してもよい。 For example, the data transfer control unit 210 may decide to swap out the memory area of the data transferred from the accelerator memory 108 to the main memory 104 (data processed in the hardware accelerator 106). The specific memory area swapped out may be a memory area of data transferred from the main memory 104 to the accelerator memory 108. The specific memory area to be swapped out may be a memory area specified by a program written by the user. The specific memory area to be swapped out may be specified by a combination of the specific methods described above.
　次に、情報処理装置２における処理の流れを説明する。 Next, the flow of processing in the information processing apparatus 2 will be described.
　図５は、本発明の第２の実施形態に係る情報処理装置２における処理の流れを示すフローチャートである。 FIG. 5 is a flowchart showing the flow of processing in the information processing apparatus 2 according to the second embodiment of the present invention.
　ステップＳ１０２において、ホストプロセッサ１０２は、当該プログラムに従って処理Ａの実行を開始する。ステップＳ１０６において、ホストプロセッサ１０２は、ハードウェアアクセラレータ１０６が処理Ｂに用いるデータを、主メモリ１０４からアクセラレータメモリ１０８に転送する。ステップＳ１０８において、ハードウェアアクセラレータ１０６は、処理Ｂを実行する。ステップＳ１１０において、例えばホストプロセッサ１０２は、ハードウェアアクセラレータ１０６における処理結果を、アクセラレータメモリ１０８から主メモリ１０４に転送する。 In step S102, the host processor 102 starts executing the process A according to the program. In step S106, the host processor 102 transfers data used by the hardware accelerator 106 for processing B from the main memory 104 to the accelerator memory 108. In step S108, the hardware accelerator 106 executes process B. In step S <b> 110, for example, the host processor 102 transfers the processing result in the hardware accelerator 106 from the accelerator memory 108 to the main memory 104.
　ステップＳ２２０において、データ転送制御部２１０が、仮想記憶管理部１１２と連携し、アクセラレータメモリ１１２における特定のメモリ領域をスワップアウトさせる。特定のメモリ領域の決定手法は、上記説明した通りである。 In step S220, the data transfer control unit 210 cooperates with the virtual memory management unit 112 to swap out a specific memory area in the accelerator memory 112. The method for determining a specific memory area is as described above.
　以上説明したように、本発明の第２の実施形態に係る情報処理装置２は、ハードウェアアクセラレータ１０６が処理Ｂを実行しているフェーズ（ステップＳ１０８）において、スワップ発生の頻度を減らすことにより、性能劣化を抑えることができる。その理由は、積極的にデータの保持が不要なメモリ領域を、仮想記憶管理部１１２が開放するからである。 As described above, the information processing apparatus 2 according to the second embodiment of the present invention reduces the frequency of occurrence of swap in the phase in which the hardware accelerator 106 executes the process B (step S108). Performance degradation can be suppressed. The reason is that the virtual storage management unit 112 frees a memory area that does not actively hold data.
　＜第３の実施形態＞
　次に、本発明の第３の実施形態に係る情報処理装置３について説明する。 <Third Embodiment>
Next, an information processing apparatus 3 according to the third embodiment of the present invention will be described.
　図６は、本発明の第３の実施形態に係る情報処理装置３の機能構成を例示するブロック図である。図６に示すように、第３の実施形態に係る情報処理装置３は、データ転送制御部１１０がデータ転送制御部３１０に置き換えられ、ホストプロセッサ１０２がデータ複製部３１６を備える構成が、第１の実施形態及び第２の実施形態に係る情報処理装置１と異なる。それ以外については、第１の実施形態及び第２の実施形態に係る情報処理装置１及び情報処理装置２と同様のため、同一の図面番号を付与すると共に、重複する説明は省略する。 FIG. 6 is a block diagram illustrating the functional configuration of the information processing apparatus 3 according to the third embodiment of the invention. As illustrated in FIG. 6, the information processing apparatus 3 according to the third embodiment has a configuration in which the data transfer control unit 110 is replaced with a data transfer control unit 310 and the host processor 102 includes a data replication unit 316. This is different from the information processing apparatus 1 according to the second embodiment and the second embodiment. Other than that, since it is the same as the information processing apparatus 1 and the information processing apparatus 2 according to the first embodiment and the second embodiment, the same drawing number is given, and a duplicate description is omitted.
　ホストプロセッサ１０２は、当該プログラムに従って処理Ａの実行を開始し、データを主メモリ１０４からアクセラレータメモリ１０８に転送する。 The host processor 102 starts execution of the process A according to the program, and transfers data from the main memory 104 to the accelerator memory 108.
　ハードウェアアクセラレータ１０６は、アクセラレータメモリ１０８に転送されたデータを用いて処理Ｂを実行し、処理結果をアクセラレータメモリ１０８からデータ複製部３１６に転送する。 The hardware accelerator 106 executes process B using the data transferred to the accelerator memory 108, and transfers the processing result from the accelerator memory 108 to the data replication unit 316.
　仮想記憶管理部１１２は、データ複製部３１６に転送された処理結果のメモリ領域をスワップアウト済みと設定する。 The virtual memory management unit 112 sets the memory area of the processing result transferred to the data replication unit 316 as swapped out.
　データ転送制御部３１０は、仮想記憶管理部１１２と連携することにより、データの転送を制御する。具体的には、データ転送制御部３１０は、ハードウェアアクセラレータ１０６において処理された結果を、データ複製部３１６に転送するよう制御する。 The data transfer control unit 310 controls data transfer by cooperating with the virtual memory management unit 112. Specifically, the data transfer control unit 310 controls to transfer the result processed in the hardware accelerator 106 to the data replication unit 316.
　データ複製部３１６は、アクセラレータメモリ１０８から転送された処理結果を主メモリの指定されたメモリ領域に書き込む。さらに、データ複製部３１６は、アクセラレータメモリ１０８から転送された処理結果を複製し、複製した処理結果を記憶装置１１４におけるスワップ領域に退避する。 The data replication unit 316 writes the processing result transferred from the accelerator memory 108 to the designated memory area of the main memory. Further, the data duplication unit 316 duplicates the processing result transferred from the accelerator memory 108 and saves the duplicated processing result in the swap area in the storage device 114.
　次に、情報処理装置３における処理の流れを説明する。 Next, the flow of processing in the information processing apparatus 3 will be described.
　図７は、本発明の第３の実施形態に係る情報処理装置３における処理の流れを示すフローチャートである。 FIG. 7 is a flowchart showing the flow of processing in the information processing apparatus 3 according to the third embodiment of the present invention.
　ステップＳ１０２において、ホストプロセッサ１０２は、当該プログラムに従って処理Ａの実行を開始する。ステップＳ１０６において、ホストプロセッサ１０２は、ハードウェアアクセラレータ１０６が処理Ｂに用いるデータを、主メモリ１０４からアクセラレータメモリ１０８に転送する。ステップＳ１０８において、ハードウェアアクセラレータ１０６は、処理Ｂを実行する。 In step S102, the host processor 102 starts executing the process A according to the program. In step S106, the host processor 102 transfers data used by the hardware accelerator 106 for processing B from the main memory 104 to the accelerator memory 108. In step S108, the hardware accelerator 106 executes process B.
　ステップＳ３３２において、データ転送制御部３１０は、ハードウェアアクセラレータ１０６において処理された結果を、アクセラレータメモリ１０８からデータ複製部３１６に転送する。 In step S332, the data transfer control unit 310 transfers the result processed in the hardware accelerator 106 from the accelerator memory 108 to the data replication unit 316.
　ステップＳ３３４において、仮想記憶管理部１１２は、アクセラレータメモリ１０８において転送されたメモリ領域をスワップアウト済みに設定する。 In step S334, the virtual memory management unit 112 sets the memory area transferred in the accelerator memory 108 as swapped out.
　ステップＳ３３６において、データ複製部３１６は、アクセラレータメモリ１０８から転送された処理結果を、主メモリ１０４の特定のメモリ領域に書き込む。 In step S336, the data replication unit 316 writes the processing result transferred from the accelerator memory 108 into a specific memory area of the main memory 104.
　ステップＳ３３８において、データ複製部３１６は、アクセラレータメモリ１０８から転送された処理結果を複製し、複製した処理結果を記憶装置１１４におけるスワップ領域に退避する。 In step S338, the data copying unit 316 copies the processing result transferred from the accelerator memory 108, and saves the copied processing result in the swap area in the storage device 114.
　以上説明したように、本発明の第３の実施形態に係る情報処理装置３は、スワップアウトによる性能劣化を回避することができる。その理由は、ハードウェアアクセラレータ１０６とホストプロセッサ１０２との間におけるデータ転送を増やすことなく、データ転送にあわせてスワップアウトを実行することができるからである。 As described above, the information processing apparatus 3 according to the third embodiment of the present invention can avoid performance degradation due to swap-out. The reason is that swap-out can be executed in accordance with the data transfer without increasing the data transfer between the hardware accelerator 106 and the host processor 102.
　＜第４の実施形態＞
　次に、本発明の第４の実施形態に係る情報処理装置４について説明する。 <Fourth Embodiment>
Next, an information processing apparatus 4 according to the fourth embodiment of the present invention will be described.
　図８は、本発明の第４の実施形態に係る情報処理装置４の機能構成を例示するブロック図である。図８に示すように、第４の実施形態に係る情報処理装置４は、データ転送制御部１１０がデータ転送制御部４１０に置き換えられた構成が、第１の実施形態に係る情報処理装置１と異なる。それ以外については、第１の実施形態に係る情報処理装置１と同様のため、同一の図面番号を付与すると共に、重複する説明は省略する。 FIG. 8 is a block diagram illustrating the functional configuration of the information processing apparatus 4 according to the fourth embodiment of the invention. As illustrated in FIG. 8, the information processing device 4 according to the fourth embodiment has a configuration in which the data transfer control unit 110 is replaced with a data transfer control unit 410, as compared with the information processing device 1 according to the first embodiment. Different. Other than that, since it is the same as that of the information processing apparatus 1 according to the first embodiment, the same drawing number is given, and a duplicate description is omitted.
　ホストプロセッサ１０２は、当該プログラムに従って処理Ａの実行を開始する。また、ホストプロセッサ１０２は、指定された領域を主メモリ１０４から、アクセラレータメモリ１０８にデータを転送する。 The host processor 102 starts executing the process A according to the program. Further, the host processor 102 transfers the designated area from the main memory 104 to the accelerator memory 108.
　データ転送制御部４１０は、仮想記憶管理部１１２と連携することにより、主メモリ１０４とアクセラレータメモリ１０８との間におけるデータの転送を制御する。具体的には、データ転送制御部４１０は、ハードウェアアクセラレータ１０６が実行する処理Ｂに用いるデータを確保するよう仮想記憶管理部１１２を制御する。 The data transfer control unit 410 controls data transfer between the main memory 104 and the accelerator memory 108 in cooperation with the virtual memory management unit 112. Specifically, the data transfer control unit 410 controls the virtual memory management unit 112 so as to secure data used for the process B executed by the hardware accelerator 106.
　仮想記憶管理部１１２は、アクセラレータメモリ１０８においてスワップアウトされたデータに対して、記憶装置１１４におけるスワップ領域からデータの読み込みを行わず、物理領域の割り当てを行うことにより、スワップイン済みと設定する。 The virtual storage management unit 112 sets the data swapped out in the accelerator memory 108 as being swapped in by allocating the physical area without reading the data from the swap area in the storage device 114.
　ハードウェアアクセラレータ１０６は、仮想記憶管理部１１２によりスワップイン済みと設定されたデータを用いて処理Ｂを実行し、処理結果をアクセラレータメモリ１０８から主メモリ１０４に転送する。 The hardware accelerator 106 executes the process B using the data set as swapped in by the virtual memory management unit 112 and transfers the processing result from the accelerator memory 108 to the main memory 104.
　次に、情報処理装置４における処理の流れを説明する。 Next, the flow of processing in the information processing apparatus 4 will be described.
　図９は、本発明の第４の実施形態に係る情報処理装置４における処理の流れを示すフローチャートである。 FIG. 9 is a flowchart showing the flow of processing in the information processing apparatus 4 according to the fourth embodiment of the present invention.
　ステップＳ１０２において、ホストプロセッサ１０２は、当該プログラムに従って処理Ａの実行を開始する。 In step S102, the host processor 102 starts executing the process A according to the program.
　ステップＳ４４２において、仮想記憶管理部１１２は、仮想記憶上において物理領域を割り当て、ハードウェアアクセラレータ１０６が実行する処理Ｂに用いるデータをスワップイン済みに設定する。具体的には、仮想記憶管理部１１２は、アクセラレータメモリ１０８からスワップアウトされた仮想記憶上のデータに対して物理領域を割り当てる。 In step S442, the virtual memory management unit 112 allocates a physical area on the virtual memory and sets the data used for the process B executed by the hardware accelerator 106 to be swapped in. Specifically, the virtual memory management unit 112 allocates a physical area to the data on the virtual memory swapped out from the accelerator memory 108.
　ステップＳ４４４において、例えばホストプロセッサ１０２は、主メモリ１０４からアクセラレータメモリ１０８に指定された領域のデータを転送する。 In step S444, for example, the host processor 102 transfers the data in the designated area from the main memory 104 to the accelerator memory 108.
　ステップＳ１０８において、ハードウェアアクセラレータ１０６は、処理Ｂを実行する。ステップＳ１１０において、例えばホストプロセッサ１０２は、ハードウェアアクセラレータ１０６における処理結果を、アクセラレータメモリ１０８から主メモリ１０４に転送する。 In step S108, the hardware accelerator 106 executes process B. In step S <b> 110, for example, the host processor 102 transfers the processing result in the hardware accelerator 106 from the accelerator memory 108 to the main memory 104.
　以上説明したように、本発明の第４の実施形態に係る情報処理装置４は、スワップインによる性能劣化を回避することができる。その理由は、ハードウェアアクセラレータ１０６とホストプロセッサ１０２との間におけるデータ転送を増やすことなく、データ転送にあわせてスワップインを実行することができるからである。 As described above, the information processing apparatus 4 according to the fourth embodiment of the present invention can avoid performance degradation due to swap-in. The reason is that the swap-in can be executed in accordance with the data transfer without increasing the data transfer between the hardware accelerator 106 and the host processor 102.
　以上、上述した実施形態を模範的な例として本発明を説明した。しかしながら、本発明は、上述した実施形態には限定されない。即ち、本発明は、本発明のスコープ内において、当業者が理解し得る様々な態様を適用することができる。 The present invention has been described above using the above-described embodiment as an exemplary example. However, the present invention is not limited to the above-described embodiment. That is, the present invention can apply various modes that can be understood by those skilled in the art within the scope of the present invention.
　この出願は、２０１３年３月１日に出願された日本出願特願２０１３－０４０９８２を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2013-040982 filed on March 1, 2013, the entire disclosure of which is incorporated herein.
　１，２，３，４　　情報処理装置
　５　　情報処理システム
　１０　　ＣＰＵ
　１２　　メモリ
　１４　　ＨＤＤ
　１６　　通信ＩＦ
　１８　　入力装置
　２０　　出力装置
　２２　　リーダーライター
　２４　　記憶媒体
　２６　　バス
　１０２，５０２　　ホストプロセッサ
　１０４，５０４　　主メモリ
　１０６、５０６　　ハードウェアアクセラレータ
　１０８，５０８　　アクセラレータメモリ
　１１０，２１０，３１０，４１０　　データ転送制御部
　１１２，５１２　　仮想記憶管理部
　１１４，５１４　　記憶装置（スワップ領域）
　３１６　　データ複製部 1, 2, 3, 4 Information processing device 5 Information processing system 10 CPU
12 Memory 14 HDD
16 Communication IF
18 Input device 20 Output device 22 Reader / writer 24 Storage medium 26 Bus 102, 502 Host processor 104, 504 Main memory 106, 506 Hardware accelerator 108, 508 Accelerator memory 110, 210, 310, 410 Data transfer control unit 112, 512 Virtual Storage management unit 114, 514 Storage device (swap area)
316 Data replication unit

Claims (8)

  1. 　ホストプロセッサに接続された第１メモリ領域とハードウェアアクセラレータに接続された第２メモリ領域とを用いて行われる仮想記憶処理を管理する仮想記憶管理手段と、
    　前記第１メモリ領域と前記第２メモリ領域との間において転送されるデータに基づいて、前記第２メモリ領域におけるデータ退避の設定及び該設定の解除を行うよう前記仮想記憶管理手段を制御するデータ転送制御手段と、
    を備える情報処理装置。     Virtual memory management means for managing virtual memory processing performed using a first memory area connected to the host processor and a second memory area connected to the hardware accelerator;
    Data for controlling the virtual memory management means to set and release the data saving in the second memory area based on data transferred between the first memory area and the second memory area Transfer control means;
    An information processing apparatus comprising:
  2. 　前記データ転送制御手段は、
    　　前記第１メモリ領域から転送される、前記ハードウェアアクセラレータにおいて実行される処理に必要なデータに基づいて、その処理に利用する前記第２メモリ領域をデータ退避の対象外に設定するよう前記仮想記憶管理手段を制御し、
    　　前記処理が完了するのに応じて、前記第１のメモリ領域に転送される処理結果のデータに基づいて、前記設定を解除するよう前記仮想記憶管理手段を制御する、
    請求項１に記載の情報処理装置。     The data transfer control means includes
    Based on the data transferred from the first memory area and necessary for the process executed by the hardware accelerator, the virtual memory is set so that the second memory area used for the process is excluded from the data save target. Control management means,
    In response to the completion of the process, the virtual storage management unit is controlled to release the setting based on data of a processing result transferred to the first memory area.
    The information processing apparatus according to claim 1.
  3. 　前記データ転送制御手段は、
    　　前記第２のメモリ領域から前記第１のメモリ領域に対して、前記処理結果を転送した際、転送した前記処理結果の情報に基づいて、前記処理に利用された前記第２のメモリ領域におけるメモリ領域のデータを退避するよう前記仮想記憶管理手段を制御する、
    請求項１または請求項２に記載の情報処理装置。     The data transfer control means includes
    When the processing result is transferred from the second memory area to the first memory area, the memory in the second memory area used for the processing based on the transferred processing result information Controlling the virtual memory management means to save the data in the area;
    The information processing apparatus according to claim 1 or 2.
  4. 　前記ホストプロセッサは、前記第２のメモリ領域から前記第１のメモリ領域に転送されるデータを複製するデータ複製手段を更に有し、
    　前記データ転送制御手段は、
    　　前記第２のメモリ領域から転送されるデータを前記第１のメモリ領域に書き込むよう前記データ複製手段を制御するとともに、前記複製手段によって複製された該データをスワップ領域にも書き込むよう前記データ複製手段を制御し、
    　　前記アクセラレータにおけるメモリ領域をデータ退避済みとして設定するよう前記仮想記憶管理手段を制御する、
    請求項１乃至３の何れかに記載の情報処理装置。     The host processor further includes data duplicating means for duplicating data transferred from the second memory area to the first memory area;
    The data transfer control means includes
    The data duplicating means controls the data duplicating means to write data transferred from the second memory area into the first memory area, and writes the data duplicated by the duplicating means into the swap area. Control
    Controlling the virtual storage management means to set the memory area in the accelerator as data saved;
    The information processing apparatus according to claim 1.
  5. 　前記データ転送制御手段は、
    　　前記ハードウェアアクセラレータにおいて実行される処理に必要なデータを転送する際に、前記仮想記憶において前記第２のメモリ領域から退避されたデータが存在する場合、前記仮想記憶における前記データについて物理領域を割り当てるよう前記仮想記憶管理手段を制御する
    請求項１乃至４の何れかに記載の情報処理装置。     The data transfer control means includes
    When transferring data necessary for processing executed in the hardware accelerator, if there is data saved from the second memory area in the virtual memory, a physical area is allocated for the data in the virtual memory. The information processing apparatus according to claim 1, wherein the virtual storage management unit is controlled.
  6. 　サーバであることを特徴とする請求項１乃至５の何れかに記載の情報処理装置。 6. The information processing apparatus according to claim 1, wherein the information processing apparatus is a server.
  7. 　コンピュータが、
    　　ホストプロセッサに接続された第１メモリ領域とハードウェアアクセラレータに接続された第２メモリ領域とを用いて行われる仮想記憶処理を仮想記憶管理手段によって管理し、
    　　前記第１メモリ領域と前記第２メモリ領域との間において転送されるデータに基づいて、前記第２メモリ領域におけるデータ退避の設定及び該設定の解除を行うよう前記仮想記憶管理手段の動作を制御する
    情報処理方法。     Computer
    Managing virtual memory processing performed using the first memory area connected to the host processor and the second memory area connected to the hardware accelerator by the virtual memory managing means;
    Based on the data transferred between the first memory area and the second memory area, the operation of the virtual memory management means is controlled so as to set and release the data saving in the second memory area. Information processing method.
  8. 　ホストプロセッサに接続された第１メモリ領域とハードウェアアクセラレータに接続された第２メモリ領域とを用いて行われる仮想記憶処理を管理する仮想記憶管理処理と、
    　前記第１メモリ領域と前記第２メモリ領域との間において転送されるデータに基づいて、前記第２メモリ領域におけるデータ退避の設定及び該設定の解除を行うよう前記仮想記憶管理処理を制御するデータ転送制御処理と、
    をコンピュータに実行させるコンピュータプログラムを格納したコンピュータ読み取り可能な記憶媒体。     A virtual memory management process for managing a virtual memory process performed using a first memory area connected to the host processor and a second memory area connected to the hardware accelerator;
    Data for controlling the virtual memory management process to set and release data saving in the second memory area based on data transferred between the first memory area and the second memory area Transfer control processing,
    A computer-readable storage medium that stores a computer program that causes a computer to execute.
PCT/JP2014/000965 2013-03-01 2014-02-25 Information processing device, information processing method, and memory medium WO2014132619A1 (en)

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