WO2014129386A1 - Command fifo circuit - Google Patents

Command fifo circuit Download PDF

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Publication number
WO2014129386A1
WO2014129386A1 PCT/JP2014/053408 JP2014053408W WO2014129386A1 WO 2014129386 A1 WO2014129386 A1 WO 2014129386A1 JP 2014053408 W JP2014053408 W JP 2014053408W WO 2014129386 A1 WO2014129386 A1 WO 2014129386A1
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circuit
signal
command
output
plurality
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PCT/JP2014/053408
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French (fr)
Japanese (ja)
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永田 恭一
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ピーエスフォー ルクスコ エスエイアールエル
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Priority to JP2013-030170 priority
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Publication of WO2014129386A1 publication Critical patent/WO2014129386A1/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Abstract

[Problem] To cause a command FIFO circuit to operate normally even in a case in which a DLL circuit is suspended at standby time. [Solution] The present invention is provided with: a point shifting circuit (110) which latches an internal command (COMIN) on the basis of input point signals (IN0 to IN3), and outputs an internal command (COMOUT) on the basis of output point signals (OUT0 to OUT3); a phase difference assessment circuit (150) which generates a count value (CNT) on the basis of an amount of time from activation of the input point signal (IN0) to activation of the output point signal (OUT0); and a phase difference setting circuit (160) which, on the basis of the count value (CNT), switches relationships between the input point signals (IN0 to IN3) and the output point signals (OUT0 to OUT3). According to the present invention, it is possible to suspend, at standby time, operation of a DLL circuit used in generation of the output point signals (OUT0 to OUT3), and therefore, it is possible to achieve reduction of current consumption.

Description

[Name of invention determined by ISA based on Rule 37.2] Command FIFO circuit

The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a command FIFO circuit that outputs an internal command at a timing based on a set latency.

Synchronous memories represented by synchronous DRAM (Synchronous Dynamic Random Access Memory) are widely used for main memory of personal computers. Since the synchronous memory inputs and outputs data in synchronization with a clock signal supplied from the controller, the data transfer rate can be increased by using a higher-speed clock signal.

However, even in a synchronous DRAM, the DRAM core is only an analog operation, and it is necessary to amplify a very weak charge by a sense operation. For this reason, the time from when the read command is issued until the first data is output cannot be shortened. After a predetermined delay time has elapsed since the read command was issued, the time is first synchronized with the external clock. Is output.

This delay time is generally called “CAS latency” and is set to an integral multiple of the clock period. For example, if the CAS latency is 5 (CL = 5), after the read command is taken in synchronization with the external clock, the first data is outputted in synchronization with the external clock after 5 cycles. A counter that counts such latency is called a “command FIFO circuit”.

The internal command output from the command FIFO circuit must be synchronized with the read data output timing. Therefore, as a signal for controlling the output timing of the internal command, it is necessary to use an output internal clock signal (LCLK) that defines the output timing of the read data. However, the internal clock signal input to the command FIFO circuit is not synchronized with the output internal clock signal (LCLK), but is synchronized with the internal clock signal (PCLK) obtained by buffering the external clock signal. is doing. For this reason, the command FIFO circuit also plays a role of transferring an internal command to a different internal clock signal (PCLK → LCLK).

A point shift circuit described in Patent Document 1 is known as a command FIFO circuit. The point shift circuit is a circuit that latches an internal command based on an input point signal and outputs the latched internal command based on an output point signal. When a point shift circuit is used as the command FIFO circuit, the number of latencies counted is defined by the phase difference between the input point signal and the output point signal.

As described above, since the output point signal needs to be synchronized with the internal clock signal (LCLK) for output, the input point signal cannot be generated by advancing its phase. For this reason, conventionally, the input point signal is generated by delaying the phase of the output point signal.

JP 2008-47267 A

However, the method of generating the input point signal by delaying the phase of the output point signal has a problem that it is difficult to stop the output internal clock signal (LCLK) during standby. When the output internal clock signal (LCLK) is stopped during standby, the generation of the output internal clock signal (LCLK) is resumed in response to the issuance of a read command or an ODT (On-DieDTermination) command. This is because it takes time until the input point signal is generated. For this reason, the input point signal may not be in time for the read command or ODT command to reach the command FIFO circuit.

In order to solve this problem, a method of generating the input point signal based on another internal clock signal (PCLK) instead of generating the input point signal by delaying the phase of the output point signal can be considered. In this case, it is necessary to correctly associate the relationship between the input point signal and the output point signal based on the latency. However, if the internal clock signal for output (LCLK) is stopped during standby, the input point signal and the output point signal are Will also be reset. For this reason, it is difficult for a conventional semiconductor device to generate an input point signal based on another internal clock signal (PCLK).

The semiconductor device according to the present invention latches an internal command based on a plurality of input point signals that are exclusively activated, and outputs the latched internal command based on a plurality of output point signals that are exclusively activated. A shift circuit, a phase difference determination circuit that generates a determination signal based on a time from when one of the plurality of input point signals is activated until one of the plurality of output point signals is activated; And a phase difference setting circuit for switching a relationship between the plurality of input point signals and the plurality of output point signals based on a determination signal.

In the present invention, since the phase difference between the input point signal and the output point signal is determined and the relationship between the input point signal and the output point signal is switched based on the result, the generation of the output point signal is temporarily stopped. Even in such a case, the relationship between the two can be correctly reproduced after restarting. As a result, the internal clock signal (LCLK) for output can be stopped during standby, and current consumption can be reduced.

1 is a block diagram showing an overall configuration of a semiconductor device 10 according to an embodiment of the present invention. 1 is a block diagram showing a configuration of a command FIFO circuit 100 according to a first embodiment of the present invention. 2 is a circuit diagram of a point shift circuit 110. FIG. 4 is a timing chart for explaining the operation of the point shift circuit 110. FIG. FIG. 6 is a timing chart for explaining the operation of the command FIFO circuit 100 when the count value CNT is “0”. FIG. 6 is a timing chart for explaining the operation of the command FIFO circuit 100 when the count value CNT is “1”. FIG. 10 is a timing chart for explaining the operation of the command FIFO circuit 100 when the count value CNT is “2”. FIG. 10 is a timing chart for explaining the operation of the command FIFO circuit 100 when the count value CNT is “3”. FIG. 5 is a timing diagram for explaining a case where a correct counting operation by the phase difference determination circuit 150 becomes difficult. It is a block diagram which shows the structure of the phase difference determination circuit 150a by the 2nd Embodiment of this invention. 10 is a table for explaining the operation of the selection circuit 154. It is a block diagram which shows the structure of the phase difference setting circuit 160a by the 2nd Embodiment of this invention. It is a circuit diagram of the command FIFO circuit 100a by the 3rd Embodiment of this invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an overall configuration of a semiconductor device 10 according to an embodiment of the present invention.

The semiconductor device 10 according to the present embodiment is a DRAM integrated on a single semiconductor chip and has a memory cell array 11. The memory cell array 11 includes a plurality of word lines WL and a plurality of bit lines BL, and has a configuration in which memory cells MC are arranged at intersections thereof. Selection of the word line WL is performed by the row decoder 12, and selection of the bit line BL is performed by the column decoder 13.

As shown in FIG. 1, the semiconductor device 10 is provided with an address terminal 21, a command terminal 22, a clock terminal 23, a data terminal 24, and power supply terminals 25 and 26 as external terminals.

The address terminal 21 is a terminal to which an address signal ADD is input from the outside. The address signal ADD input to the address terminal 21 is supplied to the address latch circuit 32 via the address input circuit 31 and is latched by the address latch circuit 32. The address signal ADD latched by the address latch circuit 32 is supplied to the row decoder 12, the column decoder 13, or the mode register 14. The mode register 14 is a circuit in which a parameter indicating the operation mode of the semiconductor device 10 is set.

The command terminal 22 is a terminal to which a command signal CMD is input from the outside. The command signal CMD includes a plurality of signals such as a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE. Here, a slash (/) at the head of the signal name means that the corresponding signal is an inverted signal or that the signal is a low active signal. The command signal CMD input to the command terminal 22 is supplied to the command decoding circuit 34 via the command input circuit 33. The command decode circuit 34 is a circuit that generates various internal commands by decoding the command signal CMD. The internal commands include an active signal IACT, a column signal ICOL, a mode register set signal MRS, a standby signal STBY, and the like.

The active signal IACT is a signal that is activated when the command signal CMD indicates row access (active command). When the active signal IACT is activated, the address signal ADD latched by the address latch circuit 32 is supplied to the row decoder 12. Thereby, the word line WL designated by the address signal ADD is selected.

The column signal ICOL is a signal that is activated when the command signal CMD indicates column access (read command or write command). When the internal column signal ICOL is activated, the address signal ADD latched in the address latch circuit 32 is supplied to the column decoder 13 via the latency counter 38. As a result, the bit line BL specified by the address signal ADD is selected. The latency counter 38 is a circuit that delays the command signal CMD and the address signal ADD issued ahead of time to the original issue timing, and the amount of delay is defined by the additive latency AL set in the mode register 14. The internal command COMIN output from the latency counter 38 is supplied to the command FIFO circuit 100 as well as the column decoder 13.

Therefore, when an active command and a read command are input in this order, and a row address and a column address are input in synchronization therewith, read data is read from the memory cell MC specified by the row address and the column address. The read data DQ is output to the outside from the data terminal 24 via the data FIFO circuit 15 and the data input / output circuit 16. On the other hand, when an active command and a write command are input in this order, and a row address and a column address are input in synchronization therewith, and then write data DQ is input to the data terminal 24, the write data DQ becomes a data input / output circuit 16 and the data FIFO circuit 15 are supplied to the memory cell array 11 and written in the memory cell MC specified by the row address and the column address. The operation of the data FIFO circuit 15 is controlled by an internal command COMOUT. The operation of the data input / output circuit 16 is performed in synchronization with the internal clock signal LCLK.

The mode register set signal MRS is a signal that is activated when the command signal CMD indicates a mode register set command. Therefore, if a mode register set command is input and a mode signal is input from the address terminal 21 in synchronization therewith, the set value of the mode register 14 can be rewritten.

The set value of the mode register 14 includes CAS latency CL in addition to the additive latency AL described above. The CAS latency CL refers to the number of clock cycles from the original issue timing of the read command until the first read data DQ is output. A signal CL indicating the CAS latency value is supplied to the command FIFO circuit 100.

The standby signal STBY is a signal that is activated when the command signal CMD indicates a standby command. When the standby signal STBY is activated, the operation of the DLL circuit 36 and the like is stopped, thereby reducing the current consumption of the semiconductor device 10.

The clock terminal 23 is a terminal to which external clock signals CK and / CK are input. The external clock signal CK and the external clock signal / CK are complementary signals, and both are supplied to the clock input circuit 35. The clock input circuit 35 generates an internal clock signal PCLK based on the external clock signals CK and / CK. The internal clock signal PCLK is supplied to the timing generator 37, whereby various internal clock signals ICLK are generated. Various internal clock signals ICLK generated by the timing generator 37 are supplied to circuit blocks such as the address latch circuit 32 and the command decode circuit 34, and define the operation timing of these circuit blocks.

The internal clock signal PCLK is also supplied to the DLL circuit 36. The DLL circuit 36 is a circuit that generates a phase-controlled internal clock signal LCLK based on the internal clock signal PCLK. As described above, the internal clock signal LCLK is supplied to the data input / output circuit 16. As a result, the read data DQ is output in synchronization with the internal clock signal LCLK. The internal clock signals PCLK and LCLK are also supplied to the command FIFO circuit 100. As described above, the DLL circuit 36 stops operating in response to the standby signal STBY. Thereafter, when a read command, a write command, or an ODT command is issued, the DLL circuit 36 resumes its operation.

The power supply terminal 25 is a terminal to which power supply potentials VDD and VSS are supplied. The power supply potentials VDD and VSS supplied to the power supply terminal 25 are supplied to the internal power supply generation circuit 39. The internal power generation circuit 39 generates various internal potentials VPP, VARY, VBLP, VOD, VPERI and the like based on the power supply potentials VDD and VSS. The internal potential VPP is a potential mainly used in the row decoder 12, the internal potentials VARY, VBLP, and VOD are mainly potentials used in the memory cell array 11, and the internal potential VPERI is used in many other circuit blocks. Potential.

The power supply terminal 26 is a terminal to which power supply potentials VDDQ and VSSQ are supplied. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal 26 are supplied to the data input / output circuit 16. Although the power supply potentials VDDQ and VSSQ are the same as the power supply potentials VDD and VSS supplied to the power supply terminal 25, respectively, the data input / output circuit prevents the power supply noise generated by the data input / output circuit 16 from propagating to other circuit blocks. For 16, the dedicated power supply potentials VDDQ and VSSQ are used.

FIG. 2 is a block diagram showing a configuration of the command FIFO circuit 100 according to the first embodiment of the present invention.

As shown in FIG. 2, the command FIFO circuit 100 receives the internal command COMIN output from the latency counter 38 shown in FIG. 1, and delays the internal command COMIN based on the CAS latency value (CL). The point shift circuit 110 which produces | generates is provided. The latch of the internal command COMIN by the point shift circuit 110 is performed based on the input point signal PIN, and the output of the internal command COMOUT from the point shift circuit 110 is performed based on the output point signal POUT.

The input point signal PIN is composed of the input point signals IN0 to IN3, and is generated by the point signal generation circuit 120. The point signal generation circuit 120 generates input point signals IN0 to IN3 having different phases by dividing the internal clock signal PCLK by four. The output point signal POUT includes input point signals OUT0 to OUT3 and is generated by the point signal generation circuit 130. The point signal generation circuit 130 generates output point signals OUT0 to OUT3 having different phases by dividing the internal clock signal LCLK by four.

FIG. 3 is a circuit diagram of the point shift circuit 110.

As shown in FIG. 3, the point shift circuit 110 includes four latch circuits L0 to L3. These latch circuits L0 to L3 are commonly supplied with an internal command COMIN, and latch the internal command COMIN in response to activation of the corresponding input point signals IN0 to IN3, respectively. The internal commands latched by the latch circuits L0 to L3 are output as internal commands COMOUT in response to activation of the corresponding output point signals OUT0 to OUT3, respectively. The internal command COMOUT is supplied to the data FIFO circuit 15 shown in FIG. 1, and is used as a timing signal that defines the output timing of read data, the input timing of write data, the operation timing of the ODT operation, and the like.

FIG. 4 is a timing chart for explaining the operation of the point shift circuit 110.

As shown in FIG. 4, the internal clock signal PCLK with 1 clock cycle = tCK is divided by 4 by the point signal generation circuit 120 to generate four input point signals IN0 to IN3. The cycle of the input point signals IN0 to IN3 is 4tCK, and their phases are shifted from each other by 1tCK. Similarly, the internal clock signal LCLK with 1 clock cycle = tCK is divided by 4 by the point signal generation circuit 130, and four output point signals OUT0 to OUT3 are generated. The cycle of the output point signals OUT0 to OUT3 is 4 tCK, and their phases are shifted by 1 tCK from each other.

For example, the internal command COMIN supplied to the point shift circuit 110 at the time t1 when the input point signal IN0 is activated is taken into the latch circuit L0 at the time t1. When the output point signal OUT0 is activated at time t2, the point shift circuit 110 outputs the internal command COMOUT. Therefore, the timing difference between the internal command COMIN and the internal command COMOUT is defined by a period T from time t1 to time t2. The period T corresponds to the CAS latency value CL.

Since the time t1 is a timing synchronized with the internal clock signal PCLK and the time t2 is a timing synchronized with the internal clock signal LCLK, the clock signal can be changed (PCLK → LCLK).

As described above, the point shift circuit 110 generates the internal command COMOUT by delaying the internal command COMIN by the period T in accordance with the CAS latency value CL. The setting of the period T according to the CAS latency value CL is performed by the delay circuit 140 shown in FIG. The delay circuit 140 is a circuit that generates the reset signal RSTIN by receiving the output point signal OUT0 and delaying it according to the CAS latency value CL. The reset signal RSTIN is input to the point signal generation circuit 120, and when activated, the point signal generation circuit 120 is reset. That is, the point signal generation circuit 120 generates the input point signal IN0 in synchronization with the next rising edge of the internal clock signal PCLK after the reset signal RSTIN is activated. Thereafter, input point signals are generated in the order of IN1, IN2, and IN3 in synchronization with the internal clock signal PCLK. With this operation, the phase difference (T) between the input point signal IN0 and the output point signal OUT0 can be controlled in accordance with the CAS latency value CL.

Note that the generation of the reset signal RSTIN by the delay circuit 140 does not have to be performed every time the output point signal OUT0 is activated, and is performed only once after the DLL circuit 36 is locked after power-on. Further, when the DLL circuit 36 relocks the internal clock signal LCLK according to a change in chip temperature, internal voltage, or the like, the reset signal RSTIN may be generated again. When the operation of the DLL circuit 36 is temporarily stopped by the standby signal STBY, the reset signal RSTIN may be generated again after the internal clock signal LCLK is locked again by restarting the DLL circuit 36.

Further, as shown in FIG. 2, the command FIFO circuit 100 includes a phase difference determination circuit 150 and a phase difference setting circuit 160.

The phase difference determination circuit 150 receives the input point signal IN0 and the output point signals OUT0 to OUT3, and determines the phase difference between the input point signal IN0 and the output point signal OUT0 in response to the start signal START. Specifically, in response to the start signal START, how many times the other output point signals OUT1 to OUT3 are activated during a period T from when the input point signal IN0 is activated until the output point signal OUT0 is activated. The count value CNT (determination signal) is output to the phase difference setting circuit 160. Therefore, the count value CNT is a value from 0 to 3. In the example shown in FIG. 4, since the output point signals OUT2 and OUT3 are activated during the period from the activation of the input point signal IN0 at time t1 to the activation of the output point signal OUT0 at time t2. The count value CNT is “2”. The start signal START is an internal signal that is activated each time the DLL circuit 36 is reset, for example, when the power is turned on or a reset command is issued.

The phase difference setting circuit 160 is a circuit that receives the count value CNT, the input point signals IN0 to IN3, and the internal command COMIN, and generates a reset signal RSTOUT based on them. The reset signal RSTOUT is input to the point signal generation circuit 130, and when activated, the point signal generation circuit 130 is reset. That is, the point signal generation circuit 130 generates the output point signal OUT0 in synchronization with the next rising edge of the internal clock signal LCLK after the reset signal RSTOUT is activated. Thereafter, output point signals are generated in the order of OUT1, OUT2, and OUT3 in synchronization with the internal clock signal LCLK.

The timing at which the phase difference setting circuit 160 generates the reset signal RSTOUT is selected based on the count value CNT. Specifically, when the count value CNT = i (0 to 3), the reset signal RSTOUT is generated in response to the activation of the input point signal INi. Therefore, as in the example shown in FIG. 4, if the count value CNT is “2”, the reset signal RSTOUT is generated in response to the activation of the input point signal IN2, as shown by the broken line R, thereby The signal generation circuit 130 is reset. The operation of the phase difference setting circuit 160 is executed in synchronization with the internal command COMIN.

5 to 8 are timing charts for explaining the operation of the command FIFO circuit 100 when the count value CNT = 0 to 3, respectively.

As shown in FIG. 5, when the internal command COMIN is activated when the count value CNT = 0, the output point signals OUT0 to OUT3 are activated in this order after the input point signal IN0 is activated. As a result, the phase difference (T) between the input point signal IN0 and the output point signal OUT0 is less than 1 tCK.

As shown in FIG. 6, when the internal command COMIN is activated when the count value CNT = 1, the output point signals OUT0 to OUT3 are activated in this order after the input point signal IN1 is activated. As a result, the phase difference (T) between the input point signal IN1 and the output point signal OUT1 is 1 tCK or more and less than 2 tCK.

As shown in FIG. 7, when the internal command COMIN is activated when the count value CNT = 2, after the input point signal IN2 is activated, the output point signals OUT0 to OUT3 are activated in this order. Thereby, the phase difference (T) between the input point signal IN2 and the output point signal OUT2 is 2 tCK or more and less than 3 tCK.

As shown in FIG. 8, when the internal command COMIN is activated when the count value CNT = 3, the output point signals OUT0 to OUT3 are activated in this order after the input point signal IN3 is activated. Thereby, the phase difference (T) between the input point signal IN3 and the output point signal OUT3 is 3 tCK or more and less than 4 tCK.

With this operation, the phase difference detected by the phase difference determination circuit 150 can be reproduced by the phase difference setting circuit 160.

The above is the circuit configuration and operation of the command FIFO circuit 100. As described above, in the present embodiment, since the command FIFO circuit 100 is provided with the phase difference determination circuit 150, the input point signals IN0 to IN3 synchronized with the internal clock signal PCLK and the internal clock signal LCLK are synchronized. It becomes possible to easily determine the phase difference between the output point signals OUT0 to OUT3. Then, by inputting the count value CNT obtained as a result of the determination to the phase difference setting circuit 160, the phase difference can be reproduced immediately after the internal command COMIN is issued.

Thus, even when the DLL circuit 36 is stopped, the input point signals IN0 to IN3 can be generated immediately without waiting for the operation of the DLL circuit 36 to resume. For this reason, the operation of the DLL circuit 36 can be stopped during standby, and the current consumption can be reduced.

Next, a second embodiment of the present invention will be described.

FIG. 9 is a timing chart for explaining a case where correct counting operation by the phase difference determination circuit 150 is difficult. In the case shown in FIG. 9, the rising edge of the input point signal IN0 and the rising edge of the output point signal OUT1 are almost overlapped. When such a metastable state occurs, if the count operation is performed in synchronization with the activation of the start signal START, it is unclear whether the rising edge of the output point signal OUT1 is counted. Therefore, since the obtained count value CNT is “2” or “3”, the correct count value CNT cannot be obtained. The present embodiment is characterized in that a circuit for avoiding such a metastable state is added to the command FIFO circuit 100.

FIG. 10 is a block diagram showing the configuration of the phase difference determination circuit 150a according to this embodiment.

As shown in FIG. 10, the phase difference determination circuit 150a according to the present embodiment includes three phase difference determination circuits 151 to 153. All of these three phase difference determination circuits 151 to 153 have the same circuit configuration as the phase difference determination circuit 150 according to the first embodiment, but there is a difference in the timing at which the input point signal IN0 is input. ing. Specifically, the input point signal IN0 is input as it is to the phase difference determination circuit 151, whereas the input point signal IN0 is input to the phase difference determination circuit 152 via one delay element DLY. The input point signal IN0 is input to the phase difference determination circuit 153 via the two delay elements DLY.

The count values CNT1 to CNT3 output from the phase difference determination circuits 151 to 153 are supplied to the selection circuit 154. The selection circuit 154 selects the count value CNT to be output based on the count values CNT1 to CNT3 and generates the selection signal SEL.

FIG. 11 is a table for explaining the operation of the selection circuit 154.

As shown in the pattern A in FIG. 11, for example, when the count values CNT1 to CNT3 are all “2”, the output count value CNT is also “2”, and the value of the selection signal SEL is the count value CNT2 that is the center value. “2” corresponding to Here, the count value underlined in FIG. 11 indicates the value to be output as the count value CNT and the types of the count values CNT1 to CNT3 corresponding to the selection signal SEL.

On the other hand, as shown in the pattern B, when the count values CNT1 and CNT2 are “2” and the count value CNT3 is “1”, the output count value CNT is majority and becomes “2”. The value of the selection signal SEL is “1” corresponding to the count value CNT1. This is because the metastable state may occur at the timing corresponding to the vicinity of the count values CNT2 and CNT3, and the count value CNT1 most distant from this state should be selected.

Similarly, as shown in pattern C, when the count value CNT1 is “2” and the count values CNT2 and CNT3 are “1”, the output count value CNT is majority and becomes “1”. The value of the signal SEL is “3” corresponding to the count value CNT3. This is because the metastable state may occur at the timing corresponding to the vicinity of the count values CNT1 and CNT2, and the count value CNT3 that is most distant from this state should be selected.

As shown in the pattern D, when the count values CNT1 to CNT3 are all “1”, the output count value CNT is “1”, and the value of the selection signal SEL corresponds to the count value CNT2 that is the center value. It becomes "2".

The count value CNT and the selection signal SEL generated in this way are supplied to the phase difference setting circuit 160a shown in FIG.

FIG. 12 is a block diagram showing a configuration of the phase difference setting circuit 160a according to the present embodiment.

As shown in FIG. 12, the phase difference setting circuit 160a according to the present embodiment includes a phase difference setting circuit 161 and a switch circuit 162 that switches the timing of the input point signals IN0 to IN3 supplied to the phase difference setting circuit 161. ing. The switch circuit 162 selects the path of the input point signals IN0 to IN3 that does not pass through the delay element DLY when the value of the selection signal SEL is “1”, and when the value of the selection signal SEL is “2”. Selects the path of the input point signals IN0 to IN3 that pass through one delay element DLY. When the value of the selection signal SEL is “3”, the input point signals IN0 to IN0 that pass through the two delay elements DLY Select the path for IN3. The individual delay elements DLY included in the phase difference setting circuit 160a have the same delay amount as the individual delay elements DLY included in the phase difference determination circuit 150a.

Then, the phase difference setting circuit 161 generates the reset signal RSTOUT based on the input point signals IN0 to IN3 and the count value CNT. The operation is the same as that of the phase difference setting circuit 160 in the first embodiment. With this configuration, the reset signal RSTOUT can be generated in a state where the metastable state is avoided.

As described above, in the present embodiment, the metastable state is surely avoided, so that the phase difference between the input point signals IN0 to IN3 and the output point signals OUT0 to OUT3 can be correctly determined. It becomes possible to correctly reproduce the phase difference.

Next, a third embodiment of the present invention will be described.

FIG. 13 is a circuit diagram of a command FIFO circuit 100a according to the third embodiment of the present invention.

As shown in FIG. 13, in the command FIFO circuit 100a according to the present embodiment, the internal clock signal PCLK and the start signal START are input to the point signal generation circuit 130a. The point signal generation circuit 130a generates the output point signals OUT0 to OUT3 based on the internal clock signal LCLK when the start signal START is activated, while the output point signal is generated based on the internal clock signal PCLK in other cases. OUT0 to OUT3 are generated.

With this configuration, the operation of the phase difference determination circuit 150 in response to the activation of the start signal START is the same as in the first embodiment, but thereafter, the output point signals OUT0 to OUT3 are based on the internal clock signal PCLK. Will be generated. Therefore, the output timing of the internal command COMOUT is not synchronized with the internal clock signal LCLK. On the other hand, the DLL circuit 36 is only activated when the start signal START is activated, that is, when the count value CNT is generated by the phase difference determination circuit 150. After that, the DLL circuit 36 can be kept stopped. As a result, the current consumption of the semiconductor device 10 can be further reduced.

The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Memory cell array 12 Row decoder 13 Column decoder 14 Mode register 15 Data FIFO circuit 16 Data input / output circuit 21 Address terminal 22 Command terminal 23 Clock terminal 24 Data terminal 25, 26 Power supply terminal 31 Address input circuit 32 Address latch circuit 33 Command input circuit 34 Command decode circuit 35 Clock input circuit 36 DLL circuit 37 Timing generator 38 Latency counter 39 Internal power generation circuit 100, 100a Command FIFO circuit 110 Point shift circuit 120, 130, 130a Point signal generation circuit 140 Delay circuits 150-153 , 150a phase difference determination circuit 154 selection circuit 160, 160a, 161 phase difference setting circuit 162 Switch circuit CNT, CNT1 to CNT3 Count value COMIN, COMOUT Internal command DLY Delay element IN0 to IN3, PIN Input point signal L0 to L3 Latch circuit OUT0 to OUT3, POUT Output point signal PCLK, LCLK Internal clock signal RSTIN, RSTOUT Reset signal SEL Select signal START Start signal STBY Standby signal

Claims (9)

  1. A point shift circuit that latches an internal command based on a plurality of input point signals that are exclusively activated and outputs the latched internal command based on a plurality of output point signals that are exclusively activated;
    A phase difference determination circuit that generates a determination signal based on a time from activation of any of the plurality of input point signals to activation of any of the plurality of output point signals;
    A semiconductor device comprising: a phase difference setting circuit that switches a relationship between the plurality of input point signals and the plurality of output point signals based on the determination signal.
  2. The point shift circuit includes a plurality of latch circuits,
    Each of the plurality of latch circuits latches the internal command in response to activation of any of the corresponding plurality of input point signals, and any of the corresponding plurality of output point signals is activated. 2. The semiconductor device according to claim 1, wherein the latched internal command is output in response to the operation.
  3. The phase difference determination circuit is based on a time from when an input point signal corresponding to a predetermined latch circuit among the plurality of latch circuits is activated until an output point signal corresponding to the predetermined latch circuit is activated. The semiconductor device according to claim 2, wherein the determination signal is generated.
  4. The phase difference determination circuit includes a plurality of output point signals between an activation of an input point signal corresponding to the predetermined latch circuit and an activation of an output point signal corresponding to the predetermined latch circuit. The semiconductor device according to claim 3, wherein the determination signal is generated based on the number of times of activation.
  5. The phase difference setting circuit activates an output point signal corresponding to the predetermined latch circuit in response to activation of an input point signal corresponding to the determination signal among the plurality of input point signals. The semiconductor device according to claim 4.
  6. A first point signal generation circuit that generates the plurality of input point signals based on a first clock signal;
    2. The semiconductor according to claim 1, further comprising: a second point signal generation circuit that generates the plurality of output point signals based on a second clock signal different from the first clock signal. apparatus.
  7. The semiconductor device according to claim 6, further comprising a DLL circuit that generates the second clock signal phase-controlled based on the first clock signal.
  8. 8. The semiconductor device according to claim 7, wherein the DLL circuit is deactivated in response to a standby command being issued.
  9. 9. The semiconductor device according to claim 8, wherein the DLL circuit is activated in response to a read command or an ODT command being issued.
PCT/JP2014/053408 2013-02-19 2014-02-14 Command fifo circuit WO2014129386A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060250883A1 (en) * 2005-05-04 2006-11-09 Kazimierz Szczypinski Integrated semiconductor memory device for synchronizing a signal with a clock signal
JP2008047267A (en) * 2006-08-21 2008-02-28 Elpida Memory Inc Latency counter
JP2009020932A (en) * 2007-07-10 2009-01-29 Elpida Memory Inc Latency counter and semiconductor storage having the same, and data processing system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060250883A1 (en) * 2005-05-04 2006-11-09 Kazimierz Szczypinski Integrated semiconductor memory device for synchronizing a signal with a clock signal
JP2008047267A (en) * 2006-08-21 2008-02-28 Elpida Memory Inc Latency counter
JP2009020932A (en) * 2007-07-10 2009-01-29 Elpida Memory Inc Latency counter and semiconductor storage having the same, and data processing system

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