WO2014125293A2

WO2014125293A2 - Receiver, transceiver, communication system and method

Info

Publication number: WO2014125293A2
Application number: PCT/GB2014/050438
Authority: WO
Inventors: Steve Duncan
Original assignee: Sub10 Systems Limited
Priority date: 2013-02-14
Filing date: 2014-02-14
Publication date: 2014-08-21
Also published as: WO2014125293A3; GB201302595D0; GB2512200A; GB201402633D0

Abstract

A communications system (10) is disclosed comprising a transmitter (20) and a receiver (30). The transmitter (20) is configured to transmit a data stream at close to the Nyquist rate. The receiver (30) is configured to sample a received signal data stream at close to the Nyquist rate and includes a synchronisation unit (36) configured to iteratively execute a synchronisation routine to identify a sample point in the received signal.

Description

Receiver, Transceiver, Communications System and Method Field of the Invention

The present invention relates to a receiver, a transceiver, a communications system (such as a transmitter and receiver combination) and method that are particularly applicable to millimetre-wave radio communications.

Background to the Invention

As demand for data throughput increases, so are communication devices such as radio modems and cable modems being required to support increasing data rates (up to and exceeding 1 Gbps). The proliferation of radio devices in use is resulting in a demand for radio equipment with small form-factor and low power consumption, so that they can be mounted unobtrusively both outdoors on street furniture, and also indoors. At the same time, market pressures are forcing down equipment prices, which means that radio modems must be designed for low cost production. However, at high data rates (typically of 1 Gbps and above), digital signal processing components in radio modems consume high power, which acts to increase both equipment size and cost. Therefore it is desirable to design a high data rate radio modem with as low cost and power consumption as possible.

Traditional time division multiplexing (TDM) radio modems have the advantage of providing timing information together with the data stream, which can provide the key timing source for 2G networks, such as Global System for Mobile Communications (GSM). In contrast, radio modems often use packet-based transport such as carrier Ethernet, and do not have inherent clock synchronisation capability, because Ethernet was not designed for transporting synchronisation signals. Ethernet clocking is only accurate to +/- 4.6 parts per million (ppm), which is not very accurate when compared with requirements for mobile network synchronisation for accuracy of the order of 50 - 250 parts per billion (ppb). In order to meet the strict timing requirements of mobile networks such as Long Term Evolution (LTE), more accurate synchronisation capability is a vital addition to radio modems which use carrier Ethernet instead of TDM.

One type of radio modem is referred to as a homodyne transceiver, also known as a synchrodyne, or zero-intermediate frequency transceiver. This is a radio modem architecture in which an incoming radio signal is demodulated using synchronous detection driven by a local oscillator whose frequency is identical to, or very close to the carrier frequency of the intended signal. This is in contrast to the standard superheterodyne receiver where this is accomplished only after an initial conversion to an intermediate frequency. Another type of radio modem is referred to as a heterodyne transceiver (of which the superheterodyne transceiver is a type). An incoming radio signal is mixed with a signal from a local oscillator and converted by the heterodyne technique to a lower, fixed, frequency signal called the intermediate frequency (IF). This IF signal is amplified and filtered, before being applied to a detector which extracts the transmitted data.

Existing radio modems with zero-intermediate-frequency (zero-IF) architecture

(homodyne transceivers), contain a transmitter and receiver as follows: the transmitter contains a modulator, Nyquist filter (root raised cosine or RRC), digital-to- analogue converter (DAC), up-converter, power-amplifier and antenna. The receiver contains an antenna, low noise amplifier (LNA), down-converter, low-pass filter, analogue-to-digital converter (ADC), Nyquist filter (RRC) and synchronisation block. The function of the combined Nyquist (RRC) filters in the transmitter and receiver is to produce a raised-cosine response, which fulfils the Nyquist criterion for zero inter- symbol-interference ( IS I) at integer multiples of the sample time. It will be

appreciated that the Nyquist ISI criterion and Nyquist sampling criterion discussed below are different things.

Nyquist-rate sampling requires that a band-limited signal must be sampled at a rate of at least twice the bandwidth of the signal, that is 2f_max, to ensure that the signal can be reconstructed exactly from the samples without aliasing. As the sampling rate is increased above the Nyquist rate, so the images of the analogue signal are moved further apart: this makes anti-aliasing filters easier to construct. The major problem with sampling at exactly the Nyquist rate is that it is extremely difficult to construct a perfect "brick-wall" filter in the frequency domain to perfectly remove the images of the analogue signal. For this reason, it is common practice to make use of RRC filters at both transmitter and receiver, which combine to form a raised-cosine frequency response.

The drawback of using RRC filters is that it requires both the DAC and the ADC to run at a rate higher than the Nyquist rate (this is known as oversampling). Oversampling minimizes the constraints on the anti-aliasing filter, but requires a fast- er-sampling ADC, which is more expensive and consumes more power. This is a fundamental design hurdle to overcome when designing a radio modem for both low cost and low power consumption. Statement of invention

According to an aspect of the present invention, there is provided a

communications system comprising a transmitter and a receiver, the transmitter being configured to transmit a data stream at close to the Nyquist rate, the receiver being configured to sample a received signal data stream at close to the Nyquist rate and includes a synchronisation unit configured to iteratively execute a

synchronisation routine to identify a sample point in the received signal.

Preferably, the transmitter includes an interpolating filter configured to filter the data stream prior to transmission at close to the Nyquist rate. Close to the Nyquist rate preferably comprises an integer, n, multiple of the Nyquist rate, n being less than 4. For example, n may equal 1 or 2.

The filter may have a non-zero coefficient gain on a single even numbered filter coefficient and a zero coefficient gain on all other even numbered filter coefficients. Typically, there are 3 non-zero coefficients at the temporal center.

Thereafter, in both directions, the coefficients alternate with zero values and non- zero values.

Preferably, the filter is a half-band filter (or a filter having similar properties to a half-band filter).

The synchronisation routine may be arranged to identify the sample point having substantially zero inter-symbol-interference between data symbols.

The synchronisation routine may include determining a sample point by correlating a training sequence with a subset of samples of the received signal data stream.

The subset of samples may comprise even or odd numbered samples of the received signal data stream.

The synchronisation routine may further comprise calculating a metric on the relative distribution of the respective subset of samples and adjusting the determined sample point in dependence on the calculated metric. The transmitter may include a transmitter sample clock and is configured to vary the phase of the clock by a predetermined phase difference for a predefined subset of samples.

According to another aspect of the present invention, there is provided a data communications method comprising:

transmitting a data stream signal at close to the Nyquist rate;

receiving the transmitted data stream signal and sampling the received signal data stream at close to the Nyquist rate including iteratively executing a

synchronisation routine to identify a sample point in the received signal.

The method may further comprise filtering the data stream by an interpolating filter prior to transmission at close to the Nyquist rate.

Close to the Nyquist rate preferably comprises an integer, n, multiple of the Nyquist rate, n being less than 4.

Preferably, n = 2 and the interpolating filter has a non-zero coefficient gain on a single even numbered filter coefficient and a zero coefficient gain on all other even numbered filter coefficients.

The synchronisation routine may include: identifying the sample point having substantially zero inter-symbol-interference between data symbols; and further may include determining a sample point by correlating a training sequence with a subset of samples of the received signal data stream.

The subset of samples may comprise one of even or odd numbered samples of the received signal data stream.

The method may further comprise calculating a metric on the relative distribution of the respective subset of samples and adjusting the determined sample point in dependence on the calculated metric.

Alternatively, n may equal 1 and the method may further comprise varying the phase of a sample clock by a predetermined phase difference for a predefined subset of samples to create a detectable pattern in the transmitted data stream signal.

According to another aspect of the present invention, there is provided a receiver arranged to receive a halfband-filtered signal and sample the received signal at close to the Nyquist rate, the receiver including a synchronisation unit for iteratively executing a synchronisation routine to identify a sample point in the received signal while substantially minimising distortion introduced by said half-band filtering.

Embodiments of the present invention are applicable to radio communications systems such as homodyne and heterodyne systems. They are also applicable to other communications systems requiring synchronisation such as cable modem based communication systems. While particularly advantageous for use in synchronous Ethernet based systems, embodiments of the present invention are also applicable to other synchronisation standards or protocols.

Selected embodiments of the present invention make use of an ADC which samples the received signal at, or close to, the Nyquist rate (so there is little or no oversampling). Preferred embodiments operate at 1 or 2 times the Nyquist rate. This reduces the system power consumption, since the power required by ADC/DAC converters and digital filters increases substantially at higher sample rates. .

Nevertheless, embodiments of the present invention are still able to support high data rates. In selected embodiments, a combined system design enables a receiving modem to correctly demodulate the received signal at these low sample rates. A beneficial effect of embodiments of the present invention is that they enable precise measurement and control of the radio timing. This can be used to reconstruct a timing reference at the receiver that is closely locked to the timing reference at the transmitter. A radio employing an embodiment of the present invention can therefore find application in Synchronous Ethernet networks, or in any other application where a precise time signal must be conveyed from one point in a network to another.

In preferred embodiments, transmitters and receivers are operated at close to the Nyquist rate. A transmitter or receiver operating close to the Nyquist rate in the context of the present application is typically operating at an integer multiple and less than 4. Existing systems typically operate at 4 or more times Nyquist rate and by operating at 2 times or 1 times the Nyquist rate, embodiments of the present invention offer substantial savings in terms of data needed to be processed.

Consequently simpler hardware and more power efficient architectures can be utilised.

In one embodiment, a communication system is operated at 2 times the Nyquist rate with even and odd numbered samples in the received data stream being treated differently by the synchronisation unit so as to identify a sample point. Preferably, a half-band filter or a filter having similar properties is applied to the signal at the transmitter such that only one even-numbered coefficient has a nonzero gain and all odd-numbered coefficients have a nonzero gain.

In another embodiment, a communication system is operated at the Nyquist rate. In this embodiment, the phase of a sample clock at the transmitter is varied for a predetermined time (for example all or a part of a header portion of each frame to be transmitted) for a subset of samples (for example alternate samples or alternate bursts) so as to create a predefined pilot burst that a receiver can use to calculate a frequency offset in spite of operating at the relatively low sample rate of 1 x Nyquist rate.

In a preferred embodiment, a receiver is arranged to receive a halfband- filtered signal and sample the received signal at close to the Nyquist rate, the receiver including a synchronisation unit for iteratively executing a synchronisation routine to identify a sample point in the received signal while substantially minimising distortion introduced by said half-band filtering.

Brief Description of the Drawings

Embodiments of the present invention are described below, by way of example only, with reference to the accompanying drawings, in which:

Figure 1 is a schematic diagram of a communication system according to an embodiment of the present invention;

Figure 2 is a schematic diagram illustrating aspects of the receiver of Figure 1 in more detail;

Figure 3 is a schematic diagram of a communications system according to another embodiment of the present invention.

Detailed Description

In common with established conventions, the phrase "consists of" is intended to mean that the following clause is a complete description of the contents of the subject. The phrase "comprises" is intended to mean that the subject contains at least the list of described objects but that the list is not necessarily exhaustive. Figure 1 is a schematic diagram of a communication system 10 according to an embodiment of the present invention that includes a transmitter 20 and a receiver 30.

The transmitter 20 is configured to transmit a data stream Γ derived from a stream of data symbols I received at an input 5. The data stream Γ is transmitted at close to the Nyquist rate as discussed below. The receiver 30 is configured to receive the transmitted data stream Γ and sample it at close to the Nyquist rate. The receiver 30 includes a synchronisation unit 36 configured to iteratively execute a synchronisation routine to identify a sample point in the received signal .

Figure 2 is a schematic diagram illustrating details of an example

implementation of the transmitter and receiver of Figure 1 .

In this embodiment, the transmitter 20 includes an interpolating filter 22 configured to filter the data stream prior to transmission at close to the Nyquist rate.

The transmitter 20 includes a modulator 21 configured to receive the data symbols I to be transmitted at the input 5. The modulator 21 produces a modulated output that is passed to the interpolating filter 22.

The interpolating filter outputs to a digital-to-analogue converter (DAC) 23 and the resulting analogue signal output is then passed through a low pass filter 24 and an RF up-converter 25 before being passed to a diplexer 26 for transmission via an antenna 27.

An oscillator 28 feeds a digital phase locked loop unit 29 that in turn controls the digital-to-analogue converter 23 and a frame sync unit.

In this embodiment, the transmitter 20 is preferably operated at 2x Nyquist rate coming out of the interpolating filter, which is 1 x Nyquist rate going into the interpolating filter. (Interpolation in this sense is commonly understood to mean the combination of upsampling and filtering).

Preferably, the interpolating filter 22 is a half-band filter or a filter having similar properties to that of a half band filter such that the filter has a non-zero coefficient gain on a single even numbered filter coefficient (tap) and a nonzero coefficient gain on all odd numbered filter coefficients (taps). The receiver 30 receives signals via its antenna 31 and passes them to a diplexer 32 and then on to an RF down-converter 33. The signal is then filtered at a low pass filter 34 before being passed to an analogue to digital converter (ADC) 35.

The ADC 35 converts the signal to the digital domain and outputs this to a synchronisation unit 36 and an adaptive filter 37, both of which are discussed in greater detail below. The synchronisation unit 36 recovers timing synchronisation from the signaland outputs an estimate of timing error to a sync loop 38 which is discussed in more detail below.

The adaptive filter 37 outputs a digital symbol output O.

Use of an adaptive filter to remove distortion from the Nyquist-rate ADC

A consequence of using only a Nyquist-rate ADC and operating without the traditional RRC filters at the transmitter and receiver, is that there is likely some residual ISI remaining at the ADC output. In preferred embodiments, an adaptive filter 37 receives the signal output from the synchronisation unit 36 and is arranged to remove distortion in the signal.

In one embodiment, the adaptive filter 37 includes an equalizer with an adaptive training algorithm that uses part of the known training sequence to update the equalizer tap coefficients to take out the remaining ISI from the signal. This produces a symbol constellation which is free from ISI, and ready for demodulation.

In one embodiment, the adaptive equalizer 37 includes a programmable interpolator (PI) 37b and an equalizer/estimator (EE) 37a.

Equalizer/Estimator

The Equalizer/Estimator (EE) 37a performs the following functions:

1 . equalization of the ISI caused by time-varying degradations of the radio channel

2. estimation of the phase noise trajectory of the transmitter and receiver local oscillators.

The equalizer 37a may be implemented by various components, such as a finite impulse response (FIR) linear equalizer or alternatively an infinite impulse response (MR) filter such as a decision feedback equalizer (DFE). Programmable Interpolator

The Programmable Interpolator (PI) 37b operates on the output of the EE 37a (i.e. the equalised signal) and includes an array of fixed-coefficient FIR filter banks, one of which is selected at any given time. There will be one filter bank for each distinct value of the fractional timing offset. The number of distinct values is a design parameter that will permit tradeoff between accuracy and storage size. Each FIR filter bank corresponds to a different value (or range of values) of the fractional timing offset reported by the Sync Block.

Use of a half-band filter in place of RRC filter

Instead of implementing a RRC filter at both transmitter and receiver, so that the combined filter response has a raised-cosine filter response, selected

embodiments of the present invention use a half-band filter at the transmitter. A half- band filter is a finite-impulse-response (FIR) filter which has the transition between passband and stop-band located at exactly ¼ of the sampling rate (f_s/4). One advantage of using a half-band filter is that almost half of the tap coefficients are zero, resulting in a greatly-reduced number of computations per output sample. In the time-domain, the half-band filter has an impulse response which is zero at even sample points, except for the central sample, see Figure 3. This ensures zero-ISI when down-sampled (decimated) by a factor of 2, provided that the timing is located on the central pulse.

Synchronisation Unit 36

In wireless communication systems, phase noise and frequency offset cause difficulties in synchronising the ADC sample point to the received signal stream. In millimetre-wave radios, the phase noise is a particular problem. Existing

synchronisation schemes make use of a digital correlator, which correlates the complex conjugate of a known training sequence with the received data stream to produce a correlation peak, which indicates the correct timing instant.

Preferred embodiments of the present invention make use of a multi-stage synchronisation routine that is executed by the synchronisation unit 36 at the receiver 30. In the following description, the sample frequency f_s is selected to be exactly twice the Nyquist rate.

1 . In the first stage 30a, a coarse timing block establishes coarse synchronisation by correlating the complex conjugate of a known training sequence with even-numbered samples of the received data stream to produce a correlation peak, at a rate of f_s/2. However, the accuracy of this stage is impaired by the non-zero contribution of the half-band filter at the samples immediately adjacent to the central sampling point, which introduce noise if the sample timing offset is not an integer multiple of f_s/2. (this is a consequence of avoiding the use of RRC filters at the transmitter and receiver).

2. In the second stage 30b, a fine timing block establishes fine synchronisation by correlating the complex conjugate of a known training sequence with odd samples of the received data stream to produce a double correlation peak, at a rate of f_s/2. When the timing instant is known exactly, the 2 correlation peaks should have equal amplitude. By iteratively adjusting the timing offset by a small fraction (typically of the order of 1 /20th of the sample period, but not restricted to this range), the fine timing block can achieve very accurate timing synchronisation.

3. In the third stage 30c, a second fine timing block augments the output of the first fine timing block by computing a metric of the relative distribution of the odd and even sample subsequences, where the metric distinguishes between samples that are widely spread in the complex plane and samples that are tightly clustered. Such a metric could be, for example, the ratio of the variance of the positive values in the In-Phase (I) or

Quadrature (Q) components of the received data stream or the variance of the modulus squared of the received data stream. It will be apparent to those skilled in the art that several alternative types of metric could in principle be used. The output of the first and second stages 30a, 30b is a signed number which is an estimate of the timing error of the receiver (i.e. time difference between the expected timing instant and the value that was actually observed).

The synchronisation sub-block may be operated as follows (each case corresponding to a variant of the receiver or a selectable operating mode of a configurable receiver. This may be selected by a physical switch, in software or may simply be selected during the building of the system.):

1 . First stage 30a on its own

2. Second stage 30b on its own

3. First stage 30a and third stage 30c together, where the outputs of the two stages are combined by a weighted sum to give the refined estimate of the timing error.

4. Second stage 30b and third stage 30c, where the output of the third stage 30c gives the magnitude of the timing error and the output of second stage 30b gives its sign.

In a further embodiment, the correlation in the first and second stages 30a, 30b may be performed between the discrete first-order complex phase differential and the discrete first-order complex phase differential of the training sequence. The discrete first-order complex phase differential of a sampled sequence x(k) {k = 0,1 ,2,...} is defined as: c(k) = x(k)x^*(k-1 ), where ^* denotes complex conjugation.

In another embodiment, the result of the correlation in the second stage 30b may be accumulated (e.g. by term-wise addition) between successive frames, provided that the ratio of the two highest correlation peaks does not depart from unity by more than a configurable threshold. The timing error is output by the synchronisation unit to the sync loop 38.

The sync loop 38 includes a sync loop controller 39, a voltage controlled crystal oscillator VCXO 40 and a phase locked loop unit 41 which controls the ADC 35.

Use of a sync tracking loop to adjust the receive oscillator

The synchronisation unit 36 seeks to provide fine timing synchronisation, even in the presence of high phase noise. However, if the transmitter and receiver oscillators 28, 40 have a frequency offset between them, then the timing will begin to drift immediately after synchronisation has been established. In selected

embodiments, a Sync Loop Controller (SLC) 39 is used to adjust a voltage-controlled crystal oscillator (VCXO) 40 at the receiver, using input information from the synchronisation unit 36, in such a way as to lock the receiver sample frequency with the transmitter sample frequency whilst maintaining a low timing error.

Simple sync loop

In one embodiment (Figure 4), the SLC 39 executes steps including:

1 . A bias term is added to the timing error estimate received from the synchronisation unit 36.

2. The biased timing error estimate is multiplied by a gain term.

The output of the second step is converted to a voltage which is then applied to the VCXO 40.

The bias and gain terms are system parameters that are typically set at build time of the system but may be variable during operation.

Advanced version of sync loop

In another embodiment (Figure 5), the Sync Loop Controller (SLC) 39 executes functions including: System Identification

A System Identification (SI) sub-block measures the time-varying aspects of the VCXO in the presence of additive noise and channel distortion estimated from the received signal. The output of the SI sub-block is a characteristic curve (in one embodiment implemented as a lookup table) giving the VCXO frequency as a function of applied voltage.

Receiver Sample Rate Control

A Receiver Sample Rate Control (RSRC) sub-block applies small corrections to the VCXO frequency in order to keep the receiver frequency locked to the transmitter.

The RSRC uses knowledge of the sync position reported by the

synchronisation unit 36 together with:

1 . estimates of the additive noise

2. a model of the transmitter and receiver frequency error spectrum

3. knowledge of previous VCXO control voltage values

4. actuator delay (delay in VCXO response after demand)

Preferably, the receiver includes a volatile or non-volatile memory in which this data is stored.

The output of the RSRC block is a control voltage that is applied to the VCXO 40 in order to compensate for the receiver sample clock frequency offset.

One advantageous feature of the RSRC block is that it distinguishes the timing error variation caused by deliberate timing adjustments made at the receiver from the timing variation caused by the relative drift of the transmitter and receiver sample clocks. Only the former is used to calculate the correct VCXO value for frequency lock. The RSRC computes the desired frequency correction for steady state operation. The SI then converts this to a voltage level to apply to the VCXO. The TA computes a dynamic offset in order to deliberately move the sync position. That dynamic offset is corrected by the SI in the same way and added to the output of the RSRC.

Timing Adjustment

The Timing Adjustment (TA) sub-block uses the sync offset correction computed by the RSRC block and a model of the VCXO dynamic response to compute a dynamic voltage profile to be applied to the VCXO in order to shift the received signal time alignment to a required point. Synchronisation is determined to be achieved when the receiver starts sampling exactly on the first sample of the training burst.

The TA sub-block further constrains the dynamic voltage profile such that the overall RMS timing deviation and maximum time interval error remain within prescribed limits during the Timing Adjustment process.

Derivation of the transmit sample clock from a precision reference

In one embodiment, the sample clock at the transmitter may be derived from precision timing reference (e.g. a Synchronous Ethernet data clock) by a clock recovery circuit (e.g. a digital phase-locked loop or DPLL).

Auxiliary Functions

These functions describe additional features, which are refinements, but are not essential components of the previously-described embodiments.

Frame Alignment

The Frame Alignment (FA) unit 43 computes an estimate of the radio propagation time between the transmitting and receiving antennas.

The FA 43 uses knowledge from the transmitter's own internal timing reference of the timing instant local to the transmitter and, via end-to-end messaging, the knowledge of the timing offset between transmit and receive frame boundaries at the far end. This has a number of uses, one of which is to enable synchronisation in the reverse direction over the link. A brief example of this capability refers to the radio transceiver which is the primary provider of the timing signal as being the "Master", and refers to the remote radio transceiver which is required to synchronise to the provided timing signal, as being the "Slave". Synchronisation in the reverse direction enables the receiver on the Master side to be synchronised with the transmitter on the Slave side. Since the receiver on the Slave side is already synchronised with the transmitter on the Master side, and this timing instant is used to lock the transmitter on the Slave side, this then allows the receiver on the Master side to also be synchronised, but with a timing offset which is equal to twice the time-of-flight (or radio propagation) delay. The FA computes the radio propagation delay, and then uses this information to adjust the timing in the reverse direction, so that the receiver on the Master end of the link can also be synchronised. This allows both the transmitter and receiver at both ends of the radio link to have their timing

synchronised, thus allowing true bi-directional clock transfer.

Synchronisation Monitoring

The Synchronisation Monitoring (SM) unit 44 computes statistics on the quality of synchronisation that has been achieved by the Sync Loop Controller (SLC) and reports them to a higher-layer management unit 45 such as an event logging system, web server, for possible alarm generation or contingency operations.

Figure 6 is a schematic diagram of a communications system according to an alternate embodiment.

In this embodiment, the communication system is operated at 1 times the Nyquist rate. Typically, such a configuration would be selected where a higher symbol rate was needed than in the embodiments discussed above. Although many of the components are common to that of the above described embodiment, by operating at the Nyquist rate, a half-band filter or equivalent at the transmitter is not needed.

In this embodiment, the phase of a sample clock at the transmitter is varied for a predetermined time by a controller 100 (for example all or a part of a header portion of each frame to be transmitted) for a subset of samples (for example alternate samples) so as to create a predefined pilot burst that a receiver can use to calculate a frequency offset in spite of operating at the relatively low sample rate of 1 x Nyquist rate. This may be achieved in many ways, although preferably the ADC has a programmable phase offset that is adjusted by the controller 100.

Only the first stage 30a and the second stage 30b of the Synchronisation unit 30 may be needed.

It will be appreciated that there are various ways in which the transmitter and receiver may be implemented. Preferably, the DAC and ADC are discrete digital components. They may optionally be integrated, for example in a system-on-chip (SOC) architecture, where they are placed in the same package as other digital components of the receiver and transmitter.

The Receiver signal processing components (synchronisation unit, adaptive filter and sync loop) may be implemented in one or more field programmable gate array (FPGA), application specific integrated circuit (ASIC) or software in any combination. The software implementation of the adaptive filter block would normally be done on a programmable DSP processor, whilst the Synchronisation unit and SLC could be implemented in software on a conventional microprocessor. The modulator may be implemented in software, FPGA or ASIC.

Worked Example

This worked example illustrates the benefits of adjusting the ADC sample timing to synchronise the receiver clock frequency with the transmitter, and so transfer the SyncE timing. By way of example, assume that the transmitted signal bandwidth is 100MHz, with a receiver sample rate of 150MHz, and symbol rate of 75MHz. Data is transmitted in frames of length 13 microseconds, each frame contains a pilot sequence of 128 symbols long, together with a cyclic prefix. A digital correlator in the receiver is used to correlate even samples of the received signal with the complex conjugate of the known pilot sequence, so producing a correlation peak to use in the first synchronisation block. A sample rate of 150MHz, when decimated by a factor of two, equates to a sample time resolution of 13ns. The receiver VCXO which controls the ADC sampling rate can adjust the sample reference clock by typically up to 15ppm, and with a typical resolution of 16 bits, this means that the ADC sample clock frequency can be adjusted with a very fine resolution, typically less than 1 ppb. The sample timing accuracy is limited not only by the ADC adjustment resolution, but also by the accuracy of the measurement of the sample timing offset, which itself is limited by the auto-correlation properties of the pilot sequence, additive noise and the phase noise of the VCXO. It is known in the art that a suitable pilot sequence should be chosen that exhibits very low autocorrelation products away from the main peak, and also that a cyclic prefix should be used to eliminate end effects and incidental cross-correlation with the data payload. Using a pilot sequence of 128 symbols allows a very high processing gain; this reduces the contribution of additive noise to the sample time offset estimate.

Using the parameter values described above, it is possible to estimate the sample timing offset to a high accuracy, typically less than 1 % of the sample period. A simple control loop with sufficiently high bandwidth is then capable of regulating the sync position to a small multiple of this resolution. In the above example, 1 % of the sample period equates to 0.01 x 13ns = 0.13ns. The training sequence is repeated every 1024 samples (i.e. 13.6 microseconds), and the sync control loop is executed every millisecond. The smallest frequency offset that will produce a detectable change from one loop invocation to the next is therefore 0.13ns in 1 ms, or approximately 1 ppm.

Maximum time interval error (MTIE) is dependent on the time excursion of the closed loop sync position, which itself depends on the ratio of the control loop bandwidth to the VCO phase noise bandwidth and the pulling range of the VCXO. The VCXO control loop will act to null the frequency offset to zero. Therefore, frequency offsets can be removed, up to a resolution which is limited by the resolution of the ADC sample rate adjuster, which in this example has a resolution of 16 bits. If, by way of example, it is assumed that due to quantization errors and noise, only 14 bits out of the 16 bits are usable, then this gives a 15ppm adjustment range with a 14-bit resolution, that is 15ppm / 2^A14 = 15ppm / 16384 = 0.9ppb. It is therefore seen from this example that the inventive step of adjusting the receiver sample timing so as to be synchronised with the transmitter sample timing then has the benefit that a frequency accuracy of the order of 1 ppb can be achieved at the receiver. A further advantage of this method is that frequency lock can be achieved very quickly, because the loop filter is running at a rate of, for example, 1 kHz, and even if a very large number of cycles (for example 100 cycles), were needed to achieve lock, this would still result in a lock time of only 0.1 seconds.

By further way of example, existing receivers for SyncE would typically allow the receiver sample clock to be free-running, and subsequently use a digital phase- locked loop (DPLL) to regenerate the timing signal. There are two main drawbacks of existing methods which are not experienced in embodiments of the present invention:

1 . Wander is not easily removed. This is highlighted by the increase in the ITU-T G.8262 MTIE mask for observation intervals tau greater than 1 second.

2. There is a trade-off in DPLL design between a wide loop filter (which rejects jitter and has quicker lock time) and a narrow loop filter (which achieves small steady-state error, but results in very long convergence times, which may be many minutes up to hours).

The various embodiments described above disclose features that can optionally be combined in a variety of ways depending on the desired

implementation. Since the features described are modular, other embodiments based on different combinations of features are also possible.

None of the described features are mutually exclusive, and any combination of may be deployed to achieve the functions described above.

It is to be appreciated that certain embodiments of the invention as discussed below may be incorporated as code (e.g., a software algorithm or program) residing in firmware and/or on computer useable medium having control logic for enabling execution on a computer system having a computer processor. Such a computer system typically includes memory storage configured to provide output from execution of the code which configures a processor in accordance with the

execution. The code can be arranged as firmware or software, and can be

organized as a set of modules such as discrete code modules, function calls, procedure calls or objects in an object-oriented programming environment. If implemented using modules, the code can comprise a single module or a plurality of modules that operate in cooperation with one another.

Optional embodiments of the invention can be understood as including the parts, elements and features referred to or indicated herein, individually or collectively, in any or all combinations of two or more of the parts, elements or features, and wherein specific integers are mentioned herein which have known equivalents in the art to which the invention relates, such known equivalents are deemed to be incorporated herein as if individually set forth.

Although illustrated embodiments of the present invention have been described, it should be understood that various changes, substitutions, and alterations can be made by one of ordinary skill in the art without departing from the present invention which is defined by the recitations in the claims below and equivalents thereof.

Claims

1 . A communications system comprising a transmitter and a receiver, the transmitter being configured to transmit a data stream at close to the Nyquist rate, the receiver being configured to sample a received signal data stream at close to the Nyquist rate and includes a synchronisation unit configured to iteratively execute a synchronisation routine to identify a sample point in the received signal.

2. The communications system of claim 1 , wherein the transmitter includes an interpolating filter configured to filter the data stream prior to

transmission at close to the Nyquist rate.

3. The communications system of claim 2, wherein close to the Nyquist rate comprises an integer, n, multiple of the Nyquist rate, n being less than 4.

4. The communications system of claim 3, wherein n = 1

The communications system of claim 3, wherein n

6. The communications system of claim 5, wherein the filter has a nonzero coefficient gain on a single even numbered filter coefficient and a zero coefficient gain on all other even numbered filter coefficients.

7. The communications system of claim 6, wherein the filter is a half-band filter.

8. The communications system of claim 6 or 7, wherein the

synchronisation routine is arranged to identify the sample point having substantially zero inter-symbol-interference between data symbols.

9. The communication system of claim 8, wherein the synchronisation routine includes:

determining a sample point by correlating a training sequence with a subset of samples of the received signal data stream.

10. The communication system of claim 8, wherein the subset of samples comprises one of even or odd numbered samples of the received signal data stream.

11 . The communication system of claim 10, the synchronisation routine further comprising calculating a metric on the relative distribution of the respective subset of samples and adjusting the determined sample point in dependence on the calculated metric.

12. The communication system of claim 4, wherein the transmitter includes a transmitter sample clock and is configured to vary the phase of the clock by a predetermined phase difference for a predefined subset of samples.

13. A data communications method comprising:

transmitting a data stream signal at close to the Nyquist rate;

synchronisation routine to identify a sample point in the received signal.

14. The data communications method of claim 13, further comprising filtering the data stream by an interpolating filter prior to transmission at close to the Nyquist rate.

15. The data communications method of claim 14, wherein close to the Nyquist rate comprises an integer, n, multiple of the Nyquist rate, n being less than 4.

16. The data communications method of claim 15, wherein n = 2 and the interpolating filter has a non-zero coefficient gain on a single even numbered filter coefficient and a zero coefficient gain on all other even numbered filter coefficients.

17. The data communications method of claim 16, wherein the

synchronisation routine includes identifying the sample point having substantially zero inter-symbol-interference between data symbols.

18. The data communications method of claim 17, wherein the

synchronisation routine includes:

determining a sample point by correlating a training sequence with a subset of 5 samples of the received signal data stream.

19. The data communications method of claim 18, wherein the subset of samples comprises one of even or odd numbered samples of the received signal data stream.

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20. The data communications method of claim 19, further comprising calculating a metric on the relative distribution of the respective subset of samples and adjusting the determined sample point in dependence on the calculated metric. 5 21 . The data communications method of claim 15, wherein n=1 , the

method further comprising varying the phase of a sample clock by a predetermined phase difference for a predefined subset of samples to create a detectable pattern in the transmitted data stream signal.

22. A receiver arranged to receive a halfband-filtered signal and sample the received signal at close to the Nyquist rate, the receiver including a synchronisation unit for iteratively executing a synchronisation routine to identify a sample point in the received signal.

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