WO2014115830A1

WO2014115830A1 - Method for manufacturing semiconductor light-emitting element

Info

Publication number: WO2014115830A1
Application number: PCT/JP2014/051472
Authority: WO
Inventors: 鈴木敦志; 難波江宏一
Original assignee: エルシード株式会社
Priority date: 2013-01-28
Filing date: 2014-01-24
Publication date: 2014-07-31
Also published as: JPWO2014115830A1

Abstract

Provided is a method for manufacturing a semiconductor light-emitting element in which a group III nitride semiconductor grown on a sapphire substrate on which convex parts or concave parts have been formed can be flawlessly separated from the sapphire substrate. Manufacturing the semiconductor light-emitting element includes: a step for forming periodic concave or convex parts on the flat part of the surface of the sapphire substrate; a step for forming a buffer layer made from a group III nitride semiconductor on the flat part and the concave or convex parts of the sapphire substrate; a step for heat-treating the sapphire substrate, removing at least a part of the buffer layer from the concave or convex parts, and leaving the buffer layer on the flat part; a step for growing the group III nitride semiconductor from the buffer layer on the flat part so as to fill the concave or convex parts; a step for causing a support substrate to adhere to the reverse surface of the sapphire substrate; and a step for causing the buffer layer on the flat part of the sapphire substrate to absorb energy from a laser, and separating the group III nitride semiconductor from the sapphire substrate.

Description

Manufacturing method of semiconductor light emitting device

The present invention relates to a method for manufacturing a semiconductor light emitting device.

High-intensity blue, green, white, and other light-emitting diodes have already been put into practical use through the accumulation of basic technologies such as low-temperature deposition buffer layer technology, p-type conductivity control, n-type conductivity control, and a method for producing high-efficiency light-emitting layers. ing. Currently, in the light emitting diode, the refractive index of the semiconductor is larger than the refractive index of the substrate, air, etc., and a large part of the light emitted from the light emitting layer cannot be extracted outside the light emitting diode by total reflection or Fresnel reflection. Improvement of light extraction efficiency is a problem.

In order to solve this problem, a structure in which a semiconductor surface is subjected to uneven processing with a period of several microns has been proposed (for example, see Non-Patent Document 1). By providing a concavo-convex structure on the light extraction side of the semiconductor surface, total reflection disappears due to the effect of light scattering, a transmittance of about 50% can be obtained over a relatively wide radiation angle, and the light extraction efficiency can be up to about 50%. Can be improved.

Furthermore, it has also been proposed to improve the light extraction efficiency by reducing the period of the concavo-convex structure to 2 times or less of the optical wavelength of the light emitting diode (see, for example, Patent Document 1). In this case, the light extraction mechanism is different from the concavo-convex structure having a period of several microns, the wave nature of light becomes obvious, the boundary of the refractive index disappears, and Fresnel reflection is suppressed. Such a structure is called a photonic crystal or a moth-eye structure, and the light extraction efficiency can be improved up to about 50%.

Furthermore, the inventors of the present application have proposed that the period of the concavo-convex structure be made smaller than the coherent length of light and that light be extracted using a diffraction action (see, for example, Patent Document 2). In Patent Document 2, a group III nitride semiconductor formed on the surface of a sapphire substrate and including a light-emitting layer and light emitted from the light-emitting layer formed on the surface side of the sapphire substrate are incident and are larger than the optical wavelength of the light. A diffractive surface in which concave or convex portions are formed with a period smaller than the coherent length of light, and an Al reflective film that is formed on the back side of the substrate and reflects light diffracted by the diffractive surface and re-enters the diffractive surface. A semiconductor light emitting device comprising is described. According to this semiconductor light emitting device, the light transmitted by the diffractive action is re-incident on the diffractive surface, and the light is transmitted again using the diffractive action on the diffractive surface, thereby extracting the light in a plurality of modes to the outside of the device. Can do.

By the way, a method for manufacturing a light-emitting element is known in which a group III nitride semiconductor is formed on a sapphire substrate, a conductive support substrate is attached to the side opposite to the sapphire substrate of the group III nitride semiconductor, and then the sapphire substrate is peeled off. (For example, see Patent Document 3). In the manufacturing method described in Patent Document 3, after a group III nitride semiconductor is grown on a sapphire substrate having a convex portion, the sapphire substrate is peeled from the group III nitride semiconductor by laser lift-off or the like. As a result, irregularities are formed on the surface of the group III nitride semiconductor.

JP 2005-354020 A International Publication No. 2011/0276779 Japanese Patent Application Laid-Open No. 2012-234853

However, in the method described in Patent Document 3, the group III nitride semiconductor is uniformly grown on the sapphire substrate. Therefore, the dislocation density and the laser light absorption coefficient in the group III nitride semiconductor are flat with the sapphire substrate. Even if it is on a part or a convex part, it does not change so much. Therefore, there is a problem that the laser beam is absorbed not only on the flat part but also on the convex part, and the concave-convex shape is damaged when the substrate is peeled off.

The present invention has been made in view of the above circumstances, and the object thereof is to accurately peel off a group III nitride semiconductor grown on a sapphire substrate on which a convex portion or a concave portion is formed from the sapphire substrate. Another object is to provide a method for manufacturing a semiconductor light emitting device.

According to the present invention, the periodic structure forming step of forming periodic recesses or protrusions on the flat portion of the surface of the sapphire substrate, and the flat portion of the sapphire substrate and the group III on the recesses or the protrusions A buffer layer forming step of forming a buffer layer made of a nitride semiconductor; and applying heat treatment to the sapphire substrate to remove at least a part of the buffer layer from the concave portion or the convex portion, and the buffer layer on the flat portion On the back surface of the sapphire substrate, a step of removing a part of the buffer layer to leave the semiconductor layer, a step of forming a group III nitride semiconductor from the buffer layer on the flat portion so as to fill the concave portion or the convex portion, and A supporting substrate pasting step for pasting a supporting substrate, and absorbing the laser energy in the buffer layer on the flat portion of the sapphire substrate, thereby allowing the group III nitride semiconductor to The method of manufacturing a semiconductor light emitting device comprising, a laser lift-off step of peeling from the sapphire substrate is provided with.

In the method for manufacturing a semiconductor light emitting device, the flat portion of the surface of the sapphire substrate may be a c-plane.

In the method for manufacturing a semiconductor light emitting device, the concave portion or the convex portion may not have a c-plane.

In the method for manufacturing a semiconductor light emitting device, the interval between the concave portions or the convex portions may be less than 1 μm.

In the method for manufacturing a semiconductor light emitting device, the depth of the concave portion or the height of the convex portion may be 100 nm or more and less than 1 μm.

According to the present invention, the group III nitride semiconductor grown on the sapphire substrate on which the convex portion or the concave portion is formed can be accurately separated from the sapphire substrate.

FIG. 1 is a schematic cross-sectional view of a semiconductor light emitting device showing an embodiment of the present invention. 2A and 2B show a sapphire substrate, in which FIG. 2A is a schematic perspective view, FIG. 2B is a schematic explanatory view showing an AA section, and FIG. 2C is a schematic enlarged explanatory view. FIG. 3 is a schematic explanatory view of the plasma etching apparatus. FIG. 4 is a flowchart showing a periodic structure forming process in the sapphire substrate. 5A shows a process of an etching method for a sapphire substrate and a mask layer, (a) shows a sapphire substrate before processing, (b) shows a state in which a mask layer is formed on sapphire, and (c) shows a mask layer. A state where a resist film is formed is shown, (d) shows a state where a mold is brought into contact with the resist film, and (e) shows a state where a pattern is formed on the resist film. FIG. 5B shows the process of the etching method of the sapphire substrate and the mask layer, (f) shows a state where the remaining film of the resist film is removed, (g) shows a state where the resist film is altered, and (h) shows The mask layer is etched using the resist film as a mask, and (i) shows the sapphire substrate etched using the mask layer as a mask. FIG. 5C shows the process of the etching method of the sapphire substrate and the mask layer, (j) shows a state where the sapphire substrate is further etched using the mask layer as a mask, and (k) shows a state where the remaining mask layer is removed from the sapphire substrate. (L) shows a state in which wet etching is performed on the sapphire substrate. FIG. 6 is a flowchart showing a method for manufacturing a light emitting device. 7A and 7B show a process of a method for manufacturing a light emitting device, where FIG. 7A shows a state where a buffer layer is formed on a sapphire substrate, FIG. 7B shows a state where a part of the buffer layer is removed, and FIG. A state in which a base layer is formed using the remaining buffer layer as a nucleus is shown. 8A and 8B show a process of a method for manufacturing a light emitting device, where FIG. 8A shows a state in which a semiconductor laminated portion is formed on a sapphire substrate, FIG. 8B shows a state in which a barrier metal layer is formed on the semiconductor laminated portion, and FIG. ) Shows a state where the support substrate is attached to the sapphire substrate. FIG. 9 is a schematic cross-sectional view of a joined body in which a support substrate is attached to a sapphire substrate. FIG. 10 is a schematic explanatory diagram of a laser irradiation apparatus. FIG. 11 is an explanatory diagram for irradiating a laser beam with a focus on the buffer layer. FIG. 12 is an explanatory view showing a state where the sapphire substrate is peeled off by laser lift-off. FIG. 13 shows a modified example, showing a sapphire substrate, in which (a) is a schematic perspective view, and (b) is a schematic explanatory view showing an AA cross section. FIG. 14 is a schematic cross-sectional view of a semiconductor light emitting device showing a modification.

1 to 12 show an embodiment of the present invention, and FIG. 1 is a schematic sectional view of a semiconductor light emitting device.

As shown in FIG. 1, the light emitting element 1 includes a first barrier metal layer 3, an adhesive 8, a second barrier metal layer 4, a semiconductor stacked portion 5 made of a group III nitride semiconductor, on a support substrate 2. A base layer 6 made of a group III nitride semiconductor and an n-side electrode 7 are formed in this order from the support substrate 2 side. A p-side electrode 9 is formed on the back surface of the support substrate 2. The semiconductor stacked unit 5 includes a p-type GaN layer 51, a multiple quantum well active layer 52, and an n-type GaN layer 53 in this order from the support substrate 2 side. The light emitting element 1 is manufactured by bonding the sapphire substrate 100 and the support substrate 2 and then removing the sapphire substrate 100 by a laser lift-off method.

FIG. 2 shows a sapphire substrate for a growth substrate, in which (a) is a schematic perspective view, (b) is a schematic explanatory view showing an AA section, and (c) is a schematic enlarged explanatory view.

In manufacturing the light emitting device 1, first, a sapphire substrate 100 is prepared as a growth substrate on which a group III nitride semiconductor is grown. As shown in FIGS. 2A and 2B, the sapphire substrate 100 has a c-plane ({0001}) on which a nitride semiconductor is grown on the surface side. On the surface, a flat portion 101 where the c-plane is exposed and a plurality of convex portions 102 periodically formed on the flat portion 101 are formed, and a light diffraction effect can be obtained. The c-plane is not exposed on the surface of each convex portion 102. The shape of each convex portion 102 may be a truncated cone shape such as a cone or a polygonal pyramid, or a truncated cone shape such as a truncated cone or a truncated polygonal truncated cone. In this embodiment, after each convex part 102 is formed in a truncated cone shape, the upper part is rounded by etching.

As shown in FIG. 2A, in a plan view, the projections 102 are formed in alignment with the intersections of the virtual triangular lattice at a predetermined cycle so that the center of each convex portion 102 is the position of the vertex of the regular triangle. . Here, the period refers to the distance between the height peak positions of adjacent convex portions 102.

In the present embodiment, as shown in FIG. 2C, each convex portion 102 has a side surface 103 extending upward from the flat portion 101, and a curve extending curvedly from the upper end of the side surface 103 toward the center side of the convex portion 102. Part 104. As will be described later, the curved portion 104 is formed by wet etching of the convex portion 102. Before the wet etching, the convex portion 102 is in a state where corners are formed by the meeting portion of the side surface 103 and the flat upper surface. By performing wet etching on the convex portion 102 in this state, the flat upper surface disappears and the entire upper side of the convex portion 102 becomes the curved portion 104. Specifically, in the present embodiment, each convex portion 102 has a base end diameter of 380 nm and a height of 350 nm. In addition, if the height of each convex part 102 is not 100 nm or more, there exists a possibility that sufficient diffraction effect cannot be obtained. The surface of the sapphire substrate 100 is a flat portion 101 in addition to the convex portions 102, so that the lateral growth of the semiconductor is promoted.

Here, a method for manufacturing the sapphire substrate 100 will be described with reference to FIGS. 3 to 5C. FIG. 3 is a schematic explanatory diagram of a plasma etching apparatus for processing a sapphire substrate.

As shown in FIG. 3, the plasma etching apparatus 200 is an inductively coupled (ICP) type, a flat substrate holding table 201 that holds the sapphire substrate 100, a container 202 that houses the substrate holding table 201, and a container 202 A coil 203 provided via a quartz plate 205 and a power source 204 connected to the substrate holding table 201. The coil 203 is a solid spiral coil, which supplies high-frequency power from the center of the coil and is grounded at the outer periphery of the coil. The sapphire substrate 100 to be etched is placed on the substrate holding table 201 directly or via a transfer tray. The substrate holding table 201 has a built-in cooling mechanism for cooling the sapphire substrate 100, and the cooling mechanism is controlled by the cooling control unit 206. The container 202 has a supply port and can supply various gases such as O ₂ gas and Ar gas.

In performing the etching with the plasma etching apparatus 200, the sapphire substrate 100 is placed on the substrate holding table 201, and then the air in the container 202 is discharged to be in a reduced pressure state. Then, a predetermined processing gas is supplied into the container 202, and the gas pressure in the container 202 is adjusted. Thereafter, high-frequency high-frequency power is supplied to the coil 203 and the substrate holder 201 for a predetermined time to generate a plasma 207 of a reactive gas. The sapphire substrate 100 is etched by the plasma 207.

Next, an etching method using the plasma etching apparatus 200 will be described with reference to FIGS. 4, 5A, 5B, and 5C.
FIG. 4 is a flowchart showing a periodic structure forming process in the sapphire substrate 100. As shown in FIG. 4, the periodic structure forming step for forming the periodic convex portions 102 on the flat portion 101 of the surface of the sapphire substrate 100 includes a mask layer forming step S1, a resist film forming step S2, and a pattern forming step S3. And a remaining film removing step S4, a resist alteration step S5, a mask layer etching step S6, a sapphire substrate etching step S7, a mask layer removing step S8, and a curved portion forming step S9.

5A shows the process of the etching method of the sapphire substrate and the mask layer, (a) shows the sapphire substrate before processing, (b) shows the state in which the mask layer is formed on the sapphire substrate, and (c) shows the mask. A state where a resist film is formed on the layer is shown, (d) shows a state where a mold is brought into contact with the resist film, and (e) shows a state where a pattern is formed on the resist film.
FIG. 5B shows the process of the etching method of the sapphire substrate and the mask layer, (f) shows the state where the remaining film of the resist film is removed, (g) shows the state where the resist film has been altered, and (h) The mask layer is etched using the resist film as a mask, and (i) shows the sapphire substrate etched using the mask layer as a mask. Incidentally, the resist film after the alteration is expressed by painting out in the drawing.
FIG. 5C shows the process of the etching method of the sapphire substrate and the mask layer, (j) shows a state where the sapphire substrate is further etched using the mask layer as a mask, and (k) shows a state where the remaining mask layer is removed from the sapphire substrate. (L) shows a state in which wet etching is performed on the sapphire substrate.

First, as shown in FIG. 5A (a), a sapphire substrate 100 before processing is prepared. Prior to etching, the sapphire substrate 100 is cleaned with a predetermined cleaning solution.

Next, as shown in FIG. 5A (b), a mask layer 130 is formed on the sapphire substrate 100 (mask layer forming step: S1). In the present embodiment, the mask layer 130 has a SiO ₂ layer 131 on the sapphire substrate 100 and a Ni layer 132 on the SiO ₂ layer 131. The thickness of each of the

layers

131 and 132 is arbitrary. For example, the SiO ₂ layer can be 1 nm to 100 nm and the Ni layer 132 can be 1 nm to 100 nm. Note that the mask layer 130 may be a single layer. The mask layer 130 is formed by a sputtering method, a vacuum evaporation method, a CVD method, or the like.

Next, as shown in FIG. 5A (c), a resist film 140 is formed on the mask layer 130 (resist film forming step: S2). In the present embodiment, a thermoplastic resin is used as the resist film 140 and is formed to have a uniform thickness by a spin coating method. The resist film 140 is made of, for example, an epoxy resin and has a thickness of, for example, not less than 100 nm and not more than 300 nm. Note that a photocurable resin can also be used as the resist film 140.

Then, the resist film 140 is heated and softened together with the sapphire substrate 100, and the resist film 140 is pressed with a mold 150 as shown in FIG. 5A (d). An uneven structure 151 is formed on the contact surface of the mold 150, and the resist film 140 is deformed along the uneven structure 151.

Thereafter, the resist film 140 is cooled and cured together with the sapphire substrate 100 while keeping the pressed state. Then, by separating the mold 150 from the resist film 140, the concavo-convex structure 141 is transferred to the resist film 140 as shown in FIG. 5A (e) (pattern forming step: S3). Here, the period of the concavo-convex structure 141 is less than 1 μm. In the present embodiment, the period of the concavo-convex structure 141 is 460 nm. Moreover, in this embodiment, the diameter of the convex part 143 of the uneven structure 141 is 100 nm or more and 300 nm or less, for example, 230 nm. Moreover, the height of the convex part 143 is 100 nm or more and 300 nm or less, for example, 250 nm. In this state, a remaining film 142 is formed in the recess of the resist film 140.

The sapphire substrate 100 on which the resist film 140 is formed as described above is attached to the substrate holding table 201 of the plasma etching apparatus 200. Then, the residual film 142 is removed by, for example, plasma ashing to expose the mask layer 130 that is a workpiece as shown in FIG. 5B (f) (residual film removing step: S4). In the present embodiment, O ₂ gas is used as a processing gas for plasma ashing. At this time, the convex portion 143 of the resist film 140 is also affected by ashing, and the side surface 44 of the convex portion 143 is not perpendicular to the surface of the mask layer 130 but is inclined by a predetermined angle.

Then, as shown in FIG. 5B (g), the resist film 140 is exposed to plasma under the condition for alteration, thereby altering the resist film 140 and increasing the etching selectivity (resist alteration step: S5). In the present embodiment, Ar gas is used as a processing gas for modifying the resist film 140. In the present embodiment, as the condition for alteration, the bias output of the power supply 204 for inducing plasma to the sapphire substrate 100 side is set to be lower than the etching condition described later.

Thereafter, the mask layer 130 as a workpiece is etched using the resist film 140 that has been exposed to plasma under etching conditions and has a high etching selectivity as a mask (mask layer etching step: S6). In the present embodiment, Ar gas is used as a processing gas for etching the resist film 140. As a result, a pattern 133 is formed in the mask layer 130 as shown in FIG. 5B (h).

Here, the processing gas, the antenna output, the bias output, and the like can be changed as appropriate for the alteration condition and the etching condition, but it is preferable to change the bias output using the same processing gas as in this embodiment. Specifically, with respect to the condition for alteration, when the processing gas is Ar gas, the antenna output of the coil 203 is 350 W, and the bias output of the power supply 204 is 50 W, curing of the resist film 140 was observed. Etching of the mask layer 130 was observed when the etching gas was Ar gas, the antenna output of the coil 203 was 350 W, and the bias output of the power source 204 was 100 W. In addition to lowering the bias output relative to the etching conditions, the resist can be cured even if the antenna output is reduced or the gas flow rate is reduced.

Next, as shown in FIG. 5B (i), the sapphire substrate 100 is etched using the mask layer 130 as a mask (sapphire substrate etching step: S7). In the present embodiment, etching is performed with the resist film 140 remaining on the mask layer 130. Further, plasma etching is performed using a chlorine-based gas such as BCl ₃ gas as a processing gas.

Then, as shown in FIG. 5C (j), as etching progresses, a convex portion 102 is formed on the sapphire substrate 100. The height of the convex portion 102 is less than 1 μm. In the present embodiment, the height of the concavo-convex structure is 350 nm. Note that the height of the concavo-convex structure can be made larger than 350 nm. Here, if the height of the concavo-convex structure is relatively shallow, for example, 300 nm, the etching may be finished with the resist film 140 remaining as shown in FIG. 5B (i).

In the present embodiment, side etching is promoted by the SiO ₂ layer 131 of the mask layer 130, and the side surface 103 of the convex portion 102 is inclined. The side etching state can also be controlled by the inclination angle of the side surface 143 of the resist film 140. If the mask layer 130 is a single layer of the Ni layer 132, the side surface 103 of the convex portion 102 can be made substantially perpendicular to the main surface.

Thereafter, as shown in FIG. 5C (k), the mask layer 130 remaining on the sapphire substrate 100 is removed using a predetermined stripping solution (mask layer removing step: S8). In this embodiment, after removing the Ni layer 132 by using high-temperature nitric acid, the SiO ₂ layer 131 is removed by using hydrofluoric acid. Note that even if the resist film 140 remains on the mask layer 130, it can be removed together with the Ni layer 132 with high-temperature nitric acid. However, if the residual amount of the resist film 140 is large, the resist film 140 is previously obtained by O ₂ ashing. Is preferably removed.

And as shown to FIG. 5C (l), the corner | angular part of the convex part 102 is removed by wet etching, and a curved part is formed (curved part formation process: S9). Here, the etching solution is arbitrary, but for example, a phosphoric acid aqueous solution heated to about 170 ° C., so-called “hot phosphoric acid” can be used. Through the above steps, the sapphire substrate 100 having a concavo-convex structure on the surface is manufactured.

According to this etching method of the sapphire substrate 100, the resist film 140 is exposed to plasma and altered, so that the etching selectivity between the mask layer 130 and the resist film 140 can be increased. Thereby, it becomes easy to process the mask layer 130 with a fine and deep shape, and the mask layer 130 with a fine shape can be formed sufficiently thick.

Further, the plasma etching apparatus 200 can continuously perform the alteration of the resist film 140 and the etching of the mask layer 130, and the man-hour is not significantly increased. In the present embodiment, the resist film 140 is altered and the mask layer 130 is etched by changing the bias output of the power supply 204, and the selectivity of the resist film 140 can be easily increased.

Furthermore, since the sapphire substrate 100 is etched using the sufficiently thick mask layer 130 as a mask, it becomes easy to process the sapphire substrate 100 in a fine and deep shape. In particular, forming a concavo-convex structure with a period of 1 μm or less and a depth of 300 nm or more in a sapphire substrate forms a resist film on the substrate on which the mask layer is formed, and etches the mask layer using the resist film. In the etching method that performs the above, it has been impossible in the past, but in the etching method of the present embodiment, it is possible. In particular, the etching method of this embodiment is suitable for forming a concavo-convex structure having a period of 1 μm or less and a depth of 500 nm or more.

The nanoscale periodic concavo-convex structure is called moth eye, but when sapphire is processed to sapphire, sapphire is a difficult-to-cut material and can only be processed to a depth of about 200 nm. However, a step of about 200 nm may be insufficient as a moth eye. It can be said that the etching method of this embodiment has solved a novel problem in the case of performing moth-eye processing on a sapphire substrate.

Although the mask layer 130 made of SiO ₂ / Ni is shown as a workpiece, it is needless to say that the mask layer 130 may be a single Ni layer or other material. In short, the resist may be altered to increase the etching selectivity between the mask layer 130 and the resist film 140.

In addition, although the bias output of the plasma etching apparatus 200 is changed to be the condition for alteration and the condition for etching, the antenna output and the gas flow rate are changed, and for example, it can be set by changing the processing gas. Good. In short, the condition for alteration may be a condition in which the resist is altered when the resist is exposed to plasma and the etching selectivity is increased.

Although the mask layer 130 includes the Ni layer 132, it goes without saying that the present invention can be applied to etching of other materials. In addition, the etching method of this embodiment is applicable also to substrates, such as SiC, Si, GaAs, GaN, InP, ZnO, besides a sapphire substrate.

Next, a method for manufacturing the light emitting element 1 will be described with reference to FIG.
FIG. 6 is a flowchart showing a method for manufacturing the light-emitting element 1. As shown in FIG. 6, the manufacturing method of the light emitting device 1 of the present embodiment includes a periodic structure forming step S10, a buffer layer forming step S20, a buffer layer partial removing step S30, a semiconductor growth step S40, and a support substrate. It includes a pasting step S50, a laser lift-off step S60, an n-side electrode forming step S70, and a p-side electrode forming step S80. The semiconductor growth step S <b> 40 includes both a step of forming the base layer 6 and a step of forming the semiconductor stacked portion 5.

7A and 7B show a process of a method for manufacturing a light emitting device, where FIG. 7A shows a state where a buffer layer is formed on a sapphire substrate, FIG. 7B shows a state where a part of the buffer layer is removed, and FIG. A state in which a base layer is formed using the remaining buffer layer as a nucleus is shown.

In the present embodiment, as shown in FIG. 7A, first, a buffer layer 61 made of a group III nitride semiconductor is formed on the flat portion 101 and the convex portion 102 of the sapphire substrate 100 (buffer layer forming step S20). . Since the buffer layer 61 is grown at a low temperature of, for example, about 500 ° C. by MOCVD (Metal Organic Chemical Vapor Deposition), it is formed with a uniform thickness on the flat portion 101 and the convex portion 102 of the sapphire substrate 100. . The thickness of the buffer layer 61 is, for example, not less than 15 nm and not more than 35 nm. The buffer layer 61 is made of a material of Ga _x Al _1-x N (0 ≦ x ≦ 1), and can be, for example, AlN. Here, if the thickness of the buffer layer 61 is less than 15 nm, the thickness of the absorbing layer may not be ensured. On the other hand, if the thickness of the buffer layer 61 exceeds 35 nm, the crystal quality of the nitride semiconductor grown on the buffer layer 61 may be degraded. The buffer layer 61 can be formed by other manufacturing methods such as a sputtering method in addition to the MOCVD method. In the case of sputtering, the substrate can be formed at a temperature of about 600 ° C., for example.

Next, as shown in FIG. 7B, the sapphire substrate 100 is subjected to a heat treatment to remove the buffer layer 61 from the convex portion 102 and leave the buffer layer 61 on the flat portion 101 (buffer layer partial removal step S30). ). The temperature of heat processing is 800 degreeC or more and 1200 degrees C or less, for example. Here, if the heat treatment temperature is less than 800 ° C., the buffer layer 61 may not be sufficiently removed from the convex portion 102. On the other hand, if the temperature of the heat treatment exceeds 1200 ° C., the buffer layer 61 may disappear. Note that the buffer layer 61 may remain slightly on the convex portion 102, and it is sufficient that at least a part of the buffer layer 61 is removed from the convex portion 102. The dislocation density of the buffer layer 61 is about 1 × 10 ¹⁰ cm ⁻² or more.

Thereafter, as shown in FIG. 7C, the underlayer 6 made of a group III nitride semiconductor is crystal-grown from the buffer layer 61 on the flat portion 101 (semiconductor growth step S40). The underlayer 6 is formed by MOCVD (Metal Organic Chemical Vapor Deposition) method. The underlayer 6 is grown at 800 ° C. or higher and 1200 ° C. or lower and grows so as to fill the convex portion 102, but does not grow from the convex portion 102. Protrusions 102 are periodically formed on the surface of the sapphire substrate 100, but flat by forming large nuclei for reducing the dislocation density at the initial stage of growth of the underlayer 6 and then promoting lateral growth. Is achieved. The dislocation density of the underlayer 6 is about 2 × 10 ⁸ cm ⁻² at a location grown about 2.5 μm from the interface. The underlayer 6 has a plurality of frustum-shaped concave portions 62 formed on the surface periodically along the convex portions 102. The thickness of the underlayer 6 is, for example, not less than 1.5 μm and not more than 4.0 μm, preferably not less than 2.5 μm and not more than 3.5 μm. If the underlayer 6 is too thin, the underlayer 6 cannot be flat and the dislocation density cannot be lowered. On the other hand, if the underlayer 6 is too thick, the warpage of the substrate becomes large, which may hinder laser lift-off. Moreover, in order to suppress the thickness of the underlayer 6, it is preferable that the height of the convex portion 102 is less than 1 μm.

8A and 8B show a process of a method for manufacturing a light emitting device, where FIG. 8A shows a state in which a semiconductor laminated portion is formed on a sapphire substrate, FIG. 8B shows a state in which a barrier metal layer is formed on the semiconductor laminated portion, and FIG. ) Shows a state where the support substrate is attached to the sapphire substrate. FIG. 9 is a schematic cross-sectional view of a joined body in which a support substrate is attached to a sapphire substrate.

As shown in FIG. 8A, an n-type GaN layer 53 as a first conductivity type layer is formed following the base layer 6. The n-type GaN layer 53 is composed of n-GaN. Next, a multiple quantum well active layer 52 as a light emitting layer is formed. The multiple quantum well active layer 52 is made of GalnN / GaN. Next, a p-type GaN layer 51 as a second conductivity type layer is formed. The p-type GaN layer 51 is composed of p-GaN. The n-type GaN layer 53 to the p-type GaN layer 51 are continuously formed by epitaxial growth of a group III nitride semiconductor (semiconductor growth step S40). In addition, when a voltage is applied to the first conductive type layer and the second conductive type layer at least including the first conductive type layer, the active layer, and the second conductive type layer, the active layer is formed by recombination of electrons and holes. The layer structure of the semiconductor layer is arbitrary as long as it emits light.

Subsequently, as shown in FIG. 8B, the barrier metal layer 4 is formed on the semiconductor stacked portion 5. The barrier metal layer 4 is formed by a sputtering method, a vacuum evaporation method, a CVD (Chemical Vapor Deposition) method, or the like. The barrier metal layer 4 includes a predetermined number of pairs of Ti / W / Ti layers formed on the p-type GaN layer 51 and a Ni layer formed on the surface of this layer.

Further, as shown in FIG. 8C, an adhesive 81 is formed on the barrier metal layer 4. The adhesive 81 is formed by a sputtering method, a vacuum deposition method, a CVD (Chemical Vapor Deposition) method, or the like. The adhesive 81 is made of, for example, Au—Sn solder.

On the other hand, as shown in FIG. 8C, the barrier metal layer 3 and the adhesive 82 are formed on the support substrate 2 in this order from the support substrate 2 side. In the present embodiment, the barrier metal layer 3 includes, for example, a Ti layer formed on the support substrate 2 and a W layer formed on the Ti layer. In the present embodiment, the adhesive 82 is made of, for example, Au—Sn solder.

Then, the sapphire substrate 100 and the support substrate 2 are heated with the

adhesives

81 and 82 in contact with each other. Thereafter, as shown in FIG. 9, the

adhesives

81 and 82 are melted and solidified to produce a joined body 160 in which the sapphire substrate 100 and the silicon substrate 2 are joined by the adhesive layer 8 (support substrate pasting step S50). Thereby, the support substrate 2 is affixed on the back surface of the sapphire substrate 100.

Next, the sapphire substrate 100 is removed by a laser lift-off method (laser lift-off step S60). FIG. 10 is a schematic explanatory view of a laser irradiation apparatus, FIG. 11 is an explanatory view of irradiating a laser with a focus on a buffer layer, and FIG. .

As shown in FIG. 10, a laser irradiation apparatus 300 is a laser oscillator 310 that oscillates a laser beam, a mirror 320 that changes the direction of the oscillated laser beam, an optical lens 330 that focuses the laser beam, and a laser beam irradiation target. A stage 340 for supporting the work object, that is, the joined body 160 is provided. The laser irradiation apparatus 300 may include a housing 350 that maintains the laser beam path in a vacuum state.

The laser oscillator 310 can be an excimer laser such as KrF or ArF. The beam emitted from the laser oscillator 310 is reflected by the mirror 320 and its direction is changed. A plurality of mirrors 320 are provided to change the direction of the laser beam. The optical lens 330 is positioned above the stage 340 and focuses the laser beam incident on the joined body 160.

The stage 340 is moved in the x direction and / or the y direction by a moving means (not shown), and moves the joined body 160 placed thereon. The laser beam is irradiated through the sapphire substrate 100 and absorbed at the focal position of the laser of the group III nitride semiconductor. In the present embodiment, as shown in FIG. 11, the laser beam is scanned in the horizontal direction with the focus of the laser beam aligned with the buffer layer 61 on the flat portion 101.

The buffer layer 61 has a higher dislocation density than the underlayer 6, and has a larger laser absorption coefficient than the underlayer 6. The buffer layer 61 is formed only on the flat portion 101. Therefore, energy can be intensively absorbed in the buffer layer 61 on the flat portion 101, and the underlying layer 6 can be accurately peeled from the sapphire substrate 100 as shown in FIG. That is, energy absorption does not occur in portions other than on the flat portion 101, and the uneven shape 62 of the underlayer 6 is not impaired.

Further, since the buffer layer 61 is grown from the surface of the sapphire substrate 100, the bonding force with the sapphire substrate 100 is higher than that of the base layer 6 on the convex portion 102. Therefore, by allowing the buffer layer 61 to absorb the energy of the laser light, the base layer 6 can be accurately peeled from the sapphire substrate 100 as shown in FIG.

Thereafter, the n-side electrode 7 is formed on the underlayer 6 (n-side electrode forming step S70), the p-side electrode 9 (p-side electrode forming step S80) is formed on the support substrate 2 thinned by polishing, and then dicing is performed. By dividing into a plurality of light emitting elements 1, the light emitting element 1 is manufactured as shown in FIG.

By manufacturing the light emitting element 1 as described above, the base layer 6 grown on the sapphire substrate 100 on which the convex portions 102 are formed can be accurately peeled from the sapphire substrate 100.

In the above embodiment, the sapphire substrate 100 on which the convex portions 102 are periodically formed is shown. However, for example, as shown in FIG. 13, the concave portions 402 are periodically formed on the flat portion 401. Alternatively, a sapphire substrate 400 may be used. Also in this sapphire substrate 400, it is preferable that the c-plane is exposed at the flat portion 401 and the c-plane is not exposed at each recess 402. 13A and 13B show a sapphire substrate, in which FIG. 13A is a schematic perspective view, and FIG. 13B is a schematic longitudinal sectional view showing a BB cross section.

As shown in FIG. 13A, in a plan view, each concave portion 402 is formed in alignment with the intersection of virtual triangular lattices at a predetermined cycle so that the center thereof is the position of the vertex of an equilateral triangle. The Here, the period refers to the distance between the peak positions of the depths in the adjacent recesses 402. As shown in FIG. 13B, each recess 402 is formed in an inverted conical shape. Specifically, each concave portion 402 has a base end portion with a diameter of 200 nm and a depth of 500 nm. The surface of the sapphire substrate 400 is a flat portion 401 in addition to the concave portions 402 so that the lateral growth of the semiconductor layer is promoted.

In the above embodiment, the vertical conduction type light emitting element 1 in which electrodes are arranged on the upper and lower sides is shown. However, as shown in FIG. 14, for example, the light emitting element 501 has electrodes arranged on only one side. Of course, it may be. As shown in FIG. 14, the light emitting element 501 is manufactured by forming a flip chip type element on a sapphire substrate and electrically connecting it to a support substrate, and then removing the sapphire substrate by a laser lift-off method. In FIG. 14, the element unit is illustrated for the sake of explanation. In practice, the sapphire substrate is peeled off after the wafer-like sapphire substrate and the support substrate in a state where the elements are continuously connected are bonded. The

In manufacturing this light emitting element 501, a base layer 506 having a recess 562, an n-type GaN layer 553, a multiple quantum well active layer 552, and a p-type GaN layer 551 are formed on a sapphire substrate (not shown). Then, a part of the semiconductor stacked portion 505 is removed by etching from the p-type GaN layer 551 side to expose the n-type GaN layer 553, the p-side electrode 509 is formed on the p-type GaN layer 551, and the n-type GaN layer 553 is formed. An n-type electrode 507 is formed respectively. On the other hand, a metal layer 512 is formed over the support substrate 502 with an insulating layer 511 interposed therebetween. Then, after the metal layer 512 of the support substrate 502 is connected to the n-side electrode 507 and the p-side electrode 509 via the

bumps

581 and 582, the sapphire substrate is removed by a laser lift-off method.

Moreover, in the said embodiment, although the flat part 101 of the sapphire substrate 100 showed what was a c surface, a surface, r surface, m surface, etc. may be sufficient.

In the above-described embodiment, the entire upper part of each convex portion 102 is curved, but a flat surface may remain at the upper end due to wet etching. In this case, if the upper end diameter is 200 nm or less, the buffer layer substantially does not remain on the upper end surface after the partial buffer layer removal step. However, when there is no flat surface at the upper end, the dislocation density of the underlayer becomes lower and the thickness until the underlayer becomes flat becomes smaller.

In the above embodiment, each convex portion 102 has a circular shape in plan view, but each convex portion 102 may have a polygonal shape in plan view. Also in this case, a flat surface may be formed at the upper end, and if the outer diameter of the upper end is 200 nm or less, the buffer layer substantially does not remain on the upper end surface after the partial removal process of the buffer layer.

As mentioned above, although embodiment of this invention was described, embodiment described above does not limit the invention which concerns on a claim. In addition, it should be noted that not all the combinations of features described in the embodiments are essential to the means for solving the problems of the invention.

The method for producing a semiconductor light-emitting device of the present invention is industrially useful because a group III nitride semiconductor grown on a sapphire substrate on which convex portions or concave portions are formed can be accurately peeled from the sapphire substrate.

DESCRIPTION OF SYMBOLS 1 Light emitting element 2 Support substrate 3 1st barrier metal layer 4 2nd barrier metal layer 5 Semiconductor laminated part 6 Underlayer 7 N side electrode 8 Adhesive 9 p side electrode 51 p-type GaN layer 52 Multiple quantum well active layer 53 n-type GaN layer 61 buffer layer 62 concave portion 100 sapphire substrate 101 flat portion 102 convex portion 103 side surface 104 curved portion 130 mask layer 131 SiO ₂ layer 132 Ni layer 140 resist film 141 concavo-convex structure 142 remaining film 143 convex portion 150 mold 151 concavo-convex structure DESCRIPTION OF SYMBOLS 160 Assembly 200 Plasma etching apparatus 201 Substrate holding stand 202 Container 203 Coil 204 Power supply 205 Quartz plate 206 Cooling control part 207 Plasma 300 Laser irradiation apparatus 310 Laser oscillator 320 Mirror 330 Optical lens 340 Stage 350 Housing 400 Sapphire substrate 401 Flat part 402 Concave part 501 Light emitting element 502 Support substrate 505 Semiconductor laminated part 506 Underlayer 511 Insulating layer 512 Metal layer 551 p-type GaN layer 552 Multiple quantum well active layer 553 n-type GaN layer 562 Concave part 581 Bump 582 Bump

Claims

A periodic structure forming step of forming periodic recesses or protrusions on the flat portion of the surface of the sapphire substrate;
A buffer layer forming step of forming a buffer layer made of a group III nitride semiconductor in the flat portion of the sapphire substrate and the concave portion or the convex portion;
Applying a heat treatment to the sapphire substrate, removing at least a part of the buffer layer from the concave portion or the convex portion, and partially removing the buffer layer to leave the buffer layer on the flat portion;
A semiconductor layer forming step of growing a group III nitride semiconductor from the buffer layer on the flat portion so as to fill the concave portion or the convex portion;
A support substrate pasting step of pasting a support substrate on the back surface of the sapphire substrate;
A laser lift-off process in which the buffer layer on the flat portion of the sapphire substrate absorbs laser energy and peels the group III nitride semiconductor from the sapphire substrate.
The method for manufacturing a semiconductor light emitting element according to claim 1, wherein the flat portion of the surface of the sapphire substrate is a c-plane.
The method for manufacturing a semiconductor light emitting element according to claim 2, wherein the concave portion or the convex portion does not have a c-plane.
The method for manufacturing a semiconductor light emitting element according to any one of claims 1 to 3, wherein an interval between the concave portions or the convex portions is less than 1 µm.
5. The method for manufacturing a semiconductor light emitting element according to claim 4, wherein the depth of the concave portion or the height of the convex portion is not less than 100 nm and less than 1 μm.