WO2014112758A1 - Dual-substrate stack memory - Google Patents

Dual-substrate stack memory Download PDF

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Publication number
WO2014112758A1
WO2014112758A1 PCT/KR2014/000357 KR2014000357W WO2014112758A1 WO 2014112758 A1 WO2014112758 A1 WO 2014112758A1 KR 2014000357 W KR2014000357 W KR 2014000357W WO 2014112758 A1 WO2014112758 A1 WO 2014112758A1
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substrate
memory cell
data
implemented
cell array
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Korean (ko)
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안상욱
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(주)실리콘화일
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a memory, in particular, by implementing blocks on two substrates by separating blocks that are electrically connected to each other but performing different functions, and then stacking and electrically connecting the two substrates, thereby operating speed and average A dual substrate stack memory for reducing power consumption.
  • MCU microcontrol unit
  • a method of using a plurality of core processors or a method of making a memory structure different from the conventional methods have been tried. It is common to increase the frequency of the master clock or main clock in order to increase the operating speed of the system, which is desirable because the increase in heat generated by the components of the system is severe. Not.
  • the memory includes a memory cell array including a plurality of memory cells for storing data, a sense amplifier, a write driver, and an external device used to write data to or read data from the memory cell array.
  • a data in / out buffer is used to temporarily store data to be written to the memory cell array and to transmit the data to the memory cell array, or temporarily store data received from the memory cell array and transmit the data to the outside.
  • the technical problem to be solved by the present invention is to implement a sense amplifier unit and a write driver for reading data written to the memory cell array and the memory cell array or the data written in the memory cell array on a single substrate, the memory cell
  • the present invention provides a dual-substrate stack memory in which a buffer for temporarily storing data read from an array or temporarily storing data to be written to the memory cell array is implemented on another substrate and then electrically bonded to each other.
  • a dual substrate stack memory includes a first substrate and a second substrate.
  • the first substrate includes a plurality of memory cell arrays and a plurality of sense amplifier parts and a write driver for reading data stored in the plurality of memory cell arrays or storing data in the memory cell array.
  • the second substrate transfers data stored in the memory cell array of the plurality of memory cell arrays of the first substrate to the outside, or is transferred from the outside, and the memory cell array of the plurality of memory cell arrays of the first substrate.
  • a data input / output buffer including a plurality of storage spaces for transferring data to be stored in the first substrate to temporarily store the data is implemented.
  • the first substrate further includes a plurality of first substrate internal pads electrically connected to the plurality of sense amplifier units and the recording driver, and the second substrate includes a plurality of second substrate internal pads connected to the data input / output buffer.
  • the upper surface of the first substrate on which the first substrate inner pads are implemented and the upper surface of the second substrate on which the second substrate inner pads are implemented may include the first substrate inner pads and the first substrate.
  • the two substrate inner pads are bonded to each other according to the position of the pads.
  • a dual substrate stack memory includes a first substrate and a second substrate.
  • the first substrate includes a memory cell array and a sense amplifier unit and a write driver unit for reading data stored in the memory cell array or storing data in the memory cell array.
  • the second substrate transfers data stored in the memory cell array transferred from the first substrate to the outside, or data input / output for transferring data from outside and to be stored in the memory cell array to the first substrate.
  • the buffer is implemented.
  • the first substrate further includes a plurality of first substrate internal pads electrically connected to the sense amplifier unit and the recording driver, and the second substrate further includes a plurality of second substrate internal pads connected to the data input / output buffer.
  • the first substrate inner pad and the second substrate inner pad are electrically connected by using a TSV method.
  • a memory cell array, a sense amplifier unit and a write driver unit are implemented on a first substrate, and circuits for processing data are implemented on a second substrate, and then bonded to each other, thereby providing a large number of regions in a given region.
  • circuits for processing data are implemented on a second substrate, and then bonded to each other, thereby providing a large number of regions in a given region.
  • a plurality of memory cell arrays can be designed to operate individually and devices for processing the same, so that circuits operating at high speed integrated on the second substrate can be selectively operated. It also has the advantage of minimizing power.
  • FIG. 1 is a block diagram of a dual substrate stack memory according to the present invention.
  • FIG. 2 is a vertical cross-sectional view of a dual substrate stack memory according to an embodiment of the present invention.
  • FIG 3 is a vertical cross-sectional view of a dual substrate stack memory according to another exemplary embodiment of the present invention.
  • FIG. 1 is a block diagram of a dual substrate stack memory according to the present invention.
  • the elements constituting the dual substrate stack memory 100 according to the present invention are separately implemented on two substrates 110 and 120.
  • the first substrate 110 includes a plurality of memory cell arrays 111 and a sense amplifier unit and a write driver 112 connected to each of the plurality of memory cell arrays 111, and data is stored on the second substrate 120.
  • a data input / output buffer 211 including a plurality of storage spaces that can be temporarily stored is implemented.
  • the second substrate 120 further includes a signal processing circuit connected to the data input / output buffer 211 to process data stored in the memory cell array 111.
  • the storage capacity may be improved by implementing a plurality of memory cell arrays 111 that actually store data on the first substrate 110.
  • the plurality of memory cell arrays 111 are operated separately from each other, input / output of data is simultaneously performed. Since it is possible, the speed of the read / write operation of the memory 100 can be improved.
  • FIG. 2 is a vertical cross-sectional view of a dual substrate stack memory according to an embodiment of the present invention.
  • the dual substrate stack memory according to the present invention may be implemented by inverting the first substrate 110 and bonding the first substrate 110 to the second substrate 120. At this time, the first substrate inner pad PAD1 and the second substrate inner pad PAD2 implemented on the first substrate 110 should be aligned to be in contact with each other. In the dual substrate stack memory 100 according to the present invention, an external pad 210 should be installed as an electrical connection window to the outside.
  • the external pad 210 is installed below the first substrate 110, and passes through the first substrate internal pad PAD1 to the external pad 210 through the first substrate 110, or TSV (through silicon via).
  • the first substrate inner pad PAD1 is electrically connected by a direct bonding method.
  • the external pad 210 is illustrated as being connected to the first substrate inner pad PAD1 for the sake of simplicity, an embodiment in which the external pad 210 is electrically connected to other components constituting the first substrate 110 is also possible. Do. In addition, a structure in which the second substrate 120 is stacked on the upper portion of the first substrate 110 is possible. In this case, the external pad 210 may be installed on the lower surface of the second substrate 120. The second substrate inner pad PAD2 may be electrically connected to the outer pad 210 by the direct bonding method.
  • FIG 3 is a vertical cross-sectional view of a dual substrate stack memory according to another exemplary embodiment of the present invention.
  • the lower surface of the first substrate 110 is bonded to the upper surface of the second substrate 120, and electrical connection between the two substrates 110 and 120 is performed. It is implemented through the TSV formed on the first substrate 110, in which case the external pad 210 as shown in Figure 2 is not necessary.
  • the embodiment illustrated in FIG. 3 has a disadvantage in that the area to be implemented in the substrate is reduced by the TSV region.
  • the plurality of layers shown between the integrated circuit implementation regions 111 and 121 and the pads PAD1 and PAD2 may be a conductive layer made of a metal layer or a polysilicon layer. to be.
  • first substrate 111 memory cell array

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

Disclosed is a dual-substrate stack memory in which: memory cell arrays, sense amplifiers for recording data on the memory cell arrays or reading the data recorded on the memory cell array, and write driving units are implemented in one substrate; and a buffer for temporarily storing data read from the memory cell arrays or temporarily storing data to be recorded on the memory cell arrays is implemented in the other substrate, so as to use the substrates by electrically bonding the substrates. The dual-substrate stack memory, according to the present invention, has a first substrate and a second substrate of which upper surfaces are bonded with each other or an upper surface and a lower surface are bonded.

Description

듀얼 기판 스택 메모리Dual Board Stack Memory
본 발명은 메모리에 관한 것으로, 특히, 서로 전기적으로 연결되어 있지만 다른 기능을 수행하는 블록들을 분리시켜 2개의 기판에 각각 구현한 후, 2개의 기판을 적층하고 이를 전기적으로 연결함으로써, 동작속도 및 평균소모전력을 감소시키는 듀얼 기판 스택 메모리에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory, in particular, by implementing blocks on two substrates by separating blocks that are electrically connected to each other but performing different functions, and then stacking and electrically connecting the two substrates, thereby operating speed and average A dual substrate stack memory for reducing power consumption.
현재 MCU(Micro Control Unit)나 시스템의 화두는 고속동작과 열의 발생을 최소화 하는 것이다. 이를 달성하기 위해 복수의 코어 프로세서를 사용하는 방식이나 메모리의 구조를 종래와는 다르게 하는 방식이 시도되고 있다. 시스템의 동작속도를 증가시키기 위해 마스터 클럭(Master clock) 또는 메인 클럭(Main clock)의 주파수를 증가시키는 것이 일반적인데, 이 경우 시스템을 구성하는 소자들로부터 발생하는 열의 증가가 심각한 수준에 이르기 때문에 바람직하지 않다. Current issues of microcontrol unit (MCU) or system are to minimize high-speed operation and heat generation. In order to achieve this, a method of using a plurality of core processors or a method of making a memory structure different from the conventional methods have been tried. It is common to increase the frequency of the master clock or main clock in order to increase the operating speed of the system, which is desirable because the increase in heat generated by the components of the system is severe. Not.
메모리는, 데이터를 저장하는 메모리 셀을 복수 개 포함하는 메모리 셀 어레이, 상기 메모리 셀 어레이에 데이터를 기록하거나 기록된 데이터를 읽는데 사용되는 센스엠프(Sense amplifier)와 기록구동장치(Write driver) 그리고 외부로부터 전달받아 상기 메모리 셀 어레이에 기록될 데이터를 일시 저장하고 상기 메모리 셀 어레이에 전달하거나, 상기 메모리 셀 어레이로부터 전달받은 데이터를 일시 저장하며 외부에 전달하는 버퍼(data in/out buffer)를 기본적으로 포함한다. The memory includes a memory cell array including a plurality of memory cells for storing data, a sense amplifier, a write driver, and an external device used to write data to or read data from the memory cell array. Basically, a data in / out buffer is used to temporarily store data to be written to the memory cell array and to transmit the data to the memory cell array, or temporarily store data received from the memory cell array and transmit the data to the outside. Include.
많은 양의 데이터를 저장하기 위해서는 많은 수의 메모리 셀 어레이가 필요하고, 이에 따라 센스엠프와 기록구동장치 그리고 버퍼의 수도 증가하게 되어 메모리 장치의 면적이 증가하게 되는 단점이 있다. 또한 메모리 장치를 고속으로 동작시키기 위해서는 메모리 셀 어레이, 센스엠프, 기록구동장치 및 버퍼를 하나의 그룹으로 할 때 복수의 그룹이 필요하게 되어 마찬가지로 메모리 장치의 면적을 증가시키는 단점이 있다. In order to store a large amount of data, a large number of memory cell arrays are required. Accordingly, the number of sense amplifiers, the write driver, and the buffers increases, thereby increasing the area of the memory device. In addition, in order to operate the memory device at a high speed, when a memory cell array, a sense amplifier, a recording driver, and a buffer are used as a group, a plurality of groups are required, which also increases the area of the memory device.
본 발명이 해결하고자 하는 기술적 과제는, 메모리 셀 어레이와 상기 메모리 셀 어레이에 데이터를 기록하거나 상기 메모리 셀 어레이에 기록된 데이터를 읽는 센스엠프부 및 기록구동부를 하나의 기판에 구현하고, 상기 메모리 셀 어레이로부터 읽은 데이터를 일시 저장하거나 상기 메모리 셀 어레이에 기록될 데이터를 일시 저장하는 버퍼를 다른 하나의 기판에 구현한 후 이를 전기적으로 접합하여 사용하는 듀얼 기판 스택 메모리를 제공하는 것에 있다. The technical problem to be solved by the present invention is to implement a sense amplifier unit and a write driver for reading data written to the memory cell array and the memory cell array or the data written in the memory cell array on a single substrate, the memory cell The present invention provides a dual-substrate stack memory in which a buffer for temporarily storing data read from an array or temporarily storing data to be written to the memory cell array is implemented on another substrate and then electrically bonded to each other.
상기 기술적 과제를 달성하기 위한 본 발명의 일면(one aspect)에 따른 듀얼 기판 스택 메모리는, 제1기판 및 제2기판으로 이루어진다. According to an aspect of the present invention, a dual substrate stack memory includes a first substrate and a second substrate.
상기 제1기판은 복수의 메모리 셀 어레이 및 상기 복수의 메모리 셀 어레이에 저장된 데이터를 읽거나 상기 메모리 셀 어레이에 데이터를 저장하는 복수의 센스엠프부 및 기록구동부가 구현된다. 상기 제2기판은 상기 제1기판의 복수의 메모리 셀 어레이 중 해당 메모리 셀 어레이에 저장되어 있던 데이터를 외부로 전달하거나, 외부로부터 전달되며 상기 제1기판의 복수의 메모리 셀 어레이 중 해당 메모리 셀 어레이에 저장되어야 할 데이터를 상기 제1기판으로 전달하며, 상기 데이터를 일시적으로 저장할 수 있는 복수의 저장 공간을 포함하는 데이터 입출력 버퍼가 구현된다. 상기 제1기판에는 상기 복수의 센스엠프부 및 기록구동부와 전기적으로 연결된 복수의 제1기판내부패드가 더 구현되어 있고, 상기 제2기판에는 상기 데이터 입출력 버퍼와 연결된 복수의 제2기판내부패드가 더 구현되어 있으며, 상기 제1기판내부패드들이 구현된 상기 제1기판의 상부면 및 상기 제2기판내부패드들이 구현된 상기 제2기판의 상부면은, 상기 제1기판내부패드들과 상기 제2기판내부패드들의 위치에 맞추어, 서로 접합된다. The first substrate includes a plurality of memory cell arrays and a plurality of sense amplifier parts and a write driver for reading data stored in the plurality of memory cell arrays or storing data in the memory cell array. The second substrate transfers data stored in the memory cell array of the plurality of memory cell arrays of the first substrate to the outside, or is transferred from the outside, and the memory cell array of the plurality of memory cell arrays of the first substrate. A data input / output buffer including a plurality of storage spaces for transferring data to be stored in the first substrate to temporarily store the data is implemented. The first substrate further includes a plurality of first substrate internal pads electrically connected to the plurality of sense amplifier units and the recording driver, and the second substrate includes a plurality of second substrate internal pads connected to the data input / output buffer. Further, the upper surface of the first substrate on which the first substrate inner pads are implemented and the upper surface of the second substrate on which the second substrate inner pads are implemented may include the first substrate inner pads and the first substrate. The two substrate inner pads are bonded to each other according to the position of the pads.
상기 기술적 과제를 달성하기 위한 본 발명의 다른 일면(another aspect)에 따른 듀얼 기판 스택 메모리는, 제1기판 및 제2기판으로 이루어진다. According to another aspect of the present invention for achieving the above technical problem, a dual substrate stack memory includes a first substrate and a second substrate.
상기 제1기판은 메모리 셀 어레이 및 상기 메모리 셀 어레이에 저장된 데이터를 읽거나 상기 메모리 셀 어레이에 데이터를 저장하는 센스엠프부 및 기록구동부가 구현된다. 상기 제2기판은 상기 제1기판으로부터 전달되는 상기 메모리 셀 어레이에 저장되어 있던 데이터를 외부로 전달하거나, 외부로부터 전달되며 상기 메모리 셀 어레이에 저장되어야 할 데이터를 상기 제1기판으로 전달하는 데이터 입출력 버퍼가 구현된다. 상기 제1기판에는 센스엠프부 및 기록구동부와 전기적으로 연결된 복수의 제1기판내부패드가 더 구현되어 있고, 상기 제2기판에는 데이터 입출력 버퍼와 연결된 복수의 제2기판내부패드가 더 구현되어 있으며, 상기 제1기판내부패드 및 상기 제2기판내부패드는 TSV방식을 이용하여 전기적으로 연결된다. The first substrate includes a memory cell array and a sense amplifier unit and a write driver unit for reading data stored in the memory cell array or storing data in the memory cell array. The second substrate transfers data stored in the memory cell array transferred from the first substrate to the outside, or data input / output for transferring data from outside and to be stored in the memory cell array to the first substrate. The buffer is implemented. The first substrate further includes a plurality of first substrate internal pads electrically connected to the sense amplifier unit and the recording driver, and the second substrate further includes a plurality of second substrate internal pads connected to the data input / output buffer. The first substrate inner pad and the second substrate inner pad are electrically connected by using a TSV method.
본 발명에 따른 듀얼 기판 스택 메모리는, 제1기판에 메모리 셀 어레이, 센스엠프부 및 기록구동부를 구현하고 제2기판에는 데이터를 처리하는 회로들을 구현한 후 이를 접합하여 사용함으로써, 주어진 영역에서 많은 양의 데이터를 저장할 수 있을 뿐만 아니라, 동시에 복수의 메모리 셀 어레이에 억세스하여 많은 양의 데이터를 쓰거나 읽을 수 있다는 장점이 있다. In the dual substrate stack memory according to the present invention, a memory cell array, a sense amplifier unit and a write driver unit are implemented on a first substrate, and circuits for processing data are implemented on a second substrate, and then bonded to each other, thereby providing a large number of regions in a given region. In addition to storing a large amount of data, there is an advantage in that a large amount of data can be written or read by simultaneously accessing a plurality of memory cell arrays.
또한 복수의 메모리 셀 어레이가 개별적으로 동작하고 이를 처리하는 장치도 개별적으로 동작하도록 설계할 수 있으며 따라서 제2기판에 집적된 고속으로 동작하는 회로들이 선별적으로 동작할 수 있어, 고속 동작에 따른 소비전력도 최소화할 수 있는 장점이 있다. In addition, a plurality of memory cell arrays can be designed to operate individually and devices for processing the same, so that circuits operating at high speed integrated on the second substrate can be selectively operated. It also has the advantage of minimizing power.
도1은 본 발명에 따른 듀얼 기판 스택 메모리의 블록도이다. 1 is a block diagram of a dual substrate stack memory according to the present invention.
도2는 본 발명의 일 실시 예에 따른 듀얼 기판 스택 메모리의 수직 단면도를 나타낸다. 2 is a vertical cross-sectional view of a dual substrate stack memory according to an embodiment of the present invention.
도3은 본 발명의 다른 일 실시 예에 따른 듀얼 기판 스택 메모리의 수직 단면도이다. 3 is a vertical cross-sectional view of a dual substrate stack memory according to another exemplary embodiment of the present invention.
본 발명과 본 발명의 동작상의 이점 및 본 발명의 실시에 의하여 달성되는 목적을 충분히 이해하기 위해서는 본 발명의 예시적인 실시 예를 설명하는 첨부 도면 및 첨부 도면에 기재된 내용을 참조하여야만 한다. In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that describe exemplary embodiments of the present invention and the contents described in the accompanying drawings.
이하 첨부한 도면을 참조하여 본 발명의 바람직한 실시 예를 설명함으로써, 본 발명을 상세히 설명한다. 각 도면에 제시된 동일한 참조부호는 동일한 부재를 나타낸다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.
도1은 본 발명에 따른 듀얼 기판 스택 메모리의 블록도이다. 1 is a block diagram of a dual substrate stack memory according to the present invention.
도1을 참조하면, 본 발명에 따른 듀얼 기판 스택 메모리(100)를 구성하는 소자들은 2개의 기판(110, 120)에 각각 분리되어 구현된다. Referring to FIG. 1, the elements constituting the dual substrate stack memory 100 according to the present invention are separately implemented on two substrates 110 and 120.
제1기판(110)에는 복수의 메모리 셀 어레이(111)와 복수의 메모리 셀 어레이(111) 각각에 연결된 센스엠프부 및 기록구동부(112)가 구현되어 있고, 제2기판(120)에는 데이터를 일시 저장할 수 있는 복수의 저장공간을 포함하는 데이터 입출력 버퍼(211)가 구현되어 있다. 도면을 간소화를 위해 도1에는 자세하게 도시하지 않았지만, 제2기판(120)에는 데이터 입출력 버퍼(211)와 연결되어 메모리 셀 어레이(111)에 저장된 데이터를 처리하는 신호처리회로가 더 구현되어 있다. The first substrate 110 includes a plurality of memory cell arrays 111 and a sense amplifier unit and a write driver 112 connected to each of the plurality of memory cell arrays 111, and data is stored on the second substrate 120. A data input / output buffer 211 including a plurality of storage spaces that can be temporarily stored is implemented. Although not illustrated in detail in FIG. 1 for the sake of simplicity, the second substrate 120 further includes a signal processing circuit connected to the data input / output buffer 211 to process data stored in the memory cell array 111.
제1기판(110)에 데이터를 실제로 저장하는 메모리 셀 어레이(111)를 복수개 구현함으로써 저장능력을 향상시킬 수 있으며, 복수의 메모리 셀 어레이(111)를 서로 분리시켜 동작시키는 경우 동시에 데이터의 입출력이 가능하기 때문에 메모리(100)의 읽기 쓰기 동작의 속도를 향상시킬 수 있다. The storage capacity may be improved by implementing a plurality of memory cell arrays 111 that actually store data on the first substrate 110. When the plurality of memory cell arrays 111 are operated separately from each other, input / output of data is simultaneously performed. Since it is possible, the speed of the read / write operation of the memory 100 can be improved.
이하에서는 2개의 기판(110, 120)을 전기적으로 연결하는 방법에 대하여 설명한다. Hereinafter, a method of electrically connecting two substrates 110 and 120 will be described.
도2는 본 발명의 일 실시 예에 따른 듀얼 기판 스택 메모리의 수직 단면도를 나타낸다. 2 is a vertical cross-sectional view of a dual substrate stack memory according to an embodiment of the present invention.
도2를 참조하면, 본 발명에 따른 듀얼 기판 스택 메모리는 제1기판(110)을 뒤집어 제2기판(120)에 접합함으로써 구현할 수 있다. 이 때 제1기판(110)에 구현된 제1기판내부패드(PAD1)와 제2기판내부패드(PAD2)가 서로 접하도록 정렬(align)하여야 한다. 본 발명에 따른 듀얼 기판 스택 메모리(100)도 외부와의 전기적인 연결 창구로 외부패드(210)가 설치되어야 한다. Referring to FIG. 2, the dual substrate stack memory according to the present invention may be implemented by inverting the first substrate 110 and bonding the first substrate 110 to the second substrate 120. At this time, the first substrate inner pad PAD1 and the second substrate inner pad PAD2 implemented on the first substrate 110 should be aligned to be in contact with each other. In the dual substrate stack memory 100 according to the present invention, an external pad 210 should be installed as an electrical connection window to the outside.
외부패드(210)는 제1기판(110)의 하부에 설치되는데, 제1기판내부패드(PAD1)로부터 제1기판(110)을 관통하여 외부패드(210)까지 이르는 TSV(Through Silicon Via) 또는 직접접합방식에 의해 제1기판내부패드(PAD1)와 전기적으로 연결된다. The external pad 210 is installed below the first substrate 110, and passes through the first substrate internal pad PAD1 to the external pad 210 through the first substrate 110, or TSV (through silicon via). The first substrate inner pad PAD1 is electrically connected by a direct bonding method.
도면의 간편을 위해 외부패드(210)가 제1기판내부패드(PAD1)에 연결되는 것으로 도시되어 있지만, 실제로는 제1기판(110)을 구성하는 다른 구성요소들과 전기적으로 연결되는 실시 예도 가능하다. 또한 제2기판(120)이 제1기판(110)의 상부에 스택되는 구조도 가능하며, 이 경우에는 외부패드(210)가 제2기판(120)의 하부면에 설치될 것이며, TSV 방식 또는 직접접합방식으로 제2기판내부패드(PAD2)가 외부패드(210)와 전기적으로 연결될 것이다. Although the external pad 210 is illustrated as being connected to the first substrate inner pad PAD1 for the sake of simplicity, an embodiment in which the external pad 210 is electrically connected to other components constituting the first substrate 110 is also possible. Do. In addition, a structure in which the second substrate 120 is stacked on the upper portion of the first substrate 110 is possible. In this case, the external pad 210 may be installed on the lower surface of the second substrate 120. The second substrate inner pad PAD2 may be electrically connected to the outer pad 210 by the direct bonding method.
도3은 본 발명의 다른 일 실시 예에 따른 듀얼 기판 스택 메모리의 수직 단면도이다. 3 is a vertical cross-sectional view of a dual substrate stack memory according to another exemplary embodiment of the present invention.
도3을 참조하면, 본 발명에 따른 듀얼 기판 스택 메모리는 제2기판(120)의 상부면에 제1기판(110)의 하부면을 접합하고, 두 기판(110, 120)의 전기적인 연결은 제1기판(110)에 형성된 TSV를 통해 구현하며, 이 경우 도2에 도시된 것과 같은 외부패드(210)는 필요 없게 된다. Referring to FIG. 3, in the dual substrate stack memory according to the present invention, the lower surface of the first substrate 110 is bonded to the upper surface of the second substrate 120, and electrical connection between the two substrates 110 and 120 is performed. It is implemented through the TSV formed on the first substrate 110, in which case the external pad 210 as shown in Figure 2 is not necessary.
다만, 도2에 도시된 경우에 비해 도3에 도시된 실시 예의 경우 TSV 영역만큼 기판에 구현시킬 면적이 줄어든다는 단점이 있다. However, compared to the case illustrated in FIG. 2, the embodiment illustrated in FIG. 3 has a disadvantage in that the area to be implemented in the substrate is reduced by the TSV region.
도2 및 도3에서 집적회로 구현영역(111, 121)과 패드(PAD1, PAD2) 사이에 도시된 복수의 층(layer)은 금속층(metal layer) 또는 다결정 실리콘 층(poly silicon layer)으로 전도층이다. 2 and 3, the plurality of layers shown between the integrated circuit implementation regions 111 and 121 and the pads PAD1 and PAD2 may be a conductive layer made of a metal layer or a polysilicon layer. to be.
이상에서는 본 발명에 대한 기술사상을 첨부 도면과 함께 서술하였지만 이는 본 발명의 바람직한 실시 예를 예시적으로 설명한 것이지 본 발명을 한정하는 것은 아니다. 또한 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 이라면 누구나 본 발명의 기술적 사상의 범주를 이탈하지 않는 범위 내에서 다양한 변형 및 모방 가능함은 명백한 사실이다. In the above description, the technical idea of the present invention has been described with the accompanying drawings, which illustrate exemplary embodiments of the present invention by way of example and do not limit the present invention. In addition, it is obvious that any person having ordinary knowledge in the technical field to which the present invention belongs can make various modifications and imitations without departing from the scope of the technical idea of the present invention.
[부호의 설명][Description of the code]
110: 제1기판 111: 메모리 셀 어레이 110: first substrate 111: memory cell array
112: 센스엠프부 및 기록구동부 112: sense amplifier unit and recording drive unit
120: 제2기판 121: 데이터 입출력 버퍼 120: second substrate 121: data input and output buffer

Claims (8)

  1. 복수의 메모리 셀 어레이 및 상기 복수의 메모리 셀 어레이에 저장된 데이터를 읽거나 상기 메모리 셀 어레이에 데이터를 저장하는 복수의 센스엠프부 및 기록구동부가 구현된 제1기판; 및 A first substrate including a plurality of memory cell arrays and a plurality of sense amplifier parts and a write driver for reading data stored in the plurality of memory cell arrays or storing data in the memory cell arrays; And
    상기 제1기판의 복수의 메모리 셀 어레이 중 해당 메모리 셀 어레이에 저장되어 있던 데이터를 외부로 전달하거나, 외부로부터 전달되며 상기 제1기판의 복수의 메모리 셀 어레이 중 해당 메모리 셀 어레이에 저장되어야 할 데이터를 상기 제1기판으로 전달하며, 상기 데이터를 일시적으로 저장할 수 있는 복수의 저장공간을 포함하는 데이터 입출력 버퍼가 구현된 제2기판;을 포함하며, Data stored in the memory cell array of the plurality of memory cell arrays of the first substrate is transferred to the outside, or data transmitted from the outside and to be stored in the memory cell array of the plurality of memory cell arrays of the first substrate And a second substrate configured to transmit a data input / output buffer to the first substrate, the data input / output buffer including a plurality of storage spaces for temporarily storing the data.
    상기 제1기판에는 상기 복수의 센스엠프부 및 기록구동부와 전기적으로 연결된 복수의 제1기판내부패드가 더 구현되어 있고, 상기 제2기판에는 상기 데이터 입출력 버퍼와 연결된 복수의 제2기판내부패드가 더 구현되어 있으며, The first substrate further includes a plurality of first substrate internal pads electrically connected to the plurality of sense amplifier units and the recording driver, and the second substrate includes a plurality of second substrate internal pads connected to the data input / output buffer. More implemented,
    상기 제1기판내부패드들이 구현된 상기 제1기판의 상부면 및 상기 제2기판내부패드들 이 구현된 상기 제2기판의 상부면은, 상기 제1기판내부패드들과 상기 제2기판내부패드들의 위치에 맞추어, 서로 접합되는 것을 특징으로 하는 듀얼 기판 스택 메모리.The upper surface of the first substrate on which the first substrate inner pads are implemented and the upper surface of the second substrate on which the second substrate inner pads are implemented are the first substrate inner pads and the second substrate inner pad. Dual-substrate stack memory characterized in that they are bonded to one another according to their position.
  2. 제1항에 있어서, The method of claim 1,
    상기 제1기판에 구현된 복수의 메모리 셀 어레이 각각은 하나의 센스엠프부 및 기록구동부와 연결되어 있는 것을 특징으로 하는 듀얼 기판 스택 메모리. And each of the plurality of memory cell arrays implemented on the first substrate is connected to one sense amplifier unit and a write driver.
  3. 제2항에 있어서, The method of claim 2,
    상기 제1기판의 하부면에는 복수의 외부패드가 더 형성되어 있으며, A plurality of external pads are further formed on the lower surface of the first substrate,
    상기 제1기판의 하부면에 형성된 외부패드는 상기 제1기판내부패드와 상기 외부패드 사이에 형성된 제1기판관통비아 또는 직접접합방식에 의해 전기적으로 연결되며, The external pad formed on the lower surface of the first substrate is electrically connected by a first substrate through via or a direct bonding method formed between the first substrate inner pad and the outer pad.
    상기 제1기판 및 상기 제2기판의 연결은 TSV(Through Silicon Via) 또는 직접접합방식인 것을 특징으로 하는 듀얼 기판 스택 메모리. Dual substrate stack memory, characterized in that the connection between the first substrate and the second substrate is a through silicon via (TSV) or direct bonding method.
  4. 제2항에 있어서, The method of claim 2,
    상기 제2기판의 하부면에는 복수의 외부패드가 더 형성되어 있으며, A plurality of external pads are further formed on the lower surface of the second substrate,
    상기 제2기판의 하부면에 형성된 외부패드는 상기 제2기판내부패드와 상기 외부패드 사이에 형성된 제2기판관통비아 또는 직접접합방식에 의해 전기적으로 연결되고, The external pad formed on the lower surface of the second substrate is electrically connected by a second substrate through via or a direct bonding method formed between the second substrate inner pad and the outer pad,
    상기 제1기판 및 상기 제2기판의 연결은 TSV(Through Silicon Via) 또는 직접접합방식인 것을 특징으로 하는 듀얼 기판 스택 메모리. Dual substrate stack memory, characterized in that the connection between the first substrate and the second substrate is a through silicon via (TSV) or direct bonding method.
  5. 제3항 또는 제4항에 있어서, The method according to claim 3 or 4,
    상기 제2기판에는 상기 데이터 입출력 버퍼와 연결된 적어도 하나의 신호처리회로가 더 구현되어 있는 것을 특징으로 하는 듀얼 기판 스택 메모리. And at least one signal processing circuit connected to the data input / output buffer is further implemented on the second substrate.
  6. 메모리 셀 어레이 및 상기 메모리 셀 어레이에 저장된 데이터를 읽거나 상기 메모리 셀 어레이에 데이터를 저장하는 센스엠프부 및 기록구동부가 구현된 제1기판; 및 A first substrate having a sense amplifier unit and a write driver configured to read a memory cell array and data stored in the memory cell array or to store data in the memory cell array; And
    상기 제1기판으로부터 전달되는 상기 메모리 셀 어레이에 저장되어 있던 데이터를 외부로 전달하거나, 외부로부터 전달되며 상기 메모리 셀 어레이에 저장되어야 할 데이터를 상기 제1기판으로 전달하는 데이터 입출력 버퍼가 구현된 제2기판;을 포함하며, A data input / output buffer configured to transfer data stored in the memory cell array transferred from the first substrate to the outside or transfer data from outside and to be stored in the memory cell array to the first substrate. Including two substrates,
    상기 제1기판에는 센스엠프부 및 기록구동부와 전기적으로 연결된 복수의 제1기판내부패드가 더 구현되어 있고, 상기 제2기판에는 데이터 입출력 버퍼와 연결된 복수의 제2기판내부패드가 더 구현되어 있으며, The first substrate further includes a plurality of first substrate internal pads electrically connected to the sense amplifier unit and the recording driver, and the second substrate further includes a plurality of second substrate internal pads connected to the data input / output buffer. ,
    상기 제1기판내부패드 및 상기 제2기판내부패드는 TSV방식 또는 직접접합방식을 이용하여 전기적으로 연결되는 것을 특징으로 하는 듀얼 기판 스택 메모리. And the first substrate inner pad and the second substrate inner pad are electrically connected using a TSV method or a direct bonding method.
  7. 제6항에 있어서, The method of claim 6,
    상기 제1기판에 구현된 복수의 메모리 셀 어레이 각각은 하나의 센스엠프부 및 기록구동부와 연결되어 있는 것을 특징으로 하는 듀얼 기판 스택 메모리. And each of the plurality of memory cell arrays implemented on the first substrate is connected to one sense amplifier unit and a write driver.
  8. 제7항에 있어서, The method of claim 7, wherein
    상기 제2기판에는 상기 복수의 데이터 입출력 버퍼와 연결된 적어도 하나의 신호처리회로가 더 구현되어 있는 것을 특징으로 하는 듀얼 기판 스택 메모리. And at least one signal processing circuit connected to the plurality of data input / output buffers is further implemented on the second substrate.
PCT/KR2014/000357 2013-01-18 2014-01-13 Dual-substrate stack memory WO2014112758A1 (en)

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KR20110030072A (en) * 2009-09-17 2011-03-23 주식회사 하이닉스반도체 Solid state disk package being able to maintain and protect data and solid state system having the same
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