WO2017023060A1 - Package substrate comprising side pads on edge, chip stack, semiconductor package, and memory module comprising same - Google Patents

Package substrate comprising side pads on edge, chip stack, semiconductor package, and memory module comprising same Download PDF

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Publication number
WO2017023060A1
WO2017023060A1 PCT/KR2016/008434 KR2016008434W WO2017023060A1 WO 2017023060 A1 WO2017023060 A1 WO 2017023060A1 KR 2016008434 W KR2016008434 W KR 2016008434W WO 2017023060 A1 WO2017023060 A1 WO 2017023060A1
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WIPO (PCT)
Prior art keywords
substrate
package
integrated
chip
pad
Prior art date
Application number
PCT/KR2016/008434
Other languages
French (fr)
Korean (ko)
Inventor
송영희
이혁
송기홍
정준희
윤성식
Original Assignee
송영희
이혁
송기홍
정준희
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Filing date
Publication date
Priority claimed from KR1020150108804A external-priority patent/KR101961377B1/en
Priority claimed from KR1020150108808A external-priority patent/KR101672967B1/en
Application filed by 송영희, 이혁, 송기홍, 정준희 filed Critical 송영희
Priority to US15/746,100 priority Critical patent/US10522522B2/en
Priority to CN201680042425.6A priority patent/CN108140636B/en
Publication of WO2017023060A1 publication Critical patent/WO2017023060A1/en

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Definitions

  • the present invention relates to a package substrate, a chip stack, and a semiconductor package including a side pad at an edge, and a memory module. More particularly, the present invention relates to a package according to a standardization trend of a solid state drive (SSD). Despite the slim and small size, high-capacity ultra-high-speed services should be provided, and the LGA-type NAND flash memory semiconductor package best suited for this is realized, and even if the required memory capacity is doubled in the future, the primary packaging is performed using a split chip stack.
  • the present invention relates to a semiconductor package capable of meeting the requirements of slimming and miniaturization even when using the same area by integrating a plurality of memory chip stacks by wire bonding each substrate using side pads on the side of the LGA package substrate.
  • FIG. 1 is a side view showing the configuration of a 16-stage multi-chip package according to the prior art.
  • one or more dies 14 are stacked in a conventional semiconductor NAND flash memory package 10.
  • the number of dies 14 that can be stacked is greatly limited. This is a cause of the capacitive limitation in implementing a high capacity semiconductor NAND flash memory.
  • FIG. 2 illustrates a side view of a conventional BGA package on package.
  • the solder balls 22 may not realize the demand for slimming and miniaturization of the SSD.
  • an object of the present invention is to provide a semiconductor package that can realize the demand of high capacity and ultra-slim.
  • Another object of the present invention is to provide a semiconductor package in which a semiconductor package in which memory semiconductor dies are arranged vertically may maintain its electrical characteristics while minimizing package height even if memory capacity is increased.
  • the semiconductor package of the present invention is mounted on an integrated substrate, the integrated substrate, a plurality of memory semiconductor die is stacked in a chip-on-chip type, the total memory capacity At least one top chip stack configured to cover a portion, mounted on the bottom package, and having a plurality of memory semiconductor dies stacked to cover the remaining of the total memory capacity, the bottom chip stack and the top chip stack It comprises an integrated wire for electrically connecting a, and an integrated protective member for sealing the integrated wire.
  • the chip stack of the present invention, the substrate pad and the side pad is printed on the upper surface, a plurality of memory semiconductor die of the multi-chip package type, a connecting member for electrically connecting the memory semiconductor die, and And a bottom protection member covering all of the semiconductor die, the connection member, and a portion of the substrate.
  • the package substrate of the present invention the insulating PCB body, the upper wiring pattern printed on the inside of the PCB body upper surface pad, the side pad is printed on the upper edge, and the inside of the PCB body And a redistribution pattern electrically connecting the substrate pad and the side pad.
  • the memory semiconductor dies are packaged by dividing them into a plurality of chip stacks without forcing the vertical arrangement of the memory semiconductor dies, it is possible to fundamentally prevent a decrease in yield caused by vertical stacking of the semiconductor dies.
  • each substrate is interposed between the plurality of memory semiconductor dies and wire bonded to electrically connect the divided packages on the side of each substrate, the length of the conductive wire is shortened in nature, and the wire bonding process is easy. Losing effect is expected.
  • each substrate is interposed between the plurality of memory semiconductor dies, an effect of effectively dispersing the high heat generated in the high capacity memory semiconductor die and preventing the thermal characteristics from deteriorating is expected.
  • MCP multi-chip package
  • Figure 2 is a side view showing a BGA package on package (PoP) configuration according to the prior art.
  • Figure 3 is a perspective view showing the configuration of the LGA semiconductor package according to the present invention.
  • FIG. 4 and 5 are side views of FIG. 3 in accordance with various multi-chip package embodiments.
  • FIG. 6 is a perspective view showing a chip stack configuration according to the present invention.
  • FIG. 7A and 7B are side views illustrating a configuration of an LGA semiconductor package according to an embodiment including four 4-chip stacks according to the present invention, respectively, as a rigid package and a flexible package.
  • FIGS. 8A and 8B are side views illustrating a configuration of an LGA semiconductor package according to another embodiment including four 4-chip stacks according to the present invention, respectively, as a rigid package and a flexible package.
  • Figure 9 is a side view showing the LGA semiconductor package configuration according to another embodiment including four 4-chip stack according to the present invention.
  • 10, 11, and 12 are side views showing a configuration in which the side pad according to the present invention is applied to a BOC package, respectively.
  • Fig. 14 is a side view showing the structure of a flexible four stack semiconductor package according to the present invention.
  • Fig. 15 is a block diagram showing an electronic circuit device configuration including a high density memory module configuration to which a DRAM memory semiconductor package according to the present invention is applied.
  • Embodiments described herein will be described with reference to plan and cross-sectional views, which are ideal schematic diagrams of the invention. Therefore, the shape of the exemplary diagram may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in forms generated according to manufacturing processes. Thus, the regions illustrated in the figures have schematic attributes, and the shape of the regions illustrated in the figures is intended to illustrate a particular form of region of the device and is not intended to limit the scope of the invention.
  • a NAND flash memory semiconductor die of a sixteen-stage chip stack is divided into four packages of a four-stage chip stack, and then packaged on an integrated substrate.
  • the electrical characteristics can be maintained while solving the problem of yield reduction caused by the high-capacity stacking.
  • the LGA semiconductor package 100 of the present invention is mounted on an integrated substrate 110 and an integrated substrate 110, and a plurality of memory semiconductor dies 220 are chip on chips.
  • the stacked top chip stack 300 which is stacked to cover the remainder of the total memory capacity, an integrated wire 130 for electrically connecting the upper and lower chip stacks 200 and 300, and an integrated protection member for sealing the integrated wire 130. 140.
  • the bottom chip stack 200 and the top chip stack 300 may be divided. However, if the plurality of packages may be bonded to each other, at least two packages may be included, and FIGS. 7A and 8A. As shown, it is preferred to be divided into four packages.
  • the chip stack may be divided into first to fourth chip stacks 200, 300a, 300b, and 300c.
  • At least one package installed on the integrated substrate 110 is referred to as the bottom chip stack 200, and at least one package bonded on the bottom chip stack 200 as the top chip stack 300. Shall be.
  • the bottom chip stack 200 may include a bottom substrate 210, a plurality of memory semiconductor dies 220 stacked on a bottom substrate 210 in a chip-on-chip form, and a plurality of memory semiconductor dies ( And a bottom protection member 240 covering the bottom substrate 210 and the semiconductor die 220, and a connection member 230 of a through electrode or bonding wire electrically connecting the 220.
  • the bottom substrate 210 may include an insulated PCB body (not shown), an upper wiring pattern (not shown) including a substrate pad 212 and a side pad 214 on an upper surface of the PCB body, and an outer surface on a bottom surface of the PCB body.
  • And / or redistribution patterns (not shown).
  • the insulated PCB body of the present invention may comprise a flexible FPCB substrate.
  • a flexible FPCB substrate for example, as flexible flexible semiconductor substrates and semiconductor dies have been recently developed, and further, flexible flexible semiconductor packages including the above-described substrates and dies have been developed, an insulated PCB body may be configured using an FPCB. . That is, the flexible LGA semiconductor package may be implemented through the flexible substrate, the flexible die, the flexible wire, and the flexible molding (see FIGS. 7B and 8B).
  • the bottom chip stack 200 may be configured as a flexible semiconductor package.
  • the bottom substrate 210 may be bent or bent.
  • the bottom substrate 210 may be formed of a polymer material.
  • the flexible substrate may be typically formed of polyimide (PI), polyester, polyethylene naphthalate (PEN), Teflon, polyethylene terephthalate (PET) or other polymeric.
  • the substrate pad 212 is formed on the bottom substrate 210.
  • the substrate pad 212 may include a flexible copper (Cu), titanium (Ti), aluminum (Al), or a metal alloy to form a curved conductive film.
  • the substrate pad 212 may include conductive metal wires formed through deposition and etching by a lithography method, but may include conductive metal wires formed by printing conductive ink by a printing method for more flexibility. have.
  • the elements of the memory semiconductor die 220 are integrated on the silicon substrate, but the thickness of the silicon substrate does not exceed several tens of micrometers so that it may be bent.
  • the adhesive member (not shown) for bonding the memory semiconductor die 220 may include a polymer material having excellent adhesion, even if the bottom substrate 210 is bent or bent, between the substrate 210 and the semiconductor die 220. Strong adhesive force is required so that peeling or separation does not occur.
  • the bottom protection member 240 may be formed of a material that is bent or bent.
  • the protection member 240 may include a material capable of providing a stress, and may include a polymer or a rubber. In particular, it may include a polyimide.
  • the semiconductor package 200 is bent or bent arbitrarily, it is flexible and stretchable, and damage caused by stress is prevented even when stress caused by stretching occurs, especially when the bottom substrate 210 is bent or stretched, the substrate 210.
  • the substrate pads 212 formed on the N may not be cut or peeled from the substrate 210, thereby preventing a damage to the lowering function due to a contact fail.
  • the external connection terminal may be omitted by directly connecting the substrate pad 212 to the side pad 214 using the redistribution pattern.
  • the bottom chip stack 200 may be configured as a conventional semiconductor package in which a variety of memory semiconductor dies are stacked in various forms on the bottom substrate 210.
  • the multilayer memory semiconductor die may take the form of a multi chip package (MCP) as follows.
  • the memory semiconductor dies 220 are stacked in a staircase form, or as shown in Fig. 5, in a vertical stacking arrangement (see 200) or in a zigzag stacking arrangement.
  • the stacked memory semiconductor dies may not exceed eight stacks.
  • some combinations of planar arrays are not excluded, and various array formats may be determined in consideration of the size and memory capacity of the SSD. It also does not interfere with the arrangement with the logic semiconductor die.
  • the semiconductor dies stacked vertically and vertically are vertical. If it is to be aligned, the semiconductor die 220 may be designed to be stacked up and down as it is.
  • the bottom substrate 210 of the present invention further includes side pads 214 that are electrically connected to the top chip stack 300 at edges to which the memory semiconductor die 220 is not bonded.
  • the side pad 214 is an area for electrically connecting the top chip stack 300 and the bottom chip stack 200 by the integrated wire 130 and also with each semiconductor die 220 through the redistribution (RDL). This is the area to be connected.
  • the top chip stack 300 and the bottom chip stack 200 are connected at one side by the integrated wire 130 in the LGA type, a plurality of packages are not connected to the BGA so that the height of the package is high. It can prevent the increase at the source and make the package slim.
  • the length of the conductive wire is shortened and electrical characteristics are maintained despite the high speed operation.
  • each substrate 210 is placed between each of the plurality of memory semiconductor dies 220, and each of the substrates 210 serves as a terminal through which the conductive wires pass, consequently, the length of the conductive wires can be prevented from becoming longer. have.
  • the side pads 214 are also electrically connected to the plurality of memory semiconductor dies 220 stacked on the bottom substrate 210 by being connected to the redistribution RDL of the bottom substrate 210.
  • Each chip stack 200 and 300 may be connected through an integrated wire 130, and the bottom chip stack 200 and the integrated substrate 110 may be connected using existing external connection terminals as they are.
  • an external contact terminal for electrically connecting the bottom chip stack 200 to the outside may be omitted without having a lower portion.
  • the side pads 214 and the plurality of memory semiconductor dies 220 are connected by redistribution lines (RDLs)
  • the height of the semiconductor package may be significantly reduced by not placing external contact terminals under the wirings.
  • each substrate 210 is inserted between the plurality of memory semiconductor dies 220, heat generated from the memory semiconductor dies 220 may be effectively discharged through each of the substrates 210 having excellent thermal conductivity, thereby improving thermal characteristics. It can be improved.
  • the function of the corresponding package can be independently designed, regardless of the type of semiconductor die packaged in the package.
  • Semiconductor dies can be stacked, which gives greater access to package versatility.
  • LGA is packaged by dividing the memory semiconductor die of the present invention into a plurality of chip stacks, and each LGA chip stack can be electrically connected without using wire bonding using side pads provided in the side space of the LGA package substrate. It is not necessary to decide only, and as shown in FIG. 9, each of the various and diversified chip stacks that can be generalized can be assembled to the LGA package substrate in various ways.
  • a DRAM memory semiconductor die of a 16-layer chip stack is packaged by dividing into four packages of a 4-layer chip stack, and then packaged on an integrated substrate.
  • the electrical characteristics can be maintained while solving the problem of yield reduction caused by the high-capacity stacking.
  • the BOC semiconductor stack package 1100 of the present invention may include an integrated substrate 1110, a split BOC bottom package 1200 attached to the integrated substrate 1110, and a bonding member on the bottom package 1200.
  • Split BOC top package 1300 stacked through 1120, an integrated wire 1130 for electrically connecting bottom and top packages 1200 and 1300, and an integrated protective member 1140 for sealing the integrated wire 1130. It includes.
  • the BOC bottom package 1200 is bonded to a bottom substrate 1210 having a window 1202 at a center thereof, and an active surface facing the bottom substrate 1210, and the first bonding pad 1222a opens the window 1202.
  • the second chip 1224 having the first chip 1222 exposed to the lower portion and the inactive surface bonded to the inactive surface of the first chip 1222, and the second bonding pad 1224a being formed on one side of the active surface. It includes.
  • the first bonding pad 1222a is wire-bonded with the bottom surface of the bottom substrate 1210 through the window 1202, and the first bonding pad 1222a and the first bonding wire 1222b are connected to the first protective member 1222c. By molding.
  • the second bonding pads 1224a are wire bonded to the top surface of the bottom substrate 1210, and the second bonding pads 1224a and the second bonding wires 1224b are molded by the second protective member 1224c. Solder balls 1212 are formed on the bottom of the bottom substrate 1210.
  • the BOC top package 1300 is bonded to a top substrate 1310 having a window 1302 at the center thereof, and an active surface facing the top substrate 1310, and the first bonding pad 1322a opens the window 1302.
  • the first chip 1322 and the non-active surface exposed to the lower portion (the upper portion when referring to the drawing) and the non-active surface are bonded to the non-active surface of the first chip 1322, and the second bonding pad 1324a is formed on one side of the active surface.
  • a second chip 1324 is formed.
  • the first bonding pads 1322a are wire bonded to the bottom surface of the top substrate 1310 through the window 1302, and the first bonding pads 1322a and the first bonding wires 1322b are connected to the first protective member 1322c. By molding.
  • the second bonding pads 1324a are wire bonded to the top surface of the top substrate 1310, and the second bonding pads 1324a and the second bonding wires 1324b are molded by the second protective member 1324c. Since the integrated wire 1130 is provided on the bottom surface of the top substrate 1310, a separate solder ball is not formed.
  • side pads are further included in the edge regions of the bottom substrate 1210 and the top substrate 1310 which are not covered by the second protection member 1224c and the second protection member 1324c.
  • An integration wire 1130 is connected between the side pads to electrically connect the top package 1300 and the bottom package 1200.
  • the memory semiconductor stack package of the present invention is to provide a flexible memory package to be applied to a wearable device requiring high capacity and high specification.
  • the BOC bottom package 1200 may be configured as a flexible semiconductor package.
  • the bottom substrate 1210 may be bent or bent.
  • the bottom substrate 1210 may be formed of a polymer material.
  • the flexible substrate may be typically formed of polyimide (PI), polyester, polyethylene naphthalate (PEN), Teflon, polyethylene terephthalate (PET) or other polymeric.
  • the bonding pad 1222a formed on the bottom substrate 1210 may include a flexible copper (Cu), titanium (Ti), aluminum (Al), or a metal alloy to form a curved conductive film.
  • the bonding pad 1222a may include conductive metal wires formed through deposition and etching by a lithography method, but may include conductive metal wires formed by printing conductive ink by a printing method for more flexibility. have.
  • the elements of the memory first chip 1222 or the second chip 1224 are integrated on the silicon substrate, but the thickness of the silicon substrate does not exceed several tens of micrometers so as to be bent.
  • the adhesive member (not shown) for bonding the first chip 1222 or the second chip 1224 includes a polymer material having excellent adhesion, even if the bottom substrate 1210 is bent or bent. A material with strong adhesion is required so that peeling or separation does not occur between the chips 1220.
  • the protection member 1224c may be formed of a material that is bent or bent.
  • the protection member 1224c may include a material capable of providing a stress, and may include a polymer or a rubber. In particular, it may include a polyimide.
  • the BOC bottom package 1200 is flexible and stretchable, and damage caused by stress is prevented even when stress due to expansion and contraction occurs, and particularly when the bottom substrate 1210 is bent or stretched, the substrate ( The bonding pads 1222a formed on the 1210 are not cut or peeled off from the substrate 1210, thereby preventing a damage to the lowering function due to a contact fail.
  • a BOC semiconductor stack package 1100 may include a first spacer 1120 on an integrated substrate 1110, a split BOC first package 1200, and a first package 1200.
  • Split BOC second package 1300 that is stacked through the second package 1300
  • split BOC third package 1400 that is stacked through the second spacer 1120 on the first package 1300
  • An integrated wire 1130 for electrically connecting the 1400
  • an integrated protective member 1140 for sealing the integrated wire 1130.
  • first and second spacers 1120 provide space between the protective member 1224c of the first package 1200 and the substrate 1310 of the second package 1300, and simultaneously provide both packages 1200 and 1300. Perform the function of splicing.
  • the BOC semiconductor stack package 1100 may include a bonding member on the integrated substrate 1110, the divided BOC first package 1200, and the first package 1200.
  • Split BOC second package 1400 partially overlapped and stacked in a step type through 1120
  • split BOC third package 1400 partially overlapped and laminated through bonding member 1120 on second package 1300
  • An integrated wire 1130 electrically connecting the first to third packages 1200, 1300, and 1400, and an integrated protective member 1140 for sealing the integrated wire 1130.
  • BGA ball grid array
  • the BGA semiconductor package appropriately responds to the increase in the number of input and output pins of the semiconductor chip, and has the advantage of reducing the package size to the size of the semiconductor chip while reducing the inductive component of the electrical connection.
  • contact fail may occur due to uneven solder amount.
  • excessive solder content can cause short circuits between neighboring solder balls during the soldering process.
  • the BGA semiconductor stack package 2100 may include an integrated substrate 2110, a BGA bottom package 2220 stacked on the integrated substrate 2110, and a bottom package 2220. Integrated protection that seals the integrated wires 2130, and the integrated wires 2130 that electrically connect the BGA bottom and top packages 2220 and 2230, and the integrated wires 2130 stacked on the bonding member 2120 thereon. And a member 2140.
  • the BGA bottom package 2220 includes a bottom substrate 2210 and a plurality of chips 2222, 2224, 2226, and 2228 on the bottom substrate 2210, and each memory semiconductor chip 2222, 2224, 2226, and 2228. Is an integrated circuit (not shown) formed therein, a plurality of chip pads 2222a, 2224a, and 2226a electrically connected to the integrated circuit, and a plurality of chip pads 2222a, 2224a, and 2226a. And a plurality of through electrodes (not shown). The plurality of chips 2222, 2224, 2226, and 2228 may be stacked through the adhesive members 2222b, 2224b, and 2226b.
  • the plurality of chips 2222, 2224, 2226, and 2228 may include memory semiconductor chips.
  • the memory semiconductor chip may include a nonvolatile memory, a frequently accessible volatile memory.
  • it may include a flash memory chip, a DRAM chip, a PRAM chip, or a combination thereof.
  • Solder balls 2212 are formed on the bottom surface of the bottom substrate 2210, and protection members 2214 are formed on the top surface of the bottom substrate 2210 to cover the plurality of chips 2222, 2224, 2226, and 2228.
  • the BGA top package 2230 includes a top substrate 2310 and a plurality of chips 2232, 2324, 2326, and 2328 on the top substrate 2310, and each of the memory semiconductor chips 2232, 2324, 2326, and 2328. Is an integrated circuit (not shown) formed therein, a plurality of chip pads 2232a, 2324a and 2326a electrically connected to the integrated circuit, and a plurality of chip pads 2232a, 2324a and 2326a for electrically connecting the integrated circuits. And a plurality of through electrodes (not shown).
  • the plurality of chips 2232, 2324, 2326, and 2328 may be stacked through the adhesive members 2232b, 2324b, and 2326b.
  • the plurality of chips 2232, 2324, 2326, and 2328 may likewise include memory semiconductor chips that include volatile or nonvolatile memory.
  • a protective member 2314 covering the plurality of chips 2232, 2324, 2326, and 2328 is formed on the top surface of the top substrate 2310, but solder balls are omitted on the bottom surface of the top substrate 2310.
  • the side pads 2310d and 2210e are further included in the edge regions of the bottom substrate 2210 not covered by the protection member 2214 and the top substrate 2310 not covered by the protection member 2314.
  • An integrated wire 2130 is connected between the pads 2310d and 2210e to electrically connect the top package 2230 and the bottom package 2220.
  • the top substrate 2310 is a cultivation that electrically connects the connection pad 2310b to the bare substrate 2310a, the connection pad 2310b exposed on the top surface of the bare substrate 2310a, and the inside of the bare substrate 2310a.
  • the connection pad 2310b and the side pad 2310d connected to the connection pad 2310b through the line pattern 2310c the redistribution pattern 2310c, and to protect the redistribution pattern 2310c. Passivation applied to 2310a).
  • the bare substrate 2310a may include a silicon substrate, a glass substrate, or a sapphire substrate. First of all, it may include a flexible substrate.
  • the bottom substrate 2210 may include a bare substrate 2210a, an upper connection pad 2210b exposed on an upper surface of the bare substrate 2210a, a lower connection pad 2210c exposed on a bottom surface of the bare substrate 2210a, and a bare substrate.
  • the redistribution pattern 2210d electrically connecting the upper and lower connection pads 2210b and 2210c to the inside of the 2210a and the side pads 2210e connected to the upper and lower connection pads 2210b and 2210c through the redistribution pattern 2210d.
  • a passivation (not shown) applied to the bare substrate 2210a to expose the upper and lower connection pads 2210b and 2210c and protect the redistribution pattern 2210d.
  • FIG. 14 illustrates a configuration of a four stack semiconductor package according to the present invention for constructing a high density memory module.
  • the semiconductor stack package may be configured as a flexible package.
  • a semiconductor 4 stack package 2100 may include an integrated substrate 2110, a BGA first package 2200, and a first package stacked on the integrated substrate 2110.
  • BGA second package 2300 stacked on the 2200 through the bonding member 2120
  • BGA third package 2400 stacked on the second package 2300 through the bonding member 2122
  • the third package An integrated wire 2130, second and third packages electrically connecting the BGA fourth package 2500, the first and second packages 2200 and 2300, which are stacked on the 2400 through the bonding member 2124.
  • An integrated protective member 2140 is included.
  • 15 is a plan view schematically illustrating a configuration of a high density memory module including a DRAM memory package according to an embodiment of the present invention.
  • the high-density memory module 400 of the present invention may have a constant distance on one side of a module substrate 410, a plurality of DRAM memory packages 420 mounted on the module substrate 410, and a module substrate 410. And a plurality of contact terminals 430 arranged in a row and electrically connecting the DRAM memory package 420.
  • the module substrate 410 may include a PCB substrate. In particular, it may include a flexible PCB. The module substrate 410 may be used on both sides. 8 illustrates the eight DRAM memory packages 420, but the present invention is not limited thereto. In addition, the module substrate 410 may further include a semiconductor package for controlling the DRAM memory package 420.
  • the DRAM memory package 420 may include at least one DRAM memory semiconductor package 1100, a bottom package 1200, or a top package 1200 and 1300 according to the present invention.
  • the contact terminal 430 may include a conductive metal for data input and output.
  • the contact terminal 430 may be variously set according to a standard specification of the high density memory module 400.
  • 16 is a block diagram schematically illustrating an electronic circuit device including a DRAM high density memory module according to an embodiment of the present invention.
  • an electronic circuit device 500 may include a microprocessor 520 disposed on a circuit board 510 and a main memory circuit 530 communicating with the microprocessor 520. And an electrical signal with the sub memory 540, an input signal processing circuit 550 for sending commands to the microprocessor 520, an output signal processing circuit 560 for receiving commands from the microprocessor 520, and other circuit boards.
  • the communication signal processing circuit 570 is exchanged. Arrows can be understood as meaning paths through which electrical signals can be transmitted.
  • the microprocessor 520 may receive and process various electrical signals, output a processing result, and control other components of the electronic circuit device 500.
  • the microprocessor 520 may be understood as, for example, a central processing unit (CPU), a main control unit (MCU), or the like.
  • the main memory circuit 530 may temporarily store data that the microprocessor 520 always or frequently needs. Since the main memory circuit 520 requires a fast speed response, the main memory circuit 520 may be formed of a semiconductor memory. More specifically, the main memory circuit 520 may be a semiconductor memory called a cache, and may be composed of SRAM, DRAM, RRAM and its application semiconductor memories, and other semiconductor memories. In the present embodiment, the main memory circuit 530 may include at least one DRAM memory semiconductor package 1100, a bottom package 1200, or a top package 1200, 1300 according to the present invention.
  • the secondary memory circuit 540 is a mass storage device, and may be a nonvolatile semiconductor memory such as a flash memory or a hard disk drive using a magnetic field.
  • the sub memory 540 may include at least one DRAM memory semiconductor package 1100, a bottom package 1200, or a top package 1200 and 1300 according to the present invention.
  • the input signal processing circuit 550 may convert an external command into an electric signal or transmit an electric signal transmitted from the outside to the microprocessor 520.
  • the input signal processing circuit 550 may include, for example, a keyboard, a mouse, a touch pad, an image recognition device, and the like.
  • the input signal processing circuit 550 may include at least one DRAM memory semiconductor package 1100, a bottom package 1200, or a top package 1200 or 1300 according to the present invention.
  • the output signal processing circuit 560 may be a component for transmitting an electrical signal processed by the microprocessor 520 to the outside.
  • the output signal processing circuit 560 may be a graphics card, an image processor, an optical transducer, a beam panel card, or various functional interface circuits.
  • the output signal processing circuit 560 may include at least one DRAM memory semiconductor package 1100, a bottom package 1200, or a top package 1200, 1300 according to the present invention.
  • the communication circuit 570 is a component for directly exchanging an electrical signal with another electronic system or another circuit board without passing through the input signal processing circuit 550 or the output signal processing circuit 560.
  • the communication circuit 570 may be a modem, a LAN card, various interface circuits, or the like of a personal computer system.
  • the communication circuit 570 may include at least one DRAM memory semiconductor package 1100, a bottom package 1200, or a top package 1200 and 1300 according to the present invention.
  • a high capacity memory is realized through a package on package (POP) package in which semiconductor dies are individually packaged and tested semiconductor dies are stacked up and down, but as the number of stacked dies increases, the yield is increased.
  • POP package on package
  • the BGA semiconductor package of the present invention is dividedly packaged into four- or eight-stage chip stacks, and each chip stack is re-integrated by wire bonding using side pads on the side of the substrate.
  • the memory package of the present invention is likely to be utilized in flexible memory packages applied to SSD products and wearable devices requiring high capacity. Or, it is likely to be used in flexible memory packages applied to wearable devices that require high capacity.

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Abstract

The semiconductor package according to the present invention comprises: an integrated substrate; a bottom chip stack, which is mounted on the integrated substrate, has multiple memory semiconductor dies stacked chip-on-chip, and takes charge of a part of the whole memory capacity; at least one top chip stack, which is mounted on the bottom package, has multiple memory semiconductor dies mounted therein, and takes charge of the rest of the whole memory capacity; an integration wire for electrically connecting the bottom chip stack and the top chip stack(s); and an integration protection member for sealing the integration wire.

Description

에지에 사이드 패드를 포함하는 패키지 기판, 칩 스택, 반도체 패키지 및 이를 포함하는 메모리 모듈 Package substrate including a side pad at the edge, a chip stack, a semiconductor package and a memory module including the same
본 발명은, 에지(edge)에 사이드 패드(side pad)를 포함하는 패키지 기판, 칩 스택, 및 반도체 패키지 그리고 메모리 모듈에 관한 것으로, 더 구체적으로는 솔리드스테이트드라이브(SSD)의 표준화 경향에 따라 패키지가 슬림화되고 소형화에도 불구하고 고용량 초고속 서비스를 제공해야 하며, 이에 가장 적합한 LGA 타입 낸드 플래시 메모리 반도체 패키지를 실현하고, 향후 요구되는 메모리 용량이 2배로 증대되더라도 분할 칩 스택을 이용하여 1차 패키징 하고, LGA 패키지 기판 측면의 사이드 패드를 이용하여 각 기판을 와이어 본딩하는 방식으로 다수 다종 메모리 칩 스택을 통합 패키징 함으로써, 동일 면적을 사용하더라도 슬림화 및 소형화의 요구를 충족할 수 있는 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package substrate, a chip stack, and a semiconductor package including a side pad at an edge, and a memory module. More particularly, the present invention relates to a package according to a standardization trend of a solid state drive (SSD). Despite the slim and small size, high-capacity ultra-high-speed services should be provided, and the LGA-type NAND flash memory semiconductor package best suited for this is realized, and even if the required memory capacity is doubled in the future, the primary packaging is performed using a split chip stack. The present invention relates to a semiconductor package capable of meeting the requirements of slimming and miniaturization even when using the same area by integrating a plurality of memory chip stacks by wire bonding each substrate using side pads on the side of the LGA package substrate.
최근 전자 제품의 기능이 증가하고 크기가 소형화됨에 따라 동일 면적에 더 많은 반도체의 실장이 요구되고 있다. 따라서 단순한 칩 적층 기술 혹은 패키지 적층 기술만으로는 최근 전자 휴대기기의 소형화 및 모바일 제품의 다양한 기능을 만족시킬 수 없다.Recently, as the functions of electronic products have increased and their sizes have been reduced, more semiconductors have to be mounted in the same area. Therefore, simple chip stacking technology or package stacking technology alone cannot satisfy the miniaturization of electronic portable devices and various functions of mobile products.
도 1에는 종래 기술에 의한 16단 멀티 칩 패키지의 구성이 측면도로 도시되어 있다.1 is a side view showing the configuration of a 16-stage multi-chip package according to the prior art.
도 1을 참조하면, 종래의 반도체 낸드 플래시 메모리 패키지(10) 내부에는 다이(14)가 한 개 이상 적층된다. 그러나 양산성을 고려하게 된다면 적층할 수 있는 다이(14)의 수가 크게 제한된다. 이는 고용량의 반도체 낸드 플래시 메모리를 구현하는데 용량적 한계의 원인이 된다.Referring to FIG. 1, one or more dies 14 are stacked in a conventional semiconductor NAND flash memory package 10. However, considering mass productivity, the number of dies 14 that can be stacked is greatly limited. This is a cause of the capacitive limitation in implementing a high capacity semiconductor NAND flash memory.
그럼에도 불구하고 고용량 메모리 추세에 비추어 16단 스택을 형성하게 되면, 기판(12)으로부터 거리가 상대적으로 멀리 떨어져 있는 상부 다이(14)에서 전기적 특성이 악화되어 수율 저하의 원인이 되고, 전체적으로 본딩 와이어(16)의 길이가 길어지는 문제점이 있다.Nevertheless, in the light of the trend of high-capacity memory, the formation of a sixteen-stage stack results in deterioration of electrical characteristics in the upper die 14, which is relatively far from the substrate 12, causing a decrease in yield. There is a problem that the length of 16) is long.
한편, 이와 같은 수율 저하를 개선하기 위하여 패키지 온 패키지(Package on Package) 기술이 소개되기도 한다. On the other hand, a package on package (Package on Package) technology is also introduced to improve such a decrease in yield.
도 2에는 종래 기술에 의한 BGA 패키지 온 패키지의 구성이 측면도로 도시되어 있다.2 illustrates a side view of a conventional BGA package on package.
도 2를 참조하면, PoP 패키지(20)는 볼 그리드 어레이(BGA)에 의하여 패키지 상호간을 연결하기 때문에 솔더 볼(22)에 의하여 SSD의 슬림화 및 소형화의 요구를 실현할 수 없다.Referring to FIG. 2, since the PoP package 20 interconnects the packages by a ball grid array (BGA), the solder balls 22 may not realize the demand for slimming and miniaturization of the SSD.
따라서 본 발명은 상기한 바와 같은 종래 기술의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 고용량화 및 초슬림화의 요구를 실현할 수 있도록 하는 반도체 패키지를 제공하는 것이다.Therefore, the present invention has been made to solve the problems of the prior art as described above, an object of the present invention is to provide a semiconductor package that can realize the demand of high capacity and ultra-slim.
본 발명의 다른 목적은 메모리 반도체 다이가 수직으로 배열되는 반도체 패키지에 있어서 메모리 용량이 증대되더라도 패키지 높이는 최소화되면서 전기적 특성은 그대로 유지될 수 있는 반도체 패키지를 제공하는 것이다.Another object of the present invention is to provide a semiconductor package in which a semiconductor package in which memory semiconductor dies are arranged vertically may maintain its electrical characteristics while minimizing package height even if memory capacity is increased.
전술한 바와 같은 목적을 달성하기 위한 본 발명의 특징에 따르면, 본 발명의 반도체 패키지는 통합 기판, 상기 통합 기판 상에 탑재되고, 복수 메모리 반도체 다이가 칩 온 칩 타입으로 적층되어, 전체 메모리 용량 중 일부를 담당하는 하나의 바텀 칩 스택, 상기 바텀 패키지 상에 탑재되고, 복수 메모리 반도체 다이가 적층되어, 전체 메모리 용량 중 나머지를 담당하는 적어도 하나 이상의 탑 칩 스택, 상기 바텀 칩 스택과 상기 탑 칩 스택을 전기적으로 연결하는 통합 와이어, 및 상기 통합 와이어를 밀봉하는 통합 보호부재를 포함하여 구성된다.According to a feature of the present invention for achieving the object as described above, the semiconductor package of the present invention is mounted on an integrated substrate, the integrated substrate, a plurality of memory semiconductor die is stacked in a chip-on-chip type, the total memory capacity At least one top chip stack configured to cover a portion, mounted on the bottom package, and having a plurality of memory semiconductor dies stacked to cover the remaining of the total memory capacity, the bottom chip stack and the top chip stack It comprises an integrated wire for electrically connecting a, and an integrated protective member for sealing the integrated wire.
본 발명의 다른 특징에 의하면, 본 발명의 칩 스택은, 상면에 기판 패드와 사이드 패드가 인쇄되는 기판, 멀티 칩 패키지 타입의 복수 메모리 반도체 다이, 상기 메모리 반도체 다이를 전기적으로 연결하는 연결부재, 및 상기 반도체 다이와 상기 연결부재 전부 그리고 상기 기판의 일부를 커버하는 바텀 보호부재를 포함한다.According to another feature of the invention, the chip stack of the present invention, the substrate pad and the side pad is printed on the upper surface, a plurality of memory semiconductor die of the multi-chip package type, a connecting member for electrically connecting the memory semiconductor die, and And a bottom protection member covering all of the semiconductor die, the connection member, and a portion of the substrate.
본 발명의 또 다른 특징에 의하면, 본 발명의 패키지 기판은, 절연 PCB 바디, 상기 PCB 바디 상면 내측에 기판 패드가 인쇄되고, 상면 에지에 사이드 패드가 인쇄되는 상부 배선 패턴, 및 상기 PCB 바디 내부에 상기 기판 패드와 상기 사이드 패드를 전기적으로 연결하는 재배선 패턴을 포함한다.According to another feature of the invention, the package substrate of the present invention, the insulating PCB body, the upper wiring pattern printed on the inside of the PCB body upper surface pad, the side pad is printed on the upper edge, and the inside of the PCB body And a redistribution pattern electrically connecting the substrate pad and the side pad.
위에서 설명한 바와 같이, 본 발명의 구성에 의하면 다음과 같은 효과를 기대할 수 있다.As described above, according to the configuration of the present invention, the following effects can be expected.
첫째, 무리하게 메모리 반도체 다이를 수직 배열하지 않고, 다수의 칩 스택으로 분할하여 패키지화 하기 때문에, 반도체 다이의 수직 적층으로 인하여 발생되는 수율 저하를 원천적으로 방지할 수 있다.First, since the memory semiconductor dies are packaged by dividing them into a plurality of chip stacks without forcing the vertical arrangement of the memory semiconductor dies, it is possible to fundamentally prevent a decrease in yield caused by vertical stacking of the semiconductor dies.
둘째, 복수 메모리 반도체 다이 사이에 각 기판이 중간 중간에 삽입 개재되고, 각 기판의 측면에서 분할 패키지를 전기적으로 연결하는 와이어 본딩 되기 때문에, 도전 와이어의 길이가 원천적으로 짧아지고, 와이어 본딩 공정이 수월해지는 효과가 기대된다.Second, since each substrate is interposed between the plurality of memory semiconductor dies and wire bonded to electrically connect the divided packages on the side of each substrate, the length of the conductive wire is shortened in nature, and the wire bonding process is easy. Losing effect is expected.
셋째, 복수 메모리 반도체 다이 사이에 각 기판이 삽입 개재되기 때문에, 고용량 메모리 반도체 다이에서 발생되는 고열을 효과적으로 분산시켜 열 특성이 저하되는 것을 방지하는 효과가 기대된다.Third, since each substrate is interposed between the plurality of memory semiconductor dies, an effect of effectively dispersing the high heat generated in the high capacity memory semiconductor die and preventing the thermal characteristics from deteriorating is expected.
도 1은 종래 기술에 의한 16단 멀티 칩 패키지(MCP) 구성을 나타내는 측면도.1 is a side view showing a 16-stage multi-chip package (MCP) configuration according to the prior art.
도 2는 종래 기술에 의한 BGA 패키지 온 패키지(PoP) 구성을 나타내는 측면도.Figure 2 is a side view showing a BGA package on package (PoP) configuration according to the prior art.
도 3은 본 발명에 의한 LGA 반도체 패키지 구성을 나타내는 사시도.Figure 3 is a perspective view showing the configuration of the LGA semiconductor package according to the present invention.
도 4 및 도 5는 다양한 멀티 칩 패키지 실시예에 따른 도 3의 측면도들.4 and 5 are side views of FIG. 3 in accordance with various multi-chip package embodiments.
도 6은 본 발명에 의한 칩 스택 구성을 나타내는 사시도.6 is a perspective view showing a chip stack configuration according to the present invention.
도 7a 및 도 7b는 본 발명에 의한 4단 칩 스택 4개를 포함하는 일 실시예에 의한 LGA 반도체 패키지의 구성을 각각 경성 패키지와 연성 패키지로 나타내는 측면도들.7A and 7B are side views illustrating a configuration of an LGA semiconductor package according to an embodiment including four 4-chip stacks according to the present invention, respectively, as a rigid package and a flexible package.
도 8a 및 도 8b는 본 발명에 의한 4단 칩 스택 4개를 포함하는 다른 실시예에 의한 LGA 반도체 패키지의 구성을 각각 경성 패키지와 연성 패키지로 나타내는 측면도들.8A and 8B are side views illustrating a configuration of an LGA semiconductor package according to another embodiment including four 4-chip stacks according to the present invention, respectively, as a rigid package and a flexible package.
도 9는 본 발명에 의한 4단 칩 스택 4개를 포함하는 또 다른 실시예에 의한 LGA 반도체 패키지 구성을 나타내는 측면도.Figure 9 is a side view showing the LGA semiconductor package configuration according to another embodiment including four 4-chip stack according to the present invention.
도 10, 도 11, 및 도 12는 본 발명에 의한 사이드 패드를 BOC 패키지에 적용한 구성을 각각 나타내는 측면도들.10, 11, and 12 are side views showing a configuration in which the side pad according to the present invention is applied to a BOC package, respectively.
도 13은 본 발명에 의한 사이드 패드를 BGA 반도체 패키지에 적용한 구성을 나타내는 측면도.It is a side view which shows the structure which applied the side pad which concerns on this invention to the BGA semiconductor package.
도 14는 본 발명에 의한 연성 4 스택 반도체 패키지의 구성을 나타내는 측면도.Fig. 14 is a side view showing the structure of a flexible four stack semiconductor package according to the present invention.
도 15는 본 발명에 의한 DRAM 메모리 반도체 패키지가 적용되는 고밀도 메모리 모듈 구성을 포함하는 전자 회로 기기 구성을 나타내는 블록도.Fig. 15 is a block diagram showing an electronic circuit device configuration including a high density memory module configuration to which a DRAM memory semiconductor package according to the present invention is applied.
본 발명의 이점 및 특징, 그리고 그것들을 달성하는 방법은 첨부되는 도면과 함께 상세하게 후술되어 있는 실시예들을 참조하면 명확해 질 것이다. 그러나 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려 주기 위해 제공되는 것이며, 본 발명은 청구항의 범주에 의해 정의될 뿐이다. 도면에서 층 및 영역들의 크기 및 상대적인 크기는 설명의 명료성을 위해 과장된 것일 수 있다. 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성 요소를 지칭한다.Advantages and features of the present invention and methods for achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
본 명세서에서 기술하는 실시예들은 본 발명의 이상적인 개략도인 평면도 및 단면도를 참고하여 설명될 것이다. 따라서 제조 기술 및/또는 허용 오차 등에 의해 예시도의 형태가 변형될 수 있다. 따라서 본 발명의 실시예들은 도시된 특정 형태로 제한되는 것이 아니라 제조 공정에 따라 생성되는 형태의 변화도 포함하는 것이다. 따라서 도면에서 예시된 영역들은 개략적인 속성을 가지며, 도면에서 예시된 영역들의 모양은 소자의 영역의 특정 형태를 예시하기 위한 것이고, 발명의 범주를 제한하기 위한 것은 아니다.Embodiments described herein will be described with reference to plan and cross-sectional views, which are ideal schematic diagrams of the invention. Therefore, the shape of the exemplary diagram may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in forms generated according to manufacturing processes. Thus, the regions illustrated in the figures have schematic attributes, and the shape of the regions illustrated in the figures is intended to illustrate a particular form of region of the device and is not intended to limit the scope of the invention.
이하, 상기한 바와 같은 구성을 가지는 본 발명에 의한 LGA 반도체 패키지의 바람직한 실시예를 첨부된 도면을 참고하여 상세하게 설명한다.Hereinafter, a preferred embodiment of the LGA semiconductor package according to the present invention having the configuration as described above will be described in detail with reference to the accompanying drawings.
본 발명의 LGA 반도체 패키지는 일례로 16단 칩 스택의 낸드 플래시 메모리 반도체 다이를 4단 칩 스택의 4개 패키지로 나누어 패키징 하고, 이를 다시 통합 기판 상에 패키징 하는 것이다. In the LGA semiconductor package of the present invention, for example, a NAND flash memory semiconductor die of a sixteen-stage chip stack is divided into four packages of a four-stage chip stack, and then packaged on an integrated substrate.
이와 같이 고용량 적층 메모리 반도체 다이를 분할하여 패키징 한 상태에서 최종 패키징 하면 고용량 적층에 따른 수율 감소의 문제를 해결하면서 전기적 특성은 그대로 유지할 수 있게 된다.When the final packaging is packaged by dividing the high-capacity stacked memory semiconductor die in this manner, the electrical characteristics can be maintained while solving the problem of yield reduction caused by the high-capacity stacking.
도 1 내지 도 6을 참조하면, 본 발명의 LGA 반도체 패키지(100)는, 통합 기판(110), 통합 기판(110) 상에 탑재되고, 복수 메모리 반도체 다이(220)가 칩 온 칩(chip on chip) 타입으로 적층되어, 전체 메모리 용량 중 일부를 담당하는 분할 바텀 칩 스택(200), 바텀 칩 스택(200) 상에 접합부재(120)를 이용하여 탑재되고, 복수 메모리 반도체 다이(220)가 적층되어, 전체 메모리 용량 중 나머지를 담당하는 분할 탑 칩 스택(300), 상하 칩 스택(200, 300)을 전기적으로 연결하는 통합 와이어(130), 및 통합 와이어(130)를 밀봉하는 통합 보호부재(140)를 포함한다.1 to 6, the LGA semiconductor package 100 of the present invention is mounted on an integrated substrate 110 and an integrated substrate 110, and a plurality of memory semiconductor dies 220 are chip on chips. chip stacked, and are mounted on the bottom chip stack 200 and the bottom chip stack 200, which are part of the total memory capacity, by using the bonding member 120. The stacked top chip stack 300 which is stacked to cover the remainder of the total memory capacity, an integrated wire 130 for electrically connecting the upper and lower chip stacks 200 and 300, and an integrated protection member for sealing the integrated wire 130. 140.
본 발명의 실시예에서 바텀 칩 스택(200)과 탑 칩 스택(300)으로 구분하였으나, 상기한 패키지가 복수개로 접합될 수 있다면, 적어도 2개의 패키지를 포함하는 것으로 하고, 도 7a 및 도 8a에 도시된 바와 같이 4개의 패키지로 분할되는 것이 바람직하다. 가령, 칩 스택은 제1칩 스택 내지 제4 칩 스택(200, 300a, 300b, 300c)으로 분할될 수 있다. In the exemplary embodiment of the present invention, the bottom chip stack 200 and the top chip stack 300 may be divided. However, if the plurality of packages may be bonded to each other, at least two packages may be included, and FIGS. 7A and 8A. As shown, it is preferred to be divided into four packages. For example, the chip stack may be divided into first to fourth chip stacks 200, 300a, 300b, and 300c.
다만 설명의 편의상 통합 기판(110) 측에 설치되는 적어도 하나의 패키지는 바텀 칩 스택(200)으로 하고, 바텀 칩 스택(200) 상에 접합되는 적어도 하나 이상의 패키지를 탑 칩 스택(300)으로 하기로 한다.However, for convenience of description, at least one package installed on the integrated substrate 110 is referred to as the bottom chip stack 200, and at least one package bonded on the bottom chip stack 200 as the top chip stack 300. Shall be.
특히 도 6을 참조하면, 바텀 칩 스택(200)은, 바텀 기판(210), 바텀 기판(210) 상에 칩 온 칩 형태로 적층되는 다수의 메모리 반도체 다이(220), 다수의 메모리 반도체 다이(220)를 전기적으로 연결하는 관통 전극 혹은 본딩 와이어의 연결부재(230), 및 바텀 기판(210)과 반도체 다이(220)를 커버하는 바텀 보호부재(240)를 포함한다.In particular, referring to FIG. 6, the bottom chip stack 200 may include a bottom substrate 210, a plurality of memory semiconductor dies 220 stacked on a bottom substrate 210 in a chip-on-chip form, and a plurality of memory semiconductor dies ( And a bottom protection member 240 covering the bottom substrate 210 and the semiconductor die 220, and a connection member 230 of a through electrode or bonding wire electrically connecting the 220.
바텀 기판(210)은, 절연 PCB 바디(도면부호 없음), PCB 바디의 상면에 기판 패드(212)와 사이드 패드(214)를 포함하는 상부 배선 패턴(도시되지 않음), PCB 바디의 저면에 외부 접속 단자를 포함하는 하부 배선 패턴(도시되지 않음), 및 PCB 바디 내부에 기판 패드(212)와 외부 접속 단자를 연결하거나 혹은 기판 패드(212)와 사이드 패드(214)를 전기적으로 연결하는 관통 전극 및/또는 재배선 패턴(도시되지 않음)을 포함한다.The bottom substrate 210 may include an insulated PCB body (not shown), an upper wiring pattern (not shown) including a substrate pad 212 and a side pad 214 on an upper surface of the PCB body, and an outer surface on a bottom surface of the PCB body. A lower wiring pattern (not shown) including connection terminals, and a through electrode connecting the substrate pad 212 and the external connection terminal to the inside of the PCB body or electrically connecting the substrate pad 212 and the side pad 214. And / or redistribution patterns (not shown).
본 발명의 절연 PCB 바디는 유연성을 가지는 FPCB 기판을 포함할 수 있다. 가령, 최근 자유자재로 휘어지는 유연 반도체 기판 및 반도체 다이가 개발되고, 나아가 전술한 기판 및 다이를 포함하는 자유자재로 휘어지는 유연 반도체 패키지가 개발됨에 따라, 절연 PCB 바디는 FPCB를 이용하여 구성될 수 있다. 즉, 유연 기판, 유연 다이, 유연 와이어, 및 유연 몰딩을 통하여 유연 LGA 반도체 패키지의 구현이 가능하다(도 7b 및 도 8b 참조).The insulated PCB body of the present invention may comprise a flexible FPCB substrate. For example, as flexible flexible semiconductor substrates and semiconductor dies have been recently developed, and further, flexible flexible semiconductor packages including the above-described substrates and dies have been developed, an insulated PCB body may be configured using an FPCB. . That is, the flexible LGA semiconductor package may be implemented through the flexible substrate, the flexible die, the flexible wire, and the flexible molding (see FIGS. 7B and 8B).
예컨대, 바텀 칩 스택(200)은 연성 반도체 패키지로 구성될 수 있다. 이를 위하여, 바텀 기판(210)은, 휘어지거나 구부러질 수 있다. 이를 위하여 바텀 기판(210)은 폴리머 재질로 형성될 수 있다. 가령, 연성 기판은 대표적으로 폴리이미드(PI), 폴리에스터(polyester), 폴리에틸렌 나프탈레이트(PEN), 테플론(Teflon), 폴리에틸렌 테레프탈레이트(PET) 또는 기타 중합체(polymeric)로 형성될 수 있다. For example, the bottom chip stack 200 may be configured as a flexible semiconductor package. To this end, the bottom substrate 210 may be bent or bent. For this purpose, the bottom substrate 210 may be formed of a polymer material. For example, the flexible substrate may be typically formed of polyimide (PI), polyester, polyethylene naphthalate (PEN), Teflon, polyethylene terephthalate (PET) or other polymeric.
기판 패드(212)는 바텀 기판(210) 상에 형성되는데, 연성 재질의 구리(Cu), 티타늄(Ti), 알루미늄(Al) 또는 금속 합금을 포함하여, 휘어지는 도전막을 형성할 수 있다. 이러한 기판 패드(212)는, 리소그래피 공법에 의한 증착 및 식각을 통하여 형성되는 전도성 금속 배선을 포함할 수 있지만, 보다 유연성을 위하여 인쇄 공법에 의한 전도성 잉크를 프린팅 하여 형성되는 전도성 금속 배선을 포함할 수 있다. The substrate pad 212 is formed on the bottom substrate 210. The substrate pad 212 may include a flexible copper (Cu), titanium (Ti), aluminum (Al), or a metal alloy to form a curved conductive film. The substrate pad 212 may include conductive metal wires formed through deposition and etching by a lithography method, but may include conductive metal wires formed by printing conductive ink by a printing method for more flexibility. have.
메모리 반도체 다이(220)의 소자들은 실리콘 기판 상에 집적되되, 휘어질 수 있도록 실리콘 기판의 두께는 수십 마이크로미터를 넘지 않는 것으로 한다. The elements of the memory semiconductor die 220 are integrated on the silicon substrate, but the thickness of the silicon substrate does not exceed several tens of micrometers so that it may be bent.
한편 메모리 반도체 다이(220)를 접합하는 접착부재(도시되지 않음)는 접착력이 우수한 고분자 물질을 포함하여 바텀 기판(210)이 휘거나 구부러지더라도, 기판(210)과 반도체 다이(220) 사이에 박리 혹은 분리 현상이 발생하지 않도록 접착력이 강한 물질이 요구된다.On the other hand, the adhesive member (not shown) for bonding the memory semiconductor die 220 may include a polymer material having excellent adhesion, even if the bottom substrate 210 is bent or bent, between the substrate 210 and the semiconductor die 220. Strong adhesive force is required so that peeling or separation does not occur.
바텀 보호부재(240)는, 휘어지거나 구부려지는 재질로 형성될 수 있다. 가령, 보호부재(240)는, 응력을 제공할 수 있는 물질을 포함하며, 폴리머 재질(polymer)이나 고무 재질(rubber)을 포함할 수 있다. 특히 폴리이미드(poly imide)를 포함할 수 있다.The bottom protection member 240 may be formed of a material that is bent or bent. For example, the protection member 240 may include a material capable of providing a stress, and may include a polymer or a rubber. In particular, it may include a polyimide.
따라서 반도체 패키지(200)를 임의로 휘거나 구부리더라도 유연하고 신축 가능하고, 신축에 따른 응력이 발생하더라도 응력에 따른 손상이 방지되고, 특히 바텀 기판(210)을 구부리거나 잡아 늘렸을 때, 기판(210) 상에 형성되는 기판 패드(212)가 절단되거나 기판(210)으로부터 박리되지 않아, 콘택 패일(contact fail)로 인하 기능 손상을 방지할 수 있다.Therefore, even if the semiconductor package 200 is bent or bent arbitrarily, it is flexible and stretchable, and damage caused by stress is prevented even when stress caused by stretching occurs, especially when the bottom substrate 210 is bent or stretched, the substrate 210. The substrate pads 212 formed on the N may not be cut or peeled from the substrate 210, thereby preventing a damage to the lowering function due to a contact fail.
한편, 본 발명은 실시예에 따라서 재배선 패턴을 이용하여 기판 패드(212)를 사이드 패드(214)에 직접 연결함으로써, 외부 접속 단자를 생략할 수 있다. Meanwhile, according to an exemplary embodiment of the present invention, the external connection terminal may be omitted by directly connecting the substrate pad 212 to the side pad 214 using the redistribution pattern.
바텀 칩 스택(200)은, 바텀 기판(210) 상에 다종 메모리 반도체 다이가 다양한 형태로 적층되는 통상의 반도체 패키지로 구성될 수 있다. 여기서 다층 메모리 반도체 다이는 아래와 같이 멀티 칩 패키지(Multi Chip Package; MCP) 형태를 취할 수 있다.The bottom chip stack 200 may be configured as a conventional semiconductor package in which a variety of memory semiconductor dies are stacked in various forms on the bottom substrate 210. The multilayer memory semiconductor die may take the form of a multi chip package (MCP) as follows.
도 4에 도시된 바와 같이, 메모리 반도체 다이(220)가 계단 형태로 적층 배열되거나, 혹은 도 5에 도시된 바와 같이, 수직으로 적층 배열(도면부호 200 참조)되거나 내지는 지그재그로 적층 배열(도면부호 300 참조)될 수 있으며, 고속 동작에 따른 전기적 특성이 악화되지 않도록 하기 위하여 적층되는 메모리 반도체 다이는 8단 스택을 넘지 않는 것으로 한다. 그러나 평면 배열을 일부 결합하는 것을 배제하지 않으며, SSD의 사이즈와 메모리 용량을 고려하여 다양한 배열 형식이 결정될 수 있다. 또한 로직 반도체 다이와 함께 배열되는 것을 방해하지 않는다.As shown in Fig. 4, the memory semiconductor dies 220 are stacked in a staircase form, or as shown in Fig. 5, in a vertical stacking arrangement (see 200) or in a zigzag stacking arrangement. In order to prevent deterioration of electrical characteristics due to high-speed operation, the stacked memory semiconductor dies may not exceed eight stacks. However, some combinations of planar arrays are not excluded, and various array formats may be determined in consideration of the size and memory capacity of the SSD. It also does not interfere with the arrangement with the logic semiconductor die.
도 5를 참조하면, 칩 스택(300)에 적층되는 메모리 반도체 다이(220) 상호간의 전기적 연결을 와이어 본딩에 의하지 않고 관통 전극(도시되지 않음)을 이용하는 경우, 상하 수직으로 적층되는 반도체 다이가 수직 정렬되어야 하는 경우 반도체 다이(220)는 그대로 상하 적층되도록 설계할 수 있다. Referring to FIG. 5, when a through electrode (not shown) is used for electrical connection between the memory semiconductor dies 220 stacked on the chip stack 300 by wire bonding, the semiconductor dies stacked vertically and vertically are vertical. If it is to be aligned, the semiconductor die 220 may be designed to be stacked up and down as it is.
이와 같이, 본 발명의 바텀 기판(210)은 메모리 반도체 다이(220)가 접합되지 않은 에지(edge)에 탑 칩 스택(300)과 전기적으로 연결되도록 하는 사이드 패드(214)가 더 형성되는 것이 특징이며, 이러한 사이드 패드(214)는 통합 와이어(130)에 의하여 탑 칩 스택(300)과 바텀 칩 스택(200)을 전기적으로 연결하는 영역이면서도 재배선(RDL)을 통하여 각 반도체 다이(220)와도 연결되는 영역이다.As described above, the bottom substrate 210 of the present invention further includes side pads 214 that are electrically connected to the top chip stack 300 at edges to which the memory semiconductor die 220 is not bonded. The side pad 214 is an area for electrically connecting the top chip stack 300 and the bottom chip stack 200 by the integrated wire 130 and also with each semiconductor die 220 through the redistribution (RDL). This is the area to be connected.
본 발명은 탑 칩 스택(300)과 바텀 칩 스택(200)이 LGA 타입으로 통합 와이어(130)에 의하여 일 측면에서 연결되기 때문에, 복수 패키지가 BGA로 연결되지 않음으로써 패키지의 높이(High)가 증가되는 것을 원천적으로 방지하고 패키지를 슬림화 할 수 있다. In the present invention, since the top chip stack 300 and the bottom chip stack 200 are connected at one side by the integrated wire 130 in the LGA type, a plurality of packages are not connected to the BGA so that the height of the package is high. It can prevent the increase at the source and make the package slim.
또한, 다수 패키지를 분할 팁 스택으로 분리하여 구성함으로써 도전 와이어의 길이가 짧아지며 고속 동작에도 불구하고 전기적 특성이 유지되는 효과가 있다. 가령, 각 복수 메모리 반도체 다이(220) 사이에 각 기판(210)이 게재되고, 각 기판(210)은 도전 와이어가 지나가는 터미널 역할을 하기 때문에, 결과적으로 도전 와이어의 길이가 길어지는 것을 방지할 수 있다.In addition, by dividing a plurality of packages into a split tip stack, the length of the conductive wire is shortened and electrical characteristics are maintained despite the high speed operation. For example, since each substrate 210 is placed between each of the plurality of memory semiconductor dies 220, and each of the substrates 210 serves as a terminal through which the conductive wires pass, consequently, the length of the conductive wires can be prevented from becoming longer. have.
사이드 패드(214)는 바텀 기판(210)의 재배선(RDL)과 연결되어 바텀 기판(210) 상에 적층되는 복수 메모리 반도체 다이(220)와도 전기적으로 연결된다. 각 칩 스택(200, 300) 사이에는 통합 와이어(130)를 통하여 연결하고, 바텀 칩 스택(200)과 통합 기판(110) 사이에는 기존 외부 접속 단자를 그대로 이용하여 연결될 수 있다.The side pads 214 are also electrically connected to the plurality of memory semiconductor dies 220 stacked on the bottom substrate 210 by being connected to the redistribution RDL of the bottom substrate 210. Each chip stack 200 and 300 may be connected through an integrated wire 130, and the bottom chip stack 200 and the integrated substrate 110 may be connected using existing external connection terminals as they are.
오히려 본 발명의 실시예에서는 바텀 칩 스택(200)을 외부와 전기적으로 연결하는 외부 접촉 단자를 하부에 구비하지 않고 생략할 수 있다. 가령, 사이드 패드(214)와 복수 메모리 반도체 다이(220)를 재배선(RDL)으로 연결하면, 외부 접촉 단자를 하부에 두지 않음으로써, 반도체 패키지의 높이(High)를 현저히 줄일 수 있게 된다.Rather, in the exemplary embodiment of the present invention, an external contact terminal for electrically connecting the bottom chip stack 200 to the outside may be omitted without having a lower portion. For example, when the side pads 214 and the plurality of memory semiconductor dies 220 are connected by redistribution lines (RDLs), the height of the semiconductor package may be significantly reduced by not placing external contact terminals under the wirings.
결과적으로 각 기판(210)이 다수 메모리 반도체 다이(220) 사이에 삽입됨으로써, 열전도성이 우수한 각 기판(210)을 통하여 메모리 반도체 다이(220)에서 발생되는 열을 효과적으로 배출할 수 있어 열 특성을 개선할 수 있다.As a result, since each substrate 210 is inserted between the plurality of memory semiconductor dies 220, heat generated from the memory semiconductor dies 220 may be effectively discharged through each of the substrates 210 having excellent thermal conductivity, thereby improving thermal characteristics. It can be improved.
이와 같이 바텀 칩 스택(200)과 탑 칩 스택(300)을 분할하여 구성하게 되면, 해당 패키지의 기능을 독립적으로 설계할 수 있고, 해당 패키지에 패키징 되는 반도체 다이의 종류에 구애받지 않고 어떠한 형태의 반도체 다이든 적층할 수 있으며, 이에 패키지 범용화에 더 접근할 수 있게 된다.As such, when the bottom chip stack 200 and the top chip stack 300 are divided and configured, the function of the corresponding package can be independently designed, regardless of the type of semiconductor die packaged in the package. Semiconductor dies can be stacked, which gives greater access to package versatility.
본 발명의 메모리 반도체 다이를 다수의 칩 스택으로 분할하여 LGA 패키징 하고, LGA 패키지 기판의 측면 공간에 마련된 사이드 패드를 이용하여 와이어 본딩에 의하지 않더라도 각 LGA 칩 스택을 전기적으로 연결할 수 있기 때문에 상하 수직 배열만을 주장할 필요는 없고, 도 9에 도시된 바와 같이 범용화 가능한 다종다양한 각 분할 칩 스택을 LGA 패키지 기판에 다양한 방법으로 조립할 수 있다.LGA is packaged by dividing the memory semiconductor die of the present invention into a plurality of chip stacks, and each LGA chip stack can be electrically connected without using wire bonding using side pads provided in the side space of the LGA package substrate. It is not necessary to insist only, and as shown in FIG. 9, each of the various and diversified chip stacks that can be generalized can be assembled to the LGA package substrate in various ways.
본 발명의 BGA 반도체 스택 패키지는 일례로 16단 칩 스택의 DRAM 메모리 반도체 다이를 4단 칩 스택의 4개 패키지로 나누어 패키징 하고, 이를 다시 통합 기판 상에 패키징 하는 것이다. In the BGA semiconductor stack package of the present invention, for example, a DRAM memory semiconductor die of a 16-layer chip stack is packaged by dividing into four packages of a 4-layer chip stack, and then packaged on an integrated substrate.
이와 같이 고용량 적층 메모리 반도체 다이를 분할하여 패키징 한 상태에서 최종 패키징 하면 고용량 적층에 따른 수율 감소의 문제를 해결하면서 전기적 특성은 그대로 유지할 수 있게 된다.When the final packaging is packaged by dividing the high-capacity stacked memory semiconductor die in this manner, the electrical characteristics can be maintained while solving the problem of yield reduction caused by the high-capacity stacking.
도 10을 참조하면, 본 발명의 BOC 반도체 스택 패키지(1100)는, 통합 기판(1110), 통합 기판(1110) 상에 부착되는 분할 BOC 바텀 패키지(1200), 바텀 패키지(1200) 상에 접합부재(1120)를 통해 적층되는 분할 BOC 탑 패키지(1300), 바텀 및 탑 패키지(1200, 1300)를 전기적으로 연결하는 통합 와이어(1130), 및 통합 와이어(1130)를 밀봉하는 통합 보호부재(1140)를 포함한다.Referring to FIG. 10, the BOC semiconductor stack package 1100 of the present invention may include an integrated substrate 1110, a split BOC bottom package 1200 attached to the integrated substrate 1110, and a bonding member on the bottom package 1200. Split BOC top package 1300 stacked through 1120, an integrated wire 1130 for electrically connecting bottom and top packages 1200 and 1300, and an integrated protective member 1140 for sealing the integrated wire 1130. It includes.
BOC 바텀 패키지(1200)는, 중심에 창(1202)을 가지는 바텀 기판(1210), 바텀 기판(1210) 상에 활성면이 마주하도록 접합되고, 제1본딩 패드(1222a)가 창(1202)을 통해 하부로 노출되는 제1칩(1222), 및 비활성면이 제1칩(1222)의 비활성면에 접합되고, 활성면의 일측에 제2본딩 패드(1224a)가 형성되는 제2칩(1224)을 포함한다.The BOC bottom package 1200 is bonded to a bottom substrate 1210 having a window 1202 at a center thereof, and an active surface facing the bottom substrate 1210, and the first bonding pad 1222a opens the window 1202. The second chip 1224 having the first chip 1222 exposed to the lower portion and the inactive surface bonded to the inactive surface of the first chip 1222, and the second bonding pad 1224a being formed on one side of the active surface. It includes.
제1본딩 패드(1222a)는 창(1202)을 통해 바텀 기판(1210)의 저면과 와이어 본딩 되고, 제1본딩 패드(1222a) 및 제1본딩 와이어(1222b)는 제1보호부재(1222c)에 의하여 몰딩 된다. The first bonding pad 1222a is wire-bonded with the bottom surface of the bottom substrate 1210 through the window 1202, and the first bonding pad 1222a and the first bonding wire 1222b are connected to the first protective member 1222c. By molding.
제2본딩 패드(1224a)는 바텀 기판(1210)의 상면과 와이어 본딩 되고, 제2본딩 패드(1224a) 및 제2본딩 와이어(1224b)는 제2보호부재(1224c)에 의하여 몰딩 된다. 바텀 기판(1210)의 저면에는 솔더 볼(1212)이 형성된다.The second bonding pads 1224a are wire bonded to the top surface of the bottom substrate 1210, and the second bonding pads 1224a and the second bonding wires 1224b are molded by the second protective member 1224c. Solder balls 1212 are formed on the bottom of the bottom substrate 1210.
BOC 탑 패키지(1300)는, 중심에 창(1302)을 가지는 탑 기판(1310), 탑 기판(1310) 상에 활성면이 마주하도록 접합되고, 제1본딩 패드(1322a)가 창(1302)을 통해 하부(도면을 기준으로 하면 상부)로 노출되는 제1칩(1322), 및 비활성면이 제1칩(1322)의 비활성면에 접합되고, 활성면의 일측에 제2본딩 패드(1324a)가 형성되는 제2칩(1324)을 포함한다.The BOC top package 1300 is bonded to a top substrate 1310 having a window 1302 at the center thereof, and an active surface facing the top substrate 1310, and the first bonding pad 1322a opens the window 1302. The first chip 1322 and the non-active surface exposed to the lower portion (the upper portion when referring to the drawing) and the non-active surface are bonded to the non-active surface of the first chip 1322, and the second bonding pad 1324a is formed on one side of the active surface. A second chip 1324 is formed.
제1본딩 패드(1322a)는 창(1302)을 통해 탑 기판(1310)의 저면과 와이어 본딩 되고, 제1본딩 패드(1322a) 및 제1본딩 와이어(1322b)는 제1보호부재(1322c)에 의하여 몰딩 된다. The first bonding pads 1322a are wire bonded to the bottom surface of the top substrate 1310 through the window 1302, and the first bonding pads 1322a and the first bonding wires 1322b are connected to the first protective member 1322c. By molding.
제2본딩 패드(1324a)는 탑 기판(1310)의 상면과 와이어 본딩 되고, 제2본딩 패드(1324a) 및 제2본딩 와이어(1324b)는 제2보호부재(1324c)에 의하여 몰딩 된다. 탑 기판(1310)의 저면에는 통합 와이어(1130)가 구비되기 때문에 별도의 솔더 볼이 형성되지 않는다.The second bonding pads 1324a are wire bonded to the top surface of the top substrate 1310, and the second bonding pads 1324a and the second bonding wires 1324b are molded by the second protective member 1324c. Since the integrated wire 1130 is provided on the bottom surface of the top substrate 1310, a separate solder ball is not formed.
무엇보다도, 제2보호부재(1224c) 및 제2보호부재(1324c)에 의하여 커버되지 않은 바텀 기판(1210) 및 탑 기판(1310)의 에지 영역에 사이드 패드(도시되지 않음)가 더 포함됨으로써, 사이드 패드 사이를 통합 와이어(1130)가 연결되어 탑 패키지(1300)와 바텀 패키지(1200)를 전기적으로 연결한다.Above all, side pads (not shown) are further included in the edge regions of the bottom substrate 1210 and the top substrate 1310 which are not covered by the second protection member 1224c and the second protection member 1324c. An integration wire 1130 is connected between the side pads to electrically connect the top package 1300 and the bottom package 1200.
한편, 본 발명의 메모리 반도체 스택 패키지는 고용량 고사양이 요구되는 웨어러블 디바이스에 적용되도록, 연성 메모리 패키지를 제공하고자 한다.Meanwhile, the memory semiconductor stack package of the present invention is to provide a flexible memory package to be applied to a wearable device requiring high capacity and high specification.
일례로, BOC 바텀 패키지(1200)는 연성 반도체 패키지로 구성될 수 있다. 이를 위하여, 바텀 기판(1210)은, 휘어지거나 구부러질 수 있다. 이를 위하여 바텀 기판(1210)은 폴리머 재질로 형성될 수 있다. 가령, 연성 기판은 대표적으로 폴리이미드(PI), 폴리에스터(polyester), 폴리에틸렌 나프탈레이트(PEN), 테플론(Teflon), 폴리에틸렌 테레프탈레이트(PET) 또는 기타 중합체(polymeric)로 형성될 수 있다. For example, the BOC bottom package 1200 may be configured as a flexible semiconductor package. To this end, the bottom substrate 1210 may be bent or bent. To this end, the bottom substrate 1210 may be formed of a polymer material. For example, the flexible substrate may be typically formed of polyimide (PI), polyester, polyethylene naphthalate (PEN), Teflon, polyethylene terephthalate (PET) or other polymeric.
바텀 기판(1210) 상에 형성되는 본딩 패드(1222a)는 연성 재질의 구리(Cu), 티타늄(Ti), 알루미늄(Al) 또는 금속 합금을 포함하여, 휘어지는 도전막을 형성할 수 있다. 이러한 본딩 패드(1222a)는, 리소그래피 공법에 의한 증착 및 식각을 통하여 형성되는 전도성 금속 배선을 포함할 수 있지만, 보다 유연성을 위하여 인쇄 공법에 의한 전도성 잉크를 프린팅 하여 형성되는 전도성 금속 배선을 포함할 수 있다. The bonding pad 1222a formed on the bottom substrate 1210 may include a flexible copper (Cu), titanium (Ti), aluminum (Al), or a metal alloy to form a curved conductive film. The bonding pad 1222a may include conductive metal wires formed through deposition and etching by a lithography method, but may include conductive metal wires formed by printing conductive ink by a printing method for more flexibility. have.
메모리 제1칩(1222) 혹은 제2칩(1224)의 소자들은 실리콘 기판 상에 집적되되, 휘어질 수 있도록 실리콘 기판의 두께는 수십 마이크로미터를 넘지 않는 것으로 한다. The elements of the memory first chip 1222 or the second chip 1224 are integrated on the silicon substrate, but the thickness of the silicon substrate does not exceed several tens of micrometers so as to be bent.
한편 제1칩(1222) 혹은 제2칩(1224)을 접합하는 접착부재(도시되지 않음)는 접착력이 우수한 고분자 물질을 포함하여 바텀 기판(1210)이 휘거나 구부러지더라도, 기판(1210)과 칩(1220) 사이에 박리 혹은 분리 현상이 발생하지 않도록 접착력이 강한 물질이 요구된다.On the other hand, the adhesive member (not shown) for bonding the first chip 1222 or the second chip 1224 includes a polymer material having excellent adhesion, even if the bottom substrate 1210 is bent or bent. A material with strong adhesion is required so that peeling or separation does not occur between the chips 1220.
보호부재(1224c)는, 휘어지거나 구부려지는 재질로 형성될 수 있다. 가령, 보호부재(1224c)는, 응력을 제공할 수 있는 물질을 포함하며, 폴리머 재질(polymer)이나 고무 재질(rubber)을 포함할 수 있다. 특히 폴리이미드(poly imide)를 포함할 수 있다.The protection member 1224c may be formed of a material that is bent or bent. For example, the protection member 1224c may include a material capable of providing a stress, and may include a polymer or a rubber. In particular, it may include a polyimide.
따라서 BOC 바텀 패키지(1200)를 임의로 휘거나 구부리더라도 유연하고 신축 가능하고, 신축에 따른 응력이 발생하더라도 응력에 따른 손상이 방지되고, 특히 바텀 기판(1210)을 구부리거나 잡아 늘렸을 때, 기판(1210) 상에 형성되는 본딩 패드(1222a)가 절단되거나 기판(1210)으로부터 박리되지 않아, 콘택 패일(contact fail)로 인하 기능 손상을 방지할 수 있다.Accordingly, even if the BOC bottom package 1200 is bent or bent arbitrarily, it is flexible and stretchable, and damage caused by stress is prevented even when stress due to expansion and contraction occurs, and particularly when the bottom substrate 1210 is bent or stretched, the substrate ( The bonding pads 1222a formed on the 1210 are not cut or peeled off from the substrate 1210, thereby preventing a damage to the lowering function due to a contact fail.
도 11을 참조하면, 본 발명의 다른 실시예의 BOC 반도체 스택 패키지(1100)는, 통합 기판(1110), 분할 BOC 제1패키지(1200), 제1패키지(1200) 상에 제1스페이서(1120)를 통해 적층되는 분할 BOC 제2패키지(1300), 제2패키지(1300) 상에 제2스페이서(1120)를 통해 적층되는 분할 BOC 제3패키지(1400), 제1 내지 제3패키지(1200, 1300, 1400)를 전기적으로 연결하는 통합 와이어(1130), 및 통합 와이어(1130)를 밀봉하는 통합 보호부재(1140)를 포함한다.Referring to FIG. 11, a BOC semiconductor stack package 1100 according to another embodiment of the present invention may include a first spacer 1120 on an integrated substrate 1110, a split BOC first package 1200, and a first package 1200. Split BOC second package 1300 that is stacked through the second package 1300, split BOC third package 1400 that is stacked through the second spacer 1120 on the first package 1300, the first to third packages 1200, 1300 , An integrated wire 1130 for electrically connecting the 1400, and an integrated protective member 1140 for sealing the integrated wire 1130.
이때 제1 및 제2스페이서(1120)는 제1패키지(1200)의 보호부재(1224c)와 제2패키지(1300)의 기판(1310) 사이에서 공간을 제공하는 동시에 양 패키지(1200, 1300)를 접합하는 기능을 수행한다.In this case, the first and second spacers 1120 provide space between the protective member 1224c of the first package 1200 and the substrate 1310 of the second package 1300, and simultaneously provide both packages 1200 and 1300. Perform the function of splicing.
도 12를 참조하면, 본 발명의 또 다른 실시예에 의한 BOC 반도체 스택 패키지(1100)는, 통합 기판(1110), 분할 BOC 제1패키지(1200), 제1패키지(1200) 상에 접합부재(1120)를 통해 일부만 오버랩되어 계단 타입으로 적층되는 분할 BOC 제2패키지(1300), 제2패키지(1300) 상에 접합부재(1120)를 통해 일부만 오버랩되어 적층되는 분할 BOC 제3패키지(1400), 제1 내지 제3패키지(1200, 1300, 1400)를 전기적으로 연결하는 통합 와이어(1130), 및 통합 와이어(1130)를 밀봉하는 통합 보호부재(1140)를 포함한다.Referring to FIG. 12, the BOC semiconductor stack package 1100 according to another embodiment of the present invention may include a bonding member on the integrated substrate 1110, the divided BOC first package 1200, and the first package 1200. Split BOC second package 1400 partially overlapped and stacked in a step type through 1120, split BOC third package 1400 partially overlapped and laminated through bonding member 1120 on second package 1300, An integrated wire 1130 electrically connecting the first to third packages 1200, 1300, and 1400, and an integrated protective member 1140 for sealing the integrated wire 1130.
전자제품의 소형화 및 경량화 경향에 따라 패키지의 사이즈가 점차 줄어들고 있다. 이러한 고집적 및 고성능 패키지 개발 노력에 의하여, 패키지의 외부 전기 접속 수단을 격자 배열(grid array) 방식으로 한 볼 그리드 어레이(Ball Grid Array: BGA) 패키지가 소개되고 있다.As the size of electronic products becomes smaller and lighter, the size of packages is gradually decreasing. Due to such high-density and high-performance package development efforts, a ball grid array (BGA) package is introduced, in which a grid array method is used for external electrical connection means of the package.
그러나 전술한 바와 같이 BGA 반도체 패키지는 반도체 칩의 입출력 핀 수 증가에 적절하게 대응하고, 전기 접속부의 유도 성분을 줄이면서 패키지 크기를 반도체 칩 수준의 크기로 줄일 수 있다는 장점을 지닌 반면, 표면 실장형 반도체 패키지(Surface Mounting Technology) 방식으로 솔더 볼을 매개로 PCB에 실장되는 경우, 솔더 양이 균일하지 않아 콘택 패일(contact fail)이 발생하는 경우가 있다. 특히 솔더 양이 지나치면 솔더링 과정에서 이웃하는 솔더 볼 간에 단락이 발행하는 경우가 있다.However, as described above, the BGA semiconductor package appropriately responds to the increase in the number of input and output pins of the semiconductor chip, and has the advantage of reducing the package size to the size of the semiconductor chip while reducing the inductive component of the electrical connection. When the PCB is mounted on a PCB through solder balls through a semiconductor mounting technology, contact fail may occur due to uneven solder amount. In particular, excessive solder content can cause short circuits between neighboring solder balls during the soldering process.
도 13을 참조하면, 본 발명의 일 실시예에 의한 BGA 반도체 스택 패키지(2100)는, 통합 기판(2110), 통합 기판(2110) 상에 적층되는 BGA 바텀 패키지(2220), 바텀 패키지(2220) 상에 접합부재(2120)를 통해 적층되는 BGA 탑 패키지(2230), BGA 바텀 및 탑 패키지(2220, 2230)를 전기적으로 연결하는 통합 와이어(2130), 및 통합 와이어(2130)를 밀봉하는 통합 보호부재(2140)를 포함한다.Referring to FIG. 13, the BGA semiconductor stack package 2100 according to an embodiment of the present invention may include an integrated substrate 2110, a BGA bottom package 2220 stacked on the integrated substrate 2110, and a bottom package 2220. Integrated protection that seals the integrated wires 2130, and the integrated wires 2130 that electrically connect the BGA bottom and top packages 2220 and 2230, and the integrated wires 2130 stacked on the bonding member 2120 thereon. And a member 2140.
BGA 바텀 패키지(2220)는, 바텀 기판(2210), 바텀 기판(2210) 상에 다수의 칩(2222, 2224, 2226, 2228)으로 구성되고, 각 메모리 반도체 칩들(2222, 2224, 2226, 2228)은 내부에 형성되는 집적 회로(도시되지 않음), 상기 집적 회로와 전기적으로 연결되는 다수의 칩 패드(2222a, 2224a, 2226a) 및, 다수의 칩 패드(2222a, 2224a, 2226a)를 전기적으로 연결하는 다수의 관통 전극(도시되지 않음)을 포함한다. 다수의 칩(2222, 2224, 2226, 2228)은 접착부재(2222b, 2224b, 2226b)를 통하여 적층될 수 있다. The BGA bottom package 2220 includes a bottom substrate 2210 and a plurality of chips 2222, 2224, 2226, and 2228 on the bottom substrate 2210, and each memory semiconductor chip 2222, 2224, 2226, and 2228. Is an integrated circuit (not shown) formed therein, a plurality of chip pads 2222a, 2224a, and 2226a electrically connected to the integrated circuit, and a plurality of chip pads 2222a, 2224a, and 2226a. And a plurality of through electrodes (not shown). The plurality of chips 2222, 2224, 2226, and 2228 may be stacked through the adhesive members 2222b, 2224b, and 2226b.
다수의 칩(2222, 2224, 2226, 2228)은 메모리 반도체 칩을 포함할 수 있다. 메모리 반도체 칩은 비휘발성 메모리, 수시로 접근 가능한 휘발성 메모리를 포함할 수 있다. 가령, 플래시 메모리 칩, DRAM 칩, PRAM 칩 또는 이들의 조합을 포함할 수 있다.The plurality of chips 2222, 2224, 2226, and 2228 may include memory semiconductor chips. The memory semiconductor chip may include a nonvolatile memory, a frequently accessible volatile memory. For example, it may include a flash memory chip, a DRAM chip, a PRAM chip, or a combination thereof.
바텀 기판(2210)의 저면에는 솔더 볼(2212)이 형성되고, 바텀 기판(2210)의 상면에는 다수의 칩(2222, 2224, 2226, 2228)을 커버하는 보호부재(2214)가 형성된다. Solder balls 2212 are formed on the bottom surface of the bottom substrate 2210, and protection members 2214 are formed on the top surface of the bottom substrate 2210 to cover the plurality of chips 2222, 2224, 2226, and 2228.
BGA 탑 패키지(2230)는, 탑 기판(2310), 탑 기판(2310) 상에 다수의 칩(2322, 2324, 2326, 2328)으로 구성되고, 각 메모리 반도체 칩들(2322, 2324, 2326, 2328)은 내부에 형성되는 집적 회로(도시되지 않음), 상기 집적 회로와 전기적으로 연결되는 다수의 칩 패드(2322a, 2324a, 2326a) 및, 다수의 칩 패드(2322a, 2324a, 2326a)를 전기적으로 연결하는 다수의 관통 전극(도시되지 않음)을 포함한다. 다수의 칩(2322, 2324, 2326, 2328)은 접착부재(2322b, 2324b, 2326b)를 통하여 적층될 수 있다. The BGA top package 2230 includes a top substrate 2310 and a plurality of chips 2232, 2324, 2326, and 2328 on the top substrate 2310, and each of the memory semiconductor chips 2232, 2324, 2326, and 2328. Is an integrated circuit (not shown) formed therein, a plurality of chip pads 2232a, 2324a and 2326a electrically connected to the integrated circuit, and a plurality of chip pads 2232a, 2324a and 2326a for electrically connecting the integrated circuits. And a plurality of through electrodes (not shown). The plurality of chips 2232, 2324, 2326, and 2328 may be stacked through the adhesive members 2232b, 2324b, and 2326b.
다수의 칩(2322, 2324, 2326, 2328)은 마찬가지로 휘발성 혹은 비휘발성 메모리를 포함하는 메모리 반도체 칩을 포함할 수 있다. The plurality of chips 2232, 2324, 2326, and 2328 may likewise include memory semiconductor chips that include volatile or nonvolatile memory.
탑 기판(2310)의 상면에는 다수의 칩(2322, 2324, 2326, 2328)을 커버하는 보호부재(2314)가 형성되지만, 탑 기판(2310)의 저면에는 솔더 볼이 형성되지 않고 생략된다. A protective member 2314 covering the plurality of chips 2232, 2324, 2326, and 2328 is formed on the top surface of the top substrate 2310, but solder balls are omitted on the bottom surface of the top substrate 2310.
특히, 보호부재(2214)에 의하여 커버되지 않는 바텀 기판(2210) 및 보호부재(2314)에 의하여 커버되지 않은 탑 기판(2310)의 에지 영역에 사이드 패드(2310d, 2210e)가 더 포함됨으로써, 사이드 패드(2310d, 2210e) 사이를 통합 와이어(2130)가 연결되어 탑 패키지(2230)와 바텀 패키지(2220)를 전기적으로 연결한다.In particular, the side pads 2310d and 2210e are further included in the edge regions of the bottom substrate 2210 not covered by the protection member 2214 and the top substrate 2310 not covered by the protection member 2314. An integrated wire 2130 is connected between the pads 2310d and 2210e to electrically connect the top package 2230 and the bottom package 2220.
가령, 탑 기판(2310)은, 베어 기판(2310a), 베어 기판(2310a)의 상면에 노출되는 접속 패드(2310b), 베어 기판(2310a)의 내부에서 접속 패드(2310b)를 전기적으로 연결하는 재배선 패턴(2310c), 재배선 패턴(2310c)을 통하여 접속 패드(2310b)와 연결되는 사이드 패드(2310d), 및 접속 패드(2310b)를 노출시키고 재배선 패턴(2310c)을 보호하기 위하여 베어 기판(2310a)에 도포되는 페시베이션을 포함할 수 있다.For example, the top substrate 2310 is a cultivation that electrically connects the connection pad 2310b to the bare substrate 2310a, the connection pad 2310b exposed on the top surface of the bare substrate 2310a, and the inside of the bare substrate 2310a. In order to expose the connection pad 2310b and the side pad 2310d connected to the connection pad 2310b through the line pattern 2310c, the redistribution pattern 2310c, and to protect the redistribution pattern 2310c. Passivation applied to 2310a).
베어 기판(2310a)은 실리콘 기판, 유리 기판 혹은 사파이어 기판을 포함할 수 있다. 무엇보다도 가요성 기판을 포함할 수 있다. The bare substrate 2310a may include a silicon substrate, a glass substrate, or a sapphire substrate. First of all, it may include a flexible substrate.
가령, 바텀 기판(2210)은 베어 기판(2210a), 베어 기판(2210a)의 상면에 노출되는 상부 접속 패드(2210b), 베어 기판(2210a)의 저면에 노출되는 하부 접속 패드(2210c), 베어 기판(2210a)의 내부에서 상하부 접속 패드(2210b, 2210c)를 전기적으로 연결하는 재배선 패턴(2210d), 재배선 패턴(2210d)을 통하여 상하부 접속 패드(2210b, 2210c)와 연결되는 사이드 패드(2210e), 상하부 접속 패드(2210b, 2210c)를 노출시키고 재배선 패턴(2210d)을 보호하기 위하여 베어 기판(2210a)에 도포되는 페시베이션(도시되지 않음)을 포함할 수 있다.For example, the bottom substrate 2210 may include a bare substrate 2210a, an upper connection pad 2210b exposed on an upper surface of the bare substrate 2210a, a lower connection pad 2210c exposed on a bottom surface of the bare substrate 2210a, and a bare substrate. The redistribution pattern 2210d electrically connecting the upper and lower connection pads 2210b and 2210c to the inside of the 2210a and the side pads 2210e connected to the upper and lower connection pads 2210b and 2210c through the redistribution pattern 2210d. And a passivation (not shown) applied to the bare substrate 2210a to expose the upper and lower connection pads 2210b and 2210c and protect the redistribution pattern 2210d.
한편, 도 14에는 고밀도 메모리 모듈을 구성하기 위한 본 발명에 의한 4 스택 반도체 패키지의 구성이 도시되어 있다. 해당 반도체 스택 패키지는 연성 패키지로 구성될 수 있다. Meanwhile, FIG. 14 illustrates a configuration of a four stack semiconductor package according to the present invention for constructing a high density memory module. The semiconductor stack package may be configured as a flexible package.
도 15를 참조하면, 본 발명의 다른 실시예에 의한 반도체 4스택 패키지(2100)는, 통합 기판(2110), 통합 기판(2110) 상에 적층되는 BGA 제1패키지(2200), 제1패키지(2200) 상에 접합부재(2120)를 통해 적층되는 BGA 제2패키지(2300), 제2패키지(2300) 상에 접합부재(2122)를 통해 적층되는 BGA 제3패키지(2400), 제3패키지(2400) 상에 접합부재(2124)를 통해 적층되는 BGA 제4패키지(2500), 제1 및 제2패키지(2200, 2300)를 전기적으로 연결하는 통합 와이어(2130), 제2 및 제3패키지(2300, 2400)를 전기적으로 연결하는 통합 와이어(2132), 제3 및 제4패키지(2400, 2500)를 전기적으로 연결하는 통합 와이어(2134), 및 통합 와이어(2130, 2140, 2150)를 밀봉하는 통합 보호부재(2140)를 포함한다.Referring to FIG. 15, a semiconductor 4 stack package 2100 according to another embodiment of the present invention may include an integrated substrate 2110, a BGA first package 2200, and a first package stacked on the integrated substrate 2110. BGA second package 2300 stacked on the 2200 through the bonding member 2120, BGA third package 2400 stacked on the second package 2300 through the bonding member 2122, and the third package ( An integrated wire 2130, second and third packages electrically connecting the BGA fourth package 2500, the first and second packages 2200 and 2300, which are stacked on the 2400 through the bonding member 2124. An integrated wire 2132 electrically connecting the 2300 and 2400, an integrated wire 2134 electrically connecting the third and fourth packages 2400 and 2500, and an integrated wire 2130, 2140, and 2150 to seal the integrated wires 2130, 2140 and 2150. An integrated protective member 2140 is included.
도 15는 본 발명의 일 실시예에 의한 DRAM 메모리 패키지를 포함하는 고밀도 메모리 모듈의 구성을 개략적으로 도시한 평면도이다. 15 is a plan view schematically illustrating a configuration of a high density memory module including a DRAM memory package according to an embodiment of the present invention.
도 15를 참조하면, 본 발명의 고밀도 메모리 모듈(400)은 모듈 기판(410), 모듈 기판(410) 상에 실장되는 다수의 DRAM 메모리 패키지(420), 모듈 기판(410)의 일측에 일정한 간격으로 배열되고 DRAM 메모리 패키지(420)를 전기적으로 연결하는 다수의 접촉 단자(430)를 포함한다.Referring to FIG. 15, the high-density memory module 400 of the present invention may have a constant distance on one side of a module substrate 410, a plurality of DRAM memory packages 420 mounted on the module substrate 410, and a module substrate 410. And a plurality of contact terminals 430 arranged in a row and electrically connecting the DRAM memory package 420.
모듈 기판(410)은 PCB 기판을 포함할 수 있다. 특히 연성 PCB를 포함할 수 있다. 모듈 기판(410)은 양면 모두 사용가능하다. 도면에는 8개의 상기 DRAM 메모리 패키지(420)를 예시하고 있으나, 여기에 제한되지 않는다. 또한 모듈 기판(410)에는 DRAM 메모리 패키지(420)를 제어하는 반도체 패키지가 더 포함될 수 있다. The module substrate 410 may include a PCB substrate. In particular, it may include a flexible PCB. The module substrate 410 may be used on both sides. 8 illustrates the eight DRAM memory packages 420, but the present invention is not limited thereto. In addition, the module substrate 410 may further include a semiconductor package for controlling the DRAM memory package 420.
DRAM 메모리 패키지(420)는 본 발명에 의한 DRAM 메모리 반도체 패키지(1100), 또는 바텀 패키지(1200)나 탑 패키지(1200, 1300)를 적어도 하나 이상 포함할 수 있다.The DRAM memory package 420 may include at least one DRAM memory semiconductor package 1100, a bottom package 1200, or a top package 1200 and 1300 according to the present invention.
접촉 단자(430)는 데이터 입출력을 위하여 도전성 금속을 포함할 수 있다. 접촉 단자(430)는 고밀도 메모리 모듈(400)의 표준 규격에 따라 다양하게 설정될 수 있다. The contact terminal 430 may include a conductive metal for data input and output. The contact terminal 430 may be variously set according to a standard specification of the high density memory module 400.
도 16은 본 발명의 일 실시예에 의한 DRAM 고밀도 메모리 모듈을 포함하는 전자 회로 기기를 개략적으로 도시한 블록 다이어그램이다. 16 is a block diagram schematically illustrating an electronic circuit device including a DRAM high density memory module according to an embodiment of the present invention.
도 16을 참조하면, 본 발명의 일 실시예에 의한 전자 회로 기기(500)는 회로 기판(510) 상에 배치된 마이크로프로세서(520), 마이크로프로세서(520)와 통신하는 주 기억 회로(530) 및 부 기억 회로(540), 마이크로프로세서(520)로 명령을 보내는 입력 신호 처리 회로(550), 마이크로프로세서(520)로부터 명령을 받는 출력 신호 처리 회로(560) 및 다른 회로 기판들과 전기 신호를 주고받는 통신 신호 처리 회로(570)를 포함한다. 화살표들은 전기적 신호가 전달될 수 있는 경로를 의미하는 것으로 이해될 수 있다.Referring to FIG. 16, an electronic circuit device 500 according to an embodiment of the present invention may include a microprocessor 520 disposed on a circuit board 510 and a main memory circuit 530 communicating with the microprocessor 520. And an electrical signal with the sub memory 540, an input signal processing circuit 550 for sending commands to the microprocessor 520, an output signal processing circuit 560 for receiving commands from the microprocessor 520, and other circuit boards. The communication signal processing circuit 570 is exchanged. Arrows can be understood as meaning paths through which electrical signals can be transmitted.
마이크로프로세서(520)는 각종 전기 신호를 받아 처리 하고 처리 결과를 출력할 수 있으며, 전자 회로 기기(500)의 다른 구성 요소들을 제어할 수 있다. 마이크로프로세서(520)는 예를 들어, 중앙처리장치(CPU: central processing unit), 및/또는 주 제어장치(MCU: main control unit) 등으로 이해될 수 있다.The microprocessor 520 may receive and process various electrical signals, output a processing result, and control other components of the electronic circuit device 500. The microprocessor 520 may be understood as, for example, a central processing unit (CPU), a main control unit (MCU), or the like.
주 기억 회로(530)는 마이크로프로세서(520)가 항상 또는 빈번하게 필요로 하는 데이터를 임시로 저장할 수 있다. 주 기억 회로(520)는 빠른 속의 응답이 필요하므로, 반도체 메모리로 구성될 수 있다. 보다 상세하게, 주 기억 회로(520)는 캐시(cache)로 불리는 반도체 메모리일 수도 있고, SRAM, DRAM, RRAM 및 그 응용 반도체 메모리들, 기타 반도체 메모리로 구성될 수 있다. 본 실시예에서, 주 기억 회로(530)는 본 발명에 의한 DRAM 메모리 반도체 패키지(1100), 또는 바텀 패키지(1200)나 탑 패키지(1200, 1300)를 적어도 하나 이상 포함할 수 있다.The main memory circuit 530 may temporarily store data that the microprocessor 520 always or frequently needs. Since the main memory circuit 520 requires a fast speed response, the main memory circuit 520 may be formed of a semiconductor memory. More specifically, the main memory circuit 520 may be a semiconductor memory called a cache, and may be composed of SRAM, DRAM, RRAM and its application semiconductor memories, and other semiconductor memories. In the present embodiment, the main memory circuit 530 may include at least one DRAM memory semiconductor package 1100, a bottom package 1200, or a top package 1200, 1300 according to the present invention.
부 기억 회로(540)는 대용량 기억 소자이고, 플래시 메모리 같은 비휘발성 반도체 메모리이거나 마그네틱 필드를 이용한 하드 디스크 드라이브일 수 있다. 부 기억 회로(540)는 본 발명에 의한 DRAM 메모리 반도체 패키지(1100), 또는 바텀 패키지(1200)나 탑 패키지(1200, 1300)를 적어도 하나 이상 포함할 수 있다.The secondary memory circuit 540 is a mass storage device, and may be a nonvolatile semiconductor memory such as a flash memory or a hard disk drive using a magnetic field. The sub memory 540 may include at least one DRAM memory semiconductor package 1100, a bottom package 1200, or a top package 1200 and 1300 according to the present invention.
입력 신호 처리 회로(550)는 외부의 명령을 전기적 신호로 바꾸거나, 외부로부터 전달된 전기적 신호를 마이크로프로세서(520)로 전달할 수 있다. 입력 신호 처리 회로(550)는 예를 들어 키보드, 마우스, 터치 패드, 이미지 인식장치 등을 포함할 수 있다. 입력 신호 처리 회로(550)는 본 발명에 의한 DRAM 메모리 반도체 패키지(1100), 또는 바텀 패키지(1200)나 탑 패키지(1200, 1300)를 적어도 하나 이상 포함할 수 있다.The input signal processing circuit 550 may convert an external command into an electric signal or transmit an electric signal transmitted from the outside to the microprocessor 520. The input signal processing circuit 550 may include, for example, a keyboard, a mouse, a touch pad, an image recognition device, and the like. The input signal processing circuit 550 may include at least one DRAM memory semiconductor package 1100, a bottom package 1200, or a top package 1200 or 1300 according to the present invention.
출력 신호 처리 회로(560)는 마이크로프로세서(520)에서 처리된 전기 신호를 외부로 전송하기 위한 구성 요소일 수 있다. 예를 들어, 출력 신호 처리 회로(560)는 그래픽 카드, 이미지 프로세서, 광학 변환기, 빔 패널 카드, 또는 다양한 기능의 인터페이스 회로 등일 수 있다. 상기 출력 신호 처리 회로(560)는 본 발명에 의한 DRAM 메모리 반도체 패키지(1100), 또는 바텀 패키지(1200)나 탑 패키지(1200, 1300)를 적어도 하나 이상 포함할 수 있다.The output signal processing circuit 560 may be a component for transmitting an electrical signal processed by the microprocessor 520 to the outside. For example, the output signal processing circuit 560 may be a graphics card, an image processor, an optical transducer, a beam panel card, or various functional interface circuits. The output signal processing circuit 560 may include at least one DRAM memory semiconductor package 1100, a bottom package 1200, or a top package 1200, 1300 according to the present invention.
통신 회로(570)는 다른 전자 시스템 또는 다른 회로 기판과 전기적 신호를 상기 입력 신호 처리 회로(550) 또는 출력 신호 처리 회로(560)를 통하지 않고 직접적으로 주고받기 위한 구성 요소이다. 예를 들어, 통신 회로(570)는 개인 컴퓨터 시스템의 모뎀, 랜카드, 또는 다양한 인터페이스 회로 등일 수 있다. 통신 회로(570)는 본 발명에 의한 DRAM 메모리 반도체 패키지(1100), 또는 바텀 패키지(1200)나 탑 패키지(1200, 1300)를 적어도 하나 이상 포함할 수 있다.The communication circuit 570 is a component for directly exchanging an electrical signal with another electronic system or another circuit board without passing through the input signal processing circuit 550 or the output signal processing circuit 560. For example, the communication circuit 570 may be a modem, a LAN card, various interface circuits, or the like of a personal computer system. The communication circuit 570 may include at least one DRAM memory semiconductor package 1100, a bottom package 1200, or a top package 1200 and 1300 according to the present invention.
이상에서 살펴본 바와 같이, 종래는 반도체 다이를 개별적으로 패키징 하고 테스트가 완료된 반도체 다이가 상하로 적층되는 POP(package on package) 패키지를 통하여 고용량 메모리를 구현하고 있으나, 적층 다이 수가 증가함에 따라 수율이 이와 비례하여 증가하기 때문에, 본 발명의 BGA 반도체 패키지는 4단 혹은 8단 칩 스택으로 분할 패키징 하고, 각 칩 스택은 기판 측면의 사이드 패드를 이용하여 와이어 본딩하는 방법으로 이를 다시 통합하여 16단 고용량 메모리를 실현하는 구성을 기술적 사상으로 하고 있음을 알 수 있다. 이와 같은 본 발명의 기본적인 기술적 사상의 범주 내에서, 당업계의 통상의 지식을 가진 자에게 있어서는 다른 많은 변형이 가능할 것이다.As described above, in the related art, a high capacity memory is realized through a package on package (POP) package in which semiconductor dies are individually packaged and tested semiconductor dies are stacked up and down, but as the number of stacked dies increases, the yield is increased. As it increases in proportion, the BGA semiconductor package of the present invention is dividedly packaged into four- or eight-stage chip stacks, and each chip stack is re-integrated by wire bonding using side pads on the side of the substrate. It can be seen that the configuration to realize the technical idea. Within the scope of the basic technical idea of the present invention, many other modifications will be possible to those skilled in the art.
본 발명의 메모리 패키지는 고용량이 요구되는 SSD 제품 및 웨어러블 디바이스에 적용되는 플랙서블 메모리 패키지에 활용될 가능성이 높다. 혹은 고용량이 요구되는 웨어러블 디바이스에 적용되는 플랙서블 메모리 패키지에 활용될 가능성이 높다.The memory package of the present invention is likely to be utilized in flexible memory packages applied to SSD products and wearable devices requiring high capacity. Or, it is likely to be used in flexible memory packages applied to wearable devices that require high capacity.

Claims (17)

  1. 통합 기판;Integrated substrates;
    상기 통합 기판 상에 탑재되고, 복수 메모리 반도체 다이가 칩 온 칩 타입으로 적층되어, 전체 메모리 용량 중 일부를 담당하는 하나의 바텀 칩 스택;A bottom chip stack mounted on the integrated substrate, wherein a plurality of memory semiconductor dies are stacked in a chip on chip type to cover a part of the total memory capacity;
    상기 바텀 패키지 상에 탑재되고, 복수 메모리 반도체 다이가 적층되어, 전체 메모리 용량 중 나머지를 담당하는 적어도 하나 이상의 탑 칩 스택;At least one top chip stack mounted on the bottom package and having a plurality of memory semiconductor dies stacked on the bottom package to cover the rest of the total memory capacity;
    상기 바텀 칩 스택과 상기 탑 칩 스택을 전기적으로 연결하는 통합 와이어; 및 An integrated wire electrically connecting the bottom chip stack and the top chip stack; And
    상기 통합 와이어를 밀봉하는 통합 보호부재를 포함하여 구성되는 것을 특징으로 하는 반도체 패키지.And an integrated protective member for sealing the integrated wire.
  2. 제 1 항에 있어서,The method of claim 1,
    상기 바텀 칩 스택은,The bottom chip stack,
    바텀 기판;A bottom substrate;
    멀티 칩 패키지 타입의 상기 메모리 반도체 다이;The memory semiconductor die of a multi-chip package type;
    상기 메모리 반도체 다이를 전기적으로 연결하는 연결부재; 및 A connection member electrically connecting the memory semiconductor die; And
    상기 반도체 다이와 상기 연결부재 그리고 상기 바텀 기판의 일부를 커버하는 바텀 보호부재를 포함하여 구성되는 것을 특징으로 하는 반도체 패키지.And a bottom protection member covering the semiconductor die, the connection member, and a portion of the bottom substrate.
  3. 제 2 항에 있어서,The method of claim 2,
    상기 바텀 기판은,The bottom substrate,
    절연 PCB 바디; Insulated PCB body;
    상기 PCB 바디 상면에 기판 패드와 사이드 패드를 포함하는 상부 배선 패턴; An upper wiring pattern including a substrate pad and a side pad on an upper surface of the PCB body;
    상기 PCB 바디 저면에 외부 접속 단자를 포함하는 하부 배선 패턴; 및A lower wiring pattern including an external connection terminal on a bottom surface of the PCB body; And
    상기 PCB 바디 내부에 상기 기판 패드와 상기 외부 접속 단자를 연결하거나 혹은 상기 기판 패드와 상기 사이드 패드를 전기적으로 연결하는 관통 전극 혹은 재배선 패턴을 포함하여 구성되는 것을 특징으로 하는 반도체 패키지.And a through electrode or a redistribution pattern connecting the substrate pad and the external connection terminal to the inside of the PCB body or electrically connecting the substrate pad and the side pad.
  4. 제 3 항에 있어서,The method of claim 3, wherein
    상기 기판 패드는 상기 바텀 보호부재에 의하여 커버되고, The substrate pad is covered by the bottom protection member,
    상기 사이드 패드는 상기 통합 보호부재에 의하여 커버되는 것을 특징으로 하는 반도체 패키지.And the side pads are covered by the integrated protection member.
  5. 제 4 항에 있어서,The method of claim 4, wherein
    상기 탑 칩 스택은, 3개 패키지를 포함함으로써, 16단 스택을 4개의 4단 칩 스택으로 분할하는 것을 특징으로 하는 반도체 패키지.The top chip stack includes three packages, thereby splitting the 16-layer stack into four 4-chip stacks.
  6. 상면에 기판 패드와 사이드 패드가 인쇄되는 기판;A substrate on which a substrate pad and a side pad are printed on an upper surface thereof;
    멀티 칩 패키지 타입의 복수 메모리 반도체 다이;A plurality of memory semiconductor dies of a multi-chip package type;
    상기 메모리 반도체 다이를 전기적으로 연결하는 연결부재; 및 A connection member electrically connecting the memory semiconductor die; And
    상기 반도체 다이와 상기 연결부재 전부 그리고 상기 기판의 일부를 커버하는 바텀 보호부재를 포함하는 것을 특징으로 하는 칩 스택.And a bottom protection member covering all of the semiconductor die, the connection member, and a portion of the substrate.
  7. 제 6 항에 있어서,The method of claim 6,
    상기 연결부재는 도전 와이어 혹은 관통 전극을 포함하는 것을 특징으로 하는 칩 스택.And the connection member comprises a conductive wire or a through electrode.
  8. 제 6 항에 있어서,The method of claim 6,
    상기 기판 패드는 상기 바텀 보호부재에 의하여 커버되고, The substrate pad is covered by the bottom protection member,
    상기 사이드 패드는 노출되는 것을 특징으로 하는 칩 스택.And the side pads are exposed.
  9. 절연 PCB 바디; Insulated PCB body;
    상기 PCB 바디 상면 내측에 기판 패드가 인쇄되고, 상면 에지에 사이드 패드가 인쇄되는 상부 배선 패턴; 및An upper wiring pattern on which a substrate pad is printed inside the upper surface of the PCB body and a side pad is printed on an upper edge thereof; And
    상기 PCB 바디 내부에 상기 기판 패드와 상기 사이드 패드를 전기적으로 연결하는 재배선 패턴을 포함하여 구성됨을 특징으로 하는 패키지 기판.And a redistribution pattern electrically connecting the substrate pad and the side pad to the inside of the PCB body.
  10. 제 9 항에 있어서,The method of claim 9,
    상기 PCB 바디 저면에 외부 접속 단자를 포함하는 하부 배선 패턴; 및 A lower wiring pattern including an external connection terminal on a bottom surface of the PCB body; And
    상기 PCB 바디 내부에 상기 기판 패드와 상기 외부 접속 단자를 연결하는 관통 전극을 더 포함하여 구성됨을 특징으로 하는 패키지 기판.And a through electrode configured to connect the substrate pad and the external connection terminal to the inside of the PCB body.
  11. 통합 기판;Integrated substrates;
    상기 통합 기판 상에 부착되는 바텀 패키지;A bottom package attached on the integrated substrate;
    상기 바텀 패키지 상에 접합부재를 통해 적층되는 탑 패키지; A top package stacked on the bottom package through a bonding member;
    상기 바텀 패키지 및 상기 탑 패키지를 전기적으로 연결하는 통합 와이어; 및 An integrated wire electrically connecting the bottom package and the top package; And
    상기 통합 와이어를 밀봉하는 통합 보호부재를 포함하는 것을 특징으로 하는 반도체 스택 패키지.And an integrated protective member for sealing the integrated wire.
  12. 제 11 항에 있어서,The method of claim 11,
    상기 바텀 패키지는, The bottom package,
    중심에 창을 가지는 바텀 기판;A bottom substrate having a window in the center;
    상기 바텀 기판 상에 활성면이 마주하도록 접합되고, 제1본딩 패드가 상기 창을 통해 하부로 노출되는 제1칩;A first chip bonded to the bottom substrate so that an active surface faces the first substrate, and a first bonding pad is exposed downward through the window;
    비활성면이 상기 제1칩의 비활성면에 접합되고, 활성면의 일측에 제2본딩 패드가 형성되는 제2칩; A second chip having an inactive surface bonded to the inactive surface of the first chip and having a second bonding pad formed on one side of the active surface;
    상기 창을 통해 상기 제1본딩 패드가 상기 바텀 기판의 저면과 와이어 본딩되는 제1본딩 와이어; A first bonding wire through which the first bonding pad is wire bonded to a bottom surface of the bottom substrate;
    상기 제1본딩 와이어를 커버하는 제1보호부재;A first protective member covering the first bonding wire;
    상기 제2본딩 패드가 상기 바텀 기판의 상면과 와이어 본딩되는 제2본딩 와이어; 및A second bonding wire in which the second bonding pad is wire bonded to an upper surface of the bottom substrate; And
    상기 제2본딩 와이어를 커버하는 제2보호부재를 포함하는 것을 특징으로 하는 반도체 스택 패키지.And a second protective member covering the second bonding wire.
  13. 제 12 항에 있어서,The method of claim 12,
    상기 바텀 기판은 상기 제2보호부재에 의하여 커버되지 않는 에지 영역에 사이드 패드를 더 포함하고, 상기 사이드 패드는 상기 통합 와이어와 연결되는 것을 특징으로 하는 반도체 스택 패키지.And the bottom substrate further includes side pads in an edge area not covered by the second protection member, and the side pads are connected to the integration wire.
  14. 통합 기판;Integrated substrates;
    상기 통합 기판 상에 적층되는 바텀 패키지;A bottom package stacked on the integrated substrate;
    상기 바텀 패키지 상에 접합부재를 통해 적층되는 탑 패키지;A top package stacked on the bottom package through a bonding member;
    상기 바텀 패키지 및 상기 탑 패키지를 전기적으로 연결하되, 상기 바텀 패키지의 기판과 상기 탑 패키지의 기판을 전기적으로 연결하는 통합 와이어; An integrated wire electrically connecting the bottom package and the top package to electrically connect the substrate of the bottom package and the substrate of the top package;
    상기 통합 와이어를 밀봉하는 통합 보호부재를 포함하는 것을 특징으로 하는 반도체 스택 패키지.And an integrated protective member for sealing the integrated wire.
  15. 제 14 항에 있어서,The method of claim 14,
    상기 탑 패키지는, The top package,
    탑 기판, Tower substrate,
    상기 탑 기판 상에 적층되는 다수 칩;A plurality of chips stacked on the top substrate;
    상기 칩 내부의 집적 회로를 전기적으로 연결하는 칩 패드;A chip pad electrically connecting the integrated circuit inside the chip;
    상기 칩 패드를 전기적으로 연결하는 관통 전극;A through electrode electrically connecting the chip pads;
    상기 칩을 고정하는 접착부재;An adhesive member for fixing the chip;
    상기 칩을 커버하는 보호부재를 포함하는 것을 특징으로 하는 반도체 스택 패키지.And a protective member covering the chip.
  16. 제 15 항에 있어서,The method of claim 15,
    상기 탑 기판은, The top substrate,
    베어 기판;Bare substrates;
    상기 베어 기판의 상면에 노출되는 접속 패드;A connection pad exposed on an upper surface of the bare substrate;
    상기 베어 기판의 내부에서 상기 접속 패드를 전기적으로 연결하는 재배선 패턴;A redistribution pattern electrically connecting the connection pads in the bare substrate;
    상기 재배선 패턴을 통하여 상기 접속 패드와 연결되는 사이드 패드;A side pad connected to the connection pad through the redistribution pattern;
    상기 접속 패드를 노출시키고 상기 재배선 패턴을 보호하기 위하여 상기 베어 기판에 도포되는 페시베이션을 포함하며,Passivation is applied to the bare substrate to expose the connection pad and protect the redistribution pattern,
    상기 사이드 패드는 상기 베어 기판의 에지에서 상기 보호부재에 의하여 커버되지 않고, 상기 통합 와이어와 전기적으로 연결되는 것을 특징으로 하는 반도체 스택 패키지.And the side pads are not covered by the protection member at edges of the bare substrate, and are electrically connected to the integrated wires.
  17. 모듈 기판;A module substrate;
    상기 모듈 기판 상에 실장되는 다수의 DRAM 메모리 패키지;A plurality of DRAM memory packages mounted on the module substrate;
    상기 모듈 기판의 일측에 일정한 간격으로 배열되고 상기 DRAM 메모리 패키지를 전기적으로 연결하는 다수의 접촉 단자를 포함하고,A plurality of contact terminals arranged at one side of the module substrate at regular intervals and electrically connecting the DRAM memory package,
    상기 DRAM 메모리 패키지는, The DRAM memory package,
    통합 기판;Integrated substrates;
    상기 통합 기판 상에 적층되되, 바텀 기판의 에지가 바텀 보호부재에 의하여 커버되지 않고 노출되는 바텀 패키지;A bottom package stacked on the integrated substrate, wherein an bottom edge of the bottom substrate is exposed without being covered by a bottom protection member;
    상기 바텀 패키지 상에 접합부재를 통해 적층되되, 탑 기판의 에지가 탑 보호부재에 의하여 커버되지 않고 노출되는 탑 패키지;A top package stacked on the bottom package through a bonding member, the top package having an edge of the top substrate not exposed by the top protection member;
    상기 바텀 패키지 및 상기 탑 패키지를 전기적으로 연결하되, 노출된 상기 바텀 기판의 에지와 상기 탑 기판의 에지를 전기적으로 연결하는 통합 와이어; An integrated wire electrically connecting the bottom package and the top package to electrically connect an edge of the exposed bottom substrate to an edge of the top substrate;
    상기 통합 와이어를 밀봉하는 통합 보호부재를 포함하는 것을 특징으로 하는 메모리 모듈.And an integrated protective member for sealing the integrated wire.
PCT/KR2016/008434 2015-07-31 2016-08-01 Package substrate comprising side pads on edge, chip stack, semiconductor package, and memory module comprising same WO2017023060A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US15/746,100 US10522522B2 (en) 2015-07-31 2016-08-01 Package substrate comprising side pads on edge, chip stack, semiconductor package, and memory module comprising same
CN201680042425.6A CN108140636B (en) 2015-07-31 2016-08-01 Semiconductor package, semiconductor stack package, and memory module

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