WO2014109830A1

WO2014109830A1 - Metal oxynitride based heterojunction field effect transistor

Info

Publication number: WO2014109830A1
Application number: PCT/US2013/070491
Authority: WO
Inventors: Yan Ye
Original assignee: Applied Materials Inc
Current assignee: Applied Materials Inc
Priority date: 2013-01-08
Filing date: 2013-11-18
Publication date: 2014-07-17
Anticipated expiration: 2015-07-08
Also published as: TW201431069A

Abstract

Embodiments of the present invention generally relate to an HFET having one or more metal oxynitride or metal oxide channel semiconductor layers with source and drain electrodes, and a gate which contacts the semiconductor layer though a junction or junctions formed between the gate and channel semiconductor. The junction can be formed by inserting a different type of semiconductor material, for example, an amorphous silicon semiconductor material, a different metal oxynitride, a p-type metal oxide semiconductor or a low work function metal oxide conductor, between the gate and channel material. The junction can be also formed by using a metal which forms a Schottky barrier as in a Schottky diode between the metal and semiconductor.

Description

METAL OXYNITRIDE BASED HETEROJUNCTION FIELD EFFECT

TRANSISTOR

BACKGROUND OF THE INVENTION

Field of the Invention

[0001] Embodiments of the present invention generally relate to a heterojunction field effect transistor (HFET) having one or more metal oxynitride channel semiconductor layers with source and drain electrodes, and a gate which contacts the semiconductor layer though a junction or junctions formed between the gate and channel semiconductor.

Description of the Related Art

[0002] Current interest in TFTs is particularly high because these devices may be used in liquid crystal active matrix displays (LCDs) of the kind often employed for computer and television flat panels. The LCDs may also contain light emitting diodes (LEDs), such as organic light emitting diodes (OLEDs) for back lighting. The LEDs and OLEDs require TFTs for addressing the activity of the displays.

[0003] The current driven through the TFTs (i.e., the on-current) is limited by the channel material (often referred to as the active material, semiconductor material or semiconductor active material) as well as the channel width and length. Additionally, the turn-on voltage is determined by the accumulation of the carrier in the channel area of the semiconductor layer which could change as the shift of the fixed charge in the semiconductor or dielectric material or the charge trapping in interfaces and the threshold voltage shifts after bias temperature stress or current temperature stress.

[0004] Silicon, as the semiconductor material, has its limitations. Amorphous silicon has a low mobility. Polycrystalline silicon, while having a higher mobility than amorphous silicon, but is expensive to produce and necessitates an annealing process. [0005] Therefore, there is a need in the art for a TFT formed of a semiconductor material that has high mobility, yet can be produced at a low cost.

SUMMARY OF THE INVENTION

[0006] Embodiments of the present invention generally relate to an HFET having one or more metal oxynitride or metal oxide channel semiconductor layers with source and drain electrodes, and a gate which contacts the semiconductor layer though a junction or junctions formed between the gate and channel semiconductor. The junction can be formed by inserting a different type of semiconductor material, for example, an amorphous silicon semiconductor material, a different metal oxynitride, a p-type metal oxide semiconductor or a low work function metal oxide conductor, between the gate and channel material. The junction can be also formed by using a metal which forms a Schottky barrier as in a Schottky diode between the metal and semiconductor.

[0007] In one embodiment, a HFET comprises a first semiconductor layer; a source electrode disposed on at least a portion of the first semiconductor layer; a drain electrode disposed on at least a portion of the first semiconductor layer; a gate dielectric layer disposed over at least a portion of the source electrode, the drain electrode and the first semiconductor layer, the gate dielectric layer having a junction therethrough to expose at least a portion of the first semiconductor layer; a second semiconductor layer formed over the gate dielectric layer and within the junction; and a gate electrode disposed over the second semiconductor layer and within the junction. The second semiconductor has a lower Fermi level than the first semiconductor, or the gate electrode metal has a work function that is lower than the Fermi level of the semiconductor interfaced to form a Schottky barrier between the metal and semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

[0009] Figure 1 is a cross-sectional schematic view of a PVD chamber according to one embodiment of the invention.

[0010] Figures 2A-2C are schematic cross-sectional views of HFETs according to various embodiments.

[0011] Figure 3 is a schematic cross-sectional illustration of an HFET according to another embodiment.

[0012] Figure 4 is a schematic cross-sectional illustration of an HFET according to another embodiment.

[0013] Figure 5 is a schematic cross-sectional illustration of an HFET according to another embodiment.

[0014] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.

DETAILED DESCRIPTION

[0015] Embodiments of the present invention generally relate to a metal oxynitride HFET having one or more channel semiconductor layers with source and drain electrodes, and a gate which contacts the semiconductor layers though a junction or junctions formed between the gate and channel semiconductor. The junction can be formed by inserting a different type of semiconductor material, for example, an amorphous silicon semiconductor material, a different metal oxynitride, a p-type metal oxide semiconductor or a low work function metal oxide conductor, between the gate and channel material. The junction can be also formed by using a metal which forms a Schottky barrier as in a Schottky diode between the metal and semiconductor.

[0016] The invention is illustratively described and may be used in a PVD chamber for processing large area substrates, such as a 4300 PVD chamber, available from AKT^®, a subsidiary of Applied Materials, Inc., Santa Clara, California. However, it should be understood that the sputtering target may have utility in other system configurations, including those systems configured to process large area round substrates and those systems produced by other manufacturers.

[0017] Figure 1 is a cross-sectional schematic view of a PVD chamber 100 according to one embodiment of the invention. The chamber 100 may be evacuated by a vacuum pump 1 14. Within the chamber 100, a substrate 102 may be disposed opposite a target 104. The substrate may be disposed on a susceptor 106 within the chamber 100. The susceptor 106 may be elevated and lowered as shown by arrows "A" by an actuator 1 12. The susceptor 106 may be elevated to raise the substrate 102 to a processing position and lowered so that the substrate 102 may be removed from the chamber 100. Lift pins 108 elevate the substrate 102 above the susceptor 106 when the susceptor 106 is in the lowered position. Grounding straps 1 10 may ground the susceptor 106 during processing. The susceptor 106 may be raised during processing to aid in uniform deposition.

[0018] The target 104 may comprise one or more targets 104. The target 104 may be bonded to a backing plate 1 16 by a bonding layer. To control the temperature of the target 104, cooling channels may be present in the backing plate 1 16. One or more magnetrons 1 18 may be disposed behind the backing plate 1 16. The magnetrons 1 18 may scan across the backing plate 1 16 in a linear movement or in a two dimensional path. The walls of the chamber may be shielded from deposition by a dark space shield 120 and a chamber shield 122.

[0019] To help provide uniform sputtering deposition across a substrate 102, an anode 124 may be placed between the target 104 and the substrate 102. In one embodiment, the anode 124 may be bead blasted stainless steel coated with arc sprayed aluminum. In one embodiment, one end of the anode 124 may be mounted to the chamber wall by a bracket 130. The anode 124 provides a charge in opposition to the target 104 so that charged ions will be attracted thereto rather than to the chamber walls which are typically at ground potential. By providing the anode 124 between the target 104 and the substrate 102, the plasma may be more uniform, which may aid in the deposition.

[0020] For reactive sputtering, it may be beneficial to provide a reactive gas into the chamber 100. One or more gas introduction tubes 126 may also span the distance across the chamber 100 between the target 104 and the substrate 102. The gas introduction tubes 126 may introduce sputtering gases such as inert gases including argon as well as reactive gases such as oxygen, nitrogen, etc. The gases may be provided to the gas introduction tubes 126 from a gas panel 132 that may introduce one or more gases such as argon, oxygen, and nitrogen. The gas introduction tubes 126 may be disposed between the substrate 102 and the target 104 at a location below the one or more anodes 124. The anodes 124 may shield the gas introduction tubes 126 from deposition during processing. Shielding the gas introduction tubes 126 with the anodes 124 may reduce the amount of deposition that may cover or clog the gas outlets. The gas introduction tubes 126 may be coupled with the anodes 124 by one or more couplers 128. [0021] As discussed herein, a TFT, or more specifically, an HFET, is formed utilizing a combination of one or more metal oxynitride layers or a metal oxynitride layer with another semiconductor material as the active channel material. Two dimensional electron gas can be formed in the transistor through confinement at the interface between two layers, instead of from external electric fields provided to the transistor. The transistor has the gate in direct contact, or through a thin dielectric layer or other semiconductor layer, with the active channel material. The source and drain electrodes are separated by an area covered by the gate electrode which could be either directly in contact with the channel or through other layers of semiconductor material or dielectric layers. The area covered by the gate and source-drain electrodes could also be treated differently through annealing or conversion.

[0022] Figures 2A-2C are schematic cross-sectional views of HFETs according to various embodiments. In the embodiments shown in Figures 2A- 2C, the HFET includes a substrate 202. Suitable materials that may be utilized for the substrate 202 include, but not limited to, silicon, germanium, silicon-germanium, soda lime glass, glass, semiconductor, plastic, steel or stainless steel substrates.

[0023] Over the substrate 202, a dielectric layer 204 may be present. Suitable materials that may be used for the dielectric layer 204 include silicon dioxide, silicon oxynitride, silicon nitride, aluminum oxide or combinations thereof. The gate dielectric layer 204 may be deposited by suitable deposition techniques including plasma enhanced chemical vapor deposition (PECVD).

[0024] Multiple semiconductor layers 206A-206C are then formed over the dielectric layer 204. In practice, the semiconductor layers 206A-206C are oftentimes referred to as the channel layer, the active layer or the semiconductor active layer.

[0025] Thereover, the source electrode 208 and the drain electrode 210 are formed. The exposed portion of the semiconductor layers 206A-206C between the source and drain electrodes 208, 210 is referred to as the active channel. Suitable materials for the source and drain electrodes 208, 210 include chromium, copper, aluminum, tantalum, titanium, molybdenum, and combinations thereof, or TCOs mentioned above. The source and drain electrodes 208, 210 may be formed by suitable deposition techniques, such as PVD followed by patterning through etching.

[0026] Over the exposed active channel and the source and drain electrodes 208, 210, a gate dielectric layer 212 may be deposited. Suitable materials that may be used for the gate dielectric layer 212 include silicon dioxide, silicon oxynitride, silicon nitride, aluminum oxide or combinations thereof. The gate dielectric layer 212 may be deposited by suitable deposition techniques including plasma enhanced chemical vapor deposition (PECVD). The gate dielectric layer 212 may then be etched to form a junction 216 and expose the uppermost semiconductor layer 206C of the active channel.

[0027] A gate electrode 214 may then be formed with at least a portion of the gate electrode 214 filling the junction 216. Suitable materials that may be utilized for the gate electrode 214 include, but are not limited to, chromium, copper, aluminum, tantalum, titanium, molybdenum, and combinations thereof, or transparent conductive oxides (TCO) such as indium tin oxide (ITO) or fluorine doped zinc oxide (ZnO:F) which are commonly used as transparent electrodes. The gate electrode 214 may be deposited by suitable deposition techniques such as PVD, MOCVD, a spin-on process and printing processes.

[0028] As shown in Figure 2A, the HFET 200 can have the junction 216 formed equidistant from both the source and drain electrodes 208, 210 as shown by arrows "A" and "B". As shown in Figure 2B, the HFET 220 can have the junction 216 formed to be closer to either the source or drain electrodes 208, 210. Arrows "C" and "D" show that the junction 216 is a greater distance from one of the electrodes 208, 210. As shown in Figure 2C, not only may the junction 216 be formed to be closer to either the source or drain electrodes 208, 210 as shown by arrows "E" and "F", but the gate electrode 214 may be positioned to be over only one of the electrodes 208, 210.

[0029] The semiconductor layers 206A-206C may comprise oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, gallium, cadmium, indium, tin, and combinations thereof. In one embodiment, the semiconductor layers 206A-206C may comprise oxygen, nitrogen, and one or more elements having a filled s orbital and a filled d orbital. In another embodiment, the semiconductor layers 206A-206C may comprise oxygen, nitrogen, and one or more elements having a filled f orbital. In another embodiment, the semiconductor layers 206A-206C may comprise oxygen, nitrogen, and one or more divalent elements. In another embodiment, the semiconductor layers 206A-206C may comprise oxygen, nitrogen, and one or more trivalent elements. In another embodiment, the semiconductor layers 206A-206C may comprise oxygen, nitrogen, and one or more tetravalent elements.

[0030] The semiconductor layers 206A-206C may also comprise a dopant. Suitable dopants that may be used include Al, Sn, Ga, Ca, Si, Ti, Cu, Ge, In, Ni, Mn, Cr, V, Mg, Si_xN_y, Al_xO_y, and SiC. The dopant can be also a non-metal such as H, C, S, F, and so on. In one embodiment, the dopant comprises aluminum. In another embodiment, the dopant comprises tin.

[0031] Examples of semiconductor layers 206A-206C include the following: ZnO_xN_y, SnO_xN_y, lnO_xN_y, CdO_xN_y, GaO_xN_y, ZnSnO_xN_y, ZnlnO_xN_y, ZnCdO_xN_y, ZnGaO_xN_y, SnlnO_xN_y, SnCdO_xN_y, SnGaO_xN_y, lnCdO_xN_y, lnGaO_xN_y, CdGaO_xN_y, ZnSnlnO_xN_y, ZnSnCdO_xN_y, ZnSnGaO_xN_y, ZnlnCdO_xN_y, ZnlnGaO_xN_y, ZnCdGaO_xN_y, SnlnCdO_xN_y, SnlnGaO_xN_y, SnCdGaO_xN_y, lnCdGaO_xN_y, ZnSnlnCdO_xN_y, ZnSnlnGaO_xN_y, ZnlnCdGaO_xN_y, and SnlnCdGaOxN_y. Examples of semiconductor layer 206A-206C include the following doped materials: ZnO_xN_y:AI, ZnO_xN_y:Sn, SnO_xN_y:AI, lnO_xN_y:AI, lnO_xN_y:Sn, CdO_xN_y:AI, CdO_xN_y:Sn, GaO_xN_y:AI, GaO_xN_y:Sn, ZnSnO_xN_y:AI, ZnlnO_xN_y:AI, ZnlnO_xN_y:Sn, ZnCdO_xN_y:AI, ZnCdO_xN_y:Sn, ZnGaO_xN_y:AI, ZnGaO_xN_y:Sn, SnlnO_xN_y:AI, SnCdO_xN_y:AI, SnGaO_xN_y:AI, lnCdO_xN_y:AI, lnCdO_xN_y:Sn, lnGaO_xN_y:AI, lnGaO_xN_y:Sn, CdGaO_xN_y:AI, CdGaO_xN_y:Sn, ZnSnlnO_xN_y:AI, ZnSnCdO_xN_y:AI, ZnSnGaO_xN_y:AI, ZnlnCdO_xN_y:AI, ZnlnCdO_xN_y:Sn, ZnlnGaO_xN_y:AI, ZnlnGaO_xN_y:Sn, ZnCdGaO_xN_y:AI, ZnCdGaO_xN_y:Sn, SnlnCdO_xN_y:AI, SnlnGaO_xN_y:AI, SnCdGaO_xN_y:AI, lnCdGaO_xN_y:AI, lnCdGaO_xN_y:Sn, ZnSnlnCdO_xN_y:AI, ZnSnlnGaO_xN_y:AI, ZnlnCdGaO_xN_y:AI, ZnlnCdGaO_xN_y:Sn, and SnlnCdGaO_xN_y:AI.

[0032] The semiconductor layers 206A-206C may be deposited by sputtering. In one embodiment, the sputtering target comprises the metal such as zinc, gallium, tin, cadmium, indium, or combinations thereof. The sputtering target may additionally comprise a dopant. Oxygen containing gas and nitrogen containing gas are introduced into the chamber to deposit the semiconductor layers 206A-206C by reactive sputtering. In one embodiment, the nitrogen containing gas comprises N₂. In another embodiment, the nitrogen containing gas comprises N₂O, NH₃, or combinations thereof. In one embodiment, the oxygen containing gas comprises O₂. In another embodiment, the oxygen containing gas comprises N₂O. The nitrogen of the nitrogen containing gas and the oxygen of the oxygen containing gas react with the metal from the sputtering target to form a semiconductor material comprising metal, oxygen, nitrogen, and optionally a dopant on the substrate. In one embodiment, the nitrogen containing gas and the oxygen containing gas are separate gases. In another embodiment, the nitrogen containing gas and the oxygen containing gas comprise the same gas. Additional additives such as B₂H₆, CO2, CO, CH₄, and combinations thereof may also be provided to the chamber during the sputtering.

[0033] Additionally, the semiconductor layers 206A-206C may comprise multi-component metal oxides (i.e., multi-cation metal oxides such as an IGZO) single cation metal oxides such (i.e., zinc oxide), or multi-anion compounds that contain at least two anions and single cation system. The cations may be N, O, S, P, C, F, I, As, Se, and so on. Additionally, the semiconductor layers 206A-206C may be selected from other semiconductor material such as metal oxides or metal nitrides.

[0034] Each semiconductor layer 206A-206C may be different. Alternatively, the first semiconductor layer 206A and the third semiconductor layer 206C may be substantially identical while the second semiconductor layer 206B is different therefrom. The layers may be different in composition for example. Having different semiconductor layers 206A-206C leads to higher mobility. Higher mobility can be achieved with grapheme and other layered semiconductor material. However, by using quantum confinement through a combination of oxynitride semiconductors and metal oxide semiconductors with different bandgap, carrier concentration or Fermi level, mobility of greater than 100 can be achieved.

[0035] When electrons are confined in a steep canyon called a quantum well, the electrons can move quickly without colliding with other impurities. Quantum wells are known using an AIGaAs/GaAs structure. Creating a heterojunction of two different metal oxynitrides or metal nitrides or metal oxides or a metal oxynitride and other semiconductor material can produce a quantum well. Through the quantum well formation, high mobility can be achieved that will lead to achievement of high mobility TFTs and other thin film electronics. The film from the metal oxynitride can have one quantum well or more to form a superlattice.

[0036] Each semiconductor layer 206A-206C will have various properties that contribute to the interaction with the respective other layers. Each semiconductor layer 206A-206C will have an energy level of vacuum (Ev), an energy level at the conduction band bottom (ECB), a charge neutrality level (ECNL), a Fermi level (EF), and an energy level at the valance band top (EVB). By controlling the Fermi level and the charge neutrality level, quantum wells can be formed and mobility can be improved.

[0037] By manipulating the Fermi level, the location of the quantum well can be preselected. If desired, the quantum well can be formed to confine the electrons at the interface of the layers. Alternatively, the quantum well can be formed to trap the electrons in the second semiconductor layer 206B. The electronic confinement is achieved through abrupt composition changes of different films that are in contact. The confinement is created by barriers formed when the charge transfer takes place across the interfaces due to Fermi level differences and charge neutrality level differences. The gate in the Figure 2 is a metal with a work function with the Fermi-level of the semiconductor interfaced.

[0038] Figure 3 is a schematic cross-sectional illustration of an HFET 300 according to another embodiment. It is to be understood that while the HFET 300 shown in Figure 3 is an HFET having a junction 216 with that is equally spaced between the source 208 and drain 210 electrode, other HFET layouts are applicable. For example, HFETs having multiple junctions are contemplated as are HFETs having a junction that is closer to one of the source 208 or drain 210 electrodes. Furthermore, HFETs, such as shown in Figure 2C are contemplated.

[0039] In the embodiment shown in Figure 3, a plurality of semiconductor layers 302, 304 are deposited over the gate dielectric layer 212 and within the junction 216. A gate electrode 306 is deposited over the semiconductor layer 304. Suitable materials that may be utilized for the gate electrode 306 include, but are not limited to, chromium, copper, aluminum, tantalum, titanium, molybdenum, and combinations thereof, or transparent conductive oxides (TCO) such as indium tin oxide (ITO) or fluorine doped zinc oxide (ZnO:F) which are commonly used as transparent electrodes. [0040] In the embodiment shown in Figure 3, two semiconductor layers 302, 304 are shown. The two semiconductor layers 302, 304 comprise different compositions and/or properties. In one embodiment, the semiconductor layers 302, 304 may both comprise amorphous silicon wherein the first semiconductor layer 302 comprises intrinsic amorphous silicon and the second semiconductor layer 304 comprises p-type amorphous silicon. The first semiconductor layer 302 is in contact with the third semiconductor layer 206C of the active channel. The first and second semiconductor layers 302, 304, while being different from each other, may also be different from the semiconductor layers of the active channel 206A-206C. Specifically, it is contemplated that semiconductor layer 302 and semiconductor layer 206C have different composition or properties such that the Fermi level of the different semiconductor layers can cause electrons to be pushed from one semiconductor layer to another semiconductor layer or, if desired, trapped within a specific semiconductor layer. Additionally, semiconductor layers 302, 304 may also have different Fermi or charge neutrality levels.

[0041] Figure 4 is a schematic cross-sectional illustration of an HFET 400 according to another embodiment. It is to be understood that while the HFET 400 shown in Figure 4 is an HFET having a junction 216 with that is equally spaced between the source 208 and drain 210 electrode, other HFET layouts are applicable. For example, HFETs having multiple junctions are contemplated as are HFETs having a junction that is closer to one of the source 208 or drain 210 electrodes. Furthermore, HFETs, such as shown in Figure 2C are contemplated.

[0042] In the embodiment shown in Figure 4, a single semiconductor layer 402 is formed within the junction 216 with the gate electrode 306 formed thereover. The semiconductor layer 402 may comprise a metal oxide or a metal oxynitride that is different than the semiconductor material used for the third semiconductor layer 206C. The semiconductor layer 402 may be different from the third semiconductor layer 206C in composition, Fermi level, charge neutrality level, etc. Suitable examples for the semiconductor layer 402 include an oxygen rich zinc oxynitride, an oxygen rich zinc oxide, tin oxynitride, indium oxynitride, tin dioxide, or combinations thereof.

[0043] Figure 5 is a schematic cross-sectional illustration of an HFET 500 according to another embodiment. It is to be understood that while the HFET 500 shown in Figure 5 is an HFET having a junction 216 with that is equally spaced between the source 208 and drain 210 electrode, other HFET layouts are applicable. For example, HFETs having multiple junctions are contemplated as are HFETs having a junction that is closer to one of the source 208 or drain 210 electrodes. Furthermore, HFETs, such as shown in Figure 2C are contemplated.

[0044] In the embodiment shown in Figure 5, a single semiconductor layer 502 is formed within the junction 216 with the gate electrode 306 formed thereover. The semiconductor layer 502 may comprise a material that is different from the third semiconductor layer 206C. The semiconductor layer 502 may be different from the third semiconductor layer 206C in composition, Fermi level, charge neutrality level, etc. The semiconductor layer 502 may comprise a p-type metal oxide or oxynitride or a low work function metal oxide conductor. Tin monoxide is an example of the semiconductor layer 502.

[0045] By having the gate in direct contact, or through a thin dielectric layer or other semiconductor layer, with the active channel material, the mobility of structure may be improved.

[0046] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

Claims:

1 . A heterojunction field effect transistor, comprising:

a first semiconductor layer;

a source electrode disposed on at least a portion of the first semiconductor layer;

a drain electrode disposed on at least a portion of the first semiconductor layer;

a gate dielectric layer disposed over at least a portion of the source electrode, the drain electrode and the first semiconductor layer, the gate dielectric layer having an junction formed therethrough to expose at least a portion of the second semiconductor layer;

a second semiconductor layer disposed over the gate dielectric layer and within the junction; and

a gate electrode disposed over the second semiconductor layer and within the junction.

2. The heterojunction field effect transistor of claim 1 , wherein the second semiconductor layer comprises a plurality of semiconductor layers.

3. The heterojunction field effect transistor of claim 2, wherein the plurality of second semiconductor layers comprises:

a first, second semiconductor layer comprising a first semiconductor material; and

a second, second semiconductor layer comprising a second semiconductor material that is different from the first semiconductor material.

4. The heterojunction field effect transistor of claim 3, wherein the first semiconductor material comprises intrinsic silicon.

5. The heterojunction field effect transistor of claim 4, wherein the second semiconductor material comprises p-type silicon.

6. The heterojunction field effect transistor of claim 5, wherein both the first semiconductor material and the second semiconductor material are amorphous.

7. The heterojunction field effect transistor of claim 6, wherein the first semiconductor material and the second semiconductor material are different than the material that comprises the first semiconductor layer.

8. The heterojunction field effect transistor of claim 7, wherein the first semiconductor layer comprises plurality of layers.

9. The heterojunction field effect transistor of claim 8, wherein plurality of first semiconductor layers have different Fermi levels.

10. The heterojunction field effect transistor of claim 1 , wherein the second semiconductor layer comprises a metal oxynitride or a metal oxide.

1 1 . The heterojunction field effect transistor of claim 10, wherein the first semiconductor layer comprises a metal oxynitride or a metal oxide that is different than the metal oxynitride of the second semiconductor layer.

12. The heterojunction field effect transistor of claim 1 1 , wherein the second semiconductor layer comprise a material selected from the group consisting of oxygen rich zinc oxynitride, zinc oxide, tin oxynitride, indium oxynitride, tin dioxide, and combinations thereof.

13. The heterojunction field effect transistor of claim 12, wherein the first semiconductor layer comprises a plurality of layers.

14. The heteroj unction field effect transistor of claim 13, wherein the plurality of first semiconductor layers have different Fermi levels.

15. The heteroj unction field effect transistor of claim 1 , wherein the second semiconductor layer comprises a p-type metal oxide, a p-type metal oxynitride, or a low work function metal oxide conductor.

16. The heterojunction field effect transistor of claim 15, wherein the second semiconductor layer comprises tin monoxide.

17. The heterojunction field effect transistor of claim 16, wherein the first semiconductor layer comprises a plurality of layers.

18. The heterojunction field effect transistor of claim 17, wherein the plurality of first semiconductor layers have different Fermi levels.

19. The heterojunction field effect transistor of claim 18, wherein the plurality of first semiconductor layers comprise metal oxynitrides.