WO2014101158A1 - 接收端检测方法、检测电路、光模块及系统 - Google Patents
接收端检测方法、检测电路、光模块及系统 Download PDFInfo
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- WO2014101158A1 WO2014101158A1 PCT/CN2012/087967 CN2012087967W WO2014101158A1 WO 2014101158 A1 WO2014101158 A1 WO 2014101158A1 CN 2012087967 W CN2012087967 W CN 2012087967W WO 2014101158 A1 WO2014101158 A1 WO 2014101158A1
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- pci
- detection
- receiving end
- pattern
- optical transmission
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- 238000001514 detection method Methods 0.000 title claims abstract description 574
- 230000003287 optical effect Effects 0.000 title claims abstract description 454
- 230000005540 biological transmission Effects 0.000 claims abstract description 310
- 238000000034 method Methods 0.000 claims abstract description 71
- 239000003990 capacitor Substances 0.000 claims description 41
- 230000002093 peripheral effect Effects 0.000 claims description 24
- 230000003068 static effect Effects 0.000 claims description 13
- 230000007704 transition Effects 0.000 claims description 9
- 230000008859 change Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 15
- 238000004891 communication Methods 0.000 abstract description 8
- 239000013307 optical fiber Substances 0.000 description 58
- 238000010586 diagram Methods 0.000 description 22
- 238000007796 conventional method Methods 0.000 description 11
- 230000008569 process Effects 0.000 description 10
- 230000007246 mechanism Effects 0.000 description 8
- 239000000835 fiber Substances 0.000 description 6
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4081—Live connection to bus, e.g. hot-plugging
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/27—Arrangements for networking
- H04B10/278—Bus-type networks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/40—Bus coupling
- G06F2213/4004—Universal serial bus hub with a plurality of upstream ports
Definitions
- the present invention relates to the field of optical communications, and in particular, to a receiving end detecting method, a detecting circuit, an optical module, and a system. Background technique
- PCI-E Peripheral Component Interconnect Express
- Intel Corporation which is widely used in personal computers, servers and data centers.
- PCI-E standard only supports electrical transmission and does not support optical transmission.
- the application of PCI-E bus is greatly limited; while optical transmission can solve this problem well, so supporting optical transmission is an inevitable trend of PCI-E bus development.
- the receiver detection function is one of the key issues to be solved.
- the so-called “receiver detection function” refers to: A mechanism for the PCI-E sender to detect whether the PCI-E receiver is in position after the power-on initialization is completed.
- the method for detecting the receiving end through the electrical connection adopted by the existing PCI-E bus mainly includes: transmitting, by the PCI-E transmitting end, a common mode voltage higher than the initial voltage to the PCI-E receiving end through the electrical connection. It is determined whether the time taken by the initial voltage to rise to the common mode voltage exceeds the threshold value to determine whether the PCI-E receiving end is in position, thereby achieving in-position detection of the PCI-E receiving end.
- the embodiment of the invention provides a receiving end detecting method, a detecting circuit, an optical module and a system.
- the technical solution is as follows:
- a method for detecting a receiving end is provided, where the method includes:
- the first detection pattern and the second detection pattern are both differential signals.
- the method before the sending, by using the optical transmission, the first detection pattern to the PCI-E receiving end, the method further includes:
- the quiescent substate to the detection.
- the active substate the transmitting the first detection pattern to the PCI-E receiving end by using the optical transmission, including:
- the detecting whether the receiving, by the PCI-E receiving end, the Second detection pattern including:
- the method further includes:
- the current link machine state is switched from the detected active substate to the polling state.
- the first detection pattern and the second detection pattern The same or different, and the frequencies of the first detection pattern and the second detection pattern are greater than a predetermined frequency threshold.
- a second aspect provides a receiving end detecting method, where the method includes:
- the first detection pattern and the second detection pattern are both differential signals.
- a third aspect provides a receiving end detecting method, where the method includes:
- the resistor network connected to the two terminals of the PCI-E transmitting end is switched from the closed state to the RC charging circuit. So that the PCI-E transmitting end determines the according to the equivalent RC charging circuit
- PCI-E receiver is in place
- the first predetermined signal and the second predetermined signal are both differential signals.
- the method before the sending the first predetermined signal to the second detecting circuit by using the optical transmission, the method further includes:
- the method includes:
- the resistor network that is respectively connected to the two terminals of the PCI-E transmitting end is configured by After the off state is switched to the on state, it includes:
- a predetermined time period from when the resistance network is switched from the off state to the on state is turned off.
- a fourth aspect provides a receiving end detecting method, where the method includes:
- the second predetermined signal is fed back through the optical transmission, so that the first detecting circuit determines two terminals to be connected with the PCI-E transmitting end according to the second predetermined signal.
- the respectively connected resistor networks are switched from the off state to the on state, so that the resistor network forms an equivalent RC charging circuit with the capacitors on the two terminals of the PCI-E transmitting end, so that the PCI-E transmitting end Determining, according to the equivalent RC charging circuit, that the receiving end is in place;
- the first predetermined signal and the second predetermined signal are both differential signals.
- the detecting, by the electrical connection, whether the PCI-E receiving end is in place includes:
- a fifth aspect provides a sending end, where the sending end includes:
- a code type sending module configured to send, by using optical transmission, a first detection pattern to a high-speed peripheral component interconnection PCI-E receiving end, so that after the PCI-E receiving end receives the first detection pattern, Optical transmission feedback second detection pattern;
- a receiving detection module configured to detect whether the second detection pattern that is received by the PCI-E receiving end by the optical transmission is received
- the in-position determining module is configured to determine the PCI-E receiving end if the detection result of the receiving detecting module is that the second detecting pattern received by the PCI-E receiving end is fed back by the optical transmission In place
- the first detection pattern and the second detection pattern are both differential signals.
- the sending end further includes: State detection module;
- the status detecting module is configured to detect whether the current link machine status is switched from the detected. static sub-state to the detected active sub-state;
- the pattern sending module is specifically configured to: after the state detecting module detects that the current link state is switched from the detecting. the static substate to the detecting. the active substate, then every predetermined time interval Sending the first detection pattern to the PCI-E receiving end.
- the receiving detection module is specifically configured to send the first detection code from the pattern sending module The predetermined detection period in which the type starts is detected whether the second detection pattern fed back by the PCI-E receiving end through the optical transmission is received.
- the sending end further includes: a state switching module
- the state switching module is configured to switch the current link state from the detected active substate to the polling state after the in-position determining module determines that the PCI-E receiving end is in place.
- the first detection pattern sent by the pattern sending module The second detection pattern detected by the receiving detection module is the same or different, and the frequencies of the first detection pattern and the second detection pattern are greater than a predetermined frequency threshold.
- a receiving end is provided, where the receiving end includes:
- a code receiving module configured to receive a high-speed peripheral component interconnection, and a first detection pattern sent by the PCI-E transmitting end by optical transmission;
- a pattern feedback module configured to: after the pattern receiving module receives the first detection pattern sent by the PCI-E transmitting end by using optical transmission, send back to the PCI-E sending end by using the optical transmission
- the second detection pattern is configured, so that the PCI-E transmitting end determines that the PCI-E receiving end is in position according to the second detection pattern
- the first detection pattern and the second detection pattern are both differential signals.
- the receiving end further includes a pattern generating module
- the pattern generation module is configured to generate a second detection pattern that is the same as or different from the first detection pattern received by the pattern receiving module.
- a first detection circuit comprising: a signal sending module, configured to send, by the optical transmission, a first predetermined signal to the second detecting circuit, so that the second detecting circuit detects the high-speed peripheral component interconnection PCI through an electrical connection after receiving the first predetermined signal- Whether the E receiving end is in position; if it is detected that the PCI-E receiving end is in position, the second predetermined signal is fed back through the optical transmission;
- a feedback detecting module configured to detect whether the second predetermined signal that is transmitted by the second detecting circuit through the optical transmission is received
- a circuit switching module configured to: if the detection result of the feedback detecting module is a second predetermined signal that receives feedback from the second detecting circuit through optical transmission, connect a resistor network respectively connected to two terminals of the PCI-E transmitting end Switching from the off state to the on state, the resistor network and the capacitors on the two terminals of the transmitting end form an equivalent resistance RC charging circuit, so that the PCI-E transmitting end is according to the equivalent RC charging circuit Determining that the PCI-E receiving end is in place;
- the first predetermined signal and the second predetermined signal are both differential signals.
- the first detecting circuit further includes: a sending end detecting module;
- the sending end detecting module is configured to detect, by using an electrical connection, whether the PCI-E transmitting end is performing receiving end detection;
- the signal sending module is configured to: if the sending end detecting module detects that the PCI-E transmitting end is performing the PCI-E receiving end detection, transmitting, by using the optical transmission, to the second detecting circuit The first predetermined signal is described.
- the sending end detecting module is specifically configured to detect whether a differential signal amplitude output by two terminals of the PCI-E transmitting end is It is less than the first threshold, and whether the common mode voltage output by the two terminals has a positive transition whose amplitude is greater than the second threshold within a predetermined period of time.
- the circuit switching module is further configured to switch from the resistor network by using a closed state After a predetermined period of time for starting the timing of the on state, the resistor network respectively connected to the two terminals of the PCI-E transmitting end is switched from the on state to the off state.
- a second detection circuit comprising:
- a signal receiving module configured to receive a first predetermined signal sent by the first detecting circuit by using the optical transmission
- the in-position detecting module configured to detect the high speed through the electrical connection after the signal receiving module receives the first predetermined signal Whether the peripheral component interconnects the PCI-E receiver is in place
- a signal feedback module configured to: when the in-position detecting module detects that the PCI-E receiving end is in position, feed back a second predetermined signal by using the optical transmission, so that the first detecting circuit is configured according to the second pre-
- the first predetermined signal and the second predetermined signal are both differential signals.
- the in-position detecting module includes: a common mode transmitting unit and a time detecting unit;
- the common mode transmitting unit is configured to send a common mode voltage by using two terminals connected to the PCI-E receiving end, where the common mode voltage is greater than an initial voltage;
- the time detecting unit is configured to detect whether a time required for the voltage of the two terminals connected to the PCI-E receiving end to rise from the initial voltage to the common mode voltage sent by the common mode transmitting unit is greater than a predetermined time Threshold.
- a ninth aspect provides a sending end, where the sending end includes:
- a transmitter a receiver, a pattern generation circuit, a pattern detection circuit, and a controller
- the transmitter is configured to send, by using optical transmission, a first detection pattern generated by the pattern generation circuit to a high-speed peripheral component interconnection PCI-E receiving end, so that the PCI-E receiving end receives the first After detecting the pattern, feeding back the second detection pattern by the optical transmission;
- the pattern detecting circuit is configured to detect whether the receiver receives the second detection pattern that is sent by the PCI-E receiving end through the optical transmission;
- the controller is configured to determine, if the detection result of the pattern detecting circuit is that the receiver receives the second detection pattern fed back by the optical transmission by the PCI-E receiving end, The PCI-E receiver is in place;
- the first detection pattern and the second detection pattern are both differential signals.
- the controller is further configured to detect whether a current link state is switched from a detected. static substate to a detected active substate;
- the transmitter is specifically configured to: after the controller detects that the current link state is switched from the detecting. the static substate to the detecting. the active substate, then the predetermined time interval is The PCI-E receiving end transmits the first detection pattern generated by the pattern generation circuit.
- the sending end further includes a timer
- the timer is configured to time a predetermined time period after the transmitter sends the first detection pattern generated by the pattern generation circuit
- the pattern detecting circuit is configured to detect, during a predetermined time period of timing of the timer, whether the receiver receives the second detection pattern fed back by the PCI-E receiving end by using the optical transmission .
- the controller is further configured to determine that the PCI-E receiving end is in place After that, the current link machine state is switched from the detected.active substate to the polling state.
- the first detection pattern and the generated by the pattern generation circuit are the same or different, and the frequencies of the first detection pattern and the second detection pattern are greater than a predetermined frequency threshold.
- the tenth aspect provides a receiving end, where the receiving end includes:
- a receiver a pattern detection circuit, a pattern generation circuit, a transmitter, and a controller
- the receiver is configured to receive a first detection pattern transmitted by the high-speed peripheral component interconnection PCI-E transmitting end by optical transmission;
- the controller configured to, after the pattern detecting circuit detects that the receiver receives the first detection pattern sent by the PCI-E transmitting end by optical transmission, control the transmitter to pass the Determining, by the PCI-E sending end, that the PCI-E receiving end is in position according to the second detection pattern;
- the first detection pattern and the second detection pattern are both differential signals.
- the pattern generating circuit is configured to generate a second detection pattern that is the same as or different from the first detection pattern received by the receiver.
- a first detection circuit includes:
- the transmitter is configured to send a first predetermined signal to the second detecting circuit by using optical transmission, so that the second detecting circuit detects the high-speed peripheral component interconnection PCI through an electrical connection after receiving the first predetermined signal. - Whether the E receiving end is in position; if it is detected that the PCI-E receiving end is in position, feeding back the second predetermined signal by the optical transmission;
- the controller is configured to detect whether the receiver receives the second predetermined signal that the second detecting circuit feeds back through the optical transmission; The controller is further configured to: if the detection result is that the receiver receives the second predetermined signal fed back by the second detection circuit by optical transmission, the two terminals connected to the PCI-E transmitting end are respectively connected The resistor network is switched from a closed state to a conductive state, so that the resistor network forms an equivalent RC charging circuit with a capacitor on the two terminals of the transmitting end, so that the PCI-E transmitting end is according to the equivalent RC The charging circuit determines that the PCI-E receiving end is in place;
- the first predetermined signal and the second predetermined signal are both differential signals.
- the first detecting circuit further includes: a state identifying circuit
- the status identifying circuit is configured to detect, by using an electrical connection, whether the PCI-E transmitting end is performing receiving end detection;
- the transmitter is configured to: if the sending end detecting circuit detects that the PCI-E transmitting end is performing the PCI-E receiving end detection, transmitting, by using the optical transmission, the second detecting circuit The first predetermined signal.
- the state identification circuit is specifically configured to detect whether a differential signal amplitude output by two terminals of the PCI-E transmitting end is It is less than the first threshold, and whether the common mode voltage output by the two terminals has a positive transition whose amplitude is greater than the second threshold within a predetermined period of time.
- the first detecting circuit further includes: a timer
- the timer is configured to time a predetermined time period after the controller switches the resistance network from an off state to an on state;
- the controller is further configured to: after the predetermined time period that is timed by the timer, provide a second detection circuit with the PCI-E twelfth aspect, where the circuit includes:
- Receiver receiver detection circuit, controller and transmitter
- the receiver is configured to receive a first predetermined signal that is sent by the first detecting circuit by using optical transmission; the receiving end detecting circuit is configured to be electrically connected after the receiver receives the first predetermined signal Check if the PCI-E receiver is in place;
- the controller is configured to, if the receiving end detecting circuit detects that the PCI-E receiving end is in position, control the transmitter to feed back a second predetermined signal by using the optical transmission, so that the first detecting circuit
- the upper capacitor forms an equivalent RC charging circuit, so that the PCI-E transmitting end determines that the PCI-E receiving end is in place according to the equivalent RC charging circuit;
- the first predetermined signal and the second predetermined signal are both differential signals.
- the receiving end detecting circuit includes: a common mode transmitting sub circuit and a time detecting sub circuit;
- the common mode transmitting sub-circuit is configured to send a common mode voltage by using two terminals connected to the PCI-E receiving end, where the common mode voltage is greater than an initial voltage;
- the time detecting sub-circuit configured to detect whether a time required for a voltage of two terminals connected to the PCI-E receiving end to rise from the initial voltage to a common mode voltage sent by the common mode transmitting sub-circuit is Greater than a predetermined threshold.
- an optical module is provided, where the optical module is integrated with various possible implementation manners, such as the seventh aspect, the seventh possible aspect, the eleventh aspect or the eleventh aspect
- a fourteenth aspect a bus system is provided, comprising: the fifth aspect, the various possible implementation manners of the fifth aspect, the ninth aspect, or the transmitting end described in the various possible implementation manners of the ninth aspect, And a receiving end as described in the sixth aspect, the various possible implementation manners of the sixth aspect, the tenth aspect, or the various possible implementation manners of the tenth aspect;
- the optical transceiver and the optical cable are connected between the transmitting end and the receiving end.
- a bus system including a transmitting end, a first detecting circuit connected to the transmitting end, a first optical module connected to the first detecting circuit, and a first optical module a second optical module connected to the optical cable, a second detecting circuit connected to the second optical module, and a receiving end connected to the second detecting circuit;
- the first detecting circuit is the first detecting circuit described in the seventh aspect, the various possible implementation manners of the seventh aspect, the eleventh aspect or the various possible implementation manners of the eleventh aspect;
- the second detecting circuit is the second detecting circuit of the eighth aspect, the various possible embodiments of the eighth aspect, the twelfth aspect or the various possible embodiments of the twelfth aspect.
- a bus system including: a transmitting end, a first optical module connected to the transmitting end, a second optical module connected to the first optical module by an optical cable, and the second optical The receiving end to which the module is connected;
- the first optical module is integrated with the first detection circuit as described in various possible implementation manners of the seventh aspect, the seventh possible aspect, the eleventh aspect or the eleventh aspect;
- the second optical module is integrated with the second detection circuit as described in the eighth aspect, the various possible embodiments of the eighth aspect, the twelfth aspect or the various possible embodiments of the twelfth aspect.
- 1A is a schematic structural diagram of a PCI-E bus system supporting electrical transmission
- 1B is a schematic diagram of switching between three states of a link state machine at a transmitting end
- FIG. 2 is a schematic structural view of an implementation environment involved in a part of embodiments of the present invention.
- FIG. 3 is a flowchart of a method for detecting a receiving end according to an embodiment of the present invention
- FIG. 4 is a flowchart of a method for detecting a receiving end according to another embodiment of the present invention.
- 5A is a schematic structural view of an implementation environment involved in a part of embodiments of the present invention.
- 5B is a schematic structural view of an implementation environment involved in a part of embodiments of the present invention.
- FIG. 6 is a flowchart of a method for detecting a receiving end according to an embodiment of the present invention.
- FIG. 7 is a flowchart of a method for detecting a receiving end according to another embodiment of the present invention.
- FIG. 8 is a structural block diagram of a bus system according to an embodiment of the present invention.
- FIG. 9 is a structural block diagram of a bus system according to another embodiment of the present invention.
- FIG. 10 is a schematic structural diagram of a bus system according to an embodiment of the present invention.
- 11 is a schematic structural diagram of a bus system according to another embodiment of the present invention
- 12 is a block diagram showing the structure of a bus system according to an embodiment of the present invention.
- FIG. 13 is a structural block diagram of a bus system according to another embodiment of the present invention.
- FIG. 14 is a schematic structural diagram of a bus system according to an embodiment of the present invention.
- FIG. 15 is a schematic structural diagram of a bus system according to another embodiment of the present invention.
- FIG. 16 is a schematic structural diagram of an optical module according to still another embodiment of the present invention. detailed description
- FIG. 1A shows a schematic structural diagram of a PCI-E bus system supporting electrical transmission.
- the PCI-E system includes two parts, a transmitting chip 120 and a receiving chip 140. The two parts can be located in different devices or in the same device.
- the PCI-E sender detects whether the PCI-E receiver is in place, it includes:
- the PCI-E transmitter sends a pair of common-mode voltages higher than the initial voltage from its own two terminals D+ and D-.
- the initial voltage can be 0 or a pair on the two terminals.
- Equal and lower voltage, common mode voltage is a pair of equal and higher voltages on the two terminals; if the PCI-E receiver is not connected to the PCI-E transmitter, ie PCI-E reception If the terminal is not in place, the PCI-E voltage; if the PCI-E receiver is connected to the PCI-E transmitter, that is, the PCI-E receiver is in place, due to the presence of capacitor C1 and resistor R1, capacitor C2 and resistor R2.
- the PCI-E transmitter can detect that the voltage on its own two terminals will rise from the initial voltage to the common mode voltage relatively slowly; The time taken by the PCI-E voltage can detect whether the PCI-E receiver is in place.
- Capacitor C1 and capacitor C2 can be parasitic resistance and AC coupling capacitors; resistors R1 and R2 can be termination resistors at the PCI-E receiver.
- the state of the link state machine includes three types: detection. Static substate (Detect.Quiet ), detection, active substate ( Detect.Active ), and polling state ( Polling ).
- the static substate indicates that the PCI-E transmitting end is in an electrical idle state, and the maximum duration of the electrical idle state is determined by The timing of the timer determines that when the timer expires, the link state opportunity is automatically detected.
- the static substate enters the detection.
- the active substate indicates that the PCI-E transmitter is undergoing PCI-E. Whether the receiving end is in the detection of the bit; the polling sub-state indicates that the PCI-E transmitting end has detected that the PCI-E receiving end is in place and starts the link negotiation process.
- the link state machine is in the detection and quiescent substate, and the first timing is started at the same time; after the timeout is completed, the state of the link state machine is Detection.
- the static substate is automatically switched to the detection.
- Active substate the PCI-E transmitter starts the receiver detection, and starts the second timing; if the PCI-E transmitter detects that the receiver is in place, the link state machine The status is detected.
- the active sub-state is switched to the polling state.
- the PCI-E sender starts to send the negotiation code stream to the PCI-E receiver, and the link starts the normal negotiation process. If the PCI-E sender does not detect the PCI-E receiver.
- the state of the link state machine is detected.
- the active substate is switched back to the detection.
- the stationary substate, and the first timing is started again, and the above process is repeated.
- the PCI-E sender is detecting.
- the active substate does not detect that the receiver is in place, the state of the link state machine will not enter the polling state, and the PCI-E sender will not go to the PCI-E receiver.
- the negotiation code stream is sent, and the link cannot be properly connected (LINK UP).
- the implementation environment is a PCI-E bus system that supports optical transmission.
- the PCI-E bus system includes: a transmitting chip 220, a first optical module 240, a second optical module 260, and a receiving chip 280.
- the transmitting chip 220 and the receiving chip 280 may be located in different devices or in the same device.
- the transmitting chip 220 includes a transmitting end 222, and the two differential lines of the transmitting end 222 are connected to the first optical module 240 through capacitors C1 and C2, respectively.
- the first optical module 240 is connected to the second optical module 260 through an optical fiber.
- the receiving chip 280 includes a receiving end 282.
- the two differential lines of the receiving end 282 are respectively connected to the second optical module 260, and the two differential lines are grounded through the resistors R1 and R2, respectively.
- the capacitor C1 and the capacitor C2 may be parasitic resistance and AC coupling capacitors; the resistors R1 and R2 may be termination resistors of the PCI-E receiving end.
- FIG. 3 is a flowchart of a method for detecting a receiving end according to an embodiment of the present invention. This embodiment is mainly illustrated by applying the receiving end detecting method to the implementation environment shown in FIG. 2.
- the receiving end detecting method includes:
- Step 302 The PCI-E transmitting end sends the first detection pattern to the PCI-E receiving end by using optical transmission.
- the PCI-E transmitting end may be the PCI-E bus system supporting the optical cable transmission shown in FIG. 2.
- the PCI-E transmitting end 222; the PCI-E receiving end may be the PCI-E receiving end 282 in the PCI-E bus system supporting the optical cable transmission shown in FIG. 2.
- the PCI-E sender can send the first detection pattern to the PCI-E receiver through optical transmission. Since the optical module and the optical cable can only transmit differential signals, the first detection pattern is a differential signal.
- the optical transmission can be performed by using an optical fiber between the first optical module 240, the second optical module 260, and the two optical modules between the PCI-E transmitting end and the PCI-E receiving end.
- the PCI-E receiving end receives the first detection pattern sent by the PCI-E transmitting end through optical transmission.
- Step 304 After receiving the first detection pattern sent by the PCI-E transmitting end by using the optical transmission, the PCI-E receiving end feeds back the second detection pattern to the PCI-E transmitting end by using the optical transmission.
- the PCI-E receiving end can feed back the second detection pattern to the PCI-E transmitting end through the optical transmission.
- the second detection pattern is also a differential signal, and the second detection pattern may be the same as or different from the first detection pattern, as long as it conforms to the pattern agreed upon by the PCI-E transmitting end and the PCI-E receiving end.
- the PCI-E transmitting end receives the second detection pattern that the PCI-E receiving end feeds back through the optical transmission.
- Step 306 The PCI-E transmitting end detects whether a second detection pattern that the PCI-E receiving end feeds back through the optical transmission is received.
- the PCI-E transmitter detects whether a second detection pattern that the PCI-E receiver transmits back through the optical transmission is received. That is, if the PCI-E receiving end is in position, the PCI-E transmitting end can receive the second detection pattern that the PCI-E receiving end feeds back through the optical transmission; if the PCI-E receiving end is not in the bit, the PCI-E The transmitting end cannot receive the second detection pattern that the PCI-E receiving end feeds back through the optical transmission.
- Step 308 If the detection result is that the second detection pattern fed back by the optical transmission is received by the PCI-E receiving end, the PCI-E transmitting end determines that the PCI-E receiving end is in place.
- the first detection pattern and the second detection pattern refer to the example coding table of the embodiment shown in FIG. 4, which is not limited thereto, as long as it conforms to the pattern agreed upon by the PCI-E sender and the PCI-E receiver. which is Yes.
- the receiving end detecting method sends a first detecting pattern to the PCI-E receiving end through optical transmission by the PCI-E transmitting end, so that the PCI-E receiving end receives the After the first detection pattern, the second detection pattern is fed back to the PCI-E transmitting end by the optical transmission; then the PCI-E transmitting end detects whether the PCI-E receiving end receives the first feedback through the optical transmission.
- FIG. 4 a flow chart of a method for detecting a receiving end according to another embodiment of the present invention is shown. This embodiment is mainly illustrated by applying the receiving end detecting method to the implementation environment shown in FIG. 2. As a more preferred embodiment provided by the embodiment shown in FIG. 3, the receiving end detecting method includes: Step 402: The PCI-E transmitting end detects whether the current link state is switched from detecting to the stationary sub-state to detecting. Active substate
- the link machine state includes any one of a detection, a stationary substate, a detection, an active substate, and a polling state.
- Step 404 After the PCI-E transmitting end detects that the current link state is switched from the detecting. the stationary sub-state to the detecting. the active sub-state, transmitting the first detection to the PCI-E receiving end by optical transmission every predetermined time interval. Pattern
- the optical transmission includes a first optical module 240, a second optical module 260, and an optical fiber between the two optical modules between the PCI-E transmitting end and the PCI-E receiving end,
- the PCI-E receiving end receives the first detection pattern transmitted by the PCI-E transmitting end by optical transmission.
- Step 406 After receiving the first detection pattern sent by the PCI-E transmitting end by using the optical transmission, the PCI-E receiving end feeds back the second detection pattern to the PCI-E transmitting end by using the optical transmission.
- the PCI-E receiving end receives the first detection pattern transmitted by the PCI-E transmitting end by optical transmission Thereafter, a second detection pattern that is the same as or different from the first detection pattern may be generated, and then the second detection pattern is fed back to the PCI-E transmitting end through the optical transmission.
- the PCI-E transmitting end receives the second detection pattern that the PCI-E receiving end feeds back through the optical transmission.
- Step 408 The PCI-E transmitting end detects, according to a predetermined time period from the sending of the first detection pattern, whether a second detection pattern that the PCI-E receiving end feeds back through the optical transmission is received.
- the PCI-E transmitting end detects whether the second detection pattern fed back by the PCI-E receiving end through the optical transmission is detected within a predetermined period of time from the start of transmitting the first detection pattern. That is, if the PCI-E receiving end is in position, the PCI-E transmitting end can receive the second detection pattern that the PCI-E receiving end feeds back through the optical transmission; if the PCI-E receiving end is not in the bit, the PCI-E sending The terminal cannot receive the second detection pattern that the PCI-E receiver transmits back through the optical transmission.
- the "predetermined time period" described herein is the length of time for the aforementioned link state machine to be detected by the detection.
- the stationary substate is switched to the second periodic time after the active substate.
- Step 410 If the detection result is that the second detection pattern fed back by the optical transmission is received by the PCI-E receiving end, the PCI-E transmitting end determines that the PCI-E receiving end is in place;
- the detection result is that the PCI-E receiving end receives the second detection pattern fed back by the optical transmission, and the PCI-E transmitting end determines The PCI-E receiver is in place. If the PCI-E transmitting end sends a second detection pattern that is not received by the PCI-E receiving end through the optical transmission within a predetermined period of time from the transmission of the first detection pattern, the PCI-E transmitting end determines the PCI-E transmitting end. The PCI-E receiver is not in position, and then the current link state is switched from the detection. Active substate back to the detection. The quiescent substate, and the first timing is restarted.
- Step 412 If the PCI-E sender determines that the PCI-E receiver is in place, the current link state is changed from the detected active state to the polling state.
- the PCI-E sender determines that the PCI-E receiver is in place, the current link state is switched from the detected.active substate to the polling state.
- the PCI-E sender sends the negotiation code stream to the PCI-E receiver, and the link starts the normal negotiation process.
- the foregoing first detection pattern and the second detection pattern satisfy the following two conditions: First, the first detection pattern and the second detection pattern are only used for receiving end in-position detection, and not in other code streams. Second occurrence; second, the frequency of the first detection pattern and the second detection pattern is greater than a predetermined threshold. Otherwise, when the frequencies of the first detection pattern and the second detection pattern are too low, the cable transmission may be distorted.
- the first detection pattern and the second detection pattern also need to be differential signals, please combine the following example coding table.
- the first detection pattern and the second detection pattern may both be K28.0 + K28.1 + K28.2 + K28.3 + K28.4. Sample code table
- the receiving end detecting method sends a first detecting pattern to the PCI-E receiving end through optical transmission by the PCI-E transmitting end, so that the PCI- After receiving the first detection pattern, the E receiving end feeds back the second detection pattern to the PCI-E transmitting end through the optical transmission; then the PCI-E transmitting end detects whether the PCI-E receiving end receives the The second detection pattern of the optical transmission feedback; if the detection result is that the second detection pattern that the PCI-E receiving end feeds back through the optical transmission is received, the PCI-E transmitting end determines the PCI- The E receiving end is in place; it solves the problem that the receiving end can not be detected by the traditional method in the PCI-E bus supporting optical transmission; the receiving end detection can also be realized in the PCI-E bus supporting optical transmission.
- FIG. 5A shows a schematic structural diagram of an implementation environment involved in a part of embodiments of the present invention.
- the implementation environment is a PCI-E bus system that supports optical transmission.
- the PCI-E bus system includes: a transmitting chip 520, a first optical module 540, a second optical module 560, and a receiving chip 580.
- the sending chip 520 and the receiving chip 580 may be located in different devices or may be located in the same device. Medium.
- the transmitting chip 520 includes a PCI-E transmitting end 522, and the two differential lines of the PCI-E transmitting end 522 are connected to the first optical module 540 through capacitors C1 and C2, respectively.
- the first optical module 540 is connected to the second optical module 560 through an optical fiber. Different from FIG. 2, the circuit portion of the first optical module 540 is integrated with the first detecting circuit 542; the circuit portion of the second optical module 560 is integrated with the second detecting circuit 562.
- the first detecting circuit 542 and the second detecting circuit 562 can communicate by multiplexing the original optical fiber between the first optical module 540 and the second optical module 560; the first detecting circuit 542 and the second detecting circuit 562 It is also possible to communicate via additional fiber optics.
- the receiving chip 580 includes a PCI-E receiving end 582.
- the two differential lines of the PCI-E receiving end 582 are respectively connected to the second optical module 560, and the two differential lines are grounded through the resistors R1 and R2, respectively.
- Capacitor C1 and capacitor C2 can be parasitic resistance and AC coupling capacitors; resistors R1 and R2 can be termination resistors at the PCI-E receiver.
- FIG. 5B there is shown a schematic structural view of an implementation environment involved in another embodiment of the present invention.
- the implementation environment is a PCI-E bus system that supports optical transmission.
- the PCI-E bus system includes: a transmitting chip 520, a first optical module 540, a second optical module 560, and a receiving chip 580.
- the transmitting chip 520 and the receiving chip 580 may be located in two different devices or may be located in the same device.
- the transmitting chip 520 includes a PCI-E transmitting end 522, and the two differential lines of the PCI-E transmitting end 522 are respectively connected to the first detecting circuit 542 through the capacitors C1 and C2, and the first detecting circuit 542 and the A light module 540 is connected.
- the first optical module 540 is connected to the second optical module 560 through an optical fiber.
- the receiving chip 580 includes a PCI-E receiving end 582.
- the two differential lines of the PCI-E receiving end 582 are respectively connected to the second detecting circuit 562.
- the second detecting circuit 562 is connected to the second optical module 560, and the PCI-E receiving is performed.
- the two differential lines of terminal 582 are grounded through resistors R1 and R2, respectively.
- the first detecting circuit 542 and the second detecting circuit 562 can communicate by multiplexing the original optical fiber between the first optical module 540 and the second optical module 560; the first detecting circuit 542 and the second detecting circuit 562 It is also possible to communicate via additional fiber optics.
- the capacitor C1 and the capacitor C2 may be parasitic resistance and AC coupling capacitors; the resistors R1 and R2 may be termination resistors of the PCI-E receiving end.
- FIG. 6 is a flowchart of a method for detecting a receiving end according to an embodiment of the present invention. This embodiment is mainly illustrated by applying the receiving end detecting method to the implementation environment shown in FIG. 5A or FIG. 5B.
- the receiving end detecting method includes:
- Step 602 The first detecting circuit sends the first predetermined signal to the second detecting circuit by using the optical transmission.
- the first detecting circuit sends the first predetermined signal to the second detecting circuit by using the optical transmission.
- the optical transmission includes the original optical fiber or the newly added optical fiber between the first optical module 540 and the second optical module 560.
- the implementation environment is the implementation environment shown in FIG. 5B, The optical transmission includes the original optical fiber or the newly added optical fiber between the first optical module 540, the second optical module 560, the first optical module 540, and the second optical module 560.
- the second detecting circuit receives the first predetermined signal transmitted by the first detecting circuit by optical transmission.
- the first predetermined signal is a differential signal for triggering the second detecting circuit to perform PCI-E receiving end detection.
- Step 604 after receiving the first predetermined signal, the second detecting circuit detects whether the PCI-E receiving end is in position through an electrical connection;
- the second detecting circuit After receiving the first predetermined signal, the second detecting circuit detects whether the PCI-E receiving end is in position by an electrical connection between itself and the PCI-E receiving end.
- Step 606 if the second detecting circuit detects that the PCI-E receiving end is in position, the second predetermined signal is fed back by the optical transmission;
- the second predetermined signal is fed back to the first detecting circuit by the optical transmission.
- the second predetermined signal is also a differential signal for feeding back to the first detection circuit that the PCI-E receiver is in place.
- Step 608 the first detecting circuit detects whether a second predetermined signal that the second detecting circuit transmits feedback through the optical transmission is received;
- Step 610 If the detection result of the first detecting circuit is that the second predetermined signal is received by the second detecting circuit through the optical transmission, the resistance network connected to the two terminals of the PCI-E transmitting end is switched from the off state to the off state.
- the on state causes the resistor network to form an equivalent RC charging circuit with the capacitors on the two terminals of the PCI-E transmitter.
- the resistor network can be exemplarily referred to Figure 16 and the corresponding description.
- the inside of the first detecting circuit includes a resistor network connected to the two terminals of the PCI-E transmitting end and a corresponding electronic switch.
- the detection result of the first detecting circuit is the second predetermined signal received by the second detecting circuit.
- the resistor network connected to the two terminals of the PCI-E transmitting end is switched from the off state to the on state, so that the resistor network and the two terminals of the PCI-E transmitting end are The capacitor forms an equivalent RC charging circuit. That is, the first detection circuit emulates itself as a "PCI-E receiver,".
- the electronic switch can be exemplarily referred to Figure 16 and the corresponding description.
- the PCI-E transmitter determines that the PCI-E receiver is in place according to the equivalent RC charging circuit.
- the receiving end detecting method implements PCI-E receiving end detection by electrically connecting the second detecting circuit and the PCI-E receiving end, and the second detecting circuit and the first detecting circuit pass the light.
- the transmissions communicate with each other, and the resistor network in the first detecting circuit forms an equivalent RC charging circuit with the capacitors on the two terminals of the PCI-E transmitting end, so that the PCI-E transmitting end detects that the PCI-E receiving end is in place;
- the problem of receiving end detection cannot be realized by the conventional method; and in the PCI-E bus supporting optical transmission, the effect of receiving end detection can also be realized. Referring to FIG.
- FIG. 7 a flow chart of a method for detecting a receiving end according to another embodiment of the present invention is shown. This embodiment is mainly illustrated by applying the receiving end detecting method to the implementation environment shown in FIG. 5A or FIG. 5B. A more preferred embodiment is provided based on the embodiment shown in Fig. 6.
- the receiving end detecting method includes:
- Step 702 The first detecting circuit detects, by using an electrical connection, whether the PCI-E transmitting end is performing receiving end detection.
- the first detecting circuit first detects whether the PCI-E receiving end is performing PCI-E receiving end detection through an electrical connection. Specifically, the first detecting circuit detects whether the differential signal amplitude outputted by the two terminals of the PCI-E transmitting end is smaller than a first threshold, for example, the differential signal amplitude is less than 65 mv, and whether the common mode voltage output by the two terminals is in a predetermined time period. In a positive transition whose amplitude is greater than the second threshold, for example, there is a positive transition of more than 500 mv in 1 ms. That is, whether the PCI-E transmitter emits a higher common mode voltage than the initial voltage.
- a first threshold for example, the differential signal amplitude is less than 65 mv
- the common mode voltage output by the two terminals is in a predetermined time period.
- a positive transition whose amplitude is greater than the second threshold for example, there is a positive transition of more than 500 mv in 1 ms. That
- Step 704 if it is detected that the PCI-E transmitting end is performing PCI-E receiving end detection, the first detecting circuit sends the first predetermined signal to the second detecting circuit by optical transmission;
- the first detecting circuit may send the first predetermined signal to the second detecting circuit by optical transmission.
- the optical transmission includes the original optical fiber or the newly added optical fiber between the first optical module 540 and the second optical module 560.
- the optical transmission includes the original optical fiber or the newly added optical fiber between the first optical module 540, the second optical module 560, the first optical module 540, and the second optical module 560.
- the first predetermined signal is a differential signal for triggering the second detection The path performs PCI-E receiver detection.
- the second detecting circuit receives the first predetermined signal transmitted by the first detecting circuit by optical transmission.
- Step 706 after receiving the first predetermined signal, the second detecting circuit detects whether the PCI-E receiving end is in position through an electrical connection;
- the second detecting circuit After receiving the first predetermined signal, the second detecting circuit detects whether the receiving end is in position through an electrical connection. Specifically, the second detecting circuit transmits the common mode voltage by using two terminals connected to the PCI-E receiving end, the common mode voltage is greater than the initial voltage; detecting the voltage of the two terminals connected to the PCI-E receiving end by the initial voltage Whether the time required to rise to the common mode voltage is greater than a predetermined threshold. If the required time is greater than the predetermined threshold, it indicates that the PCI-E receiver is in place.
- Step 708 if the second detecting circuit detects that the PCI-E receiving end is in position, feeding back the second predetermined signal by optical transmission;
- the second predetermined signal is fed back to the first detecting circuit by optical transmission.
- the second predetermined signal is also a differential signal for feeding back to the first detection circuit that the PCI-E receiver is in place.
- Step 710 The first detecting circuit detects whether a second predetermined signal that is transmitted by the second detecting circuit through the optical transmission is received.
- Step 712 If the detection result of the first detection circuit is that the second predetermined signal received by the second detection circuit is transmitted through the optical transmission, the resistance network connected to the two terminals of the PCI-E transmitting end is switched from the off state to the guide state.
- the pass state causes the resistor network to form an equivalent RC charging circuit with the capacitors on the two terminals of the PCI-E transmitting end;
- the first detection circuit includes a resistor network and a corresponding electronic switch respectively connected to the two terminals of the PCI-E transmitting end. If the detection result of the first detecting circuit is the second predetermined signal received by the second detecting circuit, Then, the resistor network connected to the two terminals of the PCI-E transmitting end is switched from the off state to the on state, so that the resistor network and the capacitor on the two terminals of the PCI-E transmitting end form an equivalent RC charging circuit. That is, the first detection circuit emulates itself as a "PCI-E receiver".
- the PCI-E transmitter determines that the PCI-E receiver is in place according to the equivalent RC charging circuit.
- the PCI-E transmitter can detect that the PCI-E receiver is in place according to the equivalent RC charging circuit. Specifically, the PCI-E transmitting end transmits a common mode voltage higher than the initial voltage to the first detecting circuit by using its own two terminals, and detects that the voltage on the two terminals is raised from the initial voltage to the common mode voltage. Whether the required time exceeds a predetermined threshold to detect whether the PCI-E receiver is in place. Due to PCI-E transmission There is an equivalent RC charging circuit formed by the capacitor and the resistor network in the first detecting circuit between the terminal and the first detecting circuit, so the PCI-E transmitting end detects that the PCI-E receiving end is in place.
- Step 714 After a predetermined period of time from when the resistance network is switched from the off state to the on state, the first detecting circuit switches the resistance network connected to the two terminals of the PCI-E transmitting end from the on state to the off state. status.
- step 712 the first detecting circuit starts timing after switching the resistor network respectively connected to the two terminals of the PCI-E transmitting end from the off state to the on state. And after the scheduled time period, switch back to the off state.
- the receiving end detecting method implements PCI-E receiving end detection by electrically connecting the second detecting circuit and the PCI-E receiving end, and the second detecting circuit and the first detecting circuit pass the light.
- the transmissions communicate with each other, and the resistor network in the first detecting circuit forms an equivalent RC charging circuit with the capacitors on the two terminals of the PCI-E transmitting end, so that the PCI-E transmitting end detects that the PCI-E receiving end is in place;
- the problem of receiving end detection cannot be realized by the conventional method; and in the PCI-E bus supporting optical transmission, the effect of receiving end detection can also be realized.
- the first detecting circuit also triggers the subsequent steps when detecting that the PCI-E transmitting end is performing PCI-E receiving end detection, and can be most compatible with the existing detecting mechanism.
- the following is an embodiment of the apparatus of the present invention, which can be used to carry out embodiments of the method of the present invention.
- FIG. 8 is a structural block diagram of a bus system according to an embodiment of the present invention. This embodiment is mainly illustrated by the fact that the bus system is a PCI-E bus system.
- the bus system includes: a PCI-E transmitter 820 and a PCI-E receiver 840.
- the PCI-E transmitter 820 includes a pattern transmission module 822, a reception detection module 824, and an in-position determination module 826.
- the code type sending module 822 is configured to send, by using optical transmission, a first detection pattern to the PCI-E receiving end 840, so that the PCI-E receiving end 840 receives the first detection pattern and then transmits the optical transmission.
- Feedback second detection pattern
- the receiving detection module 824 is configured to detect whether the second detection pattern that the PCI-E receiving end 840 feeds back through the optical transmission is received;
- the in-position determining module 826 is configured to determine the PCI-E if the detection result of the receiving and detecting module 824 is that the second detecting pattern received by the PCI-E receiving end is fed back by the optical transmission The receiving end is in place.
- the receiving end 840 includes a pattern receiving module 842 and a pattern feedback module 844.
- the code receiving module 842 is configured to receive a first detection pattern sent by the PCI-E transmitting end 820 by optical transmission;
- the pattern feedback module 844 is configured to: after the pattern receiving module 842 receives the first detection pattern sent by the PCI-E transmitting end by optical transmission, feed back to the PCI-E transmitting end 842 by using the optical transmission. Detecting a pattern, so that the PCI-E transmitting end 842 determines that the PCI-E receiving end is in position according to the second detection pattern;
- the first detection pattern and the second detection pattern are both differential signals.
- the bus system provided in this embodiment sends a first detection pattern to the PCI-E receiving end through optical transmission by the PCI-E transmitting end, so that the PCI-E receiving end receives the first After detecting the pattern, the second detection pattern is fed back to the PCI-E transmitting end by the optical transmission; then the PCI-E transmitting end detects whether the second detection by the PCI-E receiving end through the optical transmission feedback is received.
- FIG. 9 is a structural block diagram of a bus system according to another embodiment of the present invention. This embodiment is mainly illustrated by the fact that the bus system is a PCI-E bus system. As a more preferred embodiment based on the embodiment shown in Fig. 8, the bus system includes: a PCI-E transmitter 820 and a PCI-E receiver 840.
- the PCI-E transmitter 820 includes a state detection module 821, a pattern transmission module 822, a reception detection module 824, an in-position determination module 826, and a state switching module 827.
- the state detecting module 821 is configured to detect whether the current link state is switched from the detecting. the static substate to the detecting. the active substate;
- the pattern sending module 822 is configured to: after the state detecting module 821 detects that the current link machine state is switched from the detecting. the stationary sub-state to the detecting. the active sub-state, then the predetermined time interval is The PCI-E receiving end 840 transmits the first detection pattern.
- the receiving detection module 824 is configured to detect whether the second detection fed back by the PCI-E receiving end 840 is received within a predetermined period of time when the pattern sending module 822 sends the first detecting pattern to start timing. Pattern
- the in-position determining module 826 is configured to determine the PCI-E if the detection result of the receiving and detecting module 824 is that the second detecting pattern received by the PCI-E receiving end is fed back by the optical transmission The receiving end is in place;
- the state switching module 827 is configured to switch the current link state from the detected active substate to the polling state after the in-position determining module 826 determines that the PCI-E receiving end is in place.
- the first detection pattern sent by the pattern sending module 822 is the same as or different from the second detection pattern detected by the receiving detection module 824, and the first detection pattern and The frequency of the second detection pattern is greater than a predetermined frequency threshold.
- the first detection pattern and the second detection pattern are both differential signals.
- the PCI-E receiving end 840 includes a pattern receiving module 842, a pattern generating unit 843, and a pattern feedback module 844.
- the code receiving module 842 is configured to receive a first detection pattern sent by the PCI-E transmitting end 820 by optical transmission;
- a pattern generation module 843 configured to generate a second detection pattern that is the same as or different from the first detection pattern received by the pattern receiving module 842;
- the pattern feedback module 844 is configured to: after the pattern receiving module 842 receives the first detection pattern sent by the PCI-E transmitting end by optical transmission, feed back to the PCI-E transmitting end 842 by optical transmission.
- the second detection pattern generated by the pattern generation module 843 is such that the PCI-E transmitting end 842 determines that the PCI-E receiving end is in position according to the second detection pattern.
- the first detection pattern and the second detection pattern are both differential signals, and the optical transmission includes an optical module and an optical fiber.
- the bus system provided in this embodiment sends a first detection pattern to the PCI-E receiving end through optical transmission by the PCI-E transmitting end, so that the PCI-E receiving end receives the first After detecting the pattern, the second detection pattern is fed back to the PCI-E transmitting end by the optical transmission; then the PCI-E transmitting end detects whether the second detection by the PCI-E receiving end through the optical transmission feedback is received.
- FIG. 10 shows a schematic structural diagram of a bus system according to an embodiment of the present invention. This embodiment is mainly illustrated by the bus system being a PCI-E bus system.
- the bus system includes: a PCI-E transmitter 1020 and a PCI-E receiver 1040.
- the PCI-E transmitting end 1020 includes: a transmitter 1021, a receiver 1022, a pattern generation circuit 1023, a pattern detection circuit 1024, and a controller 1025.
- the PCI-E transmitter 1021 is configured to send, by using optical transmission, a first detection pattern generated by the pattern generation circuit 1023 to the PCI-E receiver 1040, so that the PCI-E receiver 1040 receives the After the first detection pattern, the second detection pattern is fed back through the optical transmission;
- the pattern detecting circuit 1024 is configured to detect whether the receiver 1022 receives the second detection pattern fed back by the PCI-E receiving end 1040 through the optical transmission;
- the controller 1025 is configured to: if the detection result of the pattern detection circuit 1024 is that the receiver 1022 receives the second detection pattern that the PCI-E receiving end 1040 feeds back through the optical transmission, Then determining that the PCI-E receiving end 1040 is in place;
- the first detection pattern and the second detection pattern are both differential signals.
- the PCI-E receiving end 1040 includes: a receiver 1041, a pattern detecting circuit 1042, a pattern generating circuit 1043, a transmitter 1044, and a controller 1045;
- the receiver 1041 is configured to receive a first detection pattern that is sent by the PCI-E transmitting end 1020 by optical transmission;
- the controller 1045 is configured to control the transmitter after the pattern detecting circuit 1042 detects that the receiver 1041 receives the first detection pattern sent by the PCI-E transmitting end 1020 by optical transmission. 1044.
- the second detection pattern generated by the pattern generation circuit 1043 is fed back to the PCI-E transmitting end 1020 by the optical transmission, so that the PCI-E transmitting end 1020 determines the location according to the second detection pattern.
- the PCI-E receiver 1040 is in place.
- the first detection pattern and the second detection pattern are both differential signals.
- the bus system provided in this embodiment sends a first detection pattern to the PCI-E receiving end through optical transmission by the PCI-E transmitting end, so that the PCI-E receiving end receives the first
- the second detection pattern is fed back to the PCI-E transmitting end by the optical transmission; then the PCI-E transmitting end detects whether the second detection by the PCI-E receiving end through the optical transmission feedback is received.
- the PCI-E transmitting end determines that the PCI-E receiving end is in place; and the optical transmission is supported.
- FIG. 11 shows a schematic structural diagram of a bus system according to another embodiment of the present invention. This embodiment is mainly illustrated by the bus system being a PCI-E bus system. A more preferred embodiment based on the embodiment shown in Fig. 10 is provided.
- the bus system includes: a PCI-E transmitter 1020 and a PCI-E receiver 1040.
- the PCI-E transmitting end 1020 includes: a transmitter 1021, a receiver 1022, a pattern generation circuit 1023, a pattern detection circuit 1024, a controller 1025, and a timer 1026.
- the controller 1025 is configured to detect whether the current link state is switched from the detection.
- the static substate to the detection.
- the active substate to the detection.
- the transmitter 1021 is configured to pass the light every predetermined time interval after the controller 1025 detects that the current link machine state is switched from the detection.the stationary substate to the detection.active substate. Transmitting, to the PCI-E receiving end 1040, the first detection pattern generated by the pattern generation circuit 1023; so that the PCI-E receiving end 1040 receives the first detection pattern, and transmits the feedback through the optical transmission. Second detection pattern;
- the timer 1026 is configured to time a predetermined time period after the transmitter 1021 sends the first detection pattern generated by the pattern generation circuit 1023;
- the pattern detecting circuit 1024 is configured to detect, during a predetermined time period counted by the timer 1026, whether the receiver 1022 receives the first feedback by the PCI-E receiving end 1040 through the optical transmission. Second detection pattern.
- the controller 1025 is configured to: if the detection result of the pattern detection circuit 1024 is that the receiver 1022 receives the second detection pattern that the PCI-E receiving end 1040 feeds back through the optical transmission, Then it is determined that the PCI-E receiving end 1040 is in place.
- the controller 1026 is further configured to switch the current link state from the detected active substate to the polling state after determining that the PCI-E receiving end 1040 is in place.
- the first detection pattern generated by the pattern generation circuit 1023 is the same as or different from the second detection pattern received by the receiver 1022, and the frequencies of the first detection pattern and the second detection pattern are Greater than the predetermined frequency threshold.
- the first detection pattern and the second detection pattern are both differential signals.
- the PCI-E receiving end 1040 includes: a receiver 1041, a pattern detecting circuit 1042, a pattern generating circuit 1043, a transmitter 1044, and a controller 1045;
- the receiver 1041 is configured to receive a first detection pattern that is sent by the PCI-E transmitting end 1020 by optical transmission;
- the pattern generation circuit 1043 is configured to generate a second detection pattern that is the same as or different from the first detection pattern received by the receiver.
- the controller 1045 is configured to control the transmitter after the pattern detecting circuit 1042 detects that the receiver 1041 receives the first detection pattern sent by the PCI-E transmitting end 1020 by optical transmission. 1044.
- the second detection pattern generated by the pattern generation circuit 1043 is fed back to the PCI-E transmitting end 1020 by the optical transmission, so that the PCI-E transmitting end 1020 determines the location according to the second detection pattern.
- the PCI-E receiver 1040 is in place.
- the bus system provided in this embodiment sends a first detection pattern to the PCI-E receiving end through optical transmission by the PCI-E transmitting end, so that the PCI-E receiving end receives the first After detecting the pattern, the second detection pattern is fed back to the PCI-E transmitting end by the optical transmission; then the PCI-E transmitting end detects whether the second detection by the PCI-E receiving end through the optical transmission feedback is received.
- FIG. 12 shows a structural block diagram of a bus system according to an embodiment of the present invention. This embodiment is mainly illustrated by the bus system being the PCI-E bus system shown in Fig. 5A or Fig. 5B.
- the bus system includes: a first detection circuit 1220 and a second detection circuit 1240.
- the first detecting circuit 1220 can be integrated in the first optical module or between the first optical module and the PCI-E transmitting end;
- the second detecting circuit 1240 can be integrated in the second optical module or between the second optical module and the PCI-E receiving end.
- the signal can be exchanged between the first detection circuit 1220 and the second detection circuit 1240 by optical transmission.
- the first detecting circuit 1220 includes a signal sending module 1222, a feedback detecting module 1224, and a circuit switching module 1226.
- the signal sending module 1222 is configured to send a first predetermined signal to the second detecting circuit 1240 by optical transmission, so that the second detecting circuit 1240 detects the PCI-E receiving through the electrical connection after receiving the first predetermined signal. Whether the terminal is in position; if it is detected that the PCI-E receiving end is in position, the second predetermined signal is fed back through the optical transmission;
- the feedback detecting module 1224 is configured to detect whether the second predetermined signal that is sent by the second detecting circuit 1240 through the optical transmission is received;
- the circuit switching module 1226 is configured to: if the detection result of the feedback detecting module 1224 is that the second predetermined signal received by the second detecting circuit 1240 is received by the optical transmission, the two terminals on the transmitting end of the PCI-E are sent The capacitor forms an equivalent RC charging circuit, so that the PCI-E transmitting end determines that the PCI-E receiving end is in place according to the equivalent RC charging circuit;
- the first predetermined signal and the second predetermined signal are both differential signals, and the optical transmission can be performed by using two or the other of the optical module and the optical fiber.
- the optical transmission may be performed by using an optical fiber; when the first detecting circuit 1220 is integrated between the first optical module and the PCI-E transmitting end, the optical transmission It can be done with optical modules and optical fibers.
- the "optical fiber” herein includes an optical fiber between the first optical module and the second optical module or a newly added optical fiber.
- the second detecting circuit 1240 includes a signal receiving module 1242, a presence detecting module 1244 and a signal feedback module 1246.
- the signal receiving module 1242 is configured to receive a first predetermined signal that is sent by the first detecting circuit 1220 by optical transmission;
- the in-position detecting module 1244 is configured to detect, by the electrical connection, whether the PCI-E receiving end is in position after the signal receiving module 1244 receives the first predetermined signal;
- the signal feedback module 1246 is configured to: if the in-position detecting module 1244 detects that the PCI-E receiving end is in position, feed back a second predetermined signal by using the optical transmission, so that the first detecting circuit 1220 is turned off. Switching to the on state, the resistor network forms an equivalent RC charging circuit with the capacitors on the two terminals of the PCI-E transmitting end, so that the PCI-E transmitting end detects the PCI-E receiving according to the equivalent RC charging circuit. The end is in place.
- the optical transmission may be performed by using an optical fiber; when the second detecting circuit 1240 is integrated between the second optical module and the PCI-E receiving end, the optical transmission It can be done with optical modules and optical fibers.
- the "optical fiber” herein includes an optical fiber between the first optical module and the second optical module or an newly added optical fiber.
- the bus system provided in this embodiment implements PCI-E receiving end detection by electrically connecting the second detecting circuit and the PCI-E receiving end, and the second detecting circuit and the first detecting circuit transmit each other through optical transmission.
- the communication, and the resistor network in the first detecting circuit form an equivalent RC charging circuit with the capacitor on the two terminals of the PCI-E transmitting end, so that the PCI-E transmitting end detects that the PCI-E receiving end is in place;
- the problem of receiving end detection cannot be realized by the conventional method; the effect of receiving end detection can also be realized in the PCI-E bus supporting optical transmission.
- FIG. 13 is a structural block diagram of a bus system according to another embodiment of the present invention.
- the bus system is mainly illustrated by the bus system being the PCI-E bus system shown in Fig. 5A or Fig. 5B. A more preferred embodiment is provided based on the embodiment shown in FIG.
- the bus system includes: a first detection circuit 1220 and a second detection circuit 1240.
- the first detecting circuit 1220 can be integrated in the first optical module or between the first optical module and the PCI-E transmitting end;
- the second detecting circuit 1240 can be integrated in the second optical module or between the second optical module and the PCI-E receiving end.
- the signal can be exchanged between the first detecting circuit 1220 and the second detecting circuit 1240 by optical transmission.
- the first detecting circuit 1220 includes a transmitting end detecting module 1221, a signal sending module 1222, a feedback detecting module 1224, and a circuit switching module 1226.
- the transmitting end detecting module 1221 is configured to detect, by using an electrical connection, whether the PCI-E transmitting end is performing PCI-E receiving end detection. Specifically, the sending end detecting module 1221 is specifically configured to detect whether a differential signal amplitude output by two terminals of the PCI-E transmitting end is less than a first threshold, and whether a common mode voltage output by the two terminals is There is a positive transition in the predetermined time period that is greater than the second threshold.
- the signal sending module 1222 is configured to: if the sending end detecting module 1221 detects that the PCI-E transmitting end is performing PCI-E receiving end detection, sending the first to the second detecting circuit 1240 by using the optical transmission a predetermined signal; the second detecting circuit 1240, after receiving the first predetermined signal, detecting whether the PCI-E receiving end is in position through an electrical connection; if detecting that the PCI-E receiving end is in place, Transmitting, by the optical transmission, a second predetermined signal;
- the feedback detecting module 1224 is configured to detect whether a second predetermined signal that is sent by the second detecting circuit 1240 through the optical transmission is received;
- the circuit switching module 1226 is configured to: if the detection result of the feedback detecting module 1224 is that the second predetermined signal received by the second detecting circuit 1240 is received by the optical transmission, the two terminals on the transmitting end of the PCI-E are sent The capacitor forms an equivalent RC charging circuit such that the PCI-E transmitting end determines that the PCI-E receiving end is in place according to the equivalent RC charging circuit.
- the circuit switching module 1226 is further configured to: after a predetermined period of time from when the resistance network is switched from the off state to the on state, the resistor network connected to the two terminals of the PCI-E transmitting end 1240 is guided. The pass state is switched back to the off state.
- the first predetermined signal and the second predetermined signal are both differential signals, and the optical transmission can be performed by using two or the other of the optical module and the optical fiber.
- the optical transmission may be performed by using an optical fiber;
- the light Transmission includes optical modules and fiber optics.
- the "fiber” here can be made by using the fiber between the first optical module and the second optical module or the newly added optical fiber.
- the second detecting circuit 1240 includes a signal receiving module 1242, a presence detecting module 1244 and a signal feedback module 1246.
- the signal receiving module 1242 is configured to receive a first predetermined signal that is sent by the first detecting circuit 1220 by optical transmission;
- the in-position detecting module 1244 is configured to detect, by the electrical connection, whether the PCI-E receiving end is in position after the signal receiving module 1244 receives the first predetermined signal.
- the in-position detecting module 1244 includes: a common mode transmitting unit 1244a and a time detecting unit 1244b;
- the common mode transmitting unit 1244a is configured to send a common mode voltage by using two terminals connected to the PCI-E receiving end, where the common mode voltage is greater than an initial voltage;
- the time detecting unit 1244b is configured to detect whether a time required for the voltage of the two terminals connected to the PCI-E receiving end to rise from the initial voltage to the common mode voltage sent by the common mode transmitting unit 1244a is Greater than a predetermined threshold.
- the signal feedback module 1246 is configured to: if the in-position detecting module 1244 detects that the PCI-E receiving end is in position, feed back a second predetermined signal by using the optical transmission, so that the first detecting circuit 1220 is configured according to the a second predetermined signal, determining a resistance network to be connected to the two terminals of the PCI-E transmitting end Switching from the off state to the on state, the resistor network forms an equivalent RC charging circuit with the capacitors on the two terminals of the PCI-E transmitting end, so that the PCI-E transmitting end detects the according to the equivalent RC charging circuit The PCI-E receiver is in place.
- the optical transmission may be performed by using an optical fiber; when the second detecting circuit 1240 is integrated between the second optical module and the PCI-E receiving end, the light Transmission can be performed using optical modules and optical fibers.
- the "optical fiber” herein includes an optical fiber between the first optical module and the second optical module or an newly added optical fiber.
- the bus system implemented in this embodiment implements PCI-E receiving end detection by electrically connecting the second detecting circuit and the PCI-E receiving end, and the second detecting circuit and the first detecting circuit transmit each other through optical transmission.
- the communication, and the resistor network in the first detecting circuit form an equivalent RC charging circuit with the capacitor on the two terminals of the PCI-E transmitting end, so that the PCI-E transmitting end detects that the PCI-E receiving end is in place;
- the problem of receiving end detection cannot be realized by the conventional method; the effect of receiving end detection can also be realized in the PCI-E bus supporting optical transmission.
- the first detecting circuit also triggers the subsequent step when detecting that the transmitting end is performing the receiving end detection, and can be most compatible with the existing detecting mechanism.
- FIG. 14 is a schematic structural diagram of a bus system according to an embodiment of the present invention. This embodiment is mainly illustrated by the bus system being the PCI-E bus system shown in Fig. 5A or Fig. 5B.
- the bus system includes a transmitting terminal 1420, a first detecting circuit 1440, a second detecting circuit 1460, and a receiving end 1480.
- the first detecting circuit 1440 can be integrated in the first optical module or between the first optical module and the PCI-E transmitting end 1420;
- the second detecting circuit 1460 can be integrated in the second optical module or between the second optical module and the PCI-E receiving end 1480.
- Signals can be exchanged between the first detection circuit 1440 and the second detection circuit 1460 by optical transmission.
- the first detecting circuit 1440 includes: a transmitter 1442, a receiver 1444, a controller 1446, and a resistor network 1448;
- the transmitter 1442 is configured to send a first predetermined signal to the second detecting circuit 1460 by optical transmission, so that the second detecting circuit 1460 detects the PCI-E by electrical connection after receiving the first predetermined signal. Whether the receiving end 1480 is in position; if it is detected that the PCI-E receiving end is in place, then Transmitting, by the optical transmission, a second predetermined signal;
- the controller 1446 is configured to detect whether the receiver 1444 receives the second predetermined signal that the second detection circuit 1460 feeds back through the optical transmission;
- the controller 1446 is further configured to: if the detection result is that the receiver 1444 receives the second predetermined signal that the second detection circuit feeds back through the optical transmission, then the two of the PCI-E transmitting end 1420
- the resistor networks respectively connected to the terminals are switched from the off state to the on state, so that the resistors on the two terminals of the resistor network 1448 and the PCI-E transmitter 1420 form an equivalent RC charging circuit, so that the PCI-E transmitter 1420 determines that the PCI-E receiver 1480 is in place based on the equivalent RC charging circuit.
- the first predetermined signal and the second predetermined signal are both differential signals, and the optical transmission can be performed by using two or the other of the optical module and the optical fiber.
- the optical transmission may be performed by using an optical fiber;
- the first detecting circuit 1420 is integrated between the first optical module and the PCI-E transmitting end, the light Transmission can be performed using optical modules and optical fibers.
- the "optical fiber” herein includes an optical fiber between the first optical module and the second optical module or an newly added optical fiber.
- the second detecting circuit 1460 includes: a receiver 1462, a receiving end detecting circuit 1464, a controller 1466, and a transmitter 1468;
- the receiver 1462 is configured to receive a first predetermined signal that is sent by the first detecting circuit 1440 by optical transmission;
- the receiving end detecting circuit 1464 is configured to detect, after the receiver 1462 receives the first predetermined signal, whether the PCI-E receiving end 1480 is in position through an electrical connection;
- the controller 1466 is configured to, if the receiving end detecting circuit 1464 detects that the PCI-E receiving end 1480 is in position, control the transmitter 1468 to feed back a second predetermined signal by using the optical transmission, so that the The first detecting circuit 1440 determines, according to the second predetermined signal, that the resistor network respectively connected to the two terminals of the PCI-E transmitting end 1420 is switched from the off state to the on state, so that the resistor network 1448 and the PCI-E are sent.
- the capacitance on the two terminals of terminal 1420 forms an equivalent RC charging circuit such that the PCI-E transmitting terminal 1420 determines that the receiving terminal 1480 is in place based on the equivalent RC charging circuit.
- the optical transmission may be performed by using an optical fiber; when the second detecting circuit 1440 is integrated between the second optical module and the PCI-E receiving end, the light Transmission can be performed using optical modules and optical fibers.
- the "fiber” here includes the first optical module and The optical fiber between the second optical modules or the newly added optical fiber.
- the bus system provided in this embodiment implements PCI-E receiving end detection by electrically connecting the second detecting circuit and the PCI-E receiving end, and the second detecting circuit and the first detecting circuit transmit each other through optical transmission.
- the communication, and the resistor network in the first detecting circuit form an equivalent RC charging circuit with the capacitor on the two terminals of the PCI-E transmitting end, so that the PCI-E transmitting end detects that the PCI-E receiving end is in place;
- the problem of receiving end detection cannot be realized by the conventional method; the effect of receiving end detection can also be realized in the PCI-E bus supporting optical transmission.
- FIG. 15 is a schematic structural diagram of a bus system according to another embodiment of the present invention.
- the bus system is mainly illustrated by the bus system being the PCI-E bus system shown in Fig. 5A or Fig. 5B.
- the bus system includes: a transmitting terminal 1420, a first detecting circuit 1440, a second detecting circuit 1460, and a receiving end 1480.
- the first detecting circuit 1440 can be integrated in the first optical module or between the first optical module and the PCI-E transmitting end 1420;
- the second detecting circuit 1460 can be integrated in the second optical module or between the second optical module and the PCI-E receiving end 1480.
- Optical transmission may be utilized between the first detection circuit 1440 and the second detection circuit 1460 to exchange signals.
- the first detecting circuit 1440 includes: a state identifying circuit 1441, a transmitter 1442, a receiver 1444, a controller 1446, a resistor network 1448, and a timer 1449;
- the state identification circuit 1441 is configured to detect, by the electrical connection, whether the PCI-E transmitting end 1420 is performing the receiving end detection. Specifically, the state identification circuit 1441 is configured to detect whether a differential signal amplitude output by the two terminals of the PCI-E transmitting end 1420 is less than a first threshold, and whether a common mode voltage output by the two terminals is There is a positive transition in the predetermined time period that is greater than the second threshold.
- the transmitter 1442 is configured to: when the sending end detecting circuit 1441 detects that the PCI-E transmitting end 1420 is performing the PCI-E receiving end detection, transmitting the optical detection to the second detecting circuit
- the first predetermined signal is sent by the 1460, so that the second detecting circuit 1460 detects, by the electrical connection, whether the PCI-E receiving end 1480 is in position after receiving the first predetermined signal; if the PCI- is detected The E receiving end is in position, and the second predetermined signal is fed back through the optical transmission;
- the controller 1446 is configured to detect whether the receiver 1444 receives the second predetermined signal that the second detecting circuit 1460 feeds back through the optical transmission; The controller 1446 is further configured to: if the detection result is that the receiver 1444 receives the second predetermined signal fed by the second detection circuit 1460 through the optical transmission, then the two will be combined with the PCI-E transmitting end 1420.
- the resistor networks 1448 respectively connected to the terminals are switched from the off state to the on state, so that the resistors on the two terminals of the resistor network 1448 and the PCI-E transmitter 1420 form an equivalent RC charging circuit, so that the PCI-E
- the transmitting end 1420 determines that the PCI-E receiving end 1480 is in position according to the equivalent RC charging circuit.
- the timer 1449 is configured to time a predetermined time period after the controller 1446 switches the resistance network respectively connected to the two terminals of the PCI-E transmitting end 1420 from the off state to the on state; 1446. Also used for a predetermined period of time after the timer 1449 is timed, the state will be turned off.
- the first predetermined signal and the second predetermined signal are both differential signals, and the optical transmission can be performed by using two or the other of the optical module and the optical fiber.
- the optical transmission may be performed by using an optical fiber;
- the first detecting circuit 1420 is integrated between the first optical module and the PCI-E transmitting end, the light Transmission can be performed using optical modules and optical fibers.
- the "optical fiber” herein includes an optical fiber between the first optical module and the second optical module or an newly added optical fiber.
- the second detecting circuit 1460 includes: a receiver 1462, a receiving end detecting circuit 1464, a controller 1466, and a transmitter 1468;
- the receiver 1462 is configured to receive a first predetermined signal sent by the first detecting circuit 1440.
- the receiving end detecting circuit 1464 is configured to detect the receiving end after the receiver 1462 receives the first predetermined signal. Whether 1480 is in place.
- the receiving end detecting circuit 1464 includes: a common mode transmitting sub-circuit 1464a and a time detecting sub-circuit 1464b;
- the common mode transmitting sub-circuit 1464a is configured to send a common mode voltage by using two terminals connected to the receiving end 1480, where the common mode voltage is greater than an initial voltage;
- the time detecting sub-circuit 1464b is configured to detect whether the voltage required to increase the voltage of the two terminals connected to the receiving end 1480 from the initial voltage to the common mode voltage sent by the common mode transmitting sub-circuit 1464a is Greater than a predetermined threshold.
- the controller 1466 is configured to control the transmitter 1468 to feed back a second predetermined signal if the receiving end detecting circuit 1464 detects that the receiving end 1480 is in position, so that the first detecting circuit 1440 detects whether to receive Go to the second predetermined signal; if the detection result is that the second pre-reception is received
- the resistor network 1448 connected to the two terminals of the transmitting end 1420 is switched from the off state to the on state, so that the capacitors on the two terminals of the resistor network 1448 and the transmitting end 1420 form an equivalent RC charge.
- a circuit such that the transmitting end 1420 detects that the receiving end 1480 is in position according to the equivalent RC charging circuit.
- the optical transmission may be performed by using an optical fiber; when the second detecting circuit 1440 is integrated between the second optical module and the PCI-E receiving end, the light Transmission can be performed using optical modules and optical fibers.
- the "optical fiber” herein includes an optical fiber between the first optical module and the second optical module or an newly added optical fiber.
- the bus system implemented in this embodiment implements PCI-E receiving end detection by electrically connecting the second detecting circuit and the PCI-E receiving end, and the second detecting circuit and the first detecting circuit transmit each other through optical transmission.
- the communication, and the resistor network in the first detecting circuit form an equivalent RC charging circuit with the capacitor on the two terminals of the PCI-E transmitting end, so that the PCI-E transmitting end detects that the PCI-E receiving end is in place;
- the problem of receiving end detection cannot be realized by the conventional method; the effect of receiving end detection can also be realized in the PCI-E bus supporting optical transmission.
- the first detecting circuit also triggers the subsequent step when detecting that the transmitting end is performing the receiving end detection, and can be most compatible with the existing detecting mechanism. It should be further noted that in the implementation scenario in which the first detection circuit and the second detection circuit are integrated in the optical module, since the optical fiber communication is bidirectional, the two ends of the communication can be the transmitting end and the receiving end, so usually every The first detection circuit and the second detection circuit are integrated in each of the optical modules. Please refer to the following examples for details.
- FIG. 16 is a schematic structural diagram of an optical module according to another embodiment of the present invention.
- the optical module may be a first optical module or a second optical module, and the optical module is integrated with a first detecting circuit and a second detecting circuit.
- the optical module includes:
- the amplifier 166 may be a TIA/LA (Trans-impedance amplifier/Limiting amplifier).
- the photodiode array 167 may be a PIN Array (Photodiode Array).
- the laser emission driver 168 may be a VCSEL Driver (Vertical Cavity Surface Emitting Laser Driver). Array, vertical cavity surface emitting laser array).
- the integrated first detection circuit portion is used when the optical module is used as an optical module connected to the PCI-E transmitting end.
- the state identifying circuit 163 is equivalent to the state identifying circuit 1421 in the previous embodiment; the laser emitting driver 168 and the laser array 169 are equivalent to the transmitter 1442 in the previous embodiment; the amplifier 166 and the photodiode array 167 are equivalent to The receiver 1444 in an embodiment; the controller 164 is equivalent to the controller 1446 in the previous embodiment; the resistor network 165 is equivalent to the resistor network 1448 in the previous embodiment; the timer 164 is equivalent to the previous embodiment. Timer 1449. For the specific process, reference may be made to the previous embodiment.
- the optical module when used as an optical module connected to the PCI-E receiving end, an integrated second detecting circuit portion is used.
- the amplifier 166 and the photodiode array 167 are equivalent to the receiver 1462 in the previous embodiment; the receiving end detecting circuit 161 is equivalent to the receiving end detecting circuit 1464 in the previous embodiment; the controller 164 is equivalent to the previous embodiment.
- the controller 1466; the laser emission driver 168 and the laser array 169 are equivalent to the transmitter 1468 in the previous embodiment.
- the optical module provided in this embodiment is integrated with the first detecting circuit and the second detecting circuit provided by the foregoing embodiment; and solved in the PCI-E bus supporting optical transmission, cannot be implemented by using a traditional method.
- the problem detected by the receiving end; the effect of the receiving end detection can also be achieved in the PCI-E bus supporting optical transmission.
- the first detection circuit also triggers the subsequent step when it detects that the transmitting end is performing the receiving end detection, and can be most compatible with the existing detection mechanism.
- a person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium.
- the storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.
- the above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., which are within the spirit and scope of the present invention, should be included in the protection of the present invention. Within the scope.
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Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015549931A JP6122509B2 (ja) | 2012-12-31 | 2012-12-31 | 受信端を検出する方法、検出回路、光モジュール及びシステム |
CN201280003265.6A CN103392303B (zh) | 2012-12-31 | 2012-12-31 | 接收端检测方法、检测电路、光模块及系统 |
EP12891165.8A EP2840725B1 (en) | 2012-12-31 | 2012-12-31 | Receiving end detection method, detection circuit, optical module and system |
PCT/CN2012/087967 WO2014101158A1 (zh) | 2012-12-31 | 2012-12-31 | 接收端检测方法、检测电路、光模块及系统 |
US14/585,476 US20150120973A1 (en) | 2012-12-31 | 2014-12-30 | Method for detecting receive end, detection circuit, optical module, and system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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PCT/CN2012/087967 WO2014101158A1 (zh) | 2012-12-31 | 2012-12-31 | 接收端检测方法、检测电路、光模块及系统 |
Related Child Applications (1)
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US14/585,476 Continuation US20150120973A1 (en) | 2012-12-31 | 2014-12-30 | Method for detecting receive end, detection circuit, optical module, and system |
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WO2014101158A1 true WO2014101158A1 (zh) | 2014-07-03 |
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PCT/CN2012/087967 WO2014101158A1 (zh) | 2012-12-31 | 2012-12-31 | 接收端检测方法、检测电路、光模块及系统 |
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US (1) | US20150120973A1 (zh) |
EP (1) | EP2840725B1 (zh) |
JP (1) | JP6122509B2 (zh) |
CN (1) | CN103392303B (zh) |
WO (1) | WO2014101158A1 (zh) |
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CN108234262A (zh) * | 2017-12-28 | 2018-06-29 | 中国电子科技集团公司第三十研究所 | 一种基于光纤传输的数据总线延长装置及方法 |
CN114520691A (zh) * | 2020-11-20 | 2022-05-20 | 广东海信宽带科技有限公司 | 一种光模块 |
TWI813144B (zh) * | 2022-01-25 | 2023-08-21 | 瑞昱半導體股份有限公司 | 接收器偵測系統與接收器偵測裝置 |
CN116527128B (zh) * | 2023-06-28 | 2023-09-22 | 苏州浪潮智能科技有限公司 | PCIe光互连链路建立方法、装置、设备、介质及系统 |
CN116561035B (zh) * | 2023-07-07 | 2023-10-31 | 西安智多晶微电子有限公司 | Fpga与mipi双向通信的方法、装置及电子设备 |
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CN101882956A (zh) * | 2010-07-08 | 2010-11-10 | 威盛电子股份有限公司 | 数据传输系统和方法 |
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CN100382064C (zh) * | 2005-12-19 | 2008-04-16 | 威盛电子股份有限公司 | 状态协调方法 |
JP5252292B2 (ja) * | 2006-11-01 | 2013-07-31 | 株式会社グラフィン | インタフェース装置及び電子装置 |
US8098993B2 (en) * | 2008-05-08 | 2012-01-17 | Alpenio, Inc. | Method and apparatus for transporting computer bus protocols over an optical link |
US20110013905A1 (en) * | 2009-07-17 | 2011-01-20 | Avago Technologies Fiber Ip (Singapore) Pte. Ltd. | Active optical cable apparatus and method for detecting optical fiber breakage |
JP5771927B2 (ja) * | 2010-09-15 | 2015-09-02 | 株式会社リコー | 通信装置、通信ユニット、通信システム、通信方法およびプログラム |
CN101977082B (zh) * | 2010-10-28 | 2015-04-29 | 长芯盛(武汉)科技有限公司 | 光收发模块、光传输装置及光传输方法 |
-
2012
- 2012-12-31 WO PCT/CN2012/087967 patent/WO2014101158A1/zh active Application Filing
- 2012-12-31 JP JP2015549931A patent/JP6122509B2/ja active Active
- 2012-12-31 CN CN201280003265.6A patent/CN103392303B/zh active Active
- 2012-12-31 EP EP12891165.8A patent/EP2840725B1/en active Active
-
2014
- 2014-12-30 US US14/585,476 patent/US20150120973A1/en not_active Abandoned
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US20050105861A1 (en) * | 2003-11-18 | 2005-05-19 | Broadcom Corporation | Apparatus and method of signal detection in an optical transceiver |
US20060285803A1 (en) * | 2005-06-20 | 2006-12-21 | Crews Darren S | Method, apparatus, and system for using an optical link with electrical link receiver detection |
CN101887151A (zh) * | 2010-04-19 | 2010-11-17 | 威盛电子股份有限公司 | 光收发模块及系统和光收发方法 |
CN101882956A (zh) * | 2010-07-08 | 2010-11-10 | 威盛电子股份有限公司 | 数据传输系统和方法 |
Also Published As
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JP6122509B2 (ja) | 2017-04-26 |
EP2840725A1 (en) | 2015-02-25 |
US20150120973A1 (en) | 2015-04-30 |
JP2016503210A (ja) | 2016-02-01 |
CN103392303B (zh) | 2015-03-11 |
EP2840725A4 (en) | 2015-08-26 |
EP2840725B1 (en) | 2017-06-14 |
CN103392303A (zh) | 2013-11-13 |
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