WO2014101122A1

WO2014101122A1 - Static random storage unit having radiation reinforcement design

Info

Publication number: WO2014101122A1
Application number: PCT/CN2012/087868
Authority: WO
Inventors: 吴利华; 于芳
Original assignee: 中国科学院微电子研究所
Priority date: 2012-12-28
Filing date: 2012-12-28
Publication date: 2014-07-03

Abstract

Disclosed is a static random storage unit having a radiation reinforcement design, comprising: a first access NMOS transistor, a first differential serial-voltage switch logic unit, a second differential serial-voltage switch logic unit, and a second access NMOS transistor all sequentially connected; the first differential serial-voltage switch logic unit and the second differential serial-voltage switch logic unit form a crosswise coupled latch; the latch is connected between a positive power supply voltage (VCC) and a power supply ground (GND); the gate terminal of the first access NMOS transistor is connected to a word line, and the source terminal or drain terminal is connected to a bit line; and the gate terminal of the second access NMOS transistor is connected to the word line, and the source terminal or drain terminal is inversely connected to the bit line. The present invention, while improving the irradiation-resistance performance of a static random storage unit, can effectively reduce the footprint caused by the radiation reinforcement design, thus reducing the footprint by 7% compared to a static random storage unit having a DICE radiation reinforcement design.

Description

A static random storage unit designed by radiation plus S

Department:! And water according to the data storage, a semiconductor memory is divided into dynamic random access memory (: a DRAM), a nonvolatile memory and static random access memory (SRAIVf) _s SRAM ······ species can be simple and low power. The consumption method achieves fast operation speed, and compared with DRAM, S:RAM does not need to periodically refresh the stored information, so design and manufacture are relatively easy, so S:RAM is widely used in the field of data storage. However, in space, aerospace and other applications, a large number of static random access memory data in the SRAM is lost, thereby destroying the normal operation of the SRAM, and as the size of the integrated feature circuit is continuously reduced, the radiation effect is on the static random storage unit. The impact is aggravated to meet the special needs of space, aerospace and other applications, and the design of the SAR is becoming more and more important.

It is known that the conventional static random access memory 7 is 6 tube single 7 , as shown in FIG. 1 , the 6 tube unit includes: first and second driving NMOS transistors 310 , 320 , first and second load PMOS transistors 315 , 325 The first driving transistor 310 and the first load PMOS transistor 3ί5 constitute a first inverter 3i, and the second driving NMOS transistor 320 and the second load PMOS transistor 325 constitute a second inverter 32, the first inverter output The two inverter inputs are connected, and the second inverter output is connected to the first inverter input, thereby forming a cross-coupled latch connected to the iE power supply ffi (VCC) and the power ground ( Between GND); two access NMOS transistors 340, 341 whose drains are respectively connected to the first inverter output 312 and the second inverter output 322, the sources of which are opposite to the bit line 30 - and the bit line respectively 302 is connected, and its drain is connected to word line 330. When reading/writing a 6-tube Panyuan, the word line is turned 330 Switch to high voltage, two pairs of complementary bit lines read/write data

The traditional 6-tube unit is affected by the Ding radiation effect in the radiation environment, especially when the climbing event occurs, if the latch's storage node transiently flips, it may cause the latch data. Flipping, resulting in data errors

As shown in FIG. 2, FIG. 2 is a static random access memory unit of a radiation-enhanced design of a DICE structure, comprising: four PMOS transistors, different inverters for inputting a tube, an inverter 41, a second inverter 42, The third inverter 43, the fourth inverter 44, the first inverter includes a driving N. MOS transistor 410 and a load PMOS transistor 415, and the second inverter includes a driving N. OS tube 420 and The load PMOS transistor 425, the third inverter includes a 'drive NMOS transistor 430 and a load PMOS transistor 435, and the fourth inverter includes a driving NMOS transistor 440 and a 'load PMOS transistor 445, and the four inverted outputs 412 As shown in FIG. 2, 413, 414, and 415 are respectively connected to the PMOS transistor and the NMOS transistor input of the corresponding inverter, thereby forming a set of latches including four storage nodes; The transistors 440, 441, 442, 443 have drains connected to the first inverter output 412, the second inverter output 4, 3, the third inverter output 414, and the second inverter output 41 5 Connected, its source is opposite to bit line 401, bit line anti-402, bit line 40], bit line anti-40 2 connections, the gates of which are connected to the word line 430 compared with the conventional 6-tube unit, which adds a set of (2) redundant latch points to form a 4-node redundant latch, thereby enhancing The stability of the memory cell, thus showing better anti-clamping performance, but its area is twice that of the traditional six-tube unit, which will greatly limit the size of the memory.

Summary of the invention

a) technical problems to be solved

In view of this, the main object of the present invention is to provide a static random storage unit with radiation reinforcement design, which can effectively reduce the area consumption caused by the radiant reinforcement design while improving the anti-irradiation performance of the static random storage unit.

(ii) Technical solutions

In order to achieve the above, the present invention provides a static random storage design of a radiant reinforcement design. Panyang, the static random access memory unit includes a first access NM.OS transistor Ϊ03. of the first connection, a first differential series i 辑单元 unit 1, a second chord series electric E switch logic unit 2 and a second Accessing the NMOS transistor 203, wherein: the first differential series voltage switching logic unit 1 and the second differential series voltage switching logic unit 2 form a cross-coupled latch, the latch being connected to the positive source voltage VCC and the power supply Between the ground GND; the terminal of the first access NMOS transistor 103 is connected to the word line 102, and the source or drain terminal is connected to the bit line 】0:1; the gate terminal of the second access NMOS transistor 203 Connected to the word line 102, the source or drain terminal is connected to the bit line counter 201.

In the above solution, the first differential series voltage switching logic unit 1 includes a first input FMOS transistor 104 and a second input PMOS transistor! 06. The first load NMOS transistor 105 and the second load NMOS transistor 107, wherein: the source or drain terminal of the first input PMOS transistor 104 is connected to the source or drain terminal of the first load NMOS transistor 1.05 to form a first difference. The first output terminal oiit10 of the series voltage switching logic unit 1; the source terminal or the drain terminal of the second input PMOS transistor 06 is connected to the source terminal or the drain terminal of the second load NMOS transistor 107 to constitute a first differential series voltage The second output terminal outi of the first input PMOS transistor 04 is the first input terminal 1⁄210 of the first differential series voltage switching logic unit 1; the first: the shed of the input PMOS transistor 106 ^: the first end The second input terminal m.l of the differential series voltage is connected to the logic unit.

In the above solution, the gate of the first load NMOS transistor 105 is connected to the second output terminal out II of the first differential series voltage logic logic block 7t, and the gate terminal of the second load NM.OS transistor 107 is terminated. a first output terminal out 10 of a differential voltage-coupled voltage switch logic, in the above solution, the second differential series voltage switch logic switch 2 includes a second input PMDS transistor 204 and a fourth input PMDS transistor 206. The third load NMOS transistor 205 and the fourth load NMOS transistor 207, wherein: the source or drain terminal of the third input PMOS transistor 204 is connected to the source or drain terminal of the load NMOS transistor 205, and constitutes the first The first output out20 of the second differential series voltage switching logic unit 2; the source or drain terminal of the fourth 'input PMOS transistor 206 is connected to the source or drain terminal of the fourth load NMOS transistor 207 to form a second differential series voltage switch The second output oui21 of the logic cell 2; the gate terminal of the second input PMOS transistor 204 is the second quaternary series voltage switching logic unit 2 The first input ra20; the gate of the first valve input PMOS transistor 206 is the second input ίη21 of the second differential series i logic unit 2.

In the above solution, the gate of the third load NMOS transistor 205 is connected to the second output out2 of the second differential series voltage switching logic unit 2, and the gate of the fourth load NMOS transistor 207 is connected to the second differential series voltage switch. Logic single redundant 2's - output ο«ί20 _ο

In the above solution, the first input end 10 of the first differential series J logic unit is connected to the first output oiit20 of the second differential series I logic unit 2, the first The second input terminal in11 of the differential series voltage switching logic singularity is connected to the second output out21 of the second differential series voltage switching logic unit 2, wherein the first differential branching voltage switching logic unit 1 An output terminal out1O is connected to the first input m20 of the second differential series electric ffi logic unit 2, and the second output terminal oiftll and the second difference of the first cover sub-series voltage switch logic unit 1 The second input m21 of the series electrical ffi switching logic unit 2 is connected, whereby the first differential series voltage switching logic unit i and the second differential series voltage switching logic unit 2 form a cross-coupled latch.

In the above solution, the drain or source end of the first access NMOS transistor 103 is connected to the first input terminal ui 0 of the first differential series voltage switch logic climbing element 1, the second access NMOS transistor The drain or source of 203 is coupled to the second input terminal mlJ of the first differential series voltage switching logic unit.

In the above solution, in the static random access memory unit and the array including the plurality of static random access memory cells 7t, the word line 1.02 is perpendicular to the power supply ground.

In the above solution, in the static random access memory list: /£ and in an array including a plurality of the static random access memory cells, the bit line 10 is parallel to the power supply ground.

In the above solution, in the static random access memory unit and the array including the plurality of static random access memory cells, the bit line reverse 201 power ground lines are parallel.

(H) Benefits

It can be seen from the above technical solution that the static random storage Pan Pan designed by the radiation reinforcement of the present invention adopts two differential series 3⁄4 pressure switch logic units to form a latch structure, and the system has an additional 6-tube unit. 2 redundant storage nodes, that is, a total of 4 storage nodes outlO. oiitl l out20 oot2 , any one of which is subject to the other 2 Control of the storage node Therefore, when any one of the storage nodes is flipped in the lifting event, the probability of the other storage nodes being reversed is greatly reduced, and the anti-smashing performance of the static random storage Panyuan can be effectively improved. Furthermore, the static random storage unit of the radiation-twisting design provided by the invention has an area reduced by 17% compared with the static random storage unit of the D CE structure, which can effectively reduce the radiation reinforcement. The area consumed by the design.

The above summary of the present invention has been described in detail by the accompanying drawings in order to clarify the features and advantages of the invention.

闘 1 shows a circuit diagram of a conventional six-tube static random access memory;

Figure 2 shows the circuit enclosure of a static random access memory unit based on a DICE structure.

Figure 3 shows a circuit diagram of a static random access memory cell designed in accordance with an embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION In order to make the objects, technical solutions and advantages of the present invention more hereinafter, an embodiment of the present invention will be described in detail by referring to the accompanying drawings. However, the present invention may be embodied in many different forms and is not limited to the examples given herein, which are provided so that this disclosure will be thorough and complete and will be fully conveyed by those skilled in the art. The idea of the invention.

As shown in FIG. 3, circle 3 shows a circuit diagram of a static random access memory unit of a sinusoidal design according to an embodiment of the present invention, the static random access memory unit including a first access NMOS transistor sequentially connected. a first differential series voltage switching logic unit, a first differential diode voltage switching logic unit 2 and a second access NMOS transistor 203, wherein:

The first differential series ffi logic unit 1 includes a first input PMOS transistor ! 04, a second input transistor 106, a ΊΜ load NMOS transistor .105, a second load NMOS transistor 107; the source or drain terminal of the first input PMOS transistor 104 is connected to the source or drain terminal of the first load NMOS transistor 105 to form a first differential series 幵The first output terminal out1O; the source or drain terminal of the second input transistor 106 is connected to the source terminal or the drain terminal of the second load NMOS transistor 107 to constitute a second output of the differential differential series voltage logic unit The output terminal of the first input PMOS transistor 104 is the first input terminal 10 of the first differential series voltage switching logic unit 1; the gate terminal of the second input PMOS transistor 106 is the first differential series voltage switching logic unit 1 The second input terminal rai1; the first load NMOS transistor]. The gate terminal of the .0, 5 is connected to the second terminal oiitl l of the differential series 3⁄4 voltage switch logic unit 1; the gate terminal of the second load NMOS transistor 107 Connected to the first differential series voltage. The first output terminal out1() of the logic unit 1 is connected.

The source terminal or the drain terminal of the first input PMOS transistor 104 is connected to the source terminal or the drain terminal of the first load NMOS transistor 05 to constitute a first output terminal o «tl of the first differential series voltage switching logic unit 1 0, either the source of the first input PMOS transistor 104 is connected to the source or drain of the first load NMOS transistor 105, or the drain of the first input PMOS transistor 04 and the first load NMOS transistor. The source or drain terminals of 105 are connected. Similarly, the source or drain of the second input PMOS transistor 106 is connected to the source or drain of the ::::: load NMOS transistor 07 to form the first differential series!! When the second output terminal o«t11 of the switching logic hua-yuan 1 is connected, the source terminal of the second input PMOS transistor 106 may be connected to the source terminal or the drain terminal of the second load NMOS transistor 07, or may be: Two input PMOS transistors! The drain terminal of .06 and the source of the second load NMOS transistor 10?, the second differential series voltage switching logic unit 2, comprising a third If-in PMOS transistor 204, - a fourth input PM: OS transistor 206, - The three-load NMOS transistor 205, ... - the fourth load NMOS transistor 207; the second: the source or drain terminal of the input PMOS transistor 204 is connected to the source or drain terminal of the king load NMOS transistor 205 to form a second sub-series The first output oirt.20 of the voltage switching logic unit 2; the source or drain terminal of the fourth input PMOS transistor 206 is connected to the source or drain terminal of the valve load NMOS transistor 207 to form a second differential series electrical switching logic The second output out21 of unit 2; the first input PMOS The gate terminal of the transistor 204 is the first input n20 of the second differential series voltage switching logic unit 2 _; the gate terminal of the fourth input PMOS transistor 206 is the second input 21 of the second differential series voltage switching logic unit 2 _; The second terminal of the load NMOS transistor 205 is connected to the second output out2 of the second differential series circuit 1; the gate of the fourth load NMOS transistor 207 is connected to the second differential series voltage switch logic 7t 2 - Output oirt.20.

When the source or drain terminal of the first input PMOS transistor 204 is connected to the source or drain terminal of the third load NMOS transistor 205 to constitute the first output ouf20 of the second differential series voltage switching logic unit 2, it may be The source terminal of the third input PMOS transistor 204 is connected to the source terminal or the drain terminal of the third load NMOS transistor 205, and may also be the drain terminal of the third input PMOS transistor 204 and the source terminal or the drain terminal of the king load NMOS transistor 205. Connected. Similarly, when the source or drain terminal of the fourth input PMOS transistor 206 is connected to the source or drain terminal of the fourth load NMOS transistor 207 to constitute the second output out2 of the second differential series voltage switching logic unit 2, The source terminal of the fourth input PMOS transistor 206 may be connected to the source or drain terminal of the valve load NM.OS transistor 207, or may be the drain terminal of the fourth input PMOS transistor 206 and the source of the fourth load NMOS transistor 207. End or drain connection

The first input terminal mlO of the first differential series voltage switching logic unit 1 is connected to the first output out20 of the second differential series voltage switching logic unit 2; the second input terminal of the first differential voltage voltage switching logic unit 1 The inll is connected to the second output out2 of the second differential series voltage switching logic element 2; the first output terminal out 0 of the first partial series voltage switching logic unit is 0 and the second differential series voltage switching logic is 7 έ a first input of 2: in20 is connected; a second output terminal l1 of the first differential series 3⁄4 switching logic unit 1 is connected to a second input in21 of the second differential series voltage switching logic unit 2; The voltage-critical logic unit: 1 and the second differential-connected switch logic unit 2 constitute a cross-coupled latch that is connected between the positive supply voltage and the power supply ground.

The first access NMOS transistor 103 has a drain terminal or a source terminal connected to the first input terminal mlO of the differential series voltage switching logic unit: 1, and its gate terminal word line is connected to the 02, and the source terminal or the drain terminal and the bit terminal are connected. Line 〗 0:1 connection.

The second access NMOS transistor 203 has a drain or source connected to the first differential series voltage The second input of the off logic dimension is connected, the » terminal is connected to the word line 102, and the source or drain terminal is connected to the bit line inverse 201.

In the static random access memory 7t and in the array including the plurality of static random access cells, the word line 102 is perpendicular to the power ground, the bit line 101 is parallel to the power ground, and the bit line is opposite 201 is parallel to the power ground.

When the static random access memory cell is "written", the bit line 101 is at a high level, the bit line 201 is at a low level, the word line 102 is at a high level, the first access NMOS transistor 103 and the second access are The NMOS transistor 203 is hiccup, and the high level on the bit line 01 and the low level on the bit line 201 are respectively connected to the first differential series voltage switch logic 1 (the input end mlO and the second) The first output terminal out1O and the second output terminal mt11 of the first differential series voltage switching logic unit 1. respectively obtain a low level and a high level; according to the connection relationship of the static random storage unit, The first input in.20 and the second input m2i of the second differential series voltage switching logic single 7G 2 will respectively obtain a low level and a high level, and the second differential series voltage is connected to the first output out20 and the second output of the logic unit 2 Out21 will respectively obtain a high level and a low level, respectively, coupled with the high level and low level of the first input terminal 0 and the second input terminal iiil l of the first differential series voltage switching logic unit, respectively, statically random Storage unit completion "Gamma] operation; When the word line 102 is low, a first differential electrical series E Jian off logic unit 1 and the second voltage differential serial latch logic unit Jian off structure 2 constitutes, hold write" data.

When the "0" operation is performed on the static random memory memory 7 £, the bit line 01. is low level, the bit line inverse 20] is high level, the word line is 02 high level, and the first access NMOS is The transistor 103 and the second access NMDS transistor 203 are both turned on, and the low level on the bit line 01 and the high level on the bit line reverse 201 are respectively connected to the first input of the first differential series voltage switch logic unit 1. On the terminal in 10 and the second input terminal in 11, the first output oirtlO and the second output terminal οιι 第 of the first differential series ffi switch logic unit 1 respectively obtain a high level and a low level; according to the connection of the static random storage unit Relationship, the ...-input m20 and the second input m21 of the second differential series voltage switching logic unit 2 will respectively obtain a high level and a low level, respectively. The second. differential series power 11: the first output of the logic unit 2 :20 and the first: output out2]. will get low level and high level respectively, and respectively with the first differential series voltage switching logic unit 1 ...- The input terminal mJ O and the second input terminal mJ l are coupled to a low level and a high level, and the static random access memory unit 71 completes writing a “0” operation; when the line 102 is at a low level, the first differential series electric ffi switch The logic unit and the second differential nucleus voltage logic unit 2 constitute a latch structure that keeps the write "(Γ data.

If the static random access memory latch data is "Γ", that is, the second output terminal outl1 of the differential series voltage switching logic unit 1 and the second output terminal otrt20 of the second differential series voltage switching logic unit 2 Is high level, the first ... - output terminal out 10 of the first differential series I switch logic unit and the second output oot2i of the second differential rate connected voltage switch logic unit 2 are low, considered to occur in a radiation environment In the single event event, it is assumed that the 3⁄4 energy particle acts on the -output oirt20 of the second differential series voltage logic unit 2, and the output oirt20 is flipped from the high 3⁄4 level to the low level 3⁄4 level due to the first differential series voltage switch The high level on the first output terminal out1O of the logic unit ί and the low level on the second output terminal otiil are flipped, which will act on the second differential series voltage switching logic unit 2 to restore the second differential series The first output out20 of the voltage switch logic Pan 2 is high.

The static random access memory cell based on the 0.2μο process is subjected to HSPICE single-particle simulation test, and the single-event flip threshold is 160MeVcm ² /mg, while the ICE-based radiation-twisted design is static random. The storage unit Hua. The particle flipping value is only 9MeV: cm ² /mg. The traditional six-tube static random storage unit has a flipping width of only 3MeV; cm ² /mg. Therefore, the static random access memory 7G of the radiant reinforcement design provided by the invention can effectively reduce the area consumption caused by the radiation reinforcement design while improving the anti-shock performance of the static random storage unit. It is to be understood that the foregoing description is only illustrative of the embodiments of the invention, and is not intended to Equivalent substitutions, improvements, etc., are intended to be included within the scope of the present invention.

Claims

Rights request

A static random access memory unit with a radiation-reinforced design, characterized in that the static random access memory unit comprises a first access 'NMOS transistor (1030, first differential series voltage switch logic single 7 ά (1), a second differential series I switch logic unit (2) and a second access NMOS transistor (203), wherein

The first differential series electric 1 switching logic unit (1) and the second differential series electric bipolar switch logic unit 7&(2) form a cross-coupled latch connected to the iE power supply voltage VCC and the power supply ground GND Between

The gate of the first access NMQS transistor (103) is connected to the word line (102.), and the source or drain terminal is connected to the bit line (101);

The gate of the second access NMQS transistor (203) is connected to the word line (102), and the source or drain terminal is connected to the bit line ('201).

2. The static random access memory cell of the radiant reinforcement design according to claim 1, wherein the differential differential series: the switching logic Pan (?) comprises a first input PMDS transistor (:) a second input PMDS transistor (.嶋, a first load NMOS transistor (105) and a second load NMOS ir body transistor (107), wherein:

The ...- input PM.OS transistor (104) source or drain terminal is connected to the source or drain of the - - load NMDS transistor U05) to form the first differential series voltage logic logic. An output (oiitlO);

The source or drain terminal of the second input PMOS transistor (106) is connected to the source or drain terminal of the second load NMOS transistor (10?) to form a second output terminal of the first differential series voltage switching logic unit (outll );

The gate terminal of the first input PMOS transistor (104) is the first input terminal (mlO) of the first differential series E-switch logic unit;

The gate of the second input PMOS transistor (106) is the second input of the first differential differential voltage switching logic unit (ml)

3. The static random access memory cell of the radiant reinforcement design according to claim 2, wherein the gate of the first load NMOS transistor (105) is terminated by a 'differential series connection The second output end (outli:) of the ffi logic unit, the gate of the second load NMOS transistor (107) is connected to the first output of the first differential series electric ffi switch logic unit (οιιϋΟ

4. The radiant-plus-static static random access memory unit of claim 1, wherein the second differential series voltage-off logic unit (2) comprises a third input PMOS transistor (204), a fourth An input PMOS transistor (206), a first load NMOS transistor (205) and a fourth load NMOS transistor (207), wherein:

The source or drain terminal of the third input PMOS transistor (204) is coupled to the source or drain terminal of the ≡ load NMOS transistor (205) to form a first output (out20) of the second differential series voltage switching logic unit _;

The source or drain terminal of the fourth input PMOS transistor ('206) is connected to the source or drain terminal of the fourth load NMDS transistor (207) to form a second output (out21) of the first series-connected I-switch logic unit;

The gate terminal of the third input PMOS transistor (204) is the first input of the second differential series voltage switch logic Pan (m20:);

The gate of the first valve input PMOS transistor (206) is the .::::: differential series voltage, which is the second input of the logic-element (m21:).

5. The static random access climbing device of the radiant reinforcement design according to claim 4, wherein the gate of the third load NMOS transistor (205) is terminated by a second differential series voltage switch logic Two outputs (out21), the fourth load NMOS transistor

Gate termination of (207): The first output of the series voltage switch logic 7 έ (0^20).

The static random access memory-element of the radiant reinforcement design according to claim 2 or 4, wherein the first input terminal (m) 0 of the first differential series voltage switching logic unit is The first output (o 20) of the second differential logic unit is connected to the second input terminal (mil) of the differential differential series switching logic unit and the second differential series 3⁄4 voltage switch a second output (out21) of the logic ramp 7t is connected, the first output terminal (out10) of the differential differential series switching logic unit is connected to the first input (iii20) of the second differential series bipolar switch logic unit The second output terminal (outl 1:) of the first differential series voltage switching logic single is connected to the second input (in2: 〖) of the second differential series voltage switching logic block 73⁄4, thereby The first lotus series voltage switch logic unit (1) And the second. light-separated series voltage switching logic unit (2) constitutes a latch that is cross-coupled.

7. The static random access memory cell designed according to claim 6, wherein a drain terminal or a source terminal of the first access NMOS transistor (103) is connected to the first 3⁄4 minute series voltage. The first input terminal (ώ!0) of the logic transistor is connected, and the drain terminal or the source terminal of the second access NMOS transistor (203) and the differential terminal voltage switching logic unit The second input (mi l ) is connected.

8. The static random access memory unit of the radiant reinforcement design according to claim 1, wherein the word line (102) is perpendicular to the power ground line in the array.

The static random access memory unit of the radiation reinforcement design according to claim 1, wherein in the static random access memory unit and the array including the plurality of static random access memory units, the bit line Π 01 ) Parallel to the power ground.

.1 0. The static random access memory unit of the radiation reinforcement design according to claim, wherein in the array, the bit line is reversed (2ου is parallel to the power ground.