WO2014092465A1

WO2014092465A1 - Method for reducing power consumption of flash memory, and device for same

Info

Publication number: WO2014092465A1
Application number: PCT/KR2013/011502
Authority: WO
Inventors: 박대진
Original assignee: 어보브반도체 주식회사
Priority date: 2012-12-12
Filing date: 2013-12-12
Publication date: 2014-06-19
Also published as: KR20140076220A; KR101419710B1

Abstract

Disclosed is a method for reducing the power consumption of a flash memory, and a device for same. The method for reducing the power consumption of a flash memory, according to an embodiment of the present invention, comprises: a step for receiving a programme code; a step for analyzing the received programme code; a step for calculating the toggle number of a bit value according to a command of the programme code, resulting from the analysis of the programme code; a step for performing a bit conversion on the bit value of the programme code on the basis of the calculated toggle number; and a step for storing the bit converted programme code in a flash memory. Therein, in the calculation step, the toggle number is calculated on the basis of the command execution order of the programme code, and thus when the data stored in the flash memory is being read, the power consumption due to pre-charge generated by toggle can be reduced.

Description

Method and apparatus for reducing power consumption of flash memory

The present invention relates to a reduction in power consumption of a flash memory, and more particularly, in order to minimize the number of toggles in a line connected to a precharge circuit, for example, a bit line, when reading data stored in the flash memory. The present invention relates to a method and apparatus for reducing power consumption of a flash memory capable of reducing power consumed by pre-charge when reading data stored in the flash memory by bit-converting and storing the instructions in the flash memory.

Flash memory is nonvolatile, which means that flash memory stores information on a semiconductor in a manner that does not require power to maintain the information on the chip. Flash memory stores information in an array of transistors called "cells", each of which stores one or more bits of information. Memory cells are based on Floating-Gate Avalanche-Injection Metal Oxide Semiconductor (FAMOS) transistors, which inherently contain CMOS (additional conductors) suspended or floating between gate and source / drain terminals. Complementary Metal Oxide Semiconductor (FET). Current flash memory devices consist of two basic array architectures. Names indicating the type of NOR flash and NAND flash logic are used in the storage cell array.

Flash cells are similar to standard MOSFET transistors except that they have two gates instead of just one gate. One gate is the same as a control gate (CG) in other MOS transistors, and the other is a floating gate (FG) insulated all around by an oxide layer. Since the FG is insulated by its oxide layer, any electrons placed on it are trapped there and thus store information.

When electrons are trapped on the FG, they modify (partially cancel) the electric field from CG, which modifies the threshold voltage (Vt) of the cell. Thus, when a cell is " read " by making CG a specific voltage, current will or will not flow between the cell's source and drain connections depending on the cell's Vt. The presence or absence of such a current can be sensed and converted to '1' or '0', whereby the stored data is reproduced.

Memory cells of memory devices are typically arranged in an array with rows and columns. In general, rows are connected via wordline conductors and rows are connected via bitline conductors. During the data read functions, the bitline conductors are precharged to the selected voltage level.

Precharge circuitry that precharges the bitline conductors requires a large amount of current to saturation, so when reading data from '0' to '1' or '1' on that bitline If a toggle frequently reads '0' frequently occurs, the current consumption increases accordingly, thereby increasing the overall power consumption in order to generate a precharge current.

Therefore, there is a need for a method of reducing power consumption of a flash memory. As a prior art developed to reduce power consumption of a flash memory, Korean Patent No. 10-0464951 entitled "Flash Memory Power Consumption Reduction Device and Method" has been proposed.

The prior art relates to a configuration for storing data in a direction of low power consumption by selectively inverting data stored in a flash memory, and solves a problem in which an operating current increases when a cell of a flash memory is erased to zero. It is to. That is, the prior art is to prevent the increase of the operating current when reading the value of 0 stored in the memory cell, and does not describe any problem with the current consumption of the precharge which can be increased by the toggle. There is a need for a method of reducing current consumption by the precharge circuit generated by the method.

The present invention is derived to solve the problems of the prior art as described above, the power consumption of the flash memory can reduce the power consumption by the pre-charge generated by the toggle when reading the data stored in the flash memory It is an object of the present invention to provide a reduction method and an apparatus thereof.

Specifically, the present invention calculates the number of toggles based on the execution order of the instructions of the program code, determines whether to convert the bit for each instruction to minimize the number of toggles, and after performing the bit conversion of the data for the determined instruction By storing the bit-converted program code in the flash memory, the number of toggles is minimized when reading the program code stored in the flash memory, thereby reducing power consumption by precharge.

In addition, an object of the present invention is to provide a method and apparatus for reducing power consumption of a flash memory that can reduce the total power consumption of a device equipped with a flash memory by reducing the power consumption by precharging when reading the flash memory. do.

In order to achieve the above object, a method of reducing power consumption of a flash memory according to an embodiment of the present invention comprises the steps of receiving a program code; Analyzing the received program code; Calculating a number of toggles of a bit value according to an instruction of the program code by analyzing the program code; Bit converting a bit value of the program code based on the calculated number of toggles; And storing the bit-converted program code in a flash memory.

The calculating may include calculating the number of toggles based on a command execution order of the program code.

The calculating may include generating an access pattern for the program code by analyzing the program code; Obtaining an access flow of the program code using the generated access pattern; And calculating the number of toggles based on the obtained access flow of the program code.

The converting of the bits may include determining whether to convert bits in each data area of the command so that the number of toggles according to the instruction execution order of the program code is minimized; And performing bit conversion on the data area of the command in which the bit conversion is determined.

The storing may store a flag bit for a data area in which the bit conversion is performed.

Furthermore, the method may further include bit converting and reading the program code bit-converted and stored in the flash memory.

The reading may be performed by bit-converting the program code stored in the flash memory using a flag bit stored in advance for a data area in which the bit conversion is performed among the program codes stored in the flash memory.

An apparatus for reducing power consumption of a flash memory according to an embodiment of the present invention may include a receiver configured to receive a program code; An analysis unit for analyzing the received program code; An operation unit configured to calculate a toggle number of bit values according to an instruction of the program code by analyzing the program code; A bit converter configured to bit convert a bit value of the program code based on the calculated number of toggles; And a storage unit which stores the bit-converted program code in a flash memory.

The calculator may calculate the number of toggles based on an instruction execution order of the program code.

The bit converter may determine whether or not to convert the bit in the data area of each instruction so that the number of toggles in accordance with the instruction execution order of the program code is the minimum; And a bit conversion performing unit performing bit conversion on the data area of the command in which the bit conversion is determined.

According to the present invention, when reading the program code stored in the flash memory by calculating the number of toggles based on the execution order of the instructions of the program code, and performing bit conversion for each of the instructions so as to minimize the number of toggles to store in the flash memory The number of toggles can be minimized to reduce power consumption by precharge.

In addition, the present invention can reduce the power consumption of the precharge circuit according to the toggle when reading the flash memory can reduce the overall power consumption of the device equipped with the flash memory.

1 illustrates a configuration of an apparatus for reducing power consumption of a flash memory according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an embodiment of an operation unit shown in FIG. 1.

FIG. 3 is a diagram illustrating another exemplary configuration of the calculator illustrated in FIG. 1.

FIG. 4 illustrates a configuration of an embodiment of the first converter illustrated in FIG. 1.

5 illustrates an example of generating an access pattern according to analysis of program code.

FIG. 6 shows a data access graph (DAG) for the access pattern shown in FIG. 5.

7 illustrates an example of a process of calculating a toggle number of program codes according to an access flow.

FIG. 8 is an exemplary diagram for describing an operation of determining and converting a bit converted data region according to an instruction execution order of a program code.

9 is a flowchart illustrating a method of reducing power consumption of a flash memory according to an embodiment of the present invention.

FIG. 10 illustrates a flowchart of an operation of step S930 illustrated in FIG. 9.

FIG. 11 is a flowchart illustrating another operation of step S930 illustrated in FIG. 9.

FIG. 12 illustrates an operation flowchart of an embodiment of a method of reading the program code stored by FIG. 9.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the term "comprises" and the like is intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features, numbers, steps It is to be understood that the present invention does not exclude in advance the possibility of the presence or the addition of operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, when it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

However, the present invention is not limited or limited by the embodiments. Like reference numerals in the drawings denote like elements.

Hereinafter, a method and apparatus for reducing power consumption of a flash memory according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 12.

Referring to FIG. 1, the apparatus according to the present invention includes a receiver 110, an analyzer 120, a calculator 130, a first converter 140, a storage 150, a flash memory 160, and a second. The converter 170 and the reader 180 are included.

The receiver 110 receives a program code from the outside.

In this case, the receiving unit 110 may receive the program code through an apparatus or a program capable of generating the program code, and also through an external storage means storing the program code.

The analyzer 120 analyzes the program code received by the receiver 110.

Here, the analysis unit 120 may analyze the program code to obtain information about the execution order of the instructions included in the program code.

The calculation unit 130 calculates a toggle number of bit values according to the instruction of the program code, based on the analysis result of the program code of the analysis unit.

That is, the calculation unit 130 calculates the number of toggles in which the bit value changes from '1' to '0' or '0' to '1' under the assumption that the instructions of the program code are stored in the flash memory 160.

At this time, the operation unit 130 may 1) calculate the number of toggles in the order of addresses for instructions sequentially stored in the flash memory 160, and 2) toggle between instructions based on the execution order of the instructions of the program code. The number may be calculated, and 3) the number of toggles of the program code may be calculated based on an access pattern obtained through analysis of the program code.

For example, in the case of 1), the calculator 130 sequentially calculates the number of toggles for the instructions to be sequentially stored in the flash memory 160. For example, the number of toggles may be sequentially calculated, such as the number of toggles between the first and second instructions, the number of toggles between the second and third instructions, and the number of toggles between the third and fourth instructions.

As another example, in case of 2), the operation unit 130 may know the execution order of the instructions according to the analysis result of the program code, and according to the order in which the instructions stored in the flash memory 160 are read according to the execution order of the instructions. The number of toggles may be calculated. At this time, the calculator 130 includes a performance order obtainer 210 and a toggle number calculator 220 as shown in FIG. 2.

The execution order acquisition unit 210 obtains an execution order for instructions of the program code through program code analysis.

Here, the command execution order refers to a connection relationship between the commands, and may mean an execution order by moving to a specific address, repetition, and the like. For example, the execution order acquisition unit 210 may identify the program code forming the loop, and determine the start code and the last code of the loop. If the condition to escape the loop is not satisfied, since the start code of the loop is likely to be executed again after the last code of the loop, the execution order acquisition unit 210 may obtain the execution order in consideration of this point. . Considering the case where the condition to escape the loop is satisfied, the execution order obtaining unit 210 may obtain the execution order in which the higher code of the loop is performed again after the last code of the loop in consideration of a weight or a probability. have.

In addition, the execution order may be obtained in the form of a conditional branch or an unconditional branch (jump, goto, etc.).

The toggle number calculator 220 calculates a toggle number of the program code based on the execution order of the acquired instructions of the program code.

As another example, in case of 3), the operation unit 130 generates an access pattern between variables or operands through analysis of the program code, and access flow of the program code using the generated access pattern. (access flow) and may calculate the number of toggles of the program code based on the acquired access flow of the program code, wherein the operation unit 130 as shown in Figure 3, the pattern generator 310, the flow It includes an acquirer 320 and a toggle number calculator 330.

The pattern generator 310 generates an access pattern for the program code through program code analysis.

For example, as shown in FIG. 5, the pattern generator 310 generates an access pattern 520 of “bdabcbbdeba” through analysis of the received program code 510.

The flow obtainer 320 acquires an access flow of program code using the access pattern 520 generated by the pattern generator 310. Here, the access flow of the program code may be a flow for variables a, b, c, d, and e, or may be a flow between instructions included in the program code.

If necessary, the flow acquirer 320 generates a data access graph DAG as shown in FIG. 6 based on the access pattern generated by the pattern generator 310, and generates the generated data access graph. May be used to obtain an access flow of program code.

Here, the data access graph may include a connection relationship 620 between the variables 610 and the number of times of connection 630, and the number of other variables connected to each of the variables through the data access graph. .

For example, in the case of variable b, it can be seen that there is a connection relationship with all other variables a, c, d, and e, and that the number of times that the variable a, c, and d are connected is twice, and thus the variables of program code We can see that variable b has the greatest effect on the total number of toggles in the program code. As the number of accesses between the variables 610 on the data access graph increases, the relationship between the variables 610 may be strengthened. For example, in FIG. 6, the variable b is associated with the variables a, d, and c twice, and the variable e is associated with the variable e.

The flow acquirer 320 may identify an operation type and an operand from a program code as shown in FIG. 7. The operands extracted from each row of the program code of FIG. 7, that is, the association between variables, can be evaluated using a data access graph as shown in FIG. 6. For example, if it is shown that there is a particularly high association between specific variables on the data access graph, the flow acquisition unit 320, if any one of the specific variables is found in the program code, the other one of the specific variables The program code containing the page can then be predicted to be executed next and the execution order of the program code can be determined.

For example, after analyzing the entire program code, assume that variable b and variable d show a particularly high correlation. The DAG can also identify the leading and trailing variables, and assumes that variable b is accessed with high probability after variable b. In the program code, the code including the variable b can be predicted to be more likely to be executed.

The toggle number calculator 330 calculates the number of toggles when the program code is stored in the flash memory 260 without bit conversion based on the access flow of the program code acquired by the flow acquirer 320.

For example, as shown in FIG. 7, the toggle number calculator 330 may use the access flow based on the data access graph or the access pattern of the program code shown in FIG. 5 or 6 to program code to be stored in the flash memory. ① Number of toggles for data in the area, ① Number of toggles between the last address data in the area and ② First address data in the area, ② Number of toggles in the area, ② Number of toggles between the last address data in the area and ③ First address data in the area By calculating the number of toggles for the data in the area and, the number of toggles when stored in the flash memory 260 without bit conversion is calculated.

In the embodiment of FIG. 2 and the embodiment of FIG. 3, the execution order of the program codes is obtained through different problem solving methods, which are likely to obtain similar conclusions. For example, in a loop that is repeated many times, as the execution is repeated many times, there is a high possibility that the association on the DAG is enhanced for the operations in the loop. In addition, in case of unconditional branching, as the program codes distant from each other are frequently executed, it is highly likely that the relationship between the variables of the corresponding program codes will be strengthened on the DAG.

When the number of toggles of the program code is calculated by the calculator 130, the first converter 140 bit-converts the bit value of the program code based on the number of toggles calculated by the calculator 130.

In this case, the first converter 140 may determine whether or not to convert a bit for each of the instructions included in the program code, and then perform bit conversion on the data area of the command in which the bit conversion is determined.

That is, as shown in FIG. 4, the first transform unit 140 includes a determiner 410 and a transform performer 420.

The determination unit 410 determines whether or not to convert the bit in the data area of each instruction so that the number of toggles for the program code is minimum.

At this time, the determination unit 410 may determine whether or not to convert the bit so that the number of toggles according to the instruction execution order of the program code is the minimum, the bit for the instruction so that the number of toggles of the program code to the minimum based on the access pattern of the program code You can also decide whether to convert.

For example, as illustrated in FIG. 8, instructions of a program code to be stored in the flash memory 160 are stored from address 1 to address 5 of the flash memory 160, and the instruction is executed. Assuming that the largest number of toggles by the second and fourth instructions occurs in sequence, the determining unit 410 converts the bits of the second and fourth instruction data among the instructions so that the number of toggles of the program code is minimum. (bit inversion) That is, the determination unit 410 may minimize the number of toggles of the program code by determining bit conversion of the second command and the fourth command data.

Here, for the address of the flash memory where the instructions are stored, although shown as address 1 to address 5, this is for convenience of description and it should be appreciated that the address of the actual flash memory may be different.

The conversion performer 420 performs bit conversion on the data area of the instruction determined by the determiner 410.

That is, the conversion performing unit 420 performs bit conversion on the data area of the second command and the fourth command determined by the determination unit 410 as shown in the example shown in FIG. 8, thereby converting the bit of the second command. The data 810 and the bit-converted data 820 of the fourth instruction.

As such, the first converter 140 may minimize the total number of toggles of the program code by bit converting the data of the command in which the bit conversion is determined.

The storage unit 150 stores the program code bit-converted by the first converter 140 in the flash memory 160.

At this time, the storage unit 150 may store the flag bits for the data area of the instruction bit-converted by the first converter 140 in a predetermined storage means, where the storage means may be a flash memory, It may be a storage means provided separately.

If necessary, the storage unit 150 may store flag bits for all instructions. In this case, the storage unit 150 stores the bit value '1' of the flag bit for the bit-converted instruction, and does not convert the bit. If the instruction is not used, the bit value '0' of the flag bit can be stored. Of course, this value may be changed depending on circumstances.

The second converter 170 checks the bit-converted data area among the program codes stored in the flash memory 160 and bit-converts the data of the data area.

In this case, the second converter 170 may bit convert the program code stored in the flash memory 160 based on the bit value of the flag bit stored in advance.

For example, as shown in the example illustrated in FIG. 8, the second converter 170 may perform bit-conversion with respect to the second command data 610 and the fourth command data 620 stored in the flash memory. Bit value '1' of the not shown) bit-converts the data of the data area, and for the command stored in the flash memory as the original data, the data of the data area is converted through the bit value '0' of the flag bit of the command. Do not bit convert.

The reading unit 180 reads the program code that is bit converted by the second converter 170, that is, the original program code.

As described above, the apparatus according to the present invention bit-transforms and stores the program code stored in the flash memory such that the number of toggles according to the instructions of the program code is minimized when the program code is stored in the flash memory. This can reduce the power consumption of the flash memory.

Furthermore, the present invention can reduce the power consumption of the flash memory, thereby reducing the overall power consumption of the device equipped with the flash memory.

9, the method according to the present invention receives a program code from the outside, and analyzes the received program code (S910, S920).

Here, the analysis of the program code may be an analysis of the instructions included in the program code, may be an analysis of the binary data of the program code, and may include all the analysis to minimize the number of toggles in the present invention.

Through the analysis of the program code, the toggle number of the bit value according to the instruction of the program code is calculated (S930).

Here, the toggle is a bit line '0' to '1' or a '1' to '0' in the first line of the flash memory connected to the precharge circuit according to the order of execution of the instructions. The number of toggles of the program code means the total number of toggles generated according to the order of execution of the instructions.

In this case, step S930 may calculate the sequential toggle number of the program code in the order of the addresses stored in the flash memory, calculate the number of toggles between the instructions based on the execution order of the instructions of the program code, and analyze the program code. It is also possible to calculate the number of toggles of the program code based on the access pattern obtained through the above, this will be described with reference to FIGS. 10 and 11.

FIG. 10 is a flowchart illustrating an example operation of operation S930 illustrated in FIG. 9, and illustrates a process of calculating a toggle number based on a command execution order.

Referring to FIG. 10, in operation S930, the number of toggles is obtained based on an analysis result of the program code in operation S920, in operation S1010.

Here, the order of execution of the instructions refers to the order of instructions that are performed while the program code is executed, and a specific instruction may be repeatedly executed by the order of execution.

When the instruction execution order is obtained in step S1010, the number of toggles of the program code is calculated based on the obtained instruction execution order (S1020).

That is, the number of toggles for the entire instruction of the program code may be calculated by calculating the number of toggles with the previous instruction and the number of toggles with the subsequent instruction according to the execution order between the instructions.

FIG. 11 is a flowchart illustrating another operation of step S930 illustrated in FIG. 9 and illustrates a process of calculating a toggle number using an access pattern.

Referring to FIG. 11, in the calculating of the number of toggles (S930), an access pattern for the program code is generated by analyzing the program code, and an access flow of the program code is obtained using the generated access pattern (S1110). S1120).

If necessary, a data access graph including a connection relationship between the instructions and the number of connections may be generated using the access pattern of the program code, and the access flow may be obtained using the generated data access graph.

When the access flow of the program code is obtained, the total number of toggles of the program code is calculated based on the obtained access flow (S1130).

Referring back to FIG. 9, when the total number of toggles of the program code is calculated by step S930, it is determined whether or not to convert a bit for each data area of the instruction based on the calculated number of toggles, and whether the bit conversion is determined or not. Performs bit conversion on (S940 and S950).

Here, whether or not to convert the data corresponding to the data area of each instruction may be determined in order to minimize the number of toggles of the program code, and whether or not to convert the bit between the instructions and the number of times each of the instructions, and even between the instructions It may be determined in consideration of the number of connections or repetitions.

If bit conversion is determined for each command and bit conversion is performed on the command for which the bit conversion is determined, the bit-converted program code is stored in the flash memory (S960).

Of course, if there is no instruction to perform bit conversion in step S940, the original program code is stored in the flash memory.

When storing the bit-converted program code in the flash memory, the flag bit of whether or not the bit is converted to the area is stored in the data of each instruction in a predetermined area or a separate storage means of the flash memory (S970).

Here, the flag bit is stored for each instruction, and the bit value of the flag bit has a value of '1' for the instruction in which bit conversion is performed and a value of '0' for an instruction in which bit conversion is not performed. Can be. Of course, the bit value of the flag bit may be interchanged depending on the situation.

Depending on the situation, the step of storing the flag bit (S970) may be performed after the step S940 where bit conversion is determined or may be performed after the step S750 where the bit conversion is performed, and any of the above processes may be performed. It may be performed in parallel with one.

Referring to FIG. 12, when a program code stored in a flash memory is read, a bit value of a flag bit for each data area of an instruction stored in the flash memory is checked (S1210).

By performing bit conversion on the data area of the instruction whose flag bit value is '0', and performing bit conversion on the data area of the instruction whose flag bit value is '1', the bit-converted program code stored in the flash memory. Read (S1220, S1230).

The method of reducing power consumption of a flash memory according to an embodiment of the present invention may be implemented in the form of program instructions that may be executed by various computer means and may be recorded in a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program instructions recorded on the media may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Magneto-optical media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

In the present invention as described above has been described by the specific embodiments, such as specific components and limited embodiments and drawings, but this is provided to help a more general understanding of the present invention, the present invention is not limited to the above embodiments. For those skilled in the art, various modifications and variations are possible from these descriptions.

Therefore, the spirit of the present invention should not be limited to the described embodiments, and all of the equivalents and equivalents of the claims, as well as the following claims, will fall within the scope of the present invention. .

A method and apparatus for reducing power consumption of a flash memory are disclosed. In accordance with another aspect of the present invention, a method of reducing power consumption of a flash memory may include: receiving a program code; Analyzing the received program code; Calculating a number of toggles of a bit value according to an instruction of the program code by analyzing the program code; Bit converting a bit value of the program code based on the calculated number of toggles; And storing the bit-converted program code in a flash memory, wherein the calculating step toggles when reading data stored in the flash memory by calculating the number of toggles based on an instruction execution order of the program code. It is possible to reduce the power consumption due to the pre-charge generated by the.

Claims

Receiving a program code;

Analyzing the received program code;

Calculating a number of toggles of a bit value according to an instruction of the program code by analyzing the program code;

Bit converting a bit value of the program code based on the calculated number of toggles; And

Storing the bit-converted program code in a flash memory

Method of reducing power consumption of the flash memory including a.
The method of claim 1,

The calculating step

And calculating the number of toggles based on an instruction execution order of the program code.
The method of claim 1,

The calculating step

Generating an access pattern for the program code by analyzing the program code;

Obtaining an access flow of the program code using the generated access pattern; And

Calculating the number of toggles based on the obtained access flow of the program code

Method for reducing power consumption of a flash memory comprising a.
The method of claim 1,

The bit conversion step

Determining whether or not to convert a bit in a data area of each instruction so that the number of toggles according to the instruction execution order of the program code is minimized; And

Performing bit conversion on the data area of the instruction in which the bit conversion is determined;

Method for reducing power consumption of a flash memory comprising a.
The method of claim 4, wherein

The storing step

And storing a flag bit for the data area on which the bit conversion has been performed.
The method of claim 1,

Bit converting and reading the program code bit-converted and stored in the flash memory

The method of reducing power consumption of a flash memory further comprising.
The method of claim 6,

The reading step

Reducing power consumption of the flash memory, characterized in that the program code stored in the flash memory is bit-transformed and read using the flag bits stored in advance in the data area of the program code stored in the flash memory. Way.
A computer-readable recording medium in which a program for executing the method of any one of claims 1 to 7 is recorded.
A receiving unit for receiving a program code;

An analysis unit for analyzing the received program code;

An operation unit configured to calculate a toggle number of bit values according to an instruction of the program code by analyzing the program code;

A conversion unit for bit converting the bit value of the program code based on the calculated number of toggles; And

A storage unit for storing the bit-converted program code in a flash memory

Device for reducing power consumption of a flash memory including a.
The method of claim 9,

The calculation unit

And calculating the number of toggles based on an instruction execution order of the program code.
The method of claim 9,

The calculation unit

A pattern generator configured to generate an access pattern for the program code by analyzing the program code;

A flow obtaining unit obtaining an access flow of the program code by using the generated access pattern; And

Toggle number calculator that calculates the number of toggles based on the obtained access flow of the program code

Apparatus for reducing power consumption of a flash memory comprising a.
The method of claim 9,

The conversion unit

A determination unit to determine whether to convert a bit in a data area of each instruction so that the number of toggles according to the instruction execution order of the program code is minimized; And

A conversion execution unit that performs bit conversion on the data area of the instruction in which the bit conversion is determined;

Apparatus for reducing power consumption of a flash memory comprising a.
The method of claim 12,

The storage unit

And a flag bit for the data area on which the bit conversion has been performed is stored in a predetermined storage means.
The method of claim 9,

A read unit for bit-converting the program code stored in the flash memory using a flag bit stored in advance for a data area of the bit-converted program code stored in the flash memory

Apparatus for reducing power consumption of a flash memory further comprising.