KR101419710B1 - Method for reducing power consumption of flash memory and apparatus thereof - Google Patents

Abstract

A method and apparatus for reducing power consumption of a flash memory are disclosed. A method of reducing power consumption of a flash memory according to an embodiment of the present invention includes: receiving program code; Analyzing the received program code; Calculating a number of toggles of a bit value according to an instruction of the program code through analysis of the program code; Bit-converting a bit value of the program code based on the calculated number of toggles; And storing the bit-converted program code in a flash memory, wherein the calculating step calculates the number of toggles based on a command execution order of the program code, so that when reading data stored in the flash memory, The power consumption due to the pre-charge generated by the pre-charge can be reduced.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for reducing power consumption of a flash memory,

The present invention relates to a reduction in power consumption of a flash memory, and more particularly, to a method and apparatus for reducing the power consumption of a flash memory such that the number of toggles in a line connected to a precharge circuit, for example, a bit line, And more particularly, to a method and apparatus for reducing power consumption of a flash memory capable of reducing power consumed by pre-charge when data stored in a flash memory is read by bit-converting an instruction and storing the bit in the flash memory.

The flash memory is non-volatile, meaning that the flash memory stores information on the semiconductor in a manner that does not require power to maintain the information of the chip. The flash memory stores information in an array of transistors called "cells ", each of which stores more than one bit of information. The memory cells are based on Floating-Gate Avalanche-Injection Metal Oxide Semiconductor (FAMOS) transistors and the FAMOS transistors are essentially CMOS (CMOS) transistors with additional conductors suspended or floating between the gate and source / drain terminals Complementary Metal Oxide Semiconductor FET (Field Effect Transistor). Current flash memory devices consist of two basic array architectures. NOR flash and NAND flash logic names are used in storage cell arrays.

The flash cell is similar to a standard MOSFET transistor except that it has two gates instead of just one gate. One gate is like a control gate (CG) in other MOS transistors, and the other gate is a floating gate (FG) in which the periphery is completely isolated by the oxide layer. Since FG is insulated by its oxide layer, any electrons placed thereon are trapped therein and thus store information.

When electrons are trapped on the FG, they modify (partially cancel) the electric field from the CG, which modifies the cell's threshold voltage, Vt. Thus, when the cell is "read" by making the CG certain voltage, current will not flow or flow between the source and drain connections of that cell depending on the Vt of the cell. The presence or absence of this current may be sensed and converted to '1' or '0', thereby reproducing the stored data.

The memory cells of the memory devices are typically arranged in an array having rows and columns. Generally, the rows are connected via a word line conductor and the rows are connected via a bit line conductor. During data read functions, bit line conductors are pre-charged to a selected voltage level.

Since the precharge circuit that precharges the bit line conductors requires a large current until saturation, when reading the data, the precharge circuit may change the bit line from '0' to '1' or '1' If the toggle for reading alternately to '0' occurs frequently, the consumed current is increased by that much, and consequently, there is a problem that the overall power consumption is increased in order to generate the pre-charge current.

Therefore, there is a need for a method of reducing the power consumption of the flash memory. Korean Patent No. 10-0464951 entitled " Device and method for reducing flash memory power consumption "has been proposed as a prior art developed to reduce the power consumption of a flash memory.

The prior art is directed to a configuration for storing data in a direction in which power consumption is reduced by selectively inverting data stored in the flash memory. The present invention solves the problem that the operation current increases when the cell of the flash memory is erased to zero . That is, the prior art is to prevent the increase of the operating current when reading the value of 0 stored in the memory cell, and there is no description about the consumption current of the precharge that can be increased by the toggle. There is a need for a method capable of reducing the consumption current by the precharge circuit generated by the precharge circuit.

Korean Registered Patent No. 10-1005632 (Registration date December 27, 2010) Korean Patent No. 10-0464951 (registered on December 24, 2004)

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the conventional art, and it is an object of the present invention to provide a flash memory which consumes power by pre-charge generated by a toggle when reading data stored in the flash memory, And to provide a method for reducing the above-mentioned problems.

Specifically, the present invention calculates the number of toggles based on the order of execution of the instructions of the program code, decides whether to perform bit conversion for each of the instructions so that the number of toggles is minimized, performs bit conversion of data on the determined instruction word By storing the bit-converted program code in the flash memory, the number of toggles can be minimized when reading the program code stored in the flash memory, thereby reducing power consumption due to precharging.

Another object of the present invention is to provide a method and apparatus for reducing power consumption of a flash memory capable of reducing the total power consumption of a device on which a flash memory is mounted by reducing consumption power by precharging when reading the flash memory do.

According to an aspect of the present invention, there is provided a method of reducing power consumption of a flash memory, including: receiving a program code; Analyzing the received program code; Calculating a number of toggles of a bit value according to an instruction of the program code through analysis of the program code; Bit-converting a bit value of the program code based on the calculated number of toggles; And storing the bit-converted program code in a flash memory.

The calculating step may calculate the number of toggles based on a command execution order of the program code.

Wherein the calculating comprises: generating an access pattern for the program code through analysis of the program code; Obtaining an access flow of the program code using the generated access pattern; And calculating the number of toggles based on the access flow of the obtained program code.

Wherein the bit conversion step comprises: determining whether or not bit conversion is performed on a data area of each of the instructions so that the number of toggles according to a command execution order of the program code is minimized; And performing a bit conversion on the data area of the instruction in which the bit conversion is determined.

The storing step may store a flag bit for the bit-converted data area.

Further, the method according to the present invention may further include a step of bit-converting and bit-converting the program code stored in the flash memory.

The reading may be performed by bit-converting the program code stored in the flash memory using flag bits previously stored in the data area in which the bit conversion is performed, among the program codes stored in the flash memory.

An apparatus for reducing power consumption of a flash memory according to an embodiment of the present invention includes a receiver for receiving a program code; An analysis unit for analyzing the received program code; An operation unit for calculating a number of toggles of a bit value according to an instruction of the program code through analysis of the program code; A bit conversion unit for bit-converting a bit value of the program code based on the calculated number of toggles; And a storage unit for storing the bit-converted program code in a flash memory.

The operation unit may calculate the number of toggles based on a command execution order of the program code.

Wherein the bit conversion unit comprises: a determination unit for determining whether or not bit conversion is performed on the data area of each of the instructions so that the number of toggles according to the instruction execution order of the program code is minimized; And a bit conversion performing unit for performing bit conversion on the data area of the instruction in which the bit conversion is determined.

According to the present invention, the number of toggles is calculated on the basis of the order of execution of the instructions of the program code, the bit conversion is performed on each of the instructions so that the number of toggles is minimized and stored in the flash memory, The number of toggles is minimized and the power consumption by precharging can be reduced.

In addition, since the consumption power of the precharge circuit according to the toggle can be reduced when the flash memory is read, the present invention can reduce the total power consumption of the device equipped with the flash memory.

FIG. 1 illustrates a configuration of an apparatus for reducing power consumption of a flash memory according to an embodiment of the present invention.
FIG. 2 shows a configuration of an operation unit shown in FIG. 1 according to an embodiment of the present invention.
FIG. 3 shows a configuration of another embodiment of the operation unit shown in FIG.
FIG. 4 shows a configuration of an embodiment of the first conversion unit shown in FIG.
5 shows an example of generating an access pattern according to analysis of a program code.
FIG. 6 shows a data access graph (DAG) for the access pattern shown in FIG.
7 shows an example of a process of calculating the number of toggles of a program code according to an access flow.
8 is an exemplary diagram for explaining an operation of determining and converting a bit-converted data area in accordance with a command execution order of the program code.
9 is a flowchart illustrating a method for reducing power consumption of a flash memory according to an exemplary embodiment of the present invention.
FIG. 10 shows an operational flow chart of an embodiment of step S930 shown in FIG.
FIG. 11 shows a flowchart of another embodiment of the operation of step S930 shown in FIG.
Figure 12 shows an operational flow diagram of an embodiment of a method of reading program code stored by Figure 9;

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the accompanying drawings.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the term "comprising" or " comprising " is intended to specify the presence of stated features, integers, steps, operations, elements, parts or combinations thereof, , But do not preclude the presence or addition of one or more other features, elements, components, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are to be interpreted in an ideal or overly formal sense unless explicitly defined in the present application Do not.

Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

However, the present invention is not limited to or limited by the embodiments. Like reference symbols in the drawings denote like elements.

Hereinafter, a method and an apparatus for reducing power consumption of a flash memory according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 12.

FIG. 1 illustrates a configuration of an apparatus for reducing power consumption of a flash memory according to an embodiment of the present invention.

1, an apparatus according to the present invention includes a receiving unit 110, an analyzing unit 120, a calculating unit 130, a first converting unit 140, a storing unit 150, a flash memory 160, A conversion unit 170 and a reading unit 180. [

The receiving unit 110 receives the program code from the outside.

At this time, the receiving unit 110 can receive the program code through a device or a program capable of generating the program code, and further via external storage means storing the program code.

The analysis unit 120 analyzes the program code received by the reception unit 110. [

Here, the analysis unit 120 may analyze the program code and obtain information on the execution order of the instructions included in the program code.

The calculation unit 130 calculates the number of toggles of the bit values according to the instruction of the program code based on the analysis result of the program code of the analysis unit.

That is, the operation unit 130 calculates the number of toggles in which the bit value changes from '1' to '0' or from '0' to '1', on the assumption that the instructions of the program code are stored in the flash memory 160.

At this time, the operation unit 130 may calculate 1) the number of toggles in the order of addresses for the instructions sequentially stored in the flash memory 160, 2) a toggle between the instructions based on the order of execution of the instructions of the program code And 3) calculate the number of toggles of the program code based on the access pattern obtained through analysis of the program code.

For example, the operation unit 130 sequentially calculates the number of toggles for instructions to be sequentially stored in the flash memory 160 in case 1). For example, the number of toggles between the first instruction and the second instruction, the number of toggles between the second instruction and the third instruction, and the number of toggles between the third instruction and the fourth instruction can be sequentially calculated.

In the case of 2), the operation unit 130 may know the execution order of the instructions according to the analysis result of the program code, and may determine the order in which the instructions stored in the flash memory 160 are read according to the order of execution of the instructions. The number of toggles may be calculated. In this case, as shown in FIG. 2, the operation unit 130 includes a performance order acquisition unit 210 and a toggle number operation unit 220.

The execution order acquisition unit 210 acquires the execution order of the instructions of the program code through the program code analysis.

Here, the instruction execution order refers to a connection relation between instructions, and may be a sequence of operations performed by movement to a specific address, repetition, and the like. For example, the execution order acquiring unit 210 can identify the program code that forms the loop, and grasp the start code and the final code of the loop. If the condition for escaping the loop is not satisfied, since the start code of the loop is likely to be executed again after the last code of the loop, the execution order acquisition unit 210 can acquire the execution order in consideration of this point . Considering the case where the condition for escaping the loop is satisfied, the execution order acquisition unit 210 may acquire a scheduled execution order such that the upper code of the loop is performed again after the last code of the loop is given or a probability is taken into account have.

The execution order may also be obtained in the form of a conditional branch or an unconditional branch (jump, goto, etc.).

The toggle number operation unit 220 calculates the number of toggles of the program code based on the order of execution of the instructions of the obtained program code.

In another example, the operation unit 130 generates an access pattern between a variable or an operand through analysis of the program code in the case of 3), and generates an access pattern of the access code of the program code using the generated access pattern and the number of toggles of the program code may be calculated based on the access flow of the acquired program code. At this time, as shown in FIG. 3, the operation unit 130 may include a pattern generation unit 310, An acquisition unit 320 and a toggle number operation unit 330. [

The pattern generation unit 310 generates an access pattern for the program code through program code analysis.

5, the pattern generating unit 310 generates an access pattern 520 of "bdabcbbdeba " through analysis of the received program code 510. In this example,

The flow obtaining unit 320 obtains the access flow of the program code using the access pattern 520 generated by the pattern generating unit 310. Here, the access flow of the program code may be a flow for the variables a, b, c, d, e, or may be a flow between the instructions contained in the program code.

If necessary, the flow acquiring unit 320 generates a data access graph (DAG) as in the example shown in FIG. 6 based on the access pattern generated by the pattern generating unit 310, and generates a data access graph May be used to obtain the access flow of the program code.

Here, the data access graph may include a connection relation 620 and a connection count 630 between the variables 610, and the number of other variables connected to each of the variables through the data access graph .

For example, the variable b has a connection relationship with all other variables a, c, d, and e, and it can be seen that the number of times the variables a, c, and d are connected is twice. And the variable b has the greatest influence on the total number of toggles of the program code. It can be seen that the relationship between the variables 610 is strengthened as the number of accesses between the variables 610 on the data access graph increases. For example, in FIG. 6, it can be seen that the variable b is associated twice with the variables a, d, and c, and once with the variable e, the relative access times (the number of associations) between the variables are different.

The flow obtaining unit 320 can identify the type of operation and the operand from the program code as shown in Fig. The relevance between the operands extracted in each row of the program code of Figure 7, i. E. Variables, can be evaluated using a data access graph such as that shown in Figure 6. [ For example, if it appears that the data access graph has a particularly high correlation between certain variables, the flow obtaining unit 320 may determine that if any one of the specific variables is found on the program code, It is predicted that the program code including the page will be executed next, and the execution order of the program code can be determined.

For example, an analysis of the entire program code assumes that variables b and d have a particularly high correlation. In the DAG, it is assumed that the leading variable and the trailing variable can be detected. After the variable b, the variable d is accessed with a high probability. In the program code, the code including the variable d is likely to be executed next to the code including the variable b.

The toggle number operation unit 330 calculates the number of toggles when the program code is stored in the flash memory 260 without bit conversion based on the access flow of the program code acquired by the flow acquisition unit 320. [

For example, as shown in FIG. 7, the toggle number calculating section 330 may calculate the number of toggles for the program code to be stored in the flash memory using the access flow based on the access pattern of the program code or the data access graph shown in FIG. 5 or 6 The number of toggles between the last address data of the area and the first address data of the second area, the number of toggles of the second area, the number of toggles between the last address data of the area and the first address data of the area , And (3) the number of toggles with respect to the data in the area, by storing the number of toggles in the flash memory 260 without bit conversion.

In the embodiment of FIG. 2 and FIG. 3, the execution order of the program code is obtained through different problem solving methods, and these methods are likely to obtain similar conclusions. For example, in the case of a loop that is repeated several times, as the execution is repeated a number of times, there is a high possibility that the association in the DAG is strengthened for operations in the loop. In addition, even in the case of an unconditional branch, since the program code far away from each other is frequently executed, the relationship between the variables of the program code is likely to be strengthened.

When the toggle count of the program code is calculated by the calculation unit 130, the first conversion unit 140 performs bit conversion on the bit value of the program code based on the number of toggles calculated by the calculation unit 130. [

In this case, the first conversion unit 140 may determine whether or not bit conversion is to be performed on each of the instructions included in the program code, and then perform bit conversion on the data region of the instruction for which bit conversion is determined.

That is, as shown in FIG. 4, the first conversion unit 140 includes a determination unit 410 and a conversion performing unit 420.

The determination unit 410 determines whether or not bit conversion is performed on the data area of each instruction so that the number of toggles with respect to the program code is minimized.

At this time, the determination unit 410 may determine whether to perform bit conversion so that the number of toggles according to the instruction execution order of the program code is minimized. Alternatively, the determination unit 410 may determine whether to perform bit conversion You can also decide whether to convert.

8, the instructions of the program code to be stored in the flash memory 160 are stored from address 1 (address 1) to address 5 (address 5) of the flash memory 160, Assuming that the number of toggles by the second instruction and the fourth instruction is the greatest, the determining unit 410 determines whether the number of toggles of the program code is the smallest, (bit inversion). That is, the determination unit 410 can minimize the number of toggles of the program code by determining the bit conversion of the second instruction word and the fourth instruction word data.

Here, address 1 to address 5 of the address of the flash memory in which the instructions are stored are shown for convenience of description, and the address of the actual flash memory may be different.

The conversion performing unit 420 performs bit conversion on the data area of the command determined by the determination unit 410. [

That is, as shown in FIG. 8, the conversion performing unit 420 performs bit conversion on the data area of the second instruction and the fourth instruction determined by the determining unit 410 to perform bit conversion Obtained data 810 and the bit-converted data 820 of the fourth instruction.

In this manner, the first conversion unit 140 can minimize the total number of toggles of the program code by bit-converting the data of the instruction word for which bit conversion is determined.

The storage unit 150 stores the program code bit-converted by the first conversion unit 140 in the flash memory 160. [

In this case, the storage unit 150 may store the flag bit for the data area of the bit-converted instruction word by the first conversion unit 140 in a predetermined storage unit, wherein the storage unit may be a flash memory, It may be a separate storage means.

If necessary, the storage unit 150 may store flag bits for all instructions. In this case, the storage unit 150 stores the bit value '1' of the flag bit for the bit-converted instruction, For non-instructions, the bit value '0' of the flag bit can be stored. Of course, this value may change according to the situation.

The second conversion unit 170 checks the bit-converted data area of the program code stored in the flash memory 160 and performs bit conversion on the data of the data area.

At this time, the second conversion unit 170 can perform bit conversion on the program code stored in the flash memory 160 based on the bit value of the flag bit stored in advance.

For example, the second conversion unit 170 converts the bit data of the second instruction data 610 and the fourth instruction data 620, which are bit-converted and stored in the flash memory, into flag bits The data of the corresponding data area is bit-converted through the bit value '1' of the instruction word, and the data of the corresponding data area is converted through the bit value '0' of the flag bit of the instruction word, No bit conversion is performed.

The reading unit 180 reads the program code bit-converted by the second conversion unit 170, that is, the original program code.

In this way, when the program code is stored in the flash memory, the apparatus according to the present invention performs bit conversion so that the number of toggles according to the instruction of the program code is minimized, , Thereby reducing the power consumption of the flash memory.

Furthermore, by reducing the power consumption of the flash memory, the present invention can reduce the total power consumption of the device on which the flash memory is mounted.

9 is a flowchart illustrating a method for reducing power consumption of a flash memory according to an exemplary embodiment of the present invention.

Referring to FIG. 9, a method according to the present invention receives a program code from the outside and analyzes the received program code (S910, S920).

Here, the analysis of the program code may be an analysis of instructions contained in the program code, an analysis of binary data of the program code, and may include all analyzes to minimize the number of toggles in the present invention.

Through the analysis of the program code, the number of toggles of the bit values according to the instruction of the program code is calculated (S930).

In this case, the toggle is switched from a bit value '0' to a bit '1' or from a bit value '1' to a bit '0' in the first line of the flash memory connected to the precharge circuit, And the number of toggles of the program code means the total number of toggles generated in accordance with the order of execution of the instruction.

At this time, the step S930 may calculate the number of sequential toggles of the program code in the order of the addresses stored in the flash memory, calculate the number of toggles between the instructions based on the order of execution of the instructions of the program code, The number of toggles of the program code may be calculated based on the access pattern obtained through the above-described access pattern. This will be described with reference to FIGS. 10 and 11. FIG.

FIG. 10 is a flowchart illustrating an operation of step S930 of FIG. 9 according to an embodiment of the present invention. Referring to FIG.

Referring to FIG. 10, the step of calculating the number of toggles (S930) acquires the order of execution of the instructions of the program code based on the analysis result of the program code in step S920 (S1010).

Here, the order of execution of the instructions means the order of the instructions that are executed when the program code is executed, and specific instructions may be repeatedly executed according to the order of execution.

When the instruction execution order is acquired in step S1010, the number of toggles of the program code is calculated based on the obtained instruction execution order (S1020).

That is, it is possible to calculate the number of toggles with respect to all the instructions of the program code by calculating the number of toggles with the previous instruction and the number of toggles with the next instruction according to the order of execution between the instructions.

FIG. 11 shows a flowchart of another embodiment of the operation of step S930 shown in FIG. 9, in which a process of calculating the number of toggles is performed using an access pattern.

Referring to FIG. 11, the step of calculating the number of toggles (S930) generates an access pattern for the program code through analysis of the program code, and acquires an access flow of the program code using the generated access pattern (S1110, S1120).

If necessary, the access pattern of the program code may be used to generate a data access graph including the connection relationship between the commands and the number of connections, and the access flow may be obtained using the generated data access graph.

When the access flow of the program code is obtained, the total number of toggles of the program code is calculated based on the obtained access flow (S1130).

Referring again to FIG. 9, if the total number of toggles of the program code is calculated in step S930, it is determined whether to perform bit conversion for each data region of the instruction based on the calculated number of toggles, (S940, S950).

Here, the data corresponding to each data region of the instruction can be determined whether or not to perform bit conversion in order to minimize the number of toggles of the program code. Whether or not bit conversion is performed depends on the number of toggles between instructions, the number of times each instruction is executed, The number of times of connection or repetition, and the like.

If bit conversion is determined for each of the instructions and bit conversion is performed for the instruction for which bit conversion is determined, the bit-converted program code is stored in the flash memory (S960).

Of course, if there is no instruction to perform bit conversion in step S940, the original program code is stored in the flash memory.

When the bit-converted program code is stored in the flash memory, flag bits of whether or not to perform bit conversion on the area are stored in a predetermined area of the flash memory or in a separate storage unit (S970).

Here, the flag bit is stored for each of the instructions, and the bit value of the flag bit has a value of '1' for an instruction in which bit conversion is performed and a value of '0' . Of course, the bit value of the flag bit may be changed according to the situation.

Depending on the situation, step S970 of storing the flag bit may be performed in the next step S940 in which the bit conversion is determined, or may be performed in the next step S750 in which bit conversion is performed. Or may be performed in parallel with one.

Figure 12 shows an operational flow diagram of an embodiment of a method of reading program code stored by Figure 9;

Referring to FIG. 12, when reading the program code stored in the flash memory, the bit value of the flag bit for each data area of the command stored in the flash memory is checked (S1210).

The bit conversion is not performed on the data area of the instruction whose flag bit value is '0', and bit conversion is performed on the data area of the instruction word whose flag bit value is '1' (S1220, S1230).

The method for reducing power consumption of a flash memory according to an exemplary embodiment of the present invention may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions recorded on the medium may be those specially designed and constructed for the present invention or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

As described above, the present invention has been described with reference to particular embodiments, such as specific elements, and specific embodiments and drawings. However, it should be understood that the present invention is not limited to the above- And various modifications and changes may be made thereto by those skilled in the art to which the present invention pertains.

Accordingly, the spirit of the present invention should not be construed as being limited to the embodiments described, and all of the equivalents or equivalents of the claims, as well as the following claims, belong to the scope of the present invention .

Claims (14)

Receiving program code;
Analyzing the received program code to obtain an execution order of the commands included in the program code;
Calculating a number of toggles of the bit values between the instructions in accordance with the order of execution of the instructions obtained through analysis of the program code;
Bit-converting a bit value of the program code based on the calculated number of toggles; And
Storing the bit-converted program code in a flash memory
Wherein the power consumption of the flash memory is reduced. delete Receiving program code;
Analyzing the received program code;
Generating an access pattern for the program code through analysis of the program code;
Generating a data access graph using the generated access pattern;
Obtaining an access flow of the program code using the generated data access graph; And
Calculating a number of tokens based on the obtained access flow of the program code;
Bit-converting a bit value of the program code based on the calculated number of toggles; And
Storing the bit-converted program code in a flash memory
Wherein the power consumption of the flash memory is reduced. The method according to claim 1,
The step of converting the bits
Determining whether or not bit conversion is performed on the data area of each of the instructions so that the number of toggles according to the order of execution of the instructions is minimized; And
Performing bit conversion on the data area of the instruction in which the bit conversion is determined
Wherein the power consumption of the flash memory is reduced. 5. The method of claim 4,
The storing step
And storing a flag bit for the data area in which the bit conversion is performed. The method according to claim 1,
And performing bit conversion on the program code stored in the flash memory
The method further comprising the step of: The method according to claim 6,
The reading step
Wherein the program code stored in the flash memory is bit-converted and read using a flag bit previously stored in the data area in which the bit conversion is performed among the program codes stored in the flash memory. Way.
A computer-readable recording medium having recorded thereon a program for executing the method according to any one of claims 1 and 3 to 7.
A receiving unit for receiving the program code;
An analysis unit for analyzing the received program code and obtaining an order of execution of the commands included in the program code;
An operation unit for calculating a number of toggles of bit values between the instructions in accordance with the order of execution of the instructions obtained through analysis of the program code;
A converter for bit-converting a bit value of the program code based on the calculated number of toggles; And
And a storage unit for storing the bit-converted program code in a flash memory
Wherein the power consumption of the flash memory is reduced. delete A receiving unit for receiving the program code;
An analysis unit for analyzing the received program code;
A pattern generator for generating an access pattern for the program code through analysis of the program code;
A flow acquiring unit for generating a data access graph using the generated access pattern and acquiring an access flow of the program code using the generated data access graph; And
A toggle number calculating section for calculating the number of tokens based on the obtained access flow of the program code,
A converter for bit-converting a bit value of the program code based on the calculated number of toggles; And
And a storage unit for storing the bit-converted program code in a flash memory
Wherein the power consumption of the flash memory is reduced. 10. The method of claim 9,
The conversion unit
A determination unit for determining whether or not to perform bit conversion on the data area of each of the instructions so that the number of toggles according to the order of execution of the instructions is minimized; And
A conversion performing unit for performing bit conversion on a data area of an instruction word for which bit conversion is determined,
Wherein the power consumption of the flash memory is reduced. 13. The method of claim 12,
The storage unit
And stores flag bits for the bit-converted data area in a predetermined storage means. 10. The method of claim 9,
A read unit for bit-converting and reading the program code stored in the flash memory by using flag bits previously stored in the data area in which the bit conversion is performed among the program codes stored in the flash memory,
Wherein the power consumption of the flash memory is reduced.

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