WO2014059563A1

WO2014059563A1 - Semiconductor device and manufacturing method thereof

Info

Publication number: WO2014059563A1
Application number: PCT/CN2012/001538
Authority: WO
Inventors: 梁擎擎; 秦长亮; 钟汇才; 尹海洲; 朱慧珑
Original assignee: 中国科学院微电子研究所
Priority date: 2012-10-16
Filing date: 2012-11-13
Publication date: 2014-04-24
Also published as: CN103730498B; CN103730498A

Abstract

A semiconductor device includes a substrate (1), a source region (1S) and a drain region (1D) in the substrate (1), a gate stack structure (6/7) between the source region (1S) and the drain region (1D) on the substrate (1), and offset spacers (2/4) surrounding the gate stack structure (6/7), and is characterized in that the source region (1S) and the gate stack structure (6/7) are symmetrically disposed about the drain region (1D). A method for manufacturing the semiconductor device, by using a double spacer structure of the offset spacers (2/4) and the gate sidewall spacer (3) to form a fine dummy gate line and using a source (1S) - drain (1D) - source (1S) symmetrical structure to improve processing accuracy of the device, increases reliability of the device in whole and improves performance.

Description

Semiconductor device and method of manufacturing the same

The present application claims priority to Chinese Patent Application No. 20121039378, filed on Jan. Technical field

The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly to a novel MOSFET having a symmetrical structure fabricated by a gate-last process and a method of fabricating the same. Background technique

As device dimensions continue to shrink, the gate insulating layer in MOSFETs is increasingly thinner and their insulating isolation tends to degrade. In addition, conventional doped polysilicon gates do not effectively control the gate work function to adjust the threshold voltage. For this reason, a high-k material is used as a gate insulating layer in the prior art and a metal material is used as a gate electrode and a metal nitride to adjust a work function.

A manufacturing method of the gate stack structure of the high-k-metal gate (HK-MG) is a so-called back gate process, that is, a dummy gate of a material such as polysilicon is deposited and etched on the substrate first, and then deposited. An interlayer dielectric layer (ILD) of a low-k dielectric covers the entire device, an ILD is etched to form a gate trench, and a gate insulating layer of a high-k material and a gate conductive layer of a metal are sequentially deposited in the gate trench.

However, since the feature size of the device has been reduced to 45 nm or less, it is limited by lithography precision, and the processing precision of depositing/etching the dummy gate and etching the gate trench cannot be effectively improved, except that it is difficult to form a small-sized dummy gate. In addition to the lines, there are also problems such as line distortion, distortion, etc., so that the finally formed metal gate lines may be bent or even broken, thereby seriously degrading device reliability. Summary of the invention

In view of the above, the object of the present invention is to overcome the above problems, break the limitation of lithography precision on gate patterning, and form an accurate and strictly symmetrical MOSFET device structure to improve the reliability of the device. SUMMARY OF THE INVENTION The above object of the present invention is achieved by providing a semiconductor device including a substrate, source and drain regions in a substrate, a gate stack structure on a substrate between a source region and a drain region, and a gate stack. An offset sidewall spacer around the structure, characterized in that: the source region and the gate stack structure are symmetrically distributed with respect to the drain region.

Wherein the top of the source and/or drain regions are flush with the top of the gate stack structure, or the top of the source and/or drain regions is lower than the top of the gate stack structure.

Wherein, the source region and the drain region further comprise a metal silicide, and a source-drain contact plug in contact with and electrically connected to the metal silicide.

The material of the offset sidewall is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, high-k materials, and combinations thereof. '

Among them, the drain area also includes an elevated drain area.

Wherein, the offset sidewall and/or the gate stack structure are separated or connected in a ring shape. The present invention also provides a method of fabricating a semiconductor device, comprising: forming a trench in a substrate; forming a first offset sidewall on a side of the trench; forming a dummy gate on the side of the first offset sidewall; Two offset sidewalls; performing ion implantation and subsequently annealing using the first offset sidewall, the dummy gate, and the second offset sidewall as a mask to form a source region and a drain region, wherein the source region is symmetrically distributed with respect to the drain region The dummy gate is removed, a gate trench is formed, and a gate stack structure is formed in the gate trench, wherein the gate stack structure is symmetrically distributed with respect to the drain region.

Wherein, the surface of the substrate has a source-drain implant region, and the conductivity type of the source-drain implant region is different from the conductivity type of the substrate.

The first offset sidewall is the same material as the second offset sidewall and is different from the dummy gate material.

The first offset sidewall spacer and/or the second offset sidewall spacer material are selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, high-k materials, and combinations thereof, and the dummy gate material is selected from the group consisting of polysilicon, amorphous silicon, Microcrystalline silicon, amorphous carbon, silicon nitride, silicon oxide, silicon oxynitride, and combinations thereof.

After forming the drain region, the method further includes: forming an insulating dielectric layer in the trench; etching the insulating dielectric layer to form a drain trench until the drain region is exposed; forming an elevated drain region in the drain trench, or depositing a filler metal , so that the lifting drain or metal is flush with the top of the dummy gate.

Wherein, after forming the source/drain or filling the metal, the method further comprises: planarizing or etching so that the top of the source region and/or the drain region is lower than the dummy gate top.

Wherein, after forming the gate stack structure, the method further comprises: forming on the source region and the drain region Metal layer; annealing causes the metal layer to react with the source and drain regions to form a metal silicide, located on the source and drain regions; and removing the unreacted metal layer.

The forming the metal silicide further includes: forming an interlayer dielectric layer; etching the interlayer dielectric layer to form a source/drain contact hole until the metal silicide on the source and drain regions is exposed; depositing metal in the source/drain contact hole/ Metal nitride, forming source and drain contact plugs.

The first offset sidewall, the second offset sidewall, the dummy gate, and the gate stack structure are separated, or are respectively connected in a ring shape.

According to the semiconductor device manufacturing method of the present invention, a fine dummy gate line is formed by the double sidewall structure of the offset sidewall spacer and the gate spacer, and the symmetrical structure of the source-drain-source is used to improve the device processing. Accuracy improves overall device reliability and improves performance. DRAWINGS

The technical solution of the present invention will be described in detail below with reference to the accompanying drawings, in which:

1 to 12 are cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with one embodiment of the present invention;

13 to 16 are cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with another embodiment of the present invention. detailed description

Features of the technical solution of the present invention and technical effects thereof will be described in detail below with reference to the accompanying drawings in conjunction with the exemplary embodiments. It should be noted that like reference numerals indicate similar structures, and the terms "first", "second", "upper", "lower", "thick", "thin", etc. as used in this application may be used. Modification of various device structures. These modifications are not intended to imply a spatial, order, or hierarchical relationship to the structure of the device being modified.

1 to 12 are cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with one embodiment of the present invention.

Referring to FIG. 1, a source-drain implant region (well region) is formed in a substrate, and a photoresist is applied and patterned to expose a portion of the source-drain implant region corresponding to the gate region and the drain region. Providing a substrate 1 made of, for example, bulk Si, bulk Ge, SOL GeOI, GaAs, SiGe, GeSn, InP, InSb, GaN, etc., and preferably bulk Si (for example, single crystal Si wafer) or SOI to be compatible with existing CMOS Process compatible. Preferably, the substrate 1 has a lightly doped first conductivity type, such as p -. Source-drain ion implantation is performed on the substrate 1 such that a portion of the substrate 1 near the surface constitutes a source leak. The entry region 1A has a second conductivity type different from the first conductivity type, and has a higher doping concentration, for example, n+. Although the source-drain implant region 1A shown in FIG. 1 is located near the top of the entire substrate 1, in practice its periphery may be surrounded by an insulating medium such as shallow trench isolation (STI) to form a well region, that is, a P-line. The n+ well region in the bottom 1, which corresponds to the active region of the device. A photoresist PR is coated on top of the substrate 1 (source/drain implantation region 1 A ), and is exposed/developed to be patterned to expose a portion located in the middle of the source/drain implantation region (well region or active region), the middle portion The source-drain implant region portion covered by the photoresist PR corresponding to the gate region 1 G and the drain region 1 D of the device will correspond to the source region 1 S of the device. Although the source region 1 S is located on both sides of the gate region 1 G and the drain region 1 D, the source region 1 S may actually surround the gate region 1G in a plan view (not shown). And drain region 1D. The width and thickness of each part are set according to the design requirements of the device layout, and will not be described here. In addition, although the source-drain implant region (well region, active region) is formed by implantation, the epitaxial source/drain region may be formed in an epitaxial manner, and in-situ doping may be performed while epitaxially having n+. Conductive type.

Referring to FIG. 2, the source and drain implant regions are etched using the photoresist pattern as a mask to form trenches until the substrate is exposed. For the Si material substrate 1 and the source/drain implantation region 1A, TMAH wet etching may be used, or a fluorocarbon plasma plasma etching may be used, and the source and drain implantation of the photoresist pattern PR may be vertically etched. In the region 1A, until the P-type substrate 1 is exposed, the gate and drain trenches 1 B are formed. As shown in FIG. 2, the gate and drain trenches 1 B have a partial overetch during etching, that is, the bottom surface of the trench 1 B may be slightly lower than the source and drain implant regions (well region, active region). The bottom surface of 1A, for example, l ~ 5nm. The width of the trench should be greater than or equal to the sum of the gate width and the drain width, for example, 50 to 500 nm.

Referring to FIG. 3, a first offset spacer 2 is formed on the sides of the gate and drain trenches 1B. Conventional shields such as silicon oxide, silicon oxynitride, silicon nitride, or even high-k materials may be used by LPCVD PECVD, HDPCVD, thermal oxidation (e.g., rapid thermal oxidation of RTO). Silicon oxide or silicon nitride is preferably used in view of cost and process simplicity. In one embodiment of the invention, the dielectric layer is silicon oxide. The bottom and sides of the dielectric layer are then anisotropically etched using conventional photolithography/etching such that the underlying dielectric layer is completely removed and the substrate 1 is exposed while the side dielectric layer remains The sidewalls of the gate and drain trenches 1B thus constitute the first offset spacers 2. The first offset spacer 2 will later serve as an isolation sidewall between the source and the source and is used to define the distribution of the gates. The thickness of the first offset side wall 2 is relatively Thin to precisely control the device lines, for example only l ~ 10nm. The first offset spacer 2 shown in FIG. 3 is two left and right, and in fact, in the top view, in addition to the two symmetrically distributed, it may be a (circular) ring distributed on the inner wall of the trench 1B. .

Referring to Fig. 4, a dummy gate 3 and a second offset side wall 4 are sequentially formed on the side of the first offset spacer 2. Similar to the formation of the first offset spacer 2, that is, the first deposition and the subsequent etching, the dummy gate 3 is formed on the side (specifically, the inner side) of the first offset spacer 2 (because it is substantially used as a sidewall structure defining a gate shape, also referred to as a gate spacer; the material thereof is, for example, polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, silicon nitride, silicon oxide, silicon oxynitride, etc., and combinations thereof And the material of the dummy gate 3 is different from the material of the first offset spacer 2 in order to have a higher etching selectivity between the two. Specifically, in one embodiment of the present invention, when the first offset sidewall 2 is silicon oxide, the dummy gate 3 may be silicon nitride. The width of the dummy gate 3 is set according to the width of the device gate, for example, 10 to 50 nm. The dummy grid 3 is shown in FIG. 4 as two structures symmetrical on the left and right sides, and may also be substantially in the top view, which is distributed inside the (circular) annular first offset side wall (circle) ring. The annular structure, that is, the dummy gate 3 may be a (circular) ring shape. Then, similarly, a second offset spacer 4 is formed on the inner side of the dummy gate 3, and the material thereof may be the same as the first offset sidewall 2 and different from the material of the dummy gate 3, and the thickness may also be 1 to 10 nm. . In one embodiment of the invention, the material of the first and second offset sidewalls is silicon oxide, and the material of the dummy gate 3 is silicon nitride. Similarly, the second offset side wall 4 is not limited to the left-right symmetric separation structure shown in Fig. 4, but may be a (circular) ring shape. It should be noted that the first offset sidewall 2, the dummy gate 3, and the second offset spacer 4 do not completely fill the gate and drain trenches 1 B , and the corresponding regions of the dummy gate 3 are used to form The gate, and the exposed substrate 1 area will be used to form the drain region. Thereafter, ion implantation is performed again, which may be vertical multiple ion implantation to form a lightly doped source and drain region (LDD structure) and heavily doped source and drain regions, or oblique ion implantation to form a halo source. Leak-doped regions (none of which are shown above).

Referring to Fig. 5, the driving annealing is performed so that the impurities in the source/drain implantation region 1A are diffused in the longitudinal direction and the lateral direction, thereby forming the source region 1 S and the drain region 1D, respectively, in the substrate. The inside of the drain ID shown in Figure 5. The substrate 1 between the drain region 1 D and the source region 1 S constitutes a channel region 1 C, which may be a plurality of separate or connected (circular) rings.

Referring to FIG. 6, the dielectric layer 5 is filled in the trench 1B, and the insulating dielectric layer 5 is planarized by CMP, etch back, etc. until the first offset spacer 2, the dummy gate 3, and the second offset spacer are exposed. 4. The material of the insulating dielectric layer 5 is preferably the same as the first offset sidewall 2 and/or the second offset sidewall 4 The materials are the same, that is, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, and are different from the material of the dummy gate 3. In one embodiment of the present invention, the insulating dielectric layer 5 is a silicon oxide prepared by a medium temperature LPCVD or a low temperature PECVD method using TEOS as a reactant. In addition, the insulating dielectric layer 5 may also be doped silicon oxide, such as BSG, PSG, BPSG, F-doped glass, C-doped glass, etc., and may also be other low-k materials, which may be formed by spin coating, spraying, or the like. Screen printing and more.

Referring to Fig. 7, the insulating dielectric layer 5 is etched to form the drain trench 5A until the drain region 1D is exposed. The insulating dielectric layer 5 for silicon oxide may be etched by HF-based wet etching, or fluorocarbon-based plasma dry etching, such as CF ₄ , CH ₃ F, CHF ₃ , CH ₂ F ₂ , C ₃ F ₆ , C ₄ F ₈ and the like, and an etching gas having a relatively large fluorocarbon is preferable. The width of the drain trench 5A is, for example, 20 to 100

Referring to Fig. 8, a lift drain region 1 RD is formed in the drain trench 5 A . The raised drain region 1RD is formed by PEC VD, MBE, and conductor material. Lifting the drain region The material of the 1RD is, for example, Si, or other high mobility materials such as SiGe and SiC to improve the stress in the channel region and further improve device performance. Thereafter, the drain region 1RD is planarized by a process such as CMP until the dummy gate 3 is exposed. In addition, a metal can be deposited in the drain trench 5A to directly form a drain contact plug (also labeled as 1RD).

Referring to Fig. 9, the dummy gate 3 is removed, and the gate trench 3A is formed until the trench region 1C in the substrate 1 is exposed. For the dummy gate 3 of silicon nitride, it can be etched and removed by hot phosphoric acid or strong oxidizing agent + strong acid wet etching solution (such as sulfuric acid + hydrogen peroxide), or fluorocarbon-based plasma dry etching. . Other materials of the dummy gate 3 can be plasma dry etching, the etching gas can be rare gas (He, Ne, Ar, Kr, Xe), etc., and can also include oxygen, chlorine, bromine vapor, etc. Rate of gas. The width of the gate trench 3A is equal to the width of the dummy gate 3 (i.e., the gate spacer), which is the same as the gate width of the final device, for example, 10 to 50 nm.

Referring to FIG. 10, a gate insulating layer 6 of a high-k material and a gate conductive layer 7 of a metal material are sequentially deposited in the gate trench 3 A to form a gate stacked structure. The high-k material of the gate insulating layer 6 includes, but is not limited to, nitrides (eg, SiN, AlN, TiN), metal oxides (mainly sub-group and lanthanide metal element oxides, such as A1 ₂ 0 ₃ , Ta ₂ 0 ₅ , Ti0 ₂ , ZnO, Zr0 ₂ , Hf0 ₂ , Ce0 ₂ , Y ₂ 0 ₃ , La ₂ 0 ₃ ), perovskite phase oxides (eg PbZr _x Ti _1-x 0 ₃ ( PZT ) , Ba _x Sr _{1 -x} Ti0 ₃ ( BST ) ). The material of the gate conductive layer 7 is, for example, Cu, Al, Ti, Ta, W, Mo, etc. and combinations thereof. Also preferably between the gate insulating layer 6 and the gate conductive layer 7 is a work function adjusting layer/diffusion barrier layer (not shown) for adjusting the device gate work function to control the threshold voltage, and preventing the gate The metal element diffuses into the channel region to reduce device performance, and the material thereof may be a nitride such as TiN, TaN, or the like. The CMP then planarizes the various layers until the gate conductive layer 7 is exposed.

Referring to Fig. 1, a metal silicide 8 is formed on the source region 1S and the drain region 1D (elevation drain region 1RD) for reducing the contact resistance. A thin metal layer (not shown) is formed on the source region 1 S and the drain region 1D by evaporation, sputtering, or the like, and the material thereof includes Ni, Pt, Co, Ti, and a combination thereof, and has a thickness of, for example, 1 to 5 nm. Annealing at 450 ~ 850 °C for 1 s ~ 2min, the thin metal layer reacts with Si in the source and drain regions to form a metal silicide 8 having a thickness of, for example, l ~ 10 nm. A thin layer of unreacted metal is then stripped. The metal silicide 8 may be a single metal silicide or a multi-metal silicide.

Referring to FIG. 12, an interlayer dielectric layer (ILD) 9 is formed on the entire device, and the ILD9 material is, for example, a low-k material including, but not limited to, an organic low-k material (for example, an organic polymer containing an aryl group or a polycyclic ring), and an inorganic low. k materials (eg amorphous carbon nitride film, polycrystalline boron nitride film, fluorosilicate glass, BSG, PSG, BPSG), porous low-k materials (eg, silicosane (SSQ)-based porous low-k materials, porous dioxide Silicon, porous SiOCH, C-doped silica, F-doped amorphous carbon, porous diamond, porous organic polymer). The ILD 9 is etched until the metal silicide 8 is exposed to form a source/drain contact hole (not shown), and the source/drain contact hole is filled with a metal/metal nitride to form a source/drain contact plug 10.

The final device structure formed in accordance with the first embodiment of the present invention is as shown in FIG. 12, including the substrate 1, the source region 1 S and the drain region 1D in the substrate 1, the gate stack between the source region IS and the drain region ID. Structure 6/7, offset spacer 2/4 located around the gate stack structure, characterized in that the source region 1 S and the gate stack structure 6/7 are symmetrically distributed with respect to the drain region 1 D. The source region 1 S and the drain region 1 D further include a metal silicide 8 and a source/drain contact plug 10 which is in contact with and electrically connected to the metal silicide. In particular, the top of source region 1 S and/or drain region 1 D is flush with the top of gate stack structure 6/7. The materials, geometries, and dimensions of the remaining components are detailed in the description of the manufacturing method and will not be described here.

13 to 16 are cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with another embodiment of the present invention. Wherein, the same parts of the second embodiment and the embodiment have been described in FIGS. 1 to 8, that is, the second embodiment is the same as the first embodiment before the step of forming the lifted drain region 1RD, and thus is no longer Explain the same part. Different portions of the second embodiment will be mainly described below with reference to FIGS. 13 to 16. And in particular, unless otherwise specified, each standard The materials and manufacturing methods used for the same components are the same as those of the first embodiment, except for the order of the manufacturing processes and the relative positional relationship.

Referring to FIG. 13, the CMP is planarized or etched such that the top surfaces of the source region 1 S and the drain region 1D (including the lift drain region 1 RD ) are lower than the top surface of the dummy gate 3. The source region 1 S of the Si material, the drain region ID, and the like can be etched by using the TMAH wet etching solution. The etching liquid does not substantially etch the offset sidewall spacers of silicon oxide, silicon nitride, silicon oxynitride or the like. 4. The dummy gate 3 and the insulating dielectric layer 5.

Referring to Fig. 14, a metal silicide 8 is formed on the source region 1 S and the drain region ID. ILD 9 is formed across the device. The CMP then planarizes the ILD 9 until the dummy gate 3 is exposed.

Referring to Figure 15, the dummy gate 3 is removed leaving a gate trench (not shown). A gate insulating layer 6 and a gate conductive layer 7 are deposited in the gate trench. The CMP planarizes the layers until the ILD 9 is exposed.

Referring to Fig. 16, the ILD 9 is etched to form a source/drain contact hole (not shown). A metal/metal nitride is deposited in the source/drain contact hole to form a source/drain contact plug 10.

The final device structure formed in accordance with the second embodiment of the present invention is as shown in FIG. 16, including the substrate 1, the source region 1 S and the drain region 1D in the substrate 1, the gate stack between the source region IS and the drain region ID. Structure 6/7, offset spacer 2/4 located around the gate stack structure, characterized in that the source region 1 S and the gate stack structure 6/7 are symmetrically distributed with respect to the drain region 1 D. The source region 1 S and the drain region 1 D further include a metal silicide 8 and a source/drain contact plug 10 which is in contact with and electrically connected to the metal silicide. In particular, the source region 1 S and/or drain region 1 D top is lower than the top of the gate stack structure 6/7. The materials and geometries and dimensions of the remaining components are detailed in the description of the manufacturing method and will not be described here.

According to the semiconductor device manufacturing method of the present invention, a fine dummy gate line is formed by the double sidewall structure of the offset sidewall spacer and the gate spacer, and the symmetrical structure of the source-drain-source is used to improve the device processing. Accuracy improves overall device reliability and improves performance.

While the invention has been described with respect to the embodiments of the embodiments of the present invention, various modifications and equivalents of the methods of forming the device structure may be made without departing from the scope of the invention. In addition, many modifications may be made to the specific circumstances or materials without departing from the scope of the invention. Therefore, the invention is not intended to be limited to the specific embodiments disclosed as the preferred embodiments of the invention, and the disclosed device structure and method of manufacture thereof will include all embodiments falling within the scope of the invention. .

Claims

Rights request

A semiconductor device comprising a substrate, a source region and a drain region in the substrate, a gate stack structure on the substrate between the source region and the drain region, and an offset sidewall spacer located around the gate stack structure, It is characterized in that: the source region and the gate stack structure are symmetrically distributed with respect to the drain region.

2. The semiconductor device according to claim 1, wherein the top of the source region and/or the drain region is flush with the top of the gate stack structure, or the top of the source region and/or the drain region is lower than the top of the gate stack structure.

3. The semiconductor device according to claim 1, wherein the source region and the drain region further comprise a metal silicide, and a source/drain contact plug in contact with and electrically connected to the metal silicide.

4. The semiconductor device according to claim 1, wherein the material of the offset spacer is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, high k materials, and combinations thereof.

5. The semiconductor device according to claim 1, wherein the drain region further comprises an elevated drain region.

The semiconductor device according to claim 1, wherein the offset spacers and/or the gate stack structure are separated or connected in a ring shape.

7. A method of fabricating a semiconductor device, comprising:

Forming a trench in the substrate;

Forming a first offset sidewall on a side of the trench;

Forming a dummy gate and a second offset sidewall on the side of the first offset sidewall; performing ion implantation and subsequently annealing using the first offset sidewall, the dummy gate, and the second offset sidewall as a mask Forming a source region and a drain region, wherein the source region is symmetrically distributed with respect to the drain region;

The dummy gate is removed, a gate trench is formed, and a gate stack structure is formed in the gate trench, wherein the gate stack structure is symmetrically distributed with respect to the drain region.

The method of fabricating a semiconductor device according to claim 7, wherein the surface of the substrate has a source/drain implant region, and the source-drain implant region has a conductivity type different from that of the substrate.

9. The method of fabricating a semiconductor device according to claim 7, wherein the first offset spacer is of the same material as the second offset spacer and is different from the dummy gate material.

10. The method of fabricating a semiconductor device according to claim 9, wherein the first offset spacer and/or the second offset sidewall material are selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, high-k materials, and combinations thereof. The dummy gate material is selected from the group consisting of polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, silicon nitride, silicon oxide, silicon oxynitride, and combinations thereof.

1 . The method of fabricating a semiconductor device according to claim 7, wherein the formation of the drain region is performed The step includes: forming an insulating dielectric layer in the trench; etching the insulating dielectric layer to form a drain trench until the drain region is exposed; forming an elevated drain region in the drain trench, or depositing a filler metal to lift the drain region or The metal is flush with the top of the dummy grid.

12. The method of fabricating a semiconductor device according to claim 11, wherein after forming the lift source drain or the fill metal, further comprising: planarizing or etching such that a top of the source region and/or the drain region is lower than the dummy gate top.

The method of fabricating a semiconductor device according to claim 7, wherein after the forming the gate stack structure, further comprising: forming a metal layer on the source region and the drain region; annealing to cause the metal layer to react with the source region and the drain region to form a metal silicide , located on the source and drain regions; remove unreacted metal layers.

14. The method of fabricating a semiconductor device according to claim 13, wherein the forming the metal silicide further comprises: forming an interlayer dielectric layer; etching the interlayer dielectric layer to form a source/drain contact hole until the source and drain regions are exposed; Metal silicide; depositing metal/metal nitride in the source-drain contact hole to form a source-drain contact plug.

The method of fabricating a semiconductor device according to claim 7, wherein the first offset spacer, the second offset spacer, the dummy gate, and the gate stack are separated, or are each connected in a ring shape.