WO2014056908A1

WO2014056908A1 - Method for producing a gan-based optoelectronic semiconductor chip by ion implantation and a corresponding optoelectronic semiconductor chip

Info

Publication number: WO2014056908A1
Application number: PCT/EP2013/070941
Authority: WO
Inventors: Matthias Peter; Korbinian Perzlmaier; Markus Maute; Johannes Baur; Karl Engl; Sebastian Taeger; Albrecht Kieslich
Original assignee: Osram Opto Semiconductors Gmbh
Priority date: 2012-10-09
Filing date: 2013-10-08
Publication date: 2014-04-17
Also published as: DE102012109590A1

Abstract

In at least one embodiment, the method is designed for producing an optoelectronic semiconductor chip (1). The method comprises the following steps: - providing a growth substrate (2); - creating a semiconductor layer sequence (3) on said growth substrate (2), wherein the semiconductor layer sequence (3) has an n-side (31), a p-side (33) and an active layer (33) intended for the generation of a radiation, the active layer (32) is arranged between the p-side (33) and the n-side (31), and the n-side (31) is closest to the growth substrate (2); and - doping the n-side (31) through the active layer (32) by means of ion implantation.

Description

METHOD FOR THE PRODUCTION OF AN OPTOELECTRONIC SEMICONDUCTOR CHIP ON GAN BASIS BY MEANS OF LONENIMPLANTANTION AND CORRESPONDING

OPTOELECTRONIC SEMICONDUCTOR CHIP

There will be a method of making a

optoelectronic semiconductor chip specified. In addition, an optoelectronic semiconductor chip is specified.

One problem to be solved is one

Optoelectronic semiconductor chip with a high

Transverse conductivity of a current spreading layer efficient

to produce.

This task is done, inter alia, by a procedure and

through an optoelectronic semiconductor chip with the

Characteristics of the independent claims solved. preferred

Further developments are the subject of the dependent claims.

In accordance with at least one embodiment, the method is for

Production of an optoelectronic semiconductor chip

set up. The semiconductor chip is

preferably around a light-emitting diode chip. It is also possible that with the method, a laser diode or a

Photodiode chip is produced.

In accordance with at least one embodiment, this includes

Method is the step of providing a

Growth substrates. The growth substrate is to

furnished, then epitaxially one

To produce semiconductor layer sequence. In which

Growth substrate is, for example, a

Sapphire substrate, a Siliziumcarbidsubstrat or even to a Silicon substrate. An upper side of the growth substrate on which the semiconductor layer sequence is deposited may be structured or smooth.

In accordance with at least one embodiment, the method comprises the step of generating a semiconductor layer sequence on the growth substrate. In this case, the semiconductor layer sequence preferably comprises an n-side, a p-side and an active layer arranged between these sides. The n-side is n-doped and may be formed by one or more layers. Accordingly, the p-side is p-doped and may also comprise one or more layers.

The active layer has one or more pn junctions or one or more quantum well structures. It is the active layer set up in the operation of the

Semiconductor chips preferably to generate electromagnetic radiation. For example, in the active layer visible light, ultraviolet radiation and / or

generates near-infrared radiation.

In accordance with at least one embodiment, the n side of the semiconductor layer sequence is closest to the growth substrate. It is possible that the n-side is in direct contact with the growth substrate or that there is a buffer layer between the n-side and the growth substrate. This buffer layer then preferably touches both the n-side and the growth substrate.

In accordance with at least one embodiment, the method comprises the step of doping the n-side. The doping takes place here by means of ion implantation. In other words, then the dopants with which the corresponding doping is achieved, not or not predominantly already incorporated during the epitaxial growth in the semiconductor layer sequence, but the dopants are completely or at least for the most part only subsequently the

Semiconductor layer sequence added by ion implantation.

In accordance with at least one embodiment, the doping of the n-side takes place through the active layer. It is then grown on the n-side before doping with ion implantation then at least the active layer.

In at least one embodiment, the method is for producing an optoelectronic semiconductor chip

set up. It includes the process at least the

following steps, preferably in the order given:

Providing a growth substrate,

Generating a semiconductor layer sequence on the

A growth substrate, wherein the semiconductor layer sequence has an n-side, a p-side, and an active layer for generating radiation, and the active layer is disposed between the p-side and the n-side, and preferably the n-side is closest to the growth substrate located, and

- Doping the n-side and / or the p-side through the active layer by means of ion implantation.

In such a method, in particular, a good cross-conductive semiconductor layer by subsequent

Introducing doping atoms or doping ions generated after a growth of the semiconductor layer sequence.

In the growth of semiconductor materials such as GaN, it can by the use of dopants in high concentrations when growing itself, morphological disturbances occur. Furthermore, doping during growth may increase strain of GaN. This can become one

greater deflection of a growth substrate in the

Growth temperatures result. This in turn can cause a more inhomogeneous temperature distribution on the

Growth substrate, which is especially critical in heteroepitactically deposited structures on substrates with a relatively large diameter and turn

Morphology disorders, especially so-called pits and

Cracks, can cause.

In particular, the growth of GaN on a foreign substrate such as sapphire or silicon is typically first island-like, for example, by means of a masking layer and then to a coherent layer. This growth is also known as SD growth. If a coherent layer is reached, it will grow evenly

Layer. The latter growth phase is also referred to as 2D growth.

In order to ensure adequate crystal quality, only comparatively low dopant concentrations, for example less than 5 × 10 3 / cm 2, can be used during 3D growth. During the 2D growth can

Dotierstoffkonzentrationen be realized to about 1.5 x lO ^ / ccrn. The higher dopant concentrations can result in a higher bending of the growth substrate, which may result in a more inhomogeneous temperature distribution on the growth substrate. Due

comparatively low, possible dopant concentrations, the transverse conductivity is limited, in particular in a buffer layer. Morphological defects such as so-called pits and Cracks are also increasing at high

Dopant concentrations on.

Through the use of ion implantation, a dopant can subsequently be introduced into a host crystal. During epitaxy, comparatively lightly doped semiconductor layers can thus be grown, in particular with a homogeneous dopant content which does not or hardly varies along a growth direction. This results in less sagging of the growth substrate during epitaxy, along with a more homogeneous one

Temperature distribution and increased quality of

grown semiconductor layer sequence connected. A

Reduced deflection of the epitaxial substrate also results in a lowered minimum process temperature. This can extend plant life and a

Particle generation can be reduced.

Furthermore, it is possible by ion implantation

subsequently higher dopant concentrations up to an interface of the semiconductor layer sequence to the

Achieve growth substrate, which is not possible in particular in the case of GaN during epitaxy, due to the limited dopant concentrations in the SD growth phase. This allows the use of

Growth substrates, in particular with diameters of over 4 inches, corresponding to approximately 10 cm. By higher

Dotierstoffkonzentrationen at this interface is also a higher transverse conductivity of the growth of the substrate nearest layer of the semiconductor layer sequence

achievable. It is therefore possible to decouple dopant profile and deflection during epitaxy, accompanied in particular with an improved transverse conductivity and a reduced contact resistance.

According to at least one embodiment of the method, the semiconductor layer sequence before doping by means of

Ion implantation of the n-side completely generated. This may mean that no further epitaxy step takes place after doping by means of ion implantation of the n-side. This allows a particularly efficient production, since the entire semiconductor layer sequence can be grown in one piece.

According to at least one embodiment, a

Dopant profile of an n-type dopant within the n-side a global maximum, based specifically on the entire

Semiconductor layer sequence and on the growth substrate, on. Furthermore, the dopant profile shows a steady course. The dopant profile may take the form of a bell curve or an asymmetric bell curve, also called skewed

Gaussian.

In accordance with at least one embodiment, the doping of the n-side takes place with silicon and / or with germanium. If a co-doping of silicon and germanium is used, it is possible that the two maxima of the dopant profiles for silicon and for germanium are at different locations. For example, the dopant profile for

Silicon have a maximum in a greater depth of the semiconductor layer sequence than the dopant profile for

Germanium.

According to at least one embodiment, in addition to

Dopant for the n-doping of the n-side, in addition Nitrogen implanted. It is possible that the nitrogen has a concentration maximum after ion implantation at a greater or even a lower depth than the n-type dopant.

In accordance with at least one embodiment, the nitrogen and / or the at least one dopant for the n-side is implanted as far as or into the growth substrate. In other words it is possible that in the

Growth substrate or at an interface between the

Growth substrate and the semiconductor layer sequence is present a nonzero dopant concentration of the n-type dopant. In this case, the concentration of the n-type dopant at the interface between the growth substrate and the semiconductor layer sequence is, for example, at least 5 × 10 18 / cm 2 or at least 1 × 10 19 / cm 2.

In accordance with at least one embodiment, the n-side doping is performed with an ion energy of at least 250 keV or of at least 300 keV or of at least 350 keV.

Alternatively or additionally, the energy is the

implanted ions during implantation at most 1.3 MeV or at most 1.0 MeV or at most

800 keV.

In the publication S.O. Kucheyev "Ion Implantation Into GaN" in Materials, Signs and Engineering, Volume 33, pages 51 to 107 from 2001 describes an ion implantation of GaN The disclosure of this document is incorporated by reference.

In accordance with at least one embodiment, the doping of the n-side takes place by means of ion implantation at a temperature the semiconductor layer sequence and the growth substrate of at least 350 ° C or at least 450 ° C or from

at least 500 ° C. Alternatively or additionally, this temperature is at most 950 ° C or at most 750 ° C or at most 600 ° C.

In accordance with at least one embodiment, an n-dopant concentration is the n-side before

Ion implantation in places or on average at most 5 x 1018 / cc or at most 1 x 10l / cm. In other words, before doping by ion implantation, the n-side is substantially undoped. Prior to ion implantation, the n-side may be an intrinsically conductive layer or sub-layer sequence.

In accordance with at least one embodiment, the n-side after doping by means of ion implantation has an n-dopant concentration of at least 2 × 10 19 / ccm or of at least 5 × 10 19 / ccm or of at least 1 × 10 20 / ccm.

The dopant concentration after doping by ion implantation may be an average

Dopant concentration or by a maximum

Dopant concentration act.

According to at least one embodiment, doping the n-side by ion implantation is followed by thermal annealing.

According to at least one embodiment, the annealing takes place at a temperature of at least 700 ° C or from

at least 850 ° C or at least 950 ° C. Alternatively or additionally, the annealing temperature is at most 1250 ° C or at most 1100 ° C or at most 975 ° C. According to at least one embodiment, the annealing takes place for a duration of at least 3 minutes. or at least 5 min. or at least 10 min. It is alternatively or additionally possible that the annealing at most 30 min. or at most 20 min. or at most 15 min. lasts. The higher the temperature during healing, the shorter it will take

Healing usually.

In accordance with at least one embodiment, a cover layer on the semiconductor layer sequence is formed before annealing

applied. The cover layer may be a

Aluminiumnitridschicht act a silicon nitride layer or even to an AlGaN layer. Due to the covering layer, leakage of nitrogen from the semiconductor layer sequence during annealing can be prevented or reduced. It is possible that the cover layer is partially or completely removed from the semiconductor layer sequence after the annealing. Likewise, the covering layer may be at least in places, for example, as a passivation on the semiconductor layer sequence

remain.

According to at least one embodiment, the

Semiconductor layer sequence on a III-V

Compound semiconductor material. In the semiconductor material is, for example, a nitride compound semiconductor material such as Al _n _In] __ _n _ _m Ga _m N or a phosphide compound semiconductor material such as Al _n _In] __ _n _ _m Ga _m P or an arsenide compound semiconductor material such as Al _n In _] __ _n _ _m Ga _m As, where each 0 ^ n <1, 0 ^ m <1 and n + m ^ 1. In this case, the semiconductor layer sequence may have dopants and additional constituents. For the sake of simplicity, however, only the essential components of Crystal lattice of the semiconductor layer sequence, that is, Al, As, Ga, In, N or P, indicated, although these may be partially replaced by small amounts of other substances and / or supplemented. The semiconductor layer sequence is preferably based on AlInGaN.

According to at least one embodiment, a thickness of the p-side is at least 80 nm or at least 100 nm or at least 200 nm or at least 400 nm. Alternatively or additionally, the thickness of the p-side is at most 1.5 ym or at most 1.2 ym or at most 800 nm.

According to at least one embodiment, the active

Layer has a thickness of at least 2.5 nm or at least 5 nm and / or a thickness of at most 50 nm or of

at most 30 nm.

In accordance with at least one embodiment, a thickness of the n-side is at least 1.0 μm or at least 1.5 μm or at least 2.5 μm. Alternatively or additionally, the thickness of the n-side is at most 6.5 ym or at most 5 ym or at most 4.5 ym. The aforementioned thicknesses can each be medium thicknesses.

In accordance with at least one embodiment, the doping of the n-side, which is carried out by ion implantation, takes place at an angle of at least 5 ° or at least 7 ° and / or at most 12 ° or at most 10 °, relative to a perpendicular to a growth surface of the growth substrate. In other words, the ions then become oblique to the

Growth substrate implanted. According to at least one embodiment of the method, the doping of the n-side takes place by means of ion implantation with a dose of at least 4 × 10 ¹⁵ / cm ^z or of at least 7 × 10 ¹⁵ / cm ^z . Alternatively or additionally, the dose is at most 8 x 10 ¹⁶ / cm or at most 3 x 10 ¹⁶ / cm

In accordance with at least one embodiment, the n-side is exposed in places by removing the active layer and the p-side. This partial exposure is preferably carried out after complete growth of the semiconductor layer sequence and preferably also after doping the n-side.

According to at least one embodiment, an electrical contact point is generated at least on partial areas of the exposed locations of the n-side. The contact point is preferably formed by one or more metallizations. About the electrical contact point is the

Semiconductor chip electrically contactable. For example, the electrical contact point is a bonding pad.

In accordance with at least one embodiment, the entire n-side, seen in plan view, is doped. In other words, the area doped by ion implantation then has the same surface area as the n-side and / or like the active layer, in particular in plan view of FIG

Wax surface seen.

According to at least one embodiment, only one

Partial region of the n-side doped by ion implantation, viewed in plan view of the growth surface. At least a portion of the n-side and / or the p-side, seen in plan view, is then not so by ion implantation doped. For example, under the

Manufacturing tolerances only such a portion doped by ion implantation, the electric

Contact point, preferably the contact point for the p-side, is covered, seen in plan view and preferably with a tolerance of at most 75% or at most 50% or at most 25% of the area of the corresponding contact point. It is possible that the n-side is doped in this doped region to a high transverse conductivity.

Alternatively or additionally, in this area, in

Seen from the top, radiation generation in the active layer be reduced or suppressed. Through this doped region can also be reduced contact resistance to the metallic, electrical contact point.

In addition, an optoelectronic semiconductor chip is specified. The optoelectronic semiconductor chip is preferably produced by a method as in connection with one or more of the abovementioned embodiments

described. Features of the semiconductor chip are therefore also disclosed for the method and vice versa.

In at least one embodiment, the

Optoelectronic semiconductor chip on a carrier and a mounted on the carrier semiconductor layer sequence. The semiconductor layer sequence comprises an n-side, a p-side and an active layer provided for generating radiation. The active layer is located between the p-side and the n-side. A dopant profile of an n-type dopant has a global maximum within the n-side. The dopant profile exhibits a steady course, at least with regard to an n-dopant and within the n-side. Hereinafter, a method described herein and an optoelectronic semiconductor chip described herein with reference to the drawings using exemplary embodiments will be explained in more detail. The same reference numerals indicate the same elements in the individual figures. However, there are no scale relationships shown, but individual elements can be shown exaggerated for better understanding.

Show it:

Figure 1 is a schematic representation of a

Embodiment of one described here

Method for producing an optoelectronic semiconductor chip described here, and

Figures 2 to 5 are schematic sectional views of

Embodiments of optoelectronic semiconductor chips described here.

FIG. 1 is a schematic sectional view of a method for producing an optoelectronic device

Semiconductor chips 1 illustrated. According to Figure 1A is a

Growth substrate 2 with a growth surface 20

provided. The growth substrate 2 is, for example, a sapphire substrate.

According to Figure 1B is on the growth surface 20 a

Semiconductor layer sequence 3 in particular epitaxially

applied. The semiconductor layer sequence 3 has an n-side 31, an active layer 32 and a p-side 33. The active layer 32 is located between the n-side 31 and the p-side 33. The n-side 31 is located closest to the growth substrate 2, and the p-side 33 is farthest from the growth substrate 2. The said layers 31, 32, 33 preferably follow immediately in the specified

Order on each other.

The n-side 31 and the p-side 33 can each be formed by a plurality of partial layers. In particular, the n-side 31 may have unskilled buffer layers, growth layers, masking layers, and / or intermediate layers that differ in their material composition

can distinguish. The semiconductor layer sequence 3 is preferably based on AlInGaN and is suitable for the production of

set up, for example, blue light.

Optionally, a covering layer 4 is produced on a side of the p-side 33 facing away from the growth substrate 2 according to FIG. 1B, for example by epitaxial growth or by

Sputtering. A thickness of the covering layer 4 is, for example, at least 20 nm or at least 25 nm and / or at most 500 nm or at most 250 nm. The covering layer 4 is preferably made of one for atomic or gaseous

Nitrogen impermeable or poorly permeable material formed.

In the case of the n-side 31, the method step according to FIG. 1B is preferably an undoped or im

Essentially undoped layer or sub-layer sequence.

In the method step, as illustrated in FIG. 1C, the n-side 31 is doped by ion implantation through an ion beam I through the active layer 32. Of the

Ion beam I is oriented obliquely to the growth surface 20. Other than illustrated, it is possible that multiple ion beams with different components such as

Silicon, germanium and / or nitrogen find use.

FIG. 1C further schematically illustrates a dopant profile P of a dopant concentration c in the direction perpendicular to the growth surface 20. The dopant profile P is shaped similar to a bell curve or a distorted bell curve and has a maximum M within the n-side 31. The dopant profile P preferably has a continuous, smooth course. The dopant profile P may be a differentiable curve.

It is possible that a dopant concentration at an interface between the growth substrate 2 and the

Semiconductor layer sequence 3 has a value greater than 0. In particular, the ions from the ion beam I can penetrate into the growth substrate 2. The active layer 32 is preferably free or substantially free of ions from the ion beam I. To achieve this, the optional cover layer 4 and the active layer 32 and the p-side 33 are preferably made as thin as possible.

Unlike in FIG. 1B, it is possible for the covering layer 4 to be applied to the semiconductor layer sequence 3 only after the step according to FIG. 1C, that is, after the ion implantation.

In Figure 1D is a thermal annealing, English

annealing, illustrated schematically. By an increased

Temperature can be generated by the ion beam I

Lattice damage in the semiconductor layer sequence 3 at least partially heal. By thermal annealing, it is possible that the

Dopant profile P 'compared to that in Figure IC

widened immediately after doping dopant profile P. Preferably, however, no or no significant change in the thermal annealing occurs

Dopant profiles P.

Optionally, the cover layer 4 after the thermal

Heal partially or completely removed.

Further process steps for the production of

Semiconductor chips 1 as a singling, attaching

electrically conductive layers, attaching

electrical contacts, an attachment of

Passivation layers and / or the generation of

Lichtauskoppelstrukturen are to simplify the

Representation in Figure 1 not shown.

Another embodiment of the semiconductor chip 1 is illustrated in connection with FIG. The n-side 31 is exposed by partially removing the active layer 32 and the p-side 33 in places. On the exposed

In the region of the n-side 31, an electrical contact point 5b is applied in the form of a metallization. The contact point 5b is located, for example, at a corner of

Semiconductor chips 1, seen in plan view.

Optionally, a current spreading layer 6 is attached to the p-side 33. The current spreading layer 6 is formed of, for example, a transparent conductive oxide such as ITO. Optionally, it is possible that the covering layer 4 shown in connection with FIG. 1 and the current spreading layer 6 are formed by the same layer. At the

Current spreading layer 6 is preferably located on a side facing away from the growth substrate 2 another

electrical contact point 5a, for example in the form of a bond pad.

In the semiconductor chip 1, as shown in FIG. 2, the growth substrate 2 is on the semiconductor layer sequence 3

remained. Not shown on the semiconductor layer sequence 3 and / or on the growth substrate 2

Be formed Lichtauskoppelstrukturen. It is optionally possible for a mirror 7, for example with or made of silver or aluminum, to be located on a side of the growth substrate 2 facing away from the semiconductor layer sequence 3.

The semiconductor chip 1, as shown in FIG. 3, is a so-called flip-chip. The semiconductor chip 1 as shown in FIG. 3 is preferable to one

Surface mounting set up. The current spreading layer 6 is in particular designed as a mirror 7 and can thus have a reflective effect. A radiation decoupling from the semiconductor chip 1 out then preferably takes place through the growth substrate 2, which at the

Semiconductor layer sequence 3 has remained.

Another embodiment of the semiconductor chip 1 is illustrated in FIG. In this semiconductor chip 1, the growth substrate is removed from the n-side 31, and a support 8 is attached to the p-side 33. The carrier 8 is formed, for example, from a ceramic such as aluminum nitride or aluminum oxide or from a metal such as molybdenum or from a semiconductor such as germanium or silicon. It may be the carrier 8, not shown electrical contacts or electrical vias to an electrical

Interconnection and contacting of the semiconductor chip 1

exhibit .

On the p-side 33 is the electrical contact point 5a, which can cover the p-side 33 substantially over the entire surface. In the direction away from the p-side 33, there is the second contact point 5b, which extends through a via 55 into the n-side 31 through the active layer 32. The via 55 is formed, for example, by a metal and has a contact surface 50 to a material of the n-side 31. On a support 8

opposite surface of the n-side 31 is optionally a

Lichtauskoppelstruktur generated.

It is possible that the electrical contact points 5a, 5b are also designed as mirrors 7. Other than illustrated, the active layer 32 may be of a variety of types

Through holes 55 be penetrated.

By the ion implantation after the epitaxial generation of the semiconductor layer sequence 3, it is possible that the n-side 31 has a high lateral electrical conductivity and that a contact resistance to the pads 5b is reduced. As a result, a more efficient and also more uniform energization of the active layer 32 can be realized. The

Contact area 50 and / or pad 5b may be in or near a maximum of the dopant profile, compare Figures IC and ID.

In the embodiment, as shown in Figure 5, only a portion of the n-side 31 is n-doped by ion implantation. In FIG. 5, this subregion is represented by a Hatch marked. It is this sub-area, seen in plan view, congruent under the n-pad 5. This subarea touches the n-pad 5 preferred. This doping by means of ion implantation in the subregion is produced before the carrier 8 is connected to the substrate

Semiconductor layer sequence 3 attached and before the

Growth substrate, not shown in Figure 5, is removed.

Notwithstanding the representation in FIG. 5, it is possible for this subarea not to extend below the entire n-contact point 5 or for this subarea to project laterally beyond the n-contact point 5. If the p-contact point not shown in FIG. 5 does not extend to the entire semiconductor layer sequence 3, then corresponding

in terms of doping by ion implantation

alternatively or additionally apply to the p-contact point.

In the n-side 31 is preferably a roughening for

Improved a Lichtauskoppeleffizienz shaped. Optionally, the roughening of the cover layer 4 and / or the

Stromüberweitungsschicht 6 covered, which layer 4, 6 of the roughening may be reshaped or, unlike

drawn, planarizing and smoothing the roughening

can be trained. The contact point 5 can touch the n-side 31 and completely penetrate the layer 4, 6.

In the semiconductor chip 1, as illustrated in FIG. 5, the growth substrate is removed and replaced by the support 8 located on the p-side 33. The mirror 7 is optionally located between the carrier 8 and the semiconductor layer sequence 3. Likewise, the growth substrate can also remain on the semiconductor layer sequence 3, analogously to FIGS. 1 to 3. Such doping, which is limited to a partial area preferably congruent with the electrical contact point 5, 5a, 5b, 50, can also be seen in FIGS. 2, 3 and 4

Find use. In this way, in particular a reduced contact resistance between the semiconductor layer sequence 3 and the contact point 5, 5a, 5b, 50 can be achieved. In such doped portions, in particular in connection with the figures 2 to 4, a possibly by the

Ion implantation impaired area of the active layer 32 before applying the n-type pad 5b, 50 removed, so that annealing can be omitted after the ion implantation.

In FIGS. 1 to 5, the subsequent doping was respectively generated in the n-side 31. Alternatively or additionally, it is also possible for the subsequent doping to take place in the p-side 33, if appropriate through the active layer 32.

The invention described here is not by the

Description limited to the embodiments.

Rather, the invention encompasses any novel feature as well as any combination of features, including in particular any combination of features in the claims, even if this feature or combination itself is not explicitly stated in the patent claims or exemplary embodiments.

This patent application claims the priority of German Patent Application 10 2012 109 590.6, the disclosure of which is hereby incorporated by reference.

Claims

claims

1. A method for producing an optoelectronic

Semiconductor chips (1) with the steps:

Providing a growth substrate (2),

Generating a semiconductor layer sequence (3) on the growth substrate (2), wherein the

Semiconductor layer sequence (3) has an n-side (31), a p-side (33) and an active layer (32) provided for generating radiation, and the active layer (32) between the p-side (33) and the n-side. Page (31) is arranged, and

- Doping the n-side (31) or the p-side (33) through the active layer (32) through means

Ion implantation.

2. Method according to the preceding claim,

in which the n-side (31) is closest to the growth substrate (2) and the n-side (31) by means of

Ion implantation is doped,

wherein the semiconductor layer sequence (2) is completely generated before doping the n-side (31) and a

Dopant profile (P) of an n-type dopant within the n-side (31) has a global maximum (M) and shows a steady course.

3. The method according to any one of the preceding claims,

in which the doping of the n-side (31) with silicon and / or germanium takes place.

4. Method according to the preceding claim,

in which additional nitrogen is implanted.

5. The method according to the preceding claim, wherein the nitrogen partially into the

Growth substrate (2) is implanted into it.

6. The method according to any one of the preceding claims,

wherein the doping of the n-side (31) is at an energy of between 250 keV and 1.3 MeV and at a temperature between 450 ° C and 750 ° C inclusive.

7. The method according to any one of the preceding claims,

in which, before the doping by ion implantation, an n-type dopant concentration of the n-side (31) is at most 5 x ΙΟ- ^ cm ^~ is 3,

wherein after doping by ion implantation, the n-type impurity concentration of the n-side (31) is at least 5 x ₁₀ 19 ^cmJ .

8. The method according to any one of the preceding claims,

wherein the doping of the n-side (31) is followed by a thermal anneal.

9. Method according to the preceding claim,

in which the annealing is carried out at a temperature between 850 ° C and 1250 ° C inclusive for a duration of between 3 minutes and 20 minutes, wherein prior to annealing a cover layer (4) made of aluminum nitride, silicon nitride or AlGaN applied to the semiconductor layer sequence (3) becomes.

10. The method according to any one of the preceding claims,

in which the semiconductor layer sequence (2) is based on AlInGaN,

wherein a thickness of the p-side (33) between including 0.2 ym and 1.2 ym, the active layer (32) has a thickness between 2.5 nm and 50 nm inclusive, and an n-side thickness (31) between 1.5 ym and 6.5 inclusive ym is.

11. The method according to any one of the preceding claims,

wherein the growth substrate (2) is a sapphire substrate,

wherein the doping of the n-side (31) by means of

Ion implantation at an angle between

including 5 ° and 12 °, based on a solder to a growth surface (20) of the growth substrate (2).

12. The method according to any one of the preceding claims,

in which the doping of the n-side (31) by means of

Ion implantation with a dose between

including 4 x 1015 cm 2 _U and 8 x ΙΟ ^ cm 2.

13. The method according to any one of the preceding claims,

wherein the n-side (31) is in places by removing the active layer (32) and the p-side (33)

is exposed,

wherein an electrical contact point (5) in the form of at least one metallization is produced at least on partial areas of these exposed locations of the n-side (31).

14. The method according to any one of the preceding claims,

in which the doping of the n-side (31) or the p-side (33) through the active layer (32) by means of ion implantation onto a subregion of the n-side (31) covered by an electrical contact point (5) and / or the p-side (33) is limited, in

Top view seen and with a tolerance of at most 50% of the area of the contact point (5),

the subregion leads to a reduction in a

Contact resistance between the

Semiconductor layer sequence (3) and the contact point (5) is arranged.

Optoelectronic semiconductor chip (1) with

a carrier (2, 8),

- One on the support (2, 8) attached

Semiconductor layer sequence (3) with an n-side (31), a p-side (33) and one to a

Radiation generation provided active layer (32) between the p-side (33) and the n-side (31), wherein a dopant profile (P) of an n-type dopant within the n-side (31) has a global maximum (M) and shows a steady course.