WO2014040588A1

WO2014040588A1 - Hf power inverter circuit, hf power inverter system, and method for switching a switching element on and off

Info

Publication number: WO2014040588A1
Application number: PCT/DE2013/100320
Authority: WO
Inventors: Sebastian Fecker
Original assignee: TRUMPF Hüttinger GmbH + Co. KG
Priority date: 2012-09-13
Filing date: 2013-09-10
Publication date: 2014-03-20
Also published as: DE102012216326A1; DE102012216326B4

Abstract

The invention relates to an HF power inverter circuit (100) comprising at least one switching element (12, 13, 17, 18) that has a control connection to which a control arrangement (30) is connected, said control arrangement switching the switching element (12, 13, 17, 18) on and off. The control arrangement has a programmable logic unit that has a first signal delay path (37, 38), which comprises at least one logic element, for delaying at least one switch-on signal part and a second signal delay path (37, 38), which is different from the first signal delay path (37, 38) and which comprises at least one logic element, for delaying at least one switch-off signal part.

Description

DESCRIPTION

RF power inverter circuit, RF power inverter system and method of turning on and off a switching element

The invention relates to an RF power inverter circuit having at least one switching element, which has a control terminal to which a drive arrangement is connected, which switches the switching element on and off, and an RF power inverter system and a method for switching on and off of a switching element ,

An RF power inverter circuit can be used to generate RF power, in particular power with an output frequency of> 1 MHz. Such RF power inverter circuits can be used, for example, to generate a plasma. An RF power inverter circuit may be formed, for example, as a Class D amplifier with a switching bridge. A switching bridge has at least two switching elements, such. As MOSFETs, IGBTs or bipolar transistors, which are connected in series and are operated in push-pull. A switching bridge with two switching elements (also referred to below as switching elements or (semiconductor) switches) is also called half bridge or bridge branch. A switching bridge with four switching elements is usually made of two half-bridges or

Bridge branches built.

Many modes and constructions of RF power inverter circuits are known. An alternative RF power inverter circuit may be formed, for example, as a Class E amplifier with a single transistor as a switching element. In this case, several switching elements can be connected in parallel Another construction is a push-pull stage with two complementary switching elements, which are connected together at one point.

The switching elements also have a control connection in addition to their power connections. Depending on the configuration of the switching element, the control connection is referred to as a gate (for example, in the case of an IGBT or FET, in particular a MOSFET), or a base (for example, in the case of a bipolar transistor). Each control connection is usually associated with a driver via which a control signal is supplied to the control terminal.

The switching commands for turning on and off a switching element are typically low power logic signals, e.g. as an output of a computer control, available. For switching, however, the switching elements require a power signal as a drive signal.

Therefore, drivers are usually provided which generate a drive signal from the on / off commands.

The transit times of the logic signal generating assemblies, (e.g., computer controllers) via drivers and possibly also

Signal transformers up to the switching elements are included

high-frequency drives above 1 MHz often already very different. When multiple switching elements are driven, an inaccurate turn-on and / or turn-off edge will result in losses and voltage spikes. For example, two switching elements may be unintentionally switched on at the same time for a short period of time due to inaccurate switching times and thus generate a short-circuit current that generates lost heat and can destroy components.

Object of the present invention is to show a different approach to control switching elements so that they are switched on or off at a predetermined switching time.

This object is achieved according to the invention by an RF power inverter circuit having at least one switching element having a control terminal to which a drive arrangement is connected which switches the switching element on and off, wherein the drive arrangement has a programmable logic module which at least one first Encompassing a logic element

Signal delay path for delaying at least one

Turn-on signal part and a second of the first

Signal delay path has various second at least one logic element signal delay path for delaying at least one switch-off signal part. According to the invention, therefore, two different signal delay paths are defined, namely one for a switch-on signal part and one for a switch-off signal part. For example, a turn-on signal part may be the rising edge of an input signal, while a turn-on signal part may be a rising edge of an input signal

Off signal part to the falling edge of an input signal can act. The rising and falling edges of an input signal can thus be delayed differently so as to exactly reach a switch-on or switch-off time. Such an HF Leistungsinverterschaltung is particularly immune to interference, since the

Drive arrangement can be formed completely digital at least up to a driver. With the arrangement according to the invention it is possible, a high-frequency signal, for example an input signal or parts of such a signal with a frequency of 13.56 MHz, in pulse width and phase very high resolution, for example in steps of 500 ps, in particular 300 ps and especially preferably 100 ps to delay up to 360 °. In this way, component tolerances and signal transit times can be compensated and adjusted.

There may be provided a combining element which combines the delayed turn-on signal part and the delayed turn-off signal part into a switching command signal. Thus, from the respective separately delayed turn-on signal parts and turn-off signal parts

Switch command signal are generated, wherein the start-stop times (pulse width) and the phase relationship of a plurality of switching command signals are adjustable to each other.

The combination element can be arranged in the programmable logic module. Thus, a switching command signal given to a driver chip can be completely generated in the programmable logic chip. This results in a single-chip solution. This is associated with a huge cost advantage. In addition, such a solution is very space-saving to arrange on a printed circuit board, compared to existing solutions.

The first and second signal delay paths may be programmed. Thus one does not need an existing one

Signal delay path to be measured in order to determine a signal propagation time, but it is possible deliberately set signal propagation times, by selecting or programming signal delay paths appropriately.

The first and / or the second signal delay path may be a

Cascading of several logic elements have. By the

Cascading of different logic elements different delay times can be set.

The logic elements can be designed as so-called look-up tables (look-up tables, LUT). In particular, logic elements of a Field Programmable Gate Array (FPGA) may be cascaded to affect signals in their propagation time and generate switching command signals that are high resolution in start, stop, and phase relationships. In particular, specific gate delays of

Logic elements of an FPGA can be used to set propagation delays of signals. A particular delay can be generated in particular by programming or linking (also called "routed") a selection from a series connection of a predefinable number of look-up tables, each of which causes a delay cascaded look-up tables different

Cause delays. Depending on the composition of

different numbers of look-up tables can thus

different signal propagation times are set.

All LUTs within a block can have multiple inputs with different runtimes, but they are clearly defined and individually programmable. All LUTs have at least one programmable runtime that coincides with a runtime of another LUT, in particular one adjacent, almost identical. This allows you to program run times very precisely.

By cascading / omitting multiple LUTs in a chain, a different delay is achieved. In this case, the linking can be done with appropriate software tools such that the exact location of the LUT and the connections is selected to ensure the most accurate setting and not inaccuracies through maturities on lines in purchasing.

In order to generate a drive signal, which can be supplied to the switching element, a driver may be provided, which is arranged between the programmable logic module and the control terminal of the switching element. The driver generates a signal which is suitable for triggering a switching operation on the switching element.

There may be provided a plurality of switching elements, wherein the programmable logic device for the switch-on signal part and the switch-off signal part of each switching element has its own

Signal delay path has. Thus, the inputs and

Off times for each switching element are set individually. As a result, the times in which both switching elements of a half-bridge are switched off can be minimized. Also, phase relationships between drive signals of two switching elements can be set exactly.

The RF power inverter circuit may comprise at least two switching elements forming a half-bridge. Furthermore, the HF Power inverter circuit having at least four full bridge forming switching elements.

In this way, another advantage can be achieved. Of the

Connection point of the switching elements in a half or

Full bridge represents the center of a bridge branch. The center of the bridge branch is formed by the two switching elements

alternately to a positive or negative pole one

DC power source, which has a certain operating voltage switched. The alternating control of the two switching elements and the switching elements of a possibly existing second bridge branch is effected by a drive arrangement comprising an oscillator, the

Frequency of the output signal determined, and may contain other components, such as phase shifter and signal conditioner. An additional capacitor for the release of the output signal of one

DC voltage component can be provided if only one half-bridge is provided.

A full bridge circuit consists of two bridge branches

(Half bridges), the midpoints are switched in each case in opposite directions to the positive and negative poles of the DC power source with the desired frequency. The AC load is placed between these two centers. An additional capacitor to free the output signal from a DC component is not necessary. When operating jumpers which are supplied with a voltage source, care must be taken that never both switching elements of a half-bridge are switched on at the same time, as otherwise a short-circuit with possible destruction of the switching elements or other components may occur. When operating jumpers that are supplied with a power source, make sure that never both switching elements of a half-bridge are switched off at the same time, otherwise there will be overvoltages with possible destruction of the

switching elements or other component can come.

On the other hand, the time span in which neither of the two or both switching elements of a half-bridge conduct, should be as short as possible in order to prevent excessive switching of the body diodes of the switching elements, because otherwise the time for their charge carrier degradation is too long. The switching elements must therefore be exactly synchronized. The problem is when the delay times between the switching commands and the switching times are not the same for each switch. The delay times depend on the geometry of the circuit in which the switches are located, the line length in the circuit

Drive arrangement, the control terminals and possibly other components, the copies scattering of the switches and the driver but also the copy scattering of other components, such as a signal transformer from. It therefore comes at runtime differences of the signals to control the switching elements, which means that the switching times of the individual switches in response to a

Switching command may be different. In accordance with the invention, transit time differences can be compensated or travel times can be set exactly.

The RF power inverter circuit may comprise at least two switching elements forming a push-pull stage.

The RF power inverter circuit may comprise at least one switching element operating in class E operation.

In all these modes and constructions of an RF power inverter circuit, further advantages can be achieved. Around To avoid switching losses, there should be no significant voltage differences between the two power electrodes (generally the drain and source of the respective MOSFETs) at the time of switching on the individual switching elements. This switching behavior is referred to as Zero Voltage Switching (ZVS). One achieves this among other things by suitable design of the output network. With a suitable dimensioning of the components, taking into account their parasitic properties as well as correct selection of the switching / waiting time of the switching element, the potential at this instant not connected to the DC power source connection is just as high as the potential at that terminal of the DC power source, which now with this terminal of the Switching elements to be switched on.

The output network may include a power transmitter.

Alternatively or in addition to the power transformer (also

Called output transformer) further impedances may be provided which allow zero-volt switching, z. As a load, in particular plasma load or laser, including possible outer circles or

Impedance matching circuits.

The RF power inverter circuit according to the invention can have a plurality of switching elements connected in parallel, wherein each switching element is connected to its own signal delay path.

The switching elements may be directly interconnected at their output terminal.

The switching elements may be interconnected at their output terminal via matching networks. The switching elements can be interconnected at their output terminal via combiners (combiners, power couplers).

By parallel operation of several switching elements, the output power can be increased. However, because the switching elements do not always work the same way and minimal inductive or capacitive differences at high frequencies have a big impact on the

Switching behavior, in particular the duration and speed, may have, it often comes to high losses in parallel operation of

Transistors. This can be avoided with this device.

The RF power inverter circuit may comprise a plurality of series-connected switching elements, wherein each switching element is connected to its own signal delay path. In this way, very high voltages can be switched over 1 kV and especially over 2 kV.

An inventive RF power inverter circuit may have switching edges of less than 30 ns rise and fall time and in particular of less than 10 ns with significantly lower switching losses and

Create combination losses.

An RF power inverter circuit according to the invention can generate powers greater than 500 W, in particular powers greater than 1 kW, with significantly lower switching losses and combining losses.

Particular advantages arise when the drive arrangement has a multiplier for duplicating a high-frequency input signal. Thus, only a single input signal is necessary. This Input signal can be supplied after the duplication of multiple delay paths, in each case one

Switch-on signal part (for example, the rising edge of the

Input signal) or a turn-off signal portion (eg, the falling edge of the input signal) are individually delayed. At least every two delayed in a delay path signal parts can be reassembled to a signal after passing through the delay paths, which then via a driver as

Drive signal can be supplied to a switching element.

Within the scope of the invention is an RF power inverter system having a plurality of RF power inverter circuits. As a result, the loss in power combiners (line couplers, combiners) can be significantly reduced, since the phase position of the output signals of the individual RF power inverter circuits can be coordinated with each other. In particular, the programmable logic components of the RF power inverter circuits can be implemented in a module, in particular in a programmable module. This reduces the need for different components and delay elements.

In addition, a significantly improved tuning of the phases

possible with each other, which significantly reduces the power loss in couplers and increases reliability.

Such an HF power inverter system can deliver power greater than 5 kW, in particular power greater than 10 kW, with significantly lower power

Generate switching losses and combination losses.

The scope of the invention also includes a method for switching on and off a switching element to a defined one

Switch-on time and switch-off time, in which in one Programmable logic device is defined in each case a delay path for a switch-on signal part and a switch-off signal part, the

Turn-on signal part and the turn-off signal part are delayed by the respectively defined delay path and the switching element is switched on based on the delayed turn-on signal part and turned off on the basis of the delayed output signal part. With such a method, it is possible to minimize the power loss in the switching element by optimally adjusting the on and off times. Furthermore, the best possible power combination with the lowest losses of two full bridges is provided by a digitally and interference-free adjustable control. In particular, your own

Delay path for rising and falling edges of a signal can be used to adjust the phase relationship between signals and the pulse width can.

The delay paths can be defined by selecting and interconnecting logic elements and interconnect lines of the programmable logic device. This can be done manually or computer assisted.

The delayed turn-on signal part and the delayed turn-off signal part may be combined into a switching command signal, which may then be amplified by a driver to a drive signal.

A driving signal for a second switching element may be generated, and the phase relationship of the driving signals may be set for the first and second switching elements. When the first and second switching elements are arranged in a bridge circuit, the bridge circuit can be operated with the lowest power losses. Furthermore, an RF signal can be multiplied as an input signal and the rising edge of a duplicated signal and the falling edge of another amplified signal can be in different

Delay paths are delayed. Thus, the

Switch-on times and switch-off times of the switching elements are set individually.

Further features and advantages of the invention will become apparent from the following description of an embodiment of the invention, with reference to the figures of the drawing, which show details essential to the invention and from the claims. The individual features can be realized individually for themselves or for several in any combination in a variant of the invention.

Preferred embodiments of the invention are shown schematically in the drawing and are explained below with reference to the figures of the drawing. Show it :

Fig. 1 a full bridge of an RF power inverter circuit;

Fig. 2 is a circuit diagram for driving two full bridges;

Fig. FIG. 3 shows a drive arrangement of an HF power inverter circuit; FIG.

Fig. 4 an alternative representation of a drive arrangement of a

RF power inverter circuit;

Fig. 5 is a diagram to illustrate the realization

Delay path; Fig. 6 a push-pull power inverter circuit;

Fig. 7 a power inverter system.

FIG. 1 shows a full bridge FBI of an HF power inverter circuit having a first half-bridge 11, which has two series-connected switching elements 12, 13, which are designed as semiconductor switches. The switching elements 12, 13 are assigned drivers 14, 15, respectively. A second half bridge 16 also has two series-connected switching elements 17, 18, with associated drivers 19, 20. The drivers 14, 15, 19, 20 are in each case connected to the control terminals of the switching elements 12, 13, 17, 18 and deliver

Drive signal for driving, i. for switching on and off, the switching elements 12, 13, 17, 18.

Between the centers M l and M2 of the first and second

Half bridge 11, 16, a load 21 is connected. The load 21 is shown schematically as an impedance, which may include the impedance of a plasma and / or an impedance matching circuit. Switch command signals may be supplied to the inputs of the drivers 14, 15, 19, 20. The generation of the switching command signals will be explained in the following figures.

FIG. 2 shows a typical circuit diagram for driving two full bridges FBI, FB2. The waveform Tl shows the drive signal of the switching element 12. The waveform T2 shows the drive signal of the switching element 13. It can be seen that the

switching elements 12, 13 are switched on and off alternately. There are never both switching elements 12, 13 at the same time

switched on.

The waveform T3 shows the drive signal of the switching element 17, while the waveform T4, the drive signal of the switching element 18 shows. The switching elements 13, 17 and 12, 18 are thus controlled so that they turn on and off at the same times. The aim of the present invention is to set the exact position of the rising and falling edges of the waveforms Tl to T4 so that the switching elements 12, 18 and 13, 17 are switched on and off exactly at the same time.

The signal curves T5 to T8 correspond to the drive signals of two further half bridges, which together form a full bridge FB2.

FIG. 3 shows a drive arrangement 30 with the aid of which

Switch command signals can be generated. This is a

high-frequency input signal 31, which has rising edges 32 and falling edges 33, in particular a signal at, for example, a frequency of 13.56 MHz, a multiplier 34 supplied. The multiplier 34 multiplies the input signal 31 into a plurality of signals 35, 36. The signal 35 is fed via a first delay path 37 and the signal 36 via a second delay path 38.

For example, in the delay path 37, only the rising edges of the signal 35 corresponding to the rising edges 32 of the signal 31 have been delayed, while in the second delay path 38, for example, the falling edges of the signal 36 corresponding to the falling edges 33 of the signal 31 are delayed. In this case, a rising edge 32 can correspond to a switch-on signal part of the signal 31 and the falling edge 33 can correspond to a switch-off signal part of the signal 31. The delayed turn-on signal parts and turn-off signal parts are present at the output of the delay path 37 and the delay path 38, respectively. The schematic illustration shows that the rising edge 32 was delayed differently than the falling edge 33. As a result, a distance t between the delayed rising edge 39 and the delayed falling edge 40 can be set. The delayed

Turn-on signal parts and turn-off signal parts are combined in pairs into pulses in the combination element 41, so that a switching command signal 42 is produced, which can be supplied to a driver. In this way, switch-on and switch-off of a switching

Elements are individually determined.

Figure 4 shows substantially the same facts as Figure 3, except that the delay paths are shown in more detail. Thus, the input signal 31 is divided by the multiplier 34 and supplied to two different delay paths 37, 38. Both delay paths 37, 38 have a plurality of so-called look-up tables LUT, wherein the signals 35, 36 do not run across all the LUTs of the respective delay path 37, 38. The

Delay paths 37, 38 are programmable. In particular, individual look-up tables LUT can be selected via which the signals 35, 36 should run. In the exemplary embodiment shown, only the look-up table 50 is selected in the delay path 37, for example, which leads to a delay of approximately 500 ps. In the delay path 38, the look-up table 51 is selected, with the result that the signal 36 also passes over the look-up tables 52, 53, so that a total of one

Delay of about 3x500ps = 1,500ps results. In combination element

41, the delayed signal parts turn to the switching command signal

42 combined. The entire arrangement 30 can be realized in a single programmable logic module, in particular an FPGA. It is understood that even more switching command signals 42 for a plurality of switching elements can be generated by an FPGA. In particular, it is possible to centrally generate all switching command signals for an HF power inverter circuit. The number of switching command signals to be generated is limited only by the resources in the FPGA. This results in a huge cost advantage, since it is a single-chip solution. The solution is also interference-proof, as it is completely digital. Compared to existing solutions, the

Arrange drive arrangement to save space on a printed circuit board. The central, digital control of the FPGA simplifies communication.

FIG. 5 shows a section of an FPGA 60. It is shown schematically here that a plurality of look-up tables 61 have been selected for realizing a delay path and it has also been determined which look-up tables 61 are interconnected by connections 62. Through the targeted selection of look-up tables 61 and their connection to one another, a delay path can be defined and the delay of a signal part brought about by the delay path can be set.

FIG. 6 shows an RF power inverter circuit 100 designed as a push-pull inverter circuit with two drive arrangements 30 according to the invention as another of many possible inverter circuits. The semiconductor switches Qi, Q ₂ are alternately turned on and off, via the choke RFC is almost one over the duration of a wave

constant current delivered. At the power output of the semiconductor switches Qi, Q ₂ is a power transformer 101 with two primary and one secondary winding 102, 103, 104. The primary windings 102, 103 are each at one end to a power output of the semiconductor switches Qi, Q ₂ interconnected. The other power connection of the

Semiconductor switch Qi, Q ₂ is connected to a common reference potential 105, preferably ground. The two primary windings 102, 103 are interconnected at their other terminal 106. The throttle RFC is also connected here. The secondary winding 104 is in turn connected at its one terminal to a reference potential, preferably ground. At the other port is the RF power. It is connected to the load R ₀ via an output network 107, in this case in the form of a parallel resonant circuit, which also acts as a filter

connected.

The semiconductor switches Qi, Q ₂ are each driven at a gate 108, 109. The control takes place with signals, as in the

Explanation of Figure 2 - Figure 5 has been described, are generated. Between drive arrangement 30 and the gates 108, 109 signal conditioning modules 111, 112 may still be arranged, which may have drivers and / or transmitters.

The RF power inverter system 1000 shown in FIG. 7 comprises a system controller 110 to which 3 RF power inverter circuits 120, 130, 140 are connected in the exemplary embodiment. The RF power inverter circuits 120, 130, 140 each include a

Control modules 150, 160, 170 and a power generation module 180, 190, 200. The outputs 210, 220, 230 of the power inverter circuits 120, 130, 140 are on a power combiner 240, too

Power coupler or combiner called, led, where the

Output powers of the power inverter circuits 120, 130, 140 are optionally phase-dependent coupled. The coupled

Total power is output at output 250 and applied to a load, not shown here. The power inverter circuits 120, 130, 140 each have measuring means 260, 270, 280, with which at least the power reflected by the load, which arrives at the power inverter circuits 120, 130, 140, can be detected. Preferably, the measuring means 260, 270, 280 are designed as directional couplers, so that both a reflected and an output power of the respective power inverter circuit 120, 130, 140 can be detected. The measured power signals related to the reflected power detected by the measuring means 260, 270, 280 are applied to a value determining unit 290, 300, 310 in the control modules 150, 160, 170. In the

Value determination units 290, 300, 310 are determined values, which are then given to the system controller 110, in particular to a determination device 320.

The determination device 320 determines the phasing of the output signals of the power inverter circuits 120, 130, 140 to be set. The phasing to be set is given by the determination device 320 to the value determination units 290, 300, 310. The system controller 110 is thus bidirectionally signaling technology with the

Power inverter circuits 120, 130, 140 connected.

The system controller 110 further includes a frequency generation unit 330, by which a high frequency excitation frequency signal is given. The frequency generation unit 330 is connected to phase adjusting devices 340, 350, 360 of the power inverter circuits 120, 130, 140. The phase adjustment devices 340, 350, 360 can be designed as phase shifters, in particular programmable logic devices, in particular as FPGAs. The phasing devices 340, 350, 360 shift that from the frequency generation unit 330 predetermined high frequency signal according to the

Value determination units 290, 300, 310 predetermined phases or

Phase positions. At the output of the modules 150, 160, 170 is thus a phase-controlled high frequency signal. This phase-locked RF signal is supplied to the RF power modules 180, 190, 200 where the respective RF power output signals are generated. The phase adjusting devices 340, 350, 360 can also be accommodated in a common building block, that is to say for example in an FPGA module 370. The value determination units 290, 300, 310 can also be accommodated in this module 370. In the the

Phase adjusters 340, 350, 360 are located in drive arrangements as shown in FIG.

Claims

claims

An RF power inverter circuit (100, 120, 130, 140) having at least one switching element (12, 13, 17, 18, Qi, Q ₂ ) having a control terminal to which a drive arrangement (30) is connected, the the switching element (12, 13, 17, 18, Qi, Q ₂ ) turns on and off, characterized in that the drive arrangement (30) comprises a programmable logic device having a first signal delay path (37, 38) comprising at least one logic element Delay of at least one Einschaltsignalteils and a second of the first signal delay path (37, 38) different second comprising at least one logic element signal delay path (37, 38) for delaying at least one turn-off signal part.

2. RF power inverter circuit according to claim 1, characterized in that a combination element (41) is provided, which combines the delayed turn-on signal part and the delayed turn-off signal part to a switching command signal (42).

3. HF power inverter circuit according to claim 2, characterized in that the combination element (41) is arranged in the programmable logic module.

4. RF power inverter circuit according to one of the preceding claims, characterized in that the first and the second signal delay path (37, 38) are programmed.

5. RF power inverter circuit according to one of the preceding claims, characterized in that the first and / or the second signal delay path (37, 38) comprises a cascading of a plurality of logic elements.

6. RF power inverter circuit according to claim 5, characterized in that the logic elements as a look-up tables formed (52, 53, 61).

7. RF power inverter circuit according to one of claims 5 or 6, characterized in that the logic elements of a field programmable gate array (60) are cascaded to influence signals in their term and generate switching command signals (42), the high resolution in Start - Stop time point and phase relationship to each other.

8. RF power inverter circuit according to one of claims 6 or 7, characterized in that all look-up tables (52, 53, 61) within a block have multiple inputs with different ^¬ term maturities that are individually programmable.

9. HF power inverter circuit according to one of the preceding claims, characterized in that the RF power ^¬ inverter circuit at least two half-bridge (11, 16) forming switching elements (12, 13, 17, 18, Qi, Q ₂ ), in particular four a full bridge (FBI) forming switching elements (12, 13, 17, 18, Qi, Q ₂ ).

10. HF power inverter circuit according to one of the preceding claims, characterized in that the HF power inverter circuit comprises at least two push-pull stage forming switching elements (Ql, Q2).

11. HF power inverter circuit according to one of the preceding claims, characterized in that the RF power inverter circuit has at least one operating in class E-mode switching element (Ql, Q2).

12. HF power inverter circuit according to one of claims 10 or 11, characterized in that the RF power inverter circuit has an output network (107) and the output network in particular a power transformer (101).

13. RF power inverter circuit according to one of the preceding claims, characterized in that the RF power inverter circuit comprises a plurality of parallel switching elements (Ql, Q2), wherein each switching element (Ql, Q2) is connected to its own signal delay path.

14. RF power inverter circuit according to claim 13, characterized in that the switching elements are interconnected directly at their output.

15. HF power inverter circuit according to claim 13, characterized in that the switching elements are interconnected at their output (Ql, Q2) via matching networks.

16. HF power inverter circuit according to claim 13, characterized in that the switching elements (Ql, Q2) are interconnected at their output via combiners.

17. HF power inverter circuit according to one of the preceding claims, characterized in that the RF power inverter circuit comprises a plurality of series-connected switching elements, wherein each switching element is connected to its own signal delay path.

18. HF power inverter circuit according to one of the preceding claims, characterized in that a plurality of switching elements (12, 13, 17, 18, Qi, Q ₂ ) are provided, wherein the programmable logic module for the switch-on signal part and the switch-off signal part of each switching element (12 , 13, 17, 18, Qi, Q ₂ ) has its own signal delay path (37, 38).

19. HF power inverter circuit according to one of the preceding claims, characterized in that the drive arrangement (30) has a multiplier (34) for duplicating a high-frequency input signal (31).

20. HF Leistungsinvertersystem (1000) with a plurality of RF power inverter circuits (100, 120, 130, 140) according to any one of the preceding claims, characterized in that the programmable logic devices of the RF power inverter circuits (100, 120, 130, 140) in a Block, in particular in a programmable block, are realized.

21. A method for switching on and off a switching element (12, 13, 17, 18, Qi, Q ₂ ) at a defined switch-on and switch-off, in which in a programmable Logic module in each case a delay path (37, 38) is defined for a Einschaltsignalteil and a Ausschaltsignalteil, the Einschaltsignalteil and the switch-off signal part by the respectively defined delay path (37, 38) are delayed and the switching element (12, 13, 17, 18, Qi , Q ₂ ) is turned on based on the delayed turn-on signal part and turned off based on the delayed output signal part.

22. The method according to claim 21, characterized in that the delay paths (37, 38) are defined by selecting logic elements (61) and connecting lines (62) of the programmable logic module and interconnecting them.

23. The method according to any one of the preceding claims 21 or 22, characterized in that the delayed turn-on signal part and the delayed turn-off signal part to a switching command signal (42) are combined.

24. The method according to any one of the preceding claims 21 to 23, characterized in that a drive signal for a second switching element (12, 13, 17, 18, Qi, Q ₂ ) is generated and the phase relationship of the drive signals for the first and second switching Element (12, 13, 17, 18, Qi, Q ₂ ) is set.

25. The method according to any one of the preceding claims 21 to 24, characterized in that an RF signal is multiplied as an input signal and the rising edge of a duplicated signal and the falling edge of another amplified signal is delayed in different delay paths.