DE102015011396A1 - Device and method for electrically connecting and disconnecting two electrical potentials and use of the device - Google Patents

Abstract

The invention relates to a device (100) and a method for electrically connecting and disconnecting two electrical potentials (1, 2). Furthermore, the invention relates to a use of the device (100). In this case, the device (100) comprises: a first module which comprises a first and a second transistor (10a, 10b), the first transistor (10a) being connected in antiseries to the second transistor (10b); and - a second module comprising a third and a fourth transistor (10c, 10d), the third transistor (10c) being connected in antiseries to the fourth transistor (10d); wherein the first module and the second module are connected in parallel.

Description

The invention relates to a device and a method for switching, d. H. for electrically connecting and disconnecting two electrical potentials. Furthermore, the invention relates to a use of the device.

Transistors, in particular field effect transistors (FET) such. As metal oxide semiconductor field effect transistors (MOSFETs) typically have one or more so-called intrinsic body diodes, which must be considered in applications in which the transistors are used.

Especially in applications where the voltage polarity across a transistor changes, unwanted cross currents can occur through its intrinsic body diode. As a result, it can happen that the transistor can not be turned off, i. H. can not be brought into an off state or in an insulating state. This is especially for clocked applications, such. This is problematic, for example, with switched capacitor (SC) converters, power factor correction (PFC) circuits, AC-DC converters, DC-AC converters, or AC switching in general. Thus, an unwanted current flow through the intrinsic body diode of a transistor can lead to a malfunction of the respective application. For example, a converter in which one or more such transistors are used as switches, especially for certain phases or clock units, may no longer function properly.

In order to avoid an unwanted current through the intrinsic body diode of a FET, there is in the prior art the possibility of dynamic switching of the backgate, d. H. of the bulk region of the transistor. However, this requires an additional driving effort and can be realized only under certain conditions or only for certain transistor types.

Another way to avoid unwanted current through the intrinsic body diode of a FET, the so-called back-to-back circuit, in which a forward polarity of body diodes is blocked by two transistors are switched antiserial.

A disadvantage of the back-to-back circuit is that the two anti-serially connected transistors of the back-to-back circuit must be made twice as large as a single transistor, so that the on-resistance R _{DS (on)} compared to the single transistor stays the same. In particular, the ratio of width W and length L of the two anti-serially connected transistors must be twice as large. This leads to a significant increase in the area consumption by a factor of 4 and a clocking control for quadrupling the drive losses P _gate .

It is therefore an object of the present invention to provide an improved apparatus and method for switching two electrical potentials. In particular, it is an object of the present invention to reduce the high drive losses that occur in a conventional back-to-back circuit. Moreover, it is an object of the present invention to provide a use of the device according to the invention.

This object is achieved by the subject matters of the independent claims. Advantageous embodiments are the subject of the dependent claims.

• – ein erstes Modul, welches einen ersten und einen zweiten Transistor umfasst, wobei der erste Transistor antiseriell zu dem zweiten Transistor geschaltet ist; und
• – ein zweites Modul, welches einen dritten und einen vierten Transistor umfasst, wobei der dritte Transistor antiseriell zu dem vierten Transistor geschaltet ist; wobei das erste Modul und das zweite Modul parallel geschaltet sind.

A first independent aspect for achieving the object relates to a device for switching or electrically connecting and disconnecting two electrical potentials. In other words, the first independent aspect of the present invention relates to a switching device for switching current between a first potential and a second potential. The device comprises:

• A first module comprising a first and a second transistor, the first transistor being connected in antiseries to the second transistor; and
• A second module comprising a third and a fourth transistor, the third transistor being connected in antiseries to the fourth transistor; wherein the first module and the second module are connected in parallel.

The transistors can z. B. FETs or SiC (silicon carbide) transistors. For example, the transistors may be MOSFETs and in particular drain extended MOSFETs (DEMOS). The transistors may also be any other types of FETs. They may be discrete or integrated transistors.

For the purposes of this invention, an antiseries circuit is generally understood to mean a circuit in which two transistors are connected in series in such a way that one terminal of the first of the two transistors connected in antiseries, in particular a source terminal, has a connection with the same name, in particular a source terminal of the second of the two transistors is connected. In other words, the transistors of an antiserial circuit are connected in series such that the intrinsic body diodes the anti-serially connected transistors are poled inversely to each other.

Each of the first and second modules can therefore be considered as a conventional back-to-back circuit per se.

With the device or circuit according to the invention a reflux blocking can be achieved, d. H. regardless of the ratio of the two potentials, an unwanted current can be avoided via the intrinsic body diodes of the transistors. Furthermore, with the device according to the invention compared to a conventional back-to-back circuit, the drive losses, especially in clocked applications, can be significantly reduced while maintaining the on-resistance.

Preferably, the first and second modules are connected in parallel such that source terminals or drain terminals of all the transistors of the first and second modules are connected to one another. In particular, each transistor has a bulk or bulk region which is connected to the source terminal of the respective transistor. The term "bonding" in the context of this invention always means an electrical connection or a short-circuiting.

In the event that the source terminals and / or bulk regions of all the transistors of the first and second modules are connected to one another, preferably the first and second modules are connected in parallel such that a drain terminal of the first transistor and a drain terminal of the third transistor are connected together. Further preferably, the first and second modules are connected in parallel in such a way that a drain terminal of the second transistor and a drain terminal of the fourth transistor are connected to one another.

In the event that the drain terminals of all the transistors of the first and second modules are connected to one another, preferably the first and second modules are connected in parallel in such a way that the source terminal of the first transistor and the source terminal of the third transistor are connected to one another are. Further preferably, the first and second modules are connected in parallel in such a way that the source terminal of the second transistor and the source terminal of the fourth transistor are connected to one another.

Further preferably, the parallel connection of the first and second module to a first node, which can be connected to a first of the two potentials to be switched or is connected in an operating state with it. Further preferably, the parallel connection of the first and second module to a second node, which can be connected to a second of the two potentials to be switched or in an operating state is connected thereto.

In the context of the present invention, an operating state is understood to mean a state in which the device is connected in operation and thus to the potentials to be switched. In particular, the device is used in the operating state as a switch between the two potentials.

In a preferred embodiment of the device, each of the transistors has a bulk region, a source connection and a drain connection, wherein all bulk regions and / or all source connections of the transistors are connected to one another. Alternatively, all the drain terminals of the transistors can be connected to each other.

In a further preferred embodiment of the device, in particular in the case where all the bulk regions and / or all the source connections of the transistors are connected to one another, in an operating state of the device the drain connection of the first transistor and the drain connection of the device third transistor connected to a first of the two potentials. Furthermore, the drain terminal of the second transistor and the drain terminal of the fourth transistor are connected to a second of the two potentials. In other words, in this embodiment, the drain of the first transistor and the drain of the third transistor are connectable to a first of the two potentials and the drain of the second transistor and the drain of the fourth transistor to a second of the two Potentials connectable.

In a further preferred embodiment of the device, in particular in the case in which all the drain terminals of the transistors are connected to one another, in an operating state of the device, the source terminal of the first transistor and the source terminal of the third transistor with a first of the two Potentials connected. Furthermore, the source terminal of the second transistor and the source terminal of the fourth transistor are connected to a second of the two potentials. In other words, in this embodiment, the source terminal of the first transistor and the source terminal of the third transistor are connectable to a first of the two potentials and the source terminal of the second transistor and the source terminal of the fourth transistor to a second of the two Potentials connectable.

In a further preferred embodiment, each of the transistors has a bulk region, a source terminal, a drain terminal and a gate terminal, wherein the bulk areas and / or the source terminals of the first, second, third and fourth transistor are connected to each other, wherein the drain terminal of the first transistor with the drain terminal of the third transistor is connected, wherein the drain terminal of the second transistor is connected to the drain terminal of the fourth transistor, and wherein each of the transistors via the associated gate terminal controlled ie switched on or off or conductive or can be switched isolating. Further, in this embodiment, preferably, the drain terminal of the first transistor and the drain terminal of the third transistor are connectable to a first of the two potentials and the drain terminal of the second transistor and the drain terminal of the fourth transistor to a second of the two potentials connectable.

Alternatively, each of the transistors has a bulk region, a source terminal, a drain terminal and a gate terminal, wherein the drain terminals of the first, second, third and fourth transistors are connected to each other, wherein the source terminal of the first transistor is connected to the source terminal of the third transistor, wherein the source terminal of the second transistor is connected to the source terminal of the fourth transistor, and wherein each of the transistors can be controlled via the associated gate terminal. Furthermore, in this embodiment, preferably the source terminal of the first transistor and the source terminal of the third transistor are connectable to a first of the two potentials and the source terminal of the second transistor and the source terminal of the fourth transistor to a second of the two potentials connectable

In a further preferred embodiment, the first transistor has a turn-on resistance R _{DS (on),} which is smaller than a turn-on resistance R _{DS (on), 3 of} the third transistor and smaller than a turn-on resistance R _{DS (on), 4 of} the fourth transistor is. Alternatively or additionally, the second transistor has an on resistance R _{DS (on), 2} , which is smaller than the on resistance R _{DS (on), 3 of} the third transistor and smaller than the on resistance R _{DS (on), 4 of} the fourth transistor.

The switch-on resistances can in particular be set or specified via the width-length ratio (W / L ratio) of the respective transistors.

In particular, the first transistor has a W / L ratio that is greater than a W / L ratio of the third transistor and greater than a W / L ratio of the fourth transistor. Alternatively or additionally, the second transistor has a W / L ratio that is greater than the W / L ratio of the third transistor and greater than the W / L ratio of the fourth transistor.

The on-resistance or the W / L ratio of the first transistor preferably corresponds to the on-resistance or the W / L ratio of the second transistor. Further preferably, the turn-on resistance or the W / L ratio of the third transistor corresponds to the on-resistance or the W / L ratio of the fourth transistor.

Preferably, in an operating state, the gate terminal of the third or fourth transistor is connected to a clock signal generator. In particular, in an operating state of the device, only the gate terminal of the third or the gate terminal of the fourth transistor is connected to a clock signal generator, d. H. the gate terminals of the first and second transistors are preferably not connected to a clock signal generator in the operating state. For the purposes of the present invention, a clock signal generator is understood in particular to be a signal generator which transmits a periodic signal having an adjustable or predetermined frequency, for example a signal. B. a frequency greater than 100 khz, outputs.

Preferably, the first and second transistors are statically controlled, i. H. Preferably, a first static control signal is applied to the gate terminal of the first transistor in the operating state of the device, and preferably a second static control signal is applied to the gate terminal of the second transistor in the operating state of the device. The static control signals may remain the same or change during operation, depending on the application. Compared to the clock signal, the static control signals change less often.

In a further preferred embodiment, the device further comprises a control unit for controlling, i. H. for switching on and off or conductive or insulating switching, the transistors based on a first and second input signal, wherein the first input signal is preferably a static signal, which depends in particular on the size of the two potentials. The second input signal is preferably a dynamic, in particular high-frequency signal.

With the first input signal, it is z. B. advantageously possible, an operating mode or a topology of a parent circuit, ie a circuit in which the device according to the invention is used or which the Device according to the invention comprises, select, set or specify. The second input signal can, for. Example, a clock signal, such as a square wave, be, which is used to operate the parent circuit. The higher-order circuit can be, for example, an SC converter or an AC-DC or DC-AC converter.

• – einen ersten Pegelwandler zum Wandeln des ersten Eingangssignals in ein modifiziertes erstes Eingangssignal;
• – einen zweiten Pegelwandler zum Wandeln des zweiten Eingangssignals in ein modifiziertes zweites Eingangssignal; und
• – eine Logik-Schaltung, welche für jeden Transistor ein zugehöriges Steuersignal auf Basis des modifizierten ersten und modifizierten zweiten Eingangssignals erzeugt.

In a further preferred embodiment, the control unit comprises:

• A first level converter for converting the first input signal into a modified first input signal;
• A second level converter for converting the second input signal into a modified second input signal; and
• - A logic circuit which generates an associated control signal for each transistor based on the modified first and modified second input signal.

The logic circuit preferably comprises TTL, CMOS or BiCMOS devices for processing the first and second modified input signals. The level converters, also called level shifters, adapt the input signals in such a way that they can be further processed by the logic circuit. With the help of the level converter advantageously the control signals for the transistors can be adjusted.

In particular, the logic circuit comprises two non-gates and two NAND gates.

In a further preferred embodiment, the control unit further comprises a charge pump for supplying the level converters and the associated drivers for the transistors with energy. The charge pump can, for. B. be a DC-DC converter or a voltage source.

In a further preferred embodiment, the control signal associated with the first and second transistors is a static control signal. Alternatively or additionally, depending on the first input signal, either the control signal associated with the third transistor or the control signal associated with the fourth transistor is a dynamic control signal, in particular a clock signal. The respective other control signal associated with the third or fourth transistor is preferably a static control signal. Thus, if the control signal associated with the third transistor is a dynamic signal, then the control signal associated with the fourth transistor is a static signal. If the control signal associated with the fourth transistor is a dynamic signal, the signal associated with the third transistor is a static signal.

Is z. For example, if the first potential is less than the second potential, then preferably the control signal associated with the fourth transistor is a dynamic signal, while the control signal associated with the third transistor is a static signal.

Is z. For example, if the first potential is greater than the second potential, then preferably the control signal associated with the third transistor is a dynamic signal, while the control signal associated with the fourth transistor is a static signal.

In either case, either only the third or only the fourth transistor is controlled with a dynamic signal. Thus, it is advantageously possible, compared to a conventional back-to-back circuit, in which the gate terminals of the two anti-serially connected transistors are connected together and thus both transistors are controlled with the same signal to minimize the drive losses.

In a further preferred embodiment, in the event that the first of the two potentials is smaller than the second of the two potentials, the control signal associated with the first transistor is such that it switches the first transistor to an on state and that to the second transistor associated control signal such that it switches the second transistor in an off state and the associated control signal to the third transistor such that it switches the third transistor in an on state and associated with the fourth transistor control signal a dynamic control signal.

In other words, in this case, i. H. when the first potential is less than the second potential, the control signal associated with the first transistor and the control signal associated with the third transistor are configured such that the first transistor and the third transistor are in an on state while that to the second Transistor associated control signal is designed such that the second transistor is in an off state.

Thus, in the case that the first potential is smaller than the second potential, the device is preferably configured such that the first and third transistors are each in an on state and the second transistor is in an off state.

Alternatively or additionally, in the event that the first of the two potentials is greater than the second of the two potentials associated with the first transistor A control signal is arranged such that it switches the first transistor in an off state and the control signal associated with the second transistor such that it switches the second transistor in an on state and the control signal associated with the fourth transistor such that the fourth transistor switches to an on state and the control signal associated with the third transistor provides a dynamic control signal.

In other words, in this case, i. H. when the first potential is greater than the second potential, the control signal associated with the second transistor and the control signal associated with the fourth transistor are configured such that the second transistor and the fourth transistor are in an on state while that to the first Transistor associated control signal is designed such that the first transistor is in an off state.

Thus, in the case where the first potential is greater than the second potential, the device is preferably configured such that the second and fourth transistors are each in an on state and the first transistor is in an off state.

• – Bereitstellen einer erfindungsgemäßen Vorrichtung; und
• – Steuern der Transistoren auf Basis des Verhältnisses der zwei elektrischen Potentiale.

Another independent aspect for achieving the object relates to a method for electrically connecting and disconnecting two electrical potentials, comprising the steps:

• - Providing a device according to the invention; and
• Controlling the transistors based on the ratio of the two electrical potentials.

In a preferred embodiment, controlling the transistors comprises generating control signals associated with the respective transistors based on first and second input signals.

The control signals may preferably be generated by means of a logic circuit. Preferably, the control signals associated with the respective transistors are generated to be as already described in the first aspect of the present invention.

In a further preferred embodiment, the transistors are controlled such that, depending on the two electrical potentials, the transistors are switched to an on state for which an intrinsic body diode associated with the respective transistor becomes conductive in an operating state of the device or would become conductive.

In particular, in the case that the first potential is smaller than the second potential, the first transistor and the third transistor are switched to an on state. The second transistor is preferably switched to an off state in this case.

In the event that the first potential is greater than the second potential, in particular the second transistor and the fourth transistor are switched to an on state. The first transistor is preferably switched to an off state in this case.

Another independent aspect for achieving the object relates to a use of the device according to the invention as a switch in clocked applications and / or as a switch for switching AC voltages. In particular, the device according to the invention can be used as a switch in an AC-DC converter and / or a DC-AC converter and / or as a switch in a PFC circuit and / or as a switch in an SC converter.

For the above-mentioned further independent aspects and in particular for related preferred embodiments, the statements made above or below apply to the embodiments of the first aspect. In particular, for an independent aspect of the present invention and for related preferred embodiments, the statements made above and below apply to the embodiments of the other aspects.

In the following, individual embodiments for solving the problem will be described by way of example with reference to the figures. In this case, the individual embodiments described have in part features that are not absolutely necessary in order to carry out the claimed subject matter, but which provide desired properties in certain applications. Thus, embodiments are also to be regarded as falling under the described technical teaching, which does not have all the features of the embodiments described below. Further, in order to avoid unnecessary repetition, certain features will be mentioned only with respect to each of the embodiments described below. It should be noted that the individual embodiments should therefore be considered not only in isolation but also in a synopsis. Based on this synopsis, those skilled in the art will recognize that individual embodiments may also be modified by incorporating one or more features of other embodiments. It should be understood that a systematic combination of the individual embodiments having single or multiple features described with respect to other embodiments may be desirable and useful and therefore contemplated and also contemplated to be considered from the description.

Brief description of the drawings

1 shows a schematic structure of a 2: 1 series-parallel converter;

2 shows a schematic representation of a 4-bit SC converter with a transmission ratio of 5/16;

3a shows the first part of a circuit diagram of the 4-bit SC converter of 2 ;

3b shows the second part of a circuit diagram of the 4-bit SC converter of 2 ;

4 shows a section of the circuit diagram of the 3b wherein the switch S33 is shown as a transistor with a conductive intrinsic body diode;

5a shows a schematic representation of the formation of intrinsic body diodes D1 and D2 in a DEMOS transistor;

5b shows a circuit diagram for the dynamic switching of the back gate in a DEMOS transistor;

5c shows an exemplary representation of the function of the circuit diagram of the 5b at a voltage V _D = 4 V and V _S = 10 V;

6 shows a circuit diagram of a conventional back-to-back circuit with DEMOS transistors;

7a shows a circuit diagram of a device according to a preferred embodiment of the present invention for V ₂ > V ₁ ;

7b shows an equivalent circuit diagram of the device of 7a ;

8a shows a circuit diagram of a device according to a preferred embodiment of the present invention for V ₂ <V ₁ ;

8b shows an equivalent circuit diagram of the device of 8a ;

9 shows a simulation diagram for the exemplary dimensioning of a device according to the invention;

10 shows a control table for the preferred control of a device according to the invention;

11 shows a schematic representation for realizing the preferred control of a device according to the invention.

Detailed description of the drawings

The 1 shows a schematic structure of a SC converter cell from a 2: 1 series-parallel converter, in which the device according to the invention can advantageously be used as a switch.

The Switched Capacitor (SC) converter features easy-to-configure ratios. This configurability allows this converter, for example, to convert a varying input voltage into a constant output voltage. The SC converter is made up of uniform 2: 1 cells according to the 1 built up. Each 2: 1 cell of the SC converter basically has the same function and halves the voltage applied to V _{IN, top} and V _{IN, bottom} and outputs them at the output V _mid .

The switches Φ1 and Φ2 are driven out of phase with a high clock frequency, which is typically in the range of 1 to 4 MHz. In the first half of the clock period, the switches Φ1 are turned on while the switches Φ2 are turned off. In the second clock period, the switches conduct Φ2, while the switches Φ1 block. The duty cycle of the two phases is 50%.

The capacitor designated C _fly serves as a so-called flying capacitor. It is connected alternately or periodically by means of the switches Φ1 and Φ2 with a potential V _{IN, top} and a potential V _{IN, bottom} .

Due to the high clock frequency and the use of DEMOS high-voltage transistors as switches, the drive losses of the switches Φ1 and Φ2 are a critical factor for the efficiency of the circuit.

In the 2 By way of example, a simplified schematic representation of a 4-bit SC converter with a gear ratio of 5/16 is shown. Such a transducer comprises four 2: 1 cells as shown in the 1 are shown.

The 3a and 3b show a complete circuit of the 4-bit SC converter with a total of four cells. For clarity, the shows 3a a first part and the 3b a second part of the circuit. The internal voltages of the nodes which occur at an input voltage of V _IN = 16 V, in addition to the 3a and 3b entered. There are two values each indicated by a slash. The first of the two values relates in each case to a first phase in which the switches Φ1 are closed and the switches Φ2 are open and the second of the two values respectively relates to a second phase in which the switches Φ1 are open and the switches Φ2 are closed.

With the aid of the switches S15, S16, S27, S28, S37 and S38, which can also be referred to as topology switches, the transmission ratio or a topology of the converter can be set or fixed.

Depending on the transmission ratio, ie depending on the position of the topology switch, varying voltage polarities occur across the respective switching transistors identified by Φ1 and Φ2, whereby their intrinsic body diodes transition into the conducting state and can lead to a malfunction or malfunction of the converter. To explain this, the one in the 3b Switch S33 shown below is replaced by an n-channel DEMOS transistor.

The 4 shows a section of the overall circuit. In the first phase, ie in the phase in which the switches 41 are closed, the voltage at the source or bulk with 10 V is substantially higher than the voltage at the drain, which is only 4 V in the example. Ie. V _SD > V _{f, diode} , where V _{f, diode} denotes the forward voltage of the intrinsic body _{diode of} the transistor. As a result, the body diode becomes conductive and there is a current flow from source to drain, which leads to a malfunction of the transducer.

The forward polarity of body diodes can, for. B. according to the prior art by a dynamic switching of the back gate (bulk area) to the lower potential or by an antiserial circuit of two MOSFETs, which is also called back-to-back circuit, are solved. These two options are described below on the basis of 5 and 6 briefly explained.

The 5a first shows a schematic representation of a DEMOS transistor with the terminals Bulk 3 , Source 4 , Gate 6 and drain 8th , In the transistor is between source 4 and bulk 3 a first intrinsic body diode D1 and between bulk 3 and drain 8th formed a second intrinsic body diode D2.

The principle of the dynamic switching of the backgate is in the 5b and 5c shown. In the 5b are the switches S1 and S2 inserted. Depending on the voltage ratio between the drain 8th and Source 4 either the switch S1 or S2 is turned on, so that a locking of the body diode D1 or D2 is guaranteed. The control of the switching transistor via the gate 6 thus takes place depending on the switch position of S1 and S2 based on the drain or the source potential.

In the 5c is the function of the circuit diagram from the 5b exemplified at a voltage ratio of V _D = 4 V and V _S = 10 V. The switching transistor S33 is to block in this case. Thus, the body diode D2 blocks, according to the switch S1 is closed and the switch S2 is open. To ensure blocking of the switching transistor, must be at the gate 6 a voltage of V _G = 4 V are applied. Between gate 6 and Source 4 Thus arises a voltage of V _GS = -6 V. Due to the asymmetrical structure of a power management circuits often used DEMOS transistor, however, only a small gate-source voltage is permissible, for example, from V _GS = ± 5 V. A dynamic switching of the backgate is thus not feasible in this application. In any case, this solution would also mean an additional driving effort for the switches S1 and S2.

In the 6 is a diagram of a conventional back-to-back circuit with DEMOS transistors shown. In this back-to-back circuit are two transistors 10a and 10b antiserially connected in series. This is the source connection 4a of the first transistor 10a with the source connection 4b of the second transistor 10b connected. The drain connection 8a of the first transistor 10a is in an operating state with a first potential V1 and the drain terminal 8b of the second transistor 10b connected to a second potential V2. The first transistor 10a has a first intrinsic body diode 13a and the second transistor 10b has a second intrinsic body diode 13b on. The gates of the two transistors 10a and 10b are via a common gate connection 6 interconnected so that both transistors 10a and 10b be controlled with the same gate or control signal. Consequently occur in both transistors, in particular in a clocked drive, drive losses.

Due to the antiserial circuit of two MOSFETs according to the 6 the forward polarity of body diodes can be blocked. The disadvantage of the back-to-back circuit, however, is that for the same on-resistance R _{DS (on) of} a single transistor, the two transistors 10a and 10b twice as large. In particular, the width (W) must be to length (L) ratio of the transistors 10a and 10b each twice as large as is usually the case with a single transistor. This leads to a significant increase in the area consumption by the factor 4 and at a clocking control for quadrupling the drive losses P _gate .

By the device or circuit according to the invention, as described below with reference to the 7 to 11 is described, these drive losses can be significantly reduced.

The 7a and 8a each show a circuit diagram of a device or circuit 100 according to a preferred embodiment of the present invention. The 7a and 8a differ only in depending on the ratio of the potentials V1 and V2 control of the device 100 , the device 100 itself, however, is the same in both cases.

The device 100 is used for electrically connecting and disconnecting the potentials V1 and V2, ie as a switch between the potentials V1 and V2. The device 100 comprises a first module which comprises a first transistor 10a and a second transistor 10b and a second module, which includes a third transistor 10c and a fourth transistor 10d includes. All transistors 10a to 10d each have a bulk or bulk area 3a to 3d , a source connection 4a to 4d , a gate connection 6a to 6d and a drain connection 8a to 8d on. In addition, each of the transistors points 10a to 10d each an associated intrinsic body diode 13a to 13d on.

The transistors 10a and 10b of the first module are antiserial and also the transistors 10c and 10d of the second module are switched antiserially. In particular, the source terminal 4a of the first transistor 10a with the source connection 4b of the second transistor 10b and the source port 4c of the third transistor 10c with the source connection 4d of the fourth transistor 10d connected. The first module and the second module, ie the first and second transistors 10a and 10b on the one hand and the third and fourth transistors 10c and 10d on the other hand, are connected in parallel. There are all bulks 3a to 3d interconnected and thus have a common potential V _phase .

Furthermore, the drain connection 8a of the first transistor 10a and the drain connection 8c of the third transistor 10c connected with each other. Accordingly, the drain connection 8b of the second transistor 10b and the drain connection 8d of the fourth transistor 10b connected with each other. At the drain connections 8a and 8c of the first and third transistors 10a and 10c is in the operating state or in the connected state of the device 100 each at the first potential V ₁ , while at the drain terminals 8b and 8d of the second and fourth transistors 10b and 10d in each case the second potential V ₂ is present.

Each of the transistors 10a to 10d can via the respective associated gate connection 6a to 6d to be controlled.

The transistors 10c and 10d advantageously have a small W / L ratio, ie a large R _{DS (on)} . These transistors 10c and 10d be according to the 7a and 8a controlled with a clock signal and are therefore also referred to as clocked switching transistors. In contrast, the transistors 10a and 10b preferably with a comparatively large W / L ratio, ie a comparatively small R _{DS (on)} and are only switched on or off statically.

In the 7a is the device 100 shown in an operating state in which the first potential V _{1 is} smaller than the second potential V ₂ . The switches 10a and 10c are static while the switch 10b is off. The desk 10d is driven with the appropriate clock signal. In the on state of the transistor 10d results in the corresponding resistor equivalent circuit diagram of 7b ,

In the 8a is the device 100 shown in an operating state in which the first potential V _{1 is} greater than the second potential V ₂ . The switches 10b and 10d are static while the switch 10a is off. The desk 10c is driven with the appropriate clock signal. In the on state of the transistor 10c results in the corresponding resistor equivalent circuit diagram of 8b ,

In the 7b and 8b In each case, the resistors designated R _A , R _B , R _C and R _D are the on resistances of the transistors 10a . 10b . 10c and 10d ,

wobei R_A = R_B = R_A,B und R_C = R_D = R_C,D.The following is an example of the case with V ₂ > V ₁ , ie the operating state or the control of the device 100 according to the 7a and 7b A closer look:
The total resistance R _{on, ges} can be calculated with the following equation:

where R _A = R _B = R _{A, B} and R _C = R _D = R _{C, D.}

The series and parallel circuit is advantageously dimensioned so that the on-resistance R _{on, ges} this circuit substantially the on-resistance of a single transistor equivalent. Preferably the P _gate Ansteuerverluste be as low as possible and maintained in the range of a single switching transistor. For the dimensioning of the device or the modified back-to-back circuit 100 For example, the gate losses are normalized to the gate losses of a conventional back-to-back circuit and designated P _{Gate, normalized} . The normalized gate losses are represented as a function of x = R _{C, D} / R _{A, B.} In the process, a search is made for a minimum (x _min or P _{gate, normalized, min} ) of the normalized gate losses. After determining a minimum, with the relationship x = R _{C, D} / R _{A, B} and Equation 1 above, the resistance values for R _{A, B} and R _{C, D} can be calculated.

In the 9 an exemplary simulation result is shown. As from the diagram of 9 can be seen, are normalized with increasing x the normalized gate losses P _gate , which through the curve 15 are shown, smaller. At the same time, however, the area consumption A _normalizes , which through the curve 17 shown clearly. In the 9 of surface consumption of the modified back-to-back circuit is normalized to the area consumption of a conventional back-to-back circuit and is designated with A _normalized.

As from the diagram of 9 can be seen, with the inventive device compared to a conventional back-to-back circuit with respect to the gate losses an improvement of up to 75% can be achieved. Depending on the particular application, an appropriate selection of x can be used to match the drive losses and the component size.

The control of the four switching transistors 10a to 10d takes place individually in the example cited. The static switches are switched on or off according to a topology, ie according to the ratio of the two potentials, and the corresponding clock signal is applied to the switch 10c or 10d guided.

The 10 shows a drive table for a preferred drive of the device 100 , Where T is the topology. The topology T represents the ratio of the two potentials V ₁ and V ₂ . Thus, T has the value 1, provided that V ₂ > V ₁ and the value 0, provided that V ₂ <V ₁ . The second column of the table describes a clock signal, z. B. the clock signal of a SC converter. In the third to sixth column of the table is in each case indicated which of the transistors 10a to 10d in an on-state or in an off-state is or should be. Here, a 1 means an on state and a 0 means an off state. The designation A stands for the first transistor 10a , B for the second transistor 10b , C for the third transistor 10c and D for the fourth transistor 10d the device 100 , For example, for T = 0 and Φ1 / Φ2 = 0, the first transistor 10a and the third transistor 10c off while the second transistor 10b and the fourth transistor 10d are turned on.

The 11 shows a schematic representation of a possible control unit 20 the device 100 according to a preferred embodiment. The control unit 20 is used to control the transistors 10a to 10d based on a first input signal 21 and a second input signal 22 , This is the first input signal 21 a static signal which describes the topology T and thus depends on the size of the two potentials V ₁ and V ₂ . At a voltage ratio V ₂ > V ₁ z. B. in the topology selection 21 the value T = 1 and for V ₂ <V ₁ corresponding to the value T = 0 are set. The second input signal 22 is a dynamic signal and corresponds to z. B. a clock signal.

The control unit 20 comprises a first level converter or level shifter 41 for converting the first input signal 21 in a modified first input signal and a second level converter or level shifter 42 for converting the second input signal 22 in a modified second input signal. The level shifter 41 for the topology selection is used here only when changing the transmission ratio of the SC converter, so that virtually no dynamic losses caused by switching with the clock frequency.

Furthermore, the control unit comprises 20 a logic or logic circuit 50 which for each transistor 10a to 10d the device 100 an associated control signal 60a to 60d generated based on the modified first and modified second input signal. By means of the control signals 60a to 60d So these are the transistors 10a to 10d controlled by the control signals 60a to 60d each to the gate terminals 6a to 6d the transistors 10a to 10d be created. The logic circuit 50 includes two non-gates 52 and 54 as well as two NAND gates 56 and 58 , whereby the coding or control according to the table of 10 can be realized.

Finally, the control unit includes 20 Furthermore, a charge pump or charge pump 30 for supplying the first and second level converter 41 and 42 with energy. The batch pump 30 is fed by a supply potential V _DD and provides for the level converter 41 and 42 two voltage levels, namely V _high and V _phase available.

The present invention enables a simple and effective implementation of a switching stage in which a cross-flow through the body diode of the switching transistors can be avoided. Dynamic drive losses are reduced by typically 70% with minimal increase in space consumption compared to a conventional back-to-back circuit. The total drive losses can be significantly reduced with only a minimal increase in space required. The circuit is also only a little more complicated than a conventional back-to-back circuit and can be used with all types of transistors. H. also, for example, in unbalanced power transistors such. B. DEMOS.

The device according to the invention 100 can be used in particular as a clocking switch in a SC converter. An advantage of the SC converter is that the voltage ratios V1 and V2 are known depending on the transmission ratio. In addition, the change in the voltage conditions V1 and V2 is significantly slower than the clock or switching frequency of the switching transistors. As a result, depending on the voltage ratio, the transistor, whose body diode would conduct, already be turned on. By making the transistor on which the clocking signal is applied small or smaller compared to the transistors connected in parallel therewith, that is, by making the W / L ratio of this transistor small or smaller, driving losses can be kept low. By utilizing a parallel connection while the required R _{DS (on)} a single switch is still assured.

LIST OF REFERENCE NUMBERS

1

First potential V ₁

2

Second potential V ₂

3

Bulk / bulk region

3a

Bulk / bulk region

3b

Bulk / bulk region

3c

Bulk / bulk region

3d

Bulk / bulk region

4

Source / source terminal

4a

Source / source terminal

4b

Source / source terminal

4c

Source / source terminal

4d

Source / source terminal

6

Gate / gate terminal

6a

Gate / gate terminal

6b

Gate / gate terminal

6c

Gate / gate terminal

6d

Gate / gate terminal

8th

Drain / drain terminal

8a

Drain / drain terminal

8b

Drain / drain terminal

8c

Drain / drain terminal

8d

Drain / drain terminal

10a

First transistor

10b

Second transistor

10c

Third transistor

10d

Fourth transistor

13a

body diode

13b

body diode

13c

body diode

13d

body diode

15

Simulation curve of normalized gate losses

17

Simulation curve of a standardized area consumption

20

Control unit / drive unit

21

First input signal

22

Second input signal

30

Charge pump / charge pump

41

First level converter or level shifter

42

Second level converter or level shifter

50

Logic / logic circuit

52

First non-gate

54

Second non-gate

56

First Nand Gate

58

Second Nand Gate

60a

control signal

60b

control signal

60c

control signal

60d

control signal

100

Device / switch device

Claims (15)

Contraption ( 100 ) for electrically connecting and disconnecting two electrical potentials ( 1 . 2 ), comprising - a first module comprising a first and a second transistor ( 10a . 10b ), wherein the first transistor ( 10a ) antiserially to the second transistor ( 10b ) is switched; and a second module comprising a third and a fourth transistor ( 10c . 10d ), wherein the third transistor ( 10c ) antiserially to the fourth transistor ( 10d ) is switched; wherein the first module and the second module are connected in parallel. Contraption ( 100 ) according to claim 1, wherein each of said transistors ( 10a - 10d ) a bulk area ( 3a - 3d ), a source connection ( 4a - 4d ) and a drain connection ( 8a - 8d ), all bulk areas ( 3a - 3d ) and / or all source connections ( 4a - 4d ) of the transistors ( 10a - 10d ), or wherein all the drain connections ( 8a - 8d ) of the transistors ( 10a - 10d ) are interconnected. Contraption ( 100 ) according to claim 1 or 2, wherein in an operating state of the device ( 100 ) all bulk areas ( 3a - 3d ) and / or all source connections ( 4a - 4d ) of the transistors ( 10a - 10d ) and wherein the drain terminal ( 8a ) of the first transistor ( 10a ) and the drain connection ( 8c ) of the third transistor ( 10c ) with a first ( 1 ) of the two potentials is connected and wherein the drain connection ( 8b ) of the second Transistor ( 10b ) and the drain connection ( 8d ) of the fourth transistor ( 10d ) with a second ( 2 ) of the two potentials is connected. Contraption ( 100 ) according to claim 1 or 2, wherein in an operating state of the device ( 100 ) all drain connections ( 8a - 8d ) of the transistors ( 10a - 10d ) and wherein the source terminal ( 4a ) of the first transistor ( 10a ) and the source connection ( 4c ) of the third transistor ( 10c ) with a first ( 1 ) of the two potentials is connected and wherein the source connection ( 4b ) of the second transistor ( 10b ) and the source connection ( 4d ) of the fourth transistor ( 10d ) with a second ( 2 ) of the two potentials is connected. Device according to claim 1, wherein each of the transistors ( 10a - 10d ) a bulk area ( 3a - 3d ), a source connection ( 4a - 4d ), a drain connection ( 8a - 8d ) and a gate terminal ( 6a - 6d ), the bulk areas ( 3a - 3d ) and / or the source connections ( 4a - 4d ) of the first, second, third and fourth transistors ( 10a - 10d ), wherein the drain connection ( 8a ) of the first transistor ( 10a ) with the drain connection ( 8c ) of the third transistor ( 10c ), the drain connection ( 8b ) of the second transistor ( 10b ) with the drain connection ( 8d ) of the fourth transistor ( 10d ), and wherein each of the transistors ( 10a - 10d ) via the associated gate connection ( 6a - 6d ), or wherein each of the transistors ( 10a - 10d ) a bulk area ( 3a - 3d ), a source connection ( 4a - 4d ), a drain connection ( 8a - 8d ) and a gate terminal ( 6a - 6d ), wherein the drain terminals ( 4a - 4d ) of the first, second, third and fourth transistors ( 10a - 10d ), wherein the source terminal ( 4a ) of the first transistor ( 10a ) with the source connection ( 4c ) of the third transistor ( 10c ), the source terminal ( 4b ) of the second transistor ( 10b ) with the source connection ( 4d ) of the fourth transistor ( 10d ), and wherein each of the transistors ( 10a - 10d ) via the associated gate connection ( 6a - 6d ) can be controlled. Contraption ( 100 ) according to one of the preceding claims, wherein the first transistor ( 10a ) has a turn-on, which is smaller than a turn-on of the third transistor ( 10c ) and smaller than a turn-on resistance of the fourth transistor ( 10d ), and / or wherein the second transistor ( 10b ) has a turn-on, which is smaller than the on-resistance of the third transistor ( 10c ) and smaller than the on-resistance of the fourth transistor ( 10d ). Contraption ( 100 ) according to one of the preceding claims, further comprising a control unit ( 20 ) for controlling the transistors ( 10a - 10d ) based on a first and second input signal ( 21 . 22 ), the first input signal ( 21 ) is preferably a static signal, which depends in particular on the size of the two potentials, and wherein the second input signal ( 22 ) is preferably a dynamic signal. Contraption ( 100 ) according to claim 7, wherein the control unit ( 20 ) comprises: - a first level converter ( 41 ) for converting the first input signal ( 21 ) in a modified first input signal; A second level converter ( 42 ) for converting the second input signal ( 22 ) in a modified second input signal; and a logic circuit ( 50 ), which for each transistor ( 10a - 10d ) an associated control signal ( 60a - 60d ) based on the modified first and modified second input signals. Contraption ( 100 ) according to claim 8, wherein the control unit ( 20 ) a charge pump ( 30 ) for supplying the first and second level converter ( 41 . 42 ) with energy. Contraption ( 100 ) according to claim 8 or 9, wherein the to the first and second transistors ( 10a . 10b ) associated control signals ( 60a . 60b ) are static signals, and / or depending on the first input signal ( 21 ) either to the third transistor ( 10c ) associated control signal ( 60c ) or that to the fourth transistor ( 10d ) associated control signal ( 60d ) is a dynamic control signal. Contraption ( 100 ) according to one of claims 8 to 10, wherein in the event that the first ( 1 ) of the two potentials smaller than the second ( 2 ) of the two potentials connected to the first transistor ( 10a ) associated control signal ( 60a ) is such that it is the first transistor ( 10a ) switches to an on state and that to the second transistor ( 10b ) Control signal ( 60b ) is such that the second transistor ( 10b ) switches to an off state and that to the third transistor ( 10c ) associated control signal ( 60c ) is such that it is the third transistor ( 10c ) switches to an on state and that to the fourth transistor ( 10d ) associated control signal ( 60d ) is a dynamic control signal, and / or in the event that the first ( 1 ) of the two potentials is greater than the second ( 2 ) of the two potentials connected to the first transistor ( 10a ) associated control signal ( 60a ) is such that it is the first transistor ( 10a ) switches to an off state and that to the second transistor ( 10b ) associated control signal ( 60b ) is such that the second transistor ( 10b ) switches to an on state and that to the fourth transistor ( 10d ) associated control signal ( 60d ) is such that it is the fourth transistor ( 10d ) switches to an on state and that to the third transistor ( 10c ) associated control signal ( 60c ) is a dynamic control signal. Method for electrically connecting and disconnecting two electrical potentials ( 1 . 2 ), comprising the steps: - providing a device ( 100 ) according to any one of the preceding claims; and - controlling the transistors ( 10a - 10d ) based on the ratio of the two electrical potentials ( 1 . 2 ). The method of claim 12, wherein controlling the transistors ( 10a - 10d ) generating to the respective transistors ( 10a - 10d ) associated control signals ( 60a - 60d ) based on a first and second input signal ( 21 . 22 ). Method according to claim 12 or 13, wherein the controlling of the transistors ( 10a - 10d ) such that, depending on the two electrical potentials ( 1 . 2 ) those transistors are switched into an on state for which an intrinsic body diode associated with the respective transistor is in an operating state of the device ( 100 ) becomes conductive. Use of the device ( 100 ) according to one of claims 1 to 11 as a switch in clocked applications and / or as a switch for switching AC voltages

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