WO2014038374A1 - Semiconductor device producing method - Google Patents

Semiconductor device producing method Download PDF

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Publication number
WO2014038374A1
WO2014038374A1 PCT/JP2013/072283 JP2013072283W WO2014038374A1 WO 2014038374 A1 WO2014038374 A1 WO 2014038374A1 JP 2013072283 W JP2013072283 W JP 2013072283W WO 2014038374 A1 WO2014038374 A1 WO 2014038374A1
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silicon substrate
gan
semiconductor film
based semiconductor
peripheral portion
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PCT/JP2013/072283
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French (fr)
Japanese (ja)
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小野　敦
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シャープ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting

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  • the present invention relates to a method for manufacturing a semiconductor device in which a GaN-based semiconductor film is formed on a silicon substrate.
  • GaN-based power devices that have a large band gap and can realize a high electron concentration by heterojunction are attracting attention.
  • Patent Document 1 Japanese Patent Laid-Open No. 2011-71180 discloses a specific direction with respect to the edge portion around the wafer with respect to the GaN substrate for manufacturing the GaN-based device. It has been proposed to prevent cracking and chipping by chamfering.
  • Patent Document 2 Japanese Patent Application Laid-Open No. 2004-319951 proposes preventing cracking and chipping by performing beveling (chamfering) on the edge portion of the GaN substrate.
  • the present inventors are engaged in the development of a GaN-based power device using an inexpensive Si substrate as the GaN-based device.
  • the present inventors epitaxially grown a GaN-based semiconductor film on a silicon substrate to form a semiconductor element, and grinding and polishing from the back surface of the silicon substrate to reduce the thickness. During this grinding and polishing, We faced the problem of frequent occurrence of a phenomenon in which the laminate composed of the silicon substrate and the GaN-based semiconductor film was broken from the edge portion.
  • the present inventors investigated the cause of this cracking and found the following.
  • the peripheral portion 101A of the silicon substrate 101 is chamfered to avoid cracks and chips, but the silicon substrate 101 is chamfered from the peripheral portion 101A. It has been found that the GaN film peripheral portion 102A of the GaN-based semiconductor film 102 wraps around to the back surface 101C side.
  • the thermal expansion coefficient of Si is 2.4 ⁇ 10 ⁇ 6 (1 / K)
  • the thermal expansion coefficient of GaN is 5.59. ⁇ 10 ⁇ 6 (1 / K). That is, there is a large difference in the coefficient of thermal expansion between the silicon substrate and the GaN-based semiconductor film.
  • MOCVD MOCVD
  • the amount of shrinkage of the GaN-based semiconductor film when the temperature drops is more than twice that of the silicon substrate.
  • the stacked body of the silicon substrate and the GaN-based semiconductor film has a warp that protrudes downward.
  • the lattice constant of Si is 3.18 ⁇
  • the lattice constant of GaN is 5.43 ⁇ , which has a large lattice strain.
  • FIG. 10C is an electron micrograph showing a deep crack 105 formed in the GaN film peripheral portion 102A and part of the silicon substrate 101 when the back surface 101C of the silicon substrate 101 is ground and polished.
  • dicing is performed by a step-cut method in order to form a chip with the GaN film peripheral portion 102A remaining on the chamfered peripheral portion 101A of the silicon substrate 101. It was also found that the narrow blade of the second axis is clogged with fragments of the hard GaN film, the blade becomes dull, and a lot of fine chips (back surface chipping) occur on the back surface 101C of the silicon substrate 101.
  • the object of the present invention is to prevent cracking when the backside polishing of a laminated body in which a GaN-based semiconductor film is epitaxially grown on a silicon substrate having a peripheral portion, and to generate backside chipping of the wafer during dicing for chip formation.
  • An object of the present invention is to provide a method of manufacturing a semiconductor device that can prevent this.
  • a method for manufacturing a semiconductor device epitaxially grows a GaN-based semiconductor film on a silicon substrate having a peripheral portion, Forming a semiconductor element including the GaN-based semiconductor film on the silicon substrate; After cutting out the peripheral part of the silicon substrate and the GaN-based semiconductor film formed on the peripheral part, The back surface of the silicon substrate is polished.
  • the GaN-based semiconductor film is covered on the side surface of the silicon substrate by cutting the peripheral portion of the silicon substrate and the GaN-based semiconductor film formed on the peripheral portion. No state. After this, by grinding and polishing the back surface of the silicon substrate, it is possible to prevent the GaN-based semiconductor film from being ground during the back surface polishing of the silicon substrate, so that cracking of the wafer can be prevented.
  • the second-axis narrow blade does not cut the GaN-based semiconductor film during the step-cut dicing for chip formation. This eliminates the phenomenon of the clogging of the narrow blade of the second axis due to hard GaN film fragments, so that the sharpness of the blade can be prevented from being reduced, and fine chipping (back surface chipping) occurs on the back surface of the silicon substrate. Can be prevented.
  • the silicon substrate is doped with Ge.
  • Ge doping to a silicon substrate is performed in order to reduce the curvature of the laminated body which epitaxially grew the GaN-type semiconductor film on the said silicon substrate.
  • the silicon substrate is placed on a rotating stage, Rotate the rotary stage to rotate the silicon substrate, A dicing blade that rotates about a rotation axis that is substantially orthogonal to the rotation axis of the rotation stage is lowered from above the GaN-based semiconductor film formed on the peripheral portion of the silicon substrate, and the silicon substrate is lowered. And the GaN-based semiconductor film formed on the periphery is cut away.
  • the peripheral portion of the silicon substrate and the GaN-based semiconductor film formed on the peripheral portion can be efficiently cut off.
  • the GaN-based semiconductor film and the silicon substrate are diced by a step cut method to cut out a plurality of semiconductor chips on which semiconductor elements are formed.
  • a wafer on which a semiconductor element including a GaN-based semiconductor film is formed can be cut into a plurality of semiconductor chips with a step cut method while efficiently suppressing backside chipping.
  • the GaN-based semiconductor film is not covered on the side surface of the silicon substrate by cutting the peripheral portion of the silicon substrate and the GaN-based semiconductor film formed on the peripheral portion. become. Thereafter, by grinding and polishing the back surface of the silicon substrate, it is possible to prevent the GaN-based semiconductor film from being ground during the back surface polishing of the silicon substrate, so that cracking of the wafer can be prevented.
  • GaN-type FET GaN-type FET which is an example of the semiconductor element produced in the said embodiment. It is a fragmentary sectional view which shows a mode that the peripheral part of the GaN-type semiconductor film formed on the silicon substrate has reached the back surface side from the peripheral part of the silicon substrate. It is a fragmentary sectional view which shows a mode that the grinding
  • a GaN-based semiconductor film 2 is epitaxially grown on a silicon substrate 1 having a chamfered peripheral portion 1A.
  • the thickness of the silicon substrate 1 is, for example, about 500 ⁇ m to 700 ⁇ m.
  • the film thickness of the GaN-based semiconductor film 2 is, for example, about 5 ⁇ m to 10 ⁇ m.
  • a semiconductor element including the GaN-based semiconductor film 2 is fabricated on the silicon substrate 1.
  • GaN-based FET field effect transistor
  • an undoped AlGaN buffer layer 92 and an undoped GaN channel layer 93 are formed on the silicon substrate 1 having a thickness of 625 ⁇ m having the chamfered peripheral portion 1A by using MOCVD (metal organic chemical vapor deposition). Then, an undoped AlGaN barrier layer 94 is formed in order.
  • the AlGaN buffer layer 92, the GaN channel layer 93, and the AlGaN barrier layer 94 constitute the GaN-based semiconductor film 2.
  • reference numeral 99 indicates a two-dimensional electron gas formed at the interface between the AlGaN barrier layer 94 and the GaN channel layer 93.
  • the silicon substrate 1 used was codoped with B (boron) -Ge (germanium) at a density of 10 19 (cm ⁇ 3 ) in order to suppress warpage.
  • the co-doped silicon substrate 1 has a high hardness and is very difficult to polish.
  • a source electrode 95, a drain electrode 96, and a gate electrode 98 are formed on the AlGaN barrier layer 94.
  • the manufacturing method of the source electrode 95, the drain electrode 96, and the gate electrode 98 is not specifically limited, For example, well-known methods, such as vapor deposition, are used. The distance between the source electrode 95 and the drain electrode 96, the position of the gate electrode 98, and the like are adjusted according to the desired performance of the field effect transistor.
  • As the material of the source electrode 95 and the drain electrode 96 Ti / Al, Hf / Al / Au, or the like is used.
  • a material of the gate electrode 98 a material that forms a Schottky barrier such as WN or TiN is used.
  • an insulating film 97 made of SiN is formed on the AlGaN barrier layer 94 by a known method such as plasma CVD. Note that the insulating film 97 may be formed before the source electrode 95, the drain electrode 96, and the gate electrode 98 are formed.
  • a two-dimensional electron gas 99 is formed between the channel layer 93 and the barrier layer 94, and the channel layer 93 is controlled by applying a voltage to the gate electrode 98. It is turned on and off.
  • the GaN-based FET when a negative voltage is applied to the gate electrode 98, a depletion layer is formed in the GaN channel layer 93 under the gate electrode 98 to be turned off, while the voltage of the gate electrode 98 is zero.
  • the GaN channel layer 93 under the gate electrode 98 is a normally-on type transistor that is turned on when the depletion layer disappears.
  • the GaN-based FET has been described as a normally-on type transistor.
  • a p-type GaN layer having a mesa structure is provided under the gate electrode, and no two-dimensional electron gas is generated under the gate electrode.
  • a normally-off type transistor may be used.
  • GaN-based FET is used as a switching element that flows a current of 5 A to 60 A at a high voltage exceeding 600 V, for example. Therefore, how to release heat generated from the junction of the FET is very important in device design.
  • epitaxial growth of the GaN-based semiconductor film 2 on the silicon substrate 1 has an advantage that it can be manufactured at low cost, but the wafer warps due to the difference in thermal expansion coefficient between the silicon substrate 1 and the GaN-based semiconductor film 2.
  • Cheap In order to suppress the warpage of the wafer, for example, a 6-inch silicon substrate adopts a substrate thickness of 625 ⁇ m in consideration of matching with a manufacturing apparatus in a normal LSI factory.
  • the film thickness of the GaN-based semiconductor film 2 formed on the silicon substrate 1 is about 5 to 10 ⁇ m at most. For this reason, in order to improve the heat dissipation characteristics, the back surface of the silicon substrate 1 is polished to reduce the thickness as will be described later.
  • the silicon substrate 1 on which the GaN-based semiconductor film 2 is epitaxially grown to form the semiconductor element is placed on a rotary stage 51, and the rotary stage 51 is attached to the arrow in FIG. 4.
  • the silicon substrate 1 is rotated by rotating around the rotation center axis J in the direction indicated by X.
  • the rotational speed of the rotary stage 51 is set to a predetermined value within a range of 1 ° / second to 6 ° / second.
  • a dicing sheet (not shown) for fixing the silicon substrate 1 to the rotary stage 51 is attached to the rotary stage 51.
  • the dicing blade 52 on the disk is rotated around a rotation axis substantially orthogonal to the rotation center axis J of the rotation stage 51.
  • the rotational speed of the dicing blade 52 is set to a predetermined value within the range of 15000 rpm to 25000 rpm.
  • the dicing blade 52 is lowered from above to below the GaN-based semiconductor film 2 formed on the peripheral portion 1A of the silicon substrate 1.
  • the dicing blade 52 cuts from the GaN-based semiconductor film 2 formed on the peripheral portion 1A of the silicon substrate 1 into the peripheral portion 1A of the silicon substrate 1 as shown in the cross-sectional view of FIG.
  • the silicon substrate 1 rotates once together with the rotary stage 51, so that the peripheral portion 1A of the silicon substrate 1 and the annular portion of the GaN-based semiconductor film 2 formed on the peripheral portion 1A are cut off.
  • the width dimension for cutting out the peripheral portion 1A is about 1 mm.
  • FIG. 3 shows a laminated body 31 of the silicon substrate 1 and the GaN-based semiconductor film 2 in a state where the peripheral portion 1A of the silicon substrate 1 and the annular portion of the GaN-based semiconductor film 2 formed on the peripheral portion 1A are removed. The cross section of is shown. As shown in FIG. 3, by chamfering the chamfered peripheral portion 1A of the silicon substrate 1 and the GaN-based semiconductor film 2 formed on the peripheral portion 1A, a GaN-based semiconductor is formed on the side surface 1B of the silicon substrate 1. The film 2 is not covered.
  • the back surface 1C of the silicon substrate 1 is polished.
  • this polishing as an example, after rough polishing with a diamond grindstone with a particle size of 360, finishing was performed with a diamond grindstone with a particle size of 2000, and the thickness was reduced to 100 ⁇ m to 300 ⁇ m (for example, 240 ⁇ m).
  • the back surface 1C of the silicon substrate 1 is polished, so that the GaN-based semiconductor film is polished during the back surface polishing of the silicon substrate 1. 2 can be prevented from being ground. Therefore, it is possible to avoid grinding the hard GaN-based semiconductor film 2 during the back surface polishing of the silicon substrate 1, reduce the stress generated in the silicon substrate 1 during the back surface polishing, and prevent the silicon substrate 1 from cracking. Thus, cracking of the wafer (laminated body 31) can be prevented.
  • the stacked body 31 of the silicon substrate 1 and the GaN-based semiconductor film 2 is diced by a step cut method to cut out a plurality of semiconductor chips on which the semiconductor elements are formed.
  • a step-cut type dicing for example, a first-axis dicing blade having a width of 40 ⁇ m is used to cut from the surface of the laminate 31 to a depth of 140 ⁇ m, and then a second-axis dicing blade having a width of 35 ⁇ m. A full cut was performed.
  • FIG. 5 is a photograph of the side surface of the semiconductor chip after dicing by the step cut method.
  • Reference numeral 55 in FIG. 5 denotes a step formed at the boundary between the cut by the first dicing plate having a wider width and the cut by the second dicing plate having a smaller width.
  • the side surface 1B of the silicon substrate 1 is not covered with the GaN-based semiconductor film 2.
  • the dicing blade having a narrow second axis width covers the GaN-based semiconductor film 2 at the time of step-cut dicing for chip formation. No cutting.
  • the phenomenon of clogging the dicing blade having a narrow second axis due to hard GaN film fragments can be eliminated, so that the sharpness of the dicing blade can be prevented from being reduced, and the back surface 1C of the silicon substrate 1 can be finely chipped (back surface chipping). ) Can be prevented.
  • FIG. 7 is a photograph of the back surface 1C of the silicon substrate 1 after dicing by the step cut method in the embodiment.
  • Reference numeral 71 in FIG. 7 is a notch due to the dicing.
  • fine chips back surface chipping
  • the step of cutting the peripheral portion 1A of the silicon substrate 1 and the annular portion of the GaN-based semiconductor film 2 formed on the peripheral portion 1A is not performed. Therefore, in this comparative example, with the GaN-based semiconductor film 2 formed on the peripheral portion 1A of the silicon substrate 1, step-cut dicing for backside polishing of the silicon substrate 1 and subsequent chip formation is performed. .
  • FIG. 8 photograph of the back surface 1C of the silicon substrate 1 after the step-cut dicing
  • FIG. 8 photograph of the back surface 1C of the silicon substrate 1 after the step-cut dicing
  • step-cut dicing for chip formation is performed in the state where the peripheral portion 1A of the silicon substrate 1 and the GaN-based semiconductor film 2 are present on the peripheral portion 1A. Therefore, the dicing blade having a narrow width on the second axis cuts the GaN-based semiconductor film 2.
  • the chamfered peripheral portion 1A of the silicon substrate 1 and the GaN-based semiconductor film 2 formed on the peripheral portion 1A are excised to obtain a silicon substrate.
  • the side surface 1B of 1 is not covered with the GaN-based semiconductor film 2, dicing for back surface polishing and chip formation is performed.
  • a silicon substrate having a chamfered peripheral portion is used, but the present invention is not limited to this, and a silicon substrate having a peripheral portion that is not chamfered may be used.
  • the GaN-based semiconductor film in the manufacturing method of the present invention includes a GaN-based semiconductor layer represented by Al x In y Ga 1-xy N (x ⁇ 0, y ⁇ 0, 0 ⁇ x + y ⁇ 1). Good. That is, the GaN-based semiconductor film in the manufacturing method of the present invention may include AlGaN, GaN, InGaN, and the like. Further, the GaN-based semiconductor device manufactured by the present invention is not limited to the HFET of the above embodiment, but may be a field effect transistor having another structure such as an insulated gate structure, or a GaN-based diode.

Abstract

This semiconductor device producing method includes the steps of: causing epitaxial growth of a GaN-based semiconductor film (2) on a silicon substrate (1) having a peripheral part (1A); forming a semiconductor element including a GaN-based semiconductor film (2) on the silicon substrate (1); removing the peripheral part (1A) of the silicon substrate (1) and the GaN-based semiconductor film (2) formed on this peripheral part (1A); and thereafter, grinding a back surface (1C) of the silicon substrate (1).

Description

半導体装置の製造方法Manufacturing method of semiconductor device
　この発明は、シリコン基板上にＧａＮ系半導体膜が形成された半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device in which a GaN-based semiconductor film is formed on a silicon substrate.
　バンドギャップが大きく、ヘテロ接合による高い電子濃度を実現し得るＧａＮ系パワーデバイスが注目されている。 GaN-based power devices that have a large band gap and can realize a high electron concentration by heterojunction are attracting attention.
　このようなＧａＮ系パワーデバイスの製造方法において、特許文献１(特開２０１１－７１１８０号公報)では、ＧａＮ系デバイスを作製するためのＧａＮ基板に対して、ウエハ周辺のエッジ部に対して特定方向の面取りを行うことで割れや欠けを防止することが提案されている。 In such a method for manufacturing a GaN-based power device, Patent Document 1 (Japanese Patent Laid-Open No. 2011-71180) discloses a specific direction with respect to the edge portion around the wafer with respect to the GaN substrate for manufacturing the GaN-based device. It has been proposed to prevent cracking and chipping by chamfering.
　また、特許文献２(特開２００４－３１９９５１号公報)では、ＧａＮ基板のエッジ部に対するベベリング(面取り)を行うことにより、割れや欠けを防止することが提案されている。 Further, Patent Document 2 (Japanese Patent Application Laid-Open No. 2004-319951) proposes preventing cracking and chipping by performing beveling (chamfering) on the edge portion of the GaN substrate.
特開２０１１－７１１８０号公報JP 2011-71180 A 特開２００４－３１９９５１号公報JP 2004-319951 A
　本発明者らは、ＧａＮ系デバイスとして安価なＳｉ基板を用いたＧａＮ系パワーデバイスの開発に携わっている。 The present inventors are engaged in the development of a GaN-based power device using an inexpensive Si substrate as the GaN-based device.
　シリコン基板上にＧａＮ系半導体膜をエピタキシャル成長させたウエハをパワーデバイスに適用する場合には、大電流,高電圧を印加することから、シリコン基板を薄くして、放熱性を上げる必要がある。 When a wafer obtained by epitaxially growing a GaN-based semiconductor film on a silicon substrate is applied to a power device, a large current and a high voltage are applied. Therefore, it is necessary to thin the silicon substrate to improve heat dissipation.
　ところが、本発明者らは、シリコン基板上にＧａＮ系半導体膜をエピタキシャル成長させて半導体素子を形成し、薄型化のためにシリコン基板の裏面から研削,研磨を行ったところ、この研削,研磨中に上記シリコン基板とＧａＮ系半導体膜とで構成される積層体がエッジ部から割れてしまう現象が多発する問題に直面した。 However, the present inventors epitaxially grown a GaN-based semiconductor film on a silicon substrate to form a semiconductor element, and grinding and polishing from the back surface of the silicon substrate to reduce the thickness. During this grinding and polishing, We faced the problem of frequent occurrence of a phenomenon in which the laminate composed of the silicon substrate and the GaN-based semiconductor film was broken from the edge portion.
　本発明者らが、この割れの原因を調査したところ、次の様なことが判明した。 The present inventors investigated the cause of this cracking and found the following.
　まず、図１０Ａの断面図に示すように、シリコン基板１０１の周辺部１０１Ａを面取りして、割れ,欠けを回避することがなされているが、このシリコン基板１０１の面取りされている周辺部１０１Ａから裏面１０１Ｃ側にまでＧａＮ系半導体膜１０２のＧａＮ膜周縁部１０２Ａが回り込んでしまっていることを見出した。 First, as shown in the cross-sectional view of FIG. 10A, the peripheral portion 101A of the silicon substrate 101 is chamfered to avoid cracks and chips, but the silicon substrate 101 is chamfered from the peripheral portion 101A. It has been found that the GaN film peripheral portion 102A of the GaN-based semiconductor film 102 wraps around to the back surface 101C side.
　次に、図１０Ｂの断面図に示すように、シリコン基板１０１の裏面１０１Ｃから研削,研磨して行く際に、研磨面１０１Ｄが周辺部１０１Ａから回り込んだＧａＮ膜周縁部１０２Ａに達すると、ＧａＮ膜周縁部１０２Ａやシリコン基板１０１の一部に欠けが生じ、研削,研磨中に発生するＧａＮ膜のかけらや応力の影響により、上記欠けからウエハの割れが発生していることが判明した。 Next, as shown in the cross-sectional view of FIG. 10B, when grinding and polishing from the back surface 101C of the silicon substrate 101, when the polishing surface 101D reaches the peripheral edge portion 102A of the GaN film that wraps around from the peripheral portion 101A, GaN It was found that cracks were generated in the peripheral edge portion 102A and part of the silicon substrate 101, and the wafer was cracked from the chips due to the influence of GaN film fragments and stress generated during grinding and polishing.
　特に、シリコン基板とＧａＮ系半導体膜との組み合わせでは、例えば、Ｓｉの熱膨張係数は２．４×１０－６(１/Ｋ)であるのに対して、ＧａＮの熱膨張係数は５．５９×１０－６(１/Ｋ)である。すなわち、上記シリコン基板とＧａＮ系半導体膜との間には、熱膨張率に大きな差が存在する。このため、シリコン基板上にＭＯＣＶＤを用いて１０００～１３００℃の高温でＧａＮ系半導体膜を形成した場合、温度低下時のＧａＮ系半導体膜の収縮量がシリコン基板の収縮量の２倍以上になって、シリコン基板とＧａＮ系半導体膜の積層体は下に凸となる反りを持ったものになる。また、Ｓｉの格子定数は３．１８Åであるのに対して、ＧａＮの格子定数は５．４３Åであり、大きな格子歪を有することになる。このように、両者の間の熱膨張係数の相違によりウエハの反りが生じやすいことに加えて、両者間の格子定数の相違に起因する比較的大きな格子歪が生じることから、シリコン基板１０１の裏面研磨中にクラックが生じやすくなっていると考えられる。 In particular, in the combination of a silicon substrate and a GaN-based semiconductor film, for example, the thermal expansion coefficient of Si is 2.4 × 10 −6 (1 / K), whereas the thermal expansion coefficient of GaN is 5.59. × 10 −6 (1 / K). That is, there is a large difference in the coefficient of thermal expansion between the silicon substrate and the GaN-based semiconductor film. For this reason, when a GaN-based semiconductor film is formed on a silicon substrate at a high temperature of 1000 to 1300 ° C. using MOCVD, the amount of shrinkage of the GaN-based semiconductor film when the temperature drops is more than twice that of the silicon substrate. Thus, the stacked body of the silicon substrate and the GaN-based semiconductor film has a warp that protrudes downward. In addition, the lattice constant of Si is 3.18Å, whereas the lattice constant of GaN is 5.43Å, which has a large lattice strain. Thus, in addition to the fact that the wafer is likely to be warped due to the difference in thermal expansion coefficient between them, a relatively large lattice strain is caused due to the difference in lattice constant between the two, so that the back surface of the silicon substrate 101 It is thought that cracks are likely to occur during polishing.
　図１０Ｃは、上記シリコン基板１０１の裏面１０１Ｃを研削,研磨して行く際に、ＧａＮ膜周縁部１０２Ａやシリコン基板１０１の一部に深いクラック１０５が生じた様子を示す電子顕微鏡写真である。 FIG. 10C is an electron micrograph showing a deep crack 105 formed in the GaN film peripheral portion 102A and part of the silicon substrate 101 when the back surface 101C of the silicon substrate 101 is ground and polished.
　また、上記ウエハを研削,研磨してから、上記シリコン基板１０１の面取りされた周辺部１０１ＡにＧａＮ膜周縁部１０２Ａが残ったままの状態で、チップ化するためにステップカット方式でダイシングを行うと、硬いＧａＮ膜の破片で２軸目の幅の狭いブレードが目詰まりし、ブレードの切れ味が悪くなり、シリコン基板１０１の裏面１０１Ｃに細かい欠け(裏面チッピング)が多く発生することも判明した。 Further, after grinding and polishing the wafer, dicing is performed by a step-cut method in order to form a chip with the GaN film peripheral portion 102A remaining on the chamfered peripheral portion 101A of the silicon substrate 101. It was also found that the narrow blade of the second axis is clogged with fragments of the hard GaN film, the blade becomes dull, and a lot of fine chips (back surface chipping) occur on the back surface 101C of the silicon substrate 101.
　そこで、この発明の課題は、周辺部を有するシリコン基板上にＧａＮ系半導体膜をエピタキシャル成長させた積層体を裏面研磨する際の割れを防止できると共にチップ化のためのダイシング時にウエハの裏面チッピングが発生することを防止できる半導体装置の製造方法を提供することにある。 Therefore, the object of the present invention is to prevent cracking when the backside polishing of a laminated body in which a GaN-based semiconductor film is epitaxially grown on a silicon substrate having a peripheral portion, and to generate backside chipping of the wafer during dicing for chip formation. An object of the present invention is to provide a method of manufacturing a semiconductor device that can prevent this.
　上記課題を解決するため、この発明の半導体装置の製造方法は、周辺部を有するシリコン基板上にＧａＮ系半導体膜をエピタキシャル成長させ、
　上記シリコン基板上に上記ＧａＮ系半導体膜を含む半導体素子を形成し、
　上記シリコン基板の周辺部およびこの周辺部上に形成された上記ＧａＮ系半導体膜を切除してから、
　上記シリコン基板の裏面を研磨することを特徴としている。 In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention epitaxially grows a GaN-based semiconductor film on a silicon substrate having a peripheral portion,
Forming a semiconductor element including the GaN-based semiconductor film on the silicon substrate;
After cutting out the peripheral part of the silicon substrate and the GaN-based semiconductor film formed on the peripheral part,
The back surface of the silicon substrate is polished.
　この発明の半導体装置の製造方法によれば、上記シリコン基板の周辺部およびこの周辺部上に形成された上記ＧａＮ系半導体膜を切除することにより、シリコン基板の側面にＧａＮ系半導体膜が被さっていない状態になる。この後に、上記シリコン基板の裏面を研削,研磨することにより、上記シリコン基板の裏面研磨中にＧａＮ系半導体膜が研削されないようにすることができるので、ウエハの割れを防止できる。 According to the method for manufacturing a semiconductor device of the present invention, the GaN-based semiconductor film is covered on the side surface of the silicon substrate by cutting the peripheral portion of the silicon substrate and the GaN-based semiconductor film formed on the peripheral portion. No state. After this, by grinding and polishing the back surface of the silicon substrate, it is possible to prevent the GaN-based semiconductor film from being ground during the back surface polishing of the silicon substrate, so that cracking of the wafer can be prevented.
　また、上記シリコン基板の側面にＧａＮ系半導体膜が被さっていないので、チップ化のためのステップカット方式のダイシング時に２軸目の幅の狭いブレードがＧａＮ系半導体膜を切削することがなくなる。これにより、硬いＧａＮ膜の破片で２軸目の幅の狭いブレードが目詰まりする現象が解消されるので、ブレードの切れ味低下を回避でき、シリコン基板の裏面に細かい欠け(裏面チッピング)が発生するのを防止できる。 Further, since the side surface of the silicon substrate is not covered with the GaN-based semiconductor film, the second-axis narrow blade does not cut the GaN-based semiconductor film during the step-cut dicing for chip formation. This eliminates the phenomenon of the clogging of the narrow blade of the second axis due to hard GaN film fragments, so that the sharpness of the blade can be prevented from being reduced, and fine chipping (back surface chipping) occurs on the back surface of the silicon substrate. Can be prevented.
　また、一実施形態の半導体装置の製造方法では、上記シリコン基板は、Ｇｅがドープされている。 In the method for manufacturing a semiconductor device according to one embodiment, the silicon substrate is doped with Ge.
　この実施形態の半導体装置の製造方法によれば、Ｇｅがドープされて硬度が高くなり割れやすくなったシリコン基板の裏面研磨時の割れやダイシング時の裏面チッピングの発生を防止できる。 According to the method for manufacturing a semiconductor device of this embodiment, it is possible to prevent the occurrence of cracking during backside polishing and backside chipping during dicing of a silicon substrate that has been doped with Ge and has increased hardness and is easily cracked.
　尚、シリコン基板へのＧｅドープは、上記シリコン基板上にＧａＮ系半導体膜をエピタキシャル成長させた積層体の反りを低減するために行われる。 In addition, Ge doping to a silicon substrate is performed in order to reduce the curvature of the laminated body which epitaxially grew the GaN-type semiconductor film on the said silicon substrate.
　また、一実施形態の半導体装置の製造方法では、上記シリコン基板を回転ステージ上に載置し、
　上記回転ステージを回転させて上記シリコン基板を回転させ、
　上記回転ステージの回転軸と略直交する回転軸周りに回転するダイシングブレードを、上記シリコン基板の周辺部上に形成された上記ＧａＮ系半導体膜の上方から下方へ向けて下降させて、上記シリコン基板の周辺部およびこの周辺部上に形成された上記ＧａＮ系半導体膜を切除する。 In one embodiment of the method for manufacturing a semiconductor device, the silicon substrate is placed on a rotating stage,
Rotate the rotary stage to rotate the silicon substrate,
A dicing blade that rotates about a rotation axis that is substantially orthogonal to the rotation axis of the rotation stage is lowered from above the GaN-based semiconductor film formed on the peripheral portion of the silicon substrate, and the silicon substrate is lowered. And the GaN-based semiconductor film formed on the periphery is cut away.
　この実施形態の半導体装置の製造方法によれば、上記シリコン基板の周辺部およびこの周辺部上に形成された上記ＧａＮ系半導体膜を効率よく切除できる。 According to the method of manufacturing a semiconductor device of this embodiment, the peripheral portion of the silicon substrate and the GaN-based semiconductor film formed on the peripheral portion can be efficiently cut off.
　また、一実施形態の半導体装置の製造方法では、上記シリコン基板の裏面を研磨した後、
　上記ＧａＮ系半導体膜およびシリコン基板をステップカット方式でダイシングして半導体素子が形成された複数の半導体チップを切り出す。 In one embodiment of the method of manufacturing a semiconductor device, after polishing the back surface of the silicon substrate,
The GaN-based semiconductor film and the silicon substrate are diced by a step cut method to cut out a plurality of semiconductor chips on which semiconductor elements are formed.
　この実施形態の半導体装置の製造方法によれば、ＧａＮ系半導体膜を含む半導体素子が形成されたウエハを、ステップカット方式で効率よくかつ裏面チッピングを抑制しつつ複数の半導体チップに切り出すことができる。 According to the method for manufacturing a semiconductor device of this embodiment, a wafer on which a semiconductor element including a GaN-based semiconductor film is formed can be cut into a plurality of semiconductor chips with a step cut method while efficiently suppressing backside chipping. .
　この発明の半導体装置の製造方法によれば、シリコン基板の周辺部およびこの周辺部上に形成されたＧａＮ系半導体膜を切除することにより、シリコン基板の側面にＧａＮ系半導体膜が被さっていない状態になる。この後に、上記シリコン基板の裏面を研削,研磨することにより、上記シリコン基板の裏面研磨中にＧａＮ系半導体膜が研削されないようにすることができるで、ウエハの割れを防止できる。 According to the method for manufacturing a semiconductor device of the present invention, the GaN-based semiconductor film is not covered on the side surface of the silicon substrate by cutting the peripheral portion of the silicon substrate and the GaN-based semiconductor film formed on the peripheral portion. become. Thereafter, by grinding and polishing the back surface of the silicon substrate, it is possible to prevent the GaN-based semiconductor film from being ground during the back surface polishing of the silicon substrate, so that cracking of the wafer can be prevented.
この発明の半導体装置の製造方法の実施形態で用いるシリコン基板とＧａＮ系半導体膜の積層体の断面図である。It is sectional drawing of the laminated body of the silicon substrate and GaN-type semiconductor film used with embodiment of the manufacturing method of the semiconductor device of this invention. 上記積層体の周辺部をダイシングブレードで切除する様子を示す断面図である。It is sectional drawing which shows a mode that the peripheral part of the said laminated body is excised with a dicing blade. 上記ダイシングブレードで切除した後の積層体の断面図である。It is sectional drawing of the laminated body after excising with the said dicing blade. 上記積層体の周辺部をダイシングブレードで切除する様子を示す斜視図である。It is a perspective view which shows a mode that the peripheral part of the said laminated body is excised with a dicing blade. 上記ダイシングブレードで周辺部が切除された上記積層体を裏面研磨しステップカット方式でダイシングした後の断面を撮影した写真を示す図である。It is a figure which shows the photograph which image | photographed the cross section after carrying out back surface grinding | polishing of the said laminated body from which the peripheral part was excised with the said dicing blade, and dicing with the step cut method. 上記周辺部を切除していない比較例の積層体を裏面研磨しステップカット方式でダイシングした後の断面を撮影した写真を示す図である。It is a figure which shows the photograph which image | photographed the cross section after carrying out back surface grinding | polishing of the laminated body of the comparative example which has not excised the said peripheral part, and dicing with the step cut system. 上記ダイシングブレードで周辺部が切除された上記積層体を裏面研磨しステップカット方式でダイシングした後の裏面を撮影した写真による部分裏面図である。It is a partial back view by the photograph which image | photographed the back surface after carrying out back surface grinding | polishing of the said laminated body by which the peripheral part was excised with the said dicing blade, and dicing with the step cut system. 上記周辺部を切除していない比較例の積層体を裏面研磨しステップカット方式でダイシングした後の裏面を撮影した写真による部分裏面図である。It is a partial back view by the photograph which image | photographed the back surface after carrying out back surface grinding | polishing of the laminated body of the comparative example which has not excised the said peripheral part, and dicing with the step cut system. 上記実施形態で作製する半導体素子の一例であるＧａＮ系ＦＥＴの断面図である。It is sectional drawing of GaN-type FET which is an example of the semiconductor element produced in the said embodiment. シリコン基板上に形成されたＧａＮ系半導体膜の周縁部がシリコン基板の周辺部から裏面側に達している様子を示す部分断面図である。It is a fragmentary sectional view which shows a mode that the peripheral part of the GaN-type semiconductor film formed on the silicon substrate has reached the back surface side from the peripheral part of the silicon substrate. 上記シリコン基板の裏面から研削,研磨して行く際に研磨面が周辺部から回り込んだＧａＮ膜周縁部に達している様子を示す部分断面図である。It is a fragmentary sectional view which shows a mode that the grinding | polishing surface has reached the peripheral part of the GaN film which went around from the peripheral part when grinding and grinding | polishing from the back surface of the said silicon substrate. 上記シリコン基板の裏面を研削,研磨して行く際にＧａＮ膜周縁部やシリコン基板の一部に深いクラックが生じた様子を示す電子顕微鏡写真による斜視図である。It is a perspective view by an electron micrograph showing a state in which deep cracks are generated in the peripheral part of the GaN film and a part of the silicon substrate when the back surface of the silicon substrate is ground and polished.
　以下、この発明を図示の実施の形態により詳細に説明する。 Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.
　この実施形態の半導体装置の製造方法では、まず、図１に示すように、面取りされた周辺部１Ａを有するシリコン基板１上にＧａＮ系半導体膜２をエピタキシャル成長させる。上記シリコン基板１の厚さは、一例として、５００μｍ～７００μｍ程度である。また、上記ＧａＮ系半導体膜２の膜厚は、一例として、５μｍ～１０μｍ程度である。 In the semiconductor device manufacturing method of this embodiment, first, as shown in FIG. 1, a GaN-based semiconductor film 2 is epitaxially grown on a silicon substrate 1 having a chamfered peripheral portion 1A. The thickness of the silicon substrate 1 is, for example, about 500 μm to 700 μm. The film thickness of the GaN-based semiconductor film 2 is, for example, about 5 μm to 10 μm.
　次に、上記シリコン基板１上に上記ＧａＮ系半導体膜２を含む半導体素子を作製する。 Next, a semiconductor element including the GaN-based semiconductor film 2 is fabricated on the silicon substrate 1.
　図９を参照して、上記半導体素子の具体的一例としてのＧａＮ系ＦＥＴ(電界効果トランジスタ)を作製する工程について説明する。 Referring to FIG. 9, a process of manufacturing a GaN-based FET (field effect transistor) as a specific example of the semiconductor element will be described.
　図９に示すように、上記面取りされた周辺部１Ａを有する厚さ６２５μｍのシリコン基板１上に、ＭＯＣＶＤ(有機金属気相成長)法を用いて、アンドープＡｌＧａＮバッファ層９２、アンドープＧａＮチャネル層９３、アンドープＡｌＧａＮバリア層９４、を順に形成する。このＡｌＧａＮバッファ層９２とＧａＮチャネル層９３とＡｌＧａＮバリア層９４がＧａＮ系半導体膜２を構成している。図９において、符号９９は、ＡｌＧａＮバリア層９４とＧａＮチャネル層９３との界面に形成される２次元電子ガスを示している。 As shown in FIG. 9, an undoped AlGaN buffer layer 92 and an undoped GaN channel layer 93 are formed on the silicon substrate 1 having a thickness of 625 μm having the chamfered peripheral portion 1A by using MOCVD (metal organic chemical vapor deposition). Then, an undoped AlGaN barrier layer 94 is formed in order. The AlGaN buffer layer 92, the GaN channel layer 93, and the AlGaN barrier layer 94 constitute the GaN-based semiconductor film 2. In FIG. 9, reference numeral 99 indicates a two-dimensional electron gas formed at the interface between the AlGaN barrier layer 94 and the GaN channel layer 93.
　ここで、上記シリコン基板１は、反りを抑制するためにＢ(ホウ素)‐Ｇｅ(ゲルマニウム)を１０１９(ｃｍ－３)台の密度でコドープを行ったものを用いた。このようにコドープを行ったシリコン基板１は、硬度が高くなっており、非常に研磨し難いものである。 Here, the silicon substrate 1 used was codoped with B (boron) -Ge (germanium) at a density of 10 19 (cm −3 ) in order to suppress warpage. The co-doped silicon substrate 1 has a high hardness and is very difficult to polish.
　上記ＡｌＧａＮバリア層９４上にソース電極９５とドレイン電極９６とゲート電極９８を形成している。このソース電極９５とドレイン電極９６とゲート電極９８の製造方法は、特に限定されず、例えば蒸着等の公知の方法を使用する。また、上記ソース電極９５とドレイン電極９６との間隔およびゲート電極９８の位置などは、電界効果トランジスタの所望する性能に応じて調整する。上記ソース電極９５とドレイン電極９６の材料としては、Ｔｉ/ＡｌやＨｆ/Ａｌ/Ａｕなどが用いられる。また、ゲート電極９８の材料としては、ＷＮやＴｉＮなどのショットキー障壁が形成されるものが用いられる。 A source electrode 95, a drain electrode 96, and a gate electrode 98 are formed on the AlGaN barrier layer 94. The manufacturing method of the source electrode 95, the drain electrode 96, and the gate electrode 98 is not specifically limited, For example, well-known methods, such as vapor deposition, are used. The distance between the source electrode 95 and the drain electrode 96, the position of the gate electrode 98, and the like are adjusted according to the desired performance of the field effect transistor. As the material of the source electrode 95 and the drain electrode 96, Ti / Al, Hf / Al / Au, or the like is used. In addition, as a material of the gate electrode 98, a material that forms a Schottky barrier such as WN or TiN is used.
　次に、上記ＡｌＧａＮバリア層９４上に、プラズマＣＶＤ等の公知の方法でＳｉＮからなる絶縁膜９７を形成する。なお、ソース電極９５,ドレイン電極９６,ゲート電極９８を形成する前に絶縁膜９７を形成してもよい。 Next, an insulating film 97 made of SiN is formed on the AlGaN barrier layer 94 by a known method such as plasma CVD. Note that the insulating film 97 may be formed before the source electrode 95, the drain electrode 96, and the gate electrode 98 are formed.
　こうして製造されたＧａＮ系ＦＥＴは、チャネル層９３とバリア層９４との間に２次元電子ガス９９が形成されており、上記ゲート電極９８に電圧を印加することにより上記チャネル層９３を制御することで、オンオフされる。このＧａＮ系ＦＥＴでは、ゲート電極９８に負電圧が印加されているときにゲート電極９８下のＧａＮチャネル層９３に空乏層が形成されてオフ状態となる一方、ゲート電極９８の電圧が零のときにゲート電極９８下のＧａＮチャネル層９３に空乏層がなくなってオン状態となるノーマリオンタイプのトランジスタである。 In the GaN-based FET manufactured in this manner, a two-dimensional electron gas 99 is formed between the channel layer 93 and the barrier layer 94, and the channel layer 93 is controlled by applying a voltage to the gate electrode 98. It is turned on and off. In this GaN-based FET, when a negative voltage is applied to the gate electrode 98, a depletion layer is formed in the GaN channel layer 93 under the gate electrode 98 to be turned off, while the voltage of the gate electrode 98 is zero. In addition, the GaN channel layer 93 under the gate electrode 98 is a normally-on type transistor that is turned on when the depletion layer disappears.
　なお、この具体的一例では、ＧａＮ系ＦＥＴをノーマリオンタイプのトランジスタとして説明したが、ゲート電極の下にメサ構造のｐ型ＧａＮ層を設けて、ゲート電極下には２次元電子ガスが生じないようにしたノーマリオフタイプのトランジスタとしてもよい。 In this specific example, the GaN-based FET has been described as a normally-on type transistor. However, a p-type GaN layer having a mesa structure is provided under the gate electrode, and no two-dimensional electron gas is generated under the gate electrode. A normally-off type transistor may be used.
　このようなＧａＮ系ＦＥＴは、例えば、６００Ｖを超える高電圧で、５Ａ～６０Ａの電流を流すスイッチング素子として用いることを想定している。したがって、ＦＥＴのジャンクションからの発熱を如何にして逃がすかということがデバイス設計上で非常に重要になる。 It is assumed that such a GaN-based FET is used as a switching element that flows a current of 5 A to 60 A at a high voltage exceeding 600 V, for example. Therefore, how to release heat generated from the junction of the FET is very important in device design.
　また、シリコン基板１へＧａＮ系半導体膜２をエピタキシャル成長させることは、安価に製造できる利点があるものの、シリコン基板１とＧａＮ系半導体膜２との間の熱膨張係数の相違によりウエハの反りが生じやすい。このウエハの反りを抑えるために、例えば、６インチのシリコン基板では、通常のＬＳＩ工場での製造装置とのマッチングも考慮して、６２５μｍの基板厚さを採用している。このシリコン基板１上に形成するＧａＮ系半導体膜２の膜厚は、高々５～１０μｍ程度である。このため、放熱特性の向上のために、後述するようにシリコン基板１の裏面を研磨して厚さを薄くすることがなされる。 In addition, epitaxial growth of the GaN-based semiconductor film 2 on the silicon substrate 1 has an advantage that it can be manufactured at low cost, but the wafer warps due to the difference in thermal expansion coefficient between the silicon substrate 1 and the GaN-based semiconductor film 2. Cheap. In order to suppress the warpage of the wafer, for example, a 6-inch silicon substrate adopts a substrate thickness of 625 μm in consideration of matching with a manufacturing apparatus in a normal LSI factory. The film thickness of the GaN-based semiconductor film 2 formed on the silicon substrate 1 is about 5 to 10 μm at most. For this reason, in order to improve the heat dissipation characteristics, the back surface of the silicon substrate 1 is polished to reduce the thickness as will be described later.
　次に、図４に示すように、上記ＧａＮ系半導体膜２がエピタキシャル成長されて上記半導体素子が形成されたシリコン基板１を回転ステージ５１上に載置し、この回転ステージ５１を、図４の矢印Ｘで示す方向に回転中心軸Ｊ周りに回転させて上記シリコン基板１を回転させる。この回転ステージ５１の回転速度は、一例として、１°/秒～６°/秒の範囲内の予め定められた値に設定される。なお、上記回転ステージ５１には、上記シリコン基板１を回転ステージ５１に固定するためのダイシングシート(図示せず)が貼られている。 Next, as shown in FIG. 4, the silicon substrate 1 on which the GaN-based semiconductor film 2 is epitaxially grown to form the semiconductor element is placed on a rotary stage 51, and the rotary stage 51 is attached to the arrow in FIG. 4. The silicon substrate 1 is rotated by rotating around the rotation center axis J in the direction indicated by X. As an example, the rotational speed of the rotary stage 51 is set to a predetermined value within a range of 1 ° / second to 6 ° / second. A dicing sheet (not shown) for fixing the silicon substrate 1 to the rotary stage 51 is attached to the rotary stage 51.
　次に、図４に示すように、円板上のダイシングブレード５２を上記回転ステージ５１の回転中心軸Ｊと略直交する回転軸周りに回転させる。このダイシングブレード５２の回転速度は、一例として、１５０００ｒｐｍから２５０００ｒｐｍの範囲内の予め定められた値に設定される。 Next, as shown in FIG. 4, the dicing blade 52 on the disk is rotated around a rotation axis substantially orthogonal to the rotation center axis J of the rotation stage 51. As an example, the rotational speed of the dicing blade 52 is set to a predetermined value within the range of 15000 rpm to 25000 rpm.
　そして、上記ダイシングブレード５２を上記シリコン基板１の周辺部１Ａ上に形成された上記ＧａＮ系半導体膜２の上方から下方へ向けて下降させる。これにより、上記ダイシングブレード５２は、図２の断面図に示すように、上記シリコン基板１の周辺部１Ａ上に形成された上記ＧａＮ系半導体膜２から上記シリコン基板１の周辺部１Ａに切れ込む。そして、回転ステージ５１とともにシリコン基板１が１回転することで、上記シリコン基板１の周辺部１Ａおよびこの周辺部１Ａ上に形成された上記ＧａＮ系半導体膜２の環状部分が切除される。上記周辺部１Ａを切除する幅寸法は、一例として、約１ｍｍである。 Then, the dicing blade 52 is lowered from above to below the GaN-based semiconductor film 2 formed on the peripheral portion 1A of the silicon substrate 1. As a result, the dicing blade 52 cuts from the GaN-based semiconductor film 2 formed on the peripheral portion 1A of the silicon substrate 1 into the peripheral portion 1A of the silicon substrate 1 as shown in the cross-sectional view of FIG. Then, the silicon substrate 1 rotates once together with the rotary stage 51, so that the peripheral portion 1A of the silicon substrate 1 and the annular portion of the GaN-based semiconductor film 2 formed on the peripheral portion 1A are cut off. As an example, the width dimension for cutting out the peripheral portion 1A is about 1 mm.
　図３に、上記シリコン基板１の周辺部１Ａおよびこの周辺部１Ａ上に形成された上記ＧａＮ系半導体膜２の環状部分が切除された状態のシリコン基板１とＧａＮ系半導体膜２の積層体３１の断面を示す。図３に示すように、上記シリコン基板１の面取りされた周辺部１Ａおよびこの周辺部１Ａ上に形成された上記ＧａＮ系半導体膜２を切除することにより、シリコン基板１の側面１ＢにＧａＮ系半導体膜２が被さっていない状態になる。 FIG. 3 shows a laminated body 31 of the silicon substrate 1 and the GaN-based semiconductor film 2 in a state where the peripheral portion 1A of the silicon substrate 1 and the annular portion of the GaN-based semiconductor film 2 formed on the peripheral portion 1A are removed. The cross section of is shown. As shown in FIG. 3, by chamfering the chamfered peripheral portion 1A of the silicon substrate 1 and the GaN-based semiconductor film 2 formed on the peripheral portion 1A, a GaN-based semiconductor is formed on the side surface 1B of the silicon substrate 1. The film 2 is not covered.
　次に、上記シリコン基板１の裏面１Ｃを研磨する。この研磨では、一例として、粒度３６０のダイヤモンド砥石で荒研磨した後、粒度２０００のダイヤモンド砥石で仕上げを行い、１００μｍ～３００μｍの厚さ(例えば２４０μｍ)まで薄くした。 Next, the back surface 1C of the silicon substrate 1 is polished. In this polishing, as an example, after rough polishing with a diamond grindstone with a particle size of 360, finishing was performed with a diamond grindstone with a particle size of 2000, and the thickness was reduced to 100 μm to 300 μm (for example, 240 μm).
　このように、シリコン基板１の側面１ＢにＧａＮ系半導体膜２が被さっていない状態にした後に、シリコン基板１の裏面１Ｃを研磨することにより、上記シリコン基板１の裏面研磨中にＧａＮ系半導体膜２が研削されないようにすることができる。したがって、シリコン基板１の裏面研磨中に硬いＧａＮ系半導体膜２が研削されることを回避して、裏面研磨中にシリコン基板１に発生する応力を低減でき、シリコン基板１にクラックが生じないようにして、ウエハ(積層体３１)の割れを防止できる。 As described above, after the side surface 1B of the silicon substrate 1 is not covered with the GaN-based semiconductor film 2, the back surface 1C of the silicon substrate 1 is polished, so that the GaN-based semiconductor film is polished during the back surface polishing of the silicon substrate 1. 2 can be prevented from being ground. Therefore, it is possible to avoid grinding the hard GaN-based semiconductor film 2 during the back surface polishing of the silicon substrate 1, reduce the stress generated in the silicon substrate 1 during the back surface polishing, and prevent the silicon substrate 1 from cracking. Thus, cracking of the wafer (laminated body 31) can be prevented.
　次に、シリコン基板１とＧａＮ系半導体膜２の積層体３１を、ステップカット方式でダイシングして上記半導体素子が形成された複数の半導体チップを切り出す。このステップカット方式のダイシングでは、例えば、幅４０μｍの１軸目のダイシングブレードを使用して、上記積層体３１の表面から１４０μｍの深さまで切れ込みを入れた後、２軸目の幅３５μｍのダイシングブレードを使用してフルカットを行った。 Next, the stacked body 31 of the silicon substrate 1 and the GaN-based semiconductor film 2 is diced by a step cut method to cut out a plurality of semiconductor chips on which the semiconductor elements are formed. In this step-cut type dicing, for example, a first-axis dicing blade having a width of 40 μm is used to cut from the surface of the laminate 31 to a depth of 140 μm, and then a second-axis dicing blade having a width of 35 μm. A full cut was performed.
　図５は、上記ステップカット方式でダイシングした後の半導体チップの側面を撮影した写真である。図５の符号５５は、１軸目の幅広のダイシングプレートによる切れ込みと２軸目の幅狭のダイシングプレートによる切れ込みとの境界に形成された段差である。上述したように、シリコン基板１の側面１ＢにはＧａＮ系半導体膜２が被さっていない状態である。 FIG. 5 is a photograph of the side surface of the semiconductor chip after dicing by the step cut method. Reference numeral 55 in FIG. 5 denotes a step formed at the boundary between the cut by the first dicing plate having a wider width and the cut by the second dicing plate having a smaller width. As described above, the side surface 1B of the silicon substrate 1 is not covered with the GaN-based semiconductor film 2.
　このように、上記シリコン基板１の側面１ＢにＧａＮ系半導体膜２が被さっていないので、チップ化のためのステップカット方式のダイシング時に２軸目の幅の狭いダイシングブレードがＧａＮ系半導体膜２を切削することがなくなる。これにより、硬いＧａＮ膜の破片で２軸目の幅の狭いダイシングブレードが目詰まりする現象が解消されるので、ダイシングブレードの切れ味低下を回避でき、シリコン基板１の裏面１Ｃに細かい欠け(裏面チッピング)が発生することを防止できる。 As described above, since the GaN-based semiconductor film 2 is not covered with the side surface 1B of the silicon substrate 1, the dicing blade having a narrow second axis width covers the GaN-based semiconductor film 2 at the time of step-cut dicing for chip formation. No cutting. As a result, the phenomenon of clogging the dicing blade having a narrow second axis due to hard GaN film fragments can be eliminated, so that the sharpness of the dicing blade can be prevented from being reduced, and the back surface 1C of the silicon substrate 1 can be finely chipped (back surface chipping). ) Can be prevented.
　図７は、上記実施形態における上記ステップカット方式のダイシング後のシリコン基板１の裏面１Ｃを撮影した写真である。図７の符号７１は、上記ダイシングによる切れ込みである。この実施形態ではダイシング後のシリコン基板１の裏面１Ｃに細かい欠け(裏面チッピング)が発生していない。 FIG. 7 is a photograph of the back surface 1C of the silicon substrate 1 after dicing by the step cut method in the embodiment. Reference numeral 71 in FIG. 7 is a notch due to the dicing. In this embodiment, fine chips (back surface chipping) are not generated on the back surface 1C of the silicon substrate 1 after dicing.
　一方、上記実施形態に対する比較例では、シリコン基板１の周辺部１Ａおよびこの周辺部１Ａ上に形成された上記ＧａＮ系半導体膜２の環状部分を切除する工程を行わない。したがって、この比較例では、上記シリコン基板１の周辺部１Ａ上にＧａＮ系半導体膜２が形成された状態で、シリコン基板１の裏面研磨とその後のチップ化のためのステップカット方式のダイシングを行う。この比較例では、図８(ステップカット方式のダイシング後のシリコン基板１の裏面１Ｃを撮影した写真)に示すように、上記ダイシングによる切れ込み８１に隣接するシリコン基板１の裏面１Ｃに細かい欠け(裏面チッピング)８２が発生している。図６は、この比較例におけるステップカット方式のダイシング後の半導体チップの側面を撮影した写真である。図６に示すように、この比較例では、シリコン基板１の周辺部１Ａおよびこの周辺部１Ａ上にＧａＮ系半導体膜２が存在している状態でチップ化のためのステップカット方式のダイシングを行うので、２軸目の幅の狭いダイシングブレードがＧａＮ系半導体膜２を切削することになる。よって、この比較例では、硬いＧａＮ膜の破片で２軸目の幅の狭いダイシングブレードが目詰まりする現象が生じて、ダイシングブレードの切れ味が低下し、シリコン基板１の裏面１Ｃに細かい欠け(裏面チッピング)８２が発生することとなる。 On the other hand, in the comparative example for the above embodiment, the step of cutting the peripheral portion 1A of the silicon substrate 1 and the annular portion of the GaN-based semiconductor film 2 formed on the peripheral portion 1A is not performed. Therefore, in this comparative example, with the GaN-based semiconductor film 2 formed on the peripheral portion 1A of the silicon substrate 1, step-cut dicing for backside polishing of the silicon substrate 1 and subsequent chip formation is performed. . In this comparative example, as shown in FIG. 8 (photograph of the back surface 1C of the silicon substrate 1 after the step-cut dicing), the back surface 1C of the silicon substrate 1 adjacent to the notch 81 by the dicing described above (a back surface). Chipping) 82 has occurred. FIG. 6 is a photograph of the side surface of the semiconductor chip after dicing by the step cut method in this comparative example. As shown in FIG. 6, in this comparative example, step-cut dicing for chip formation is performed in the state where the peripheral portion 1A of the silicon substrate 1 and the GaN-based semiconductor film 2 are present on the peripheral portion 1A. Therefore, the dicing blade having a narrow width on the second axis cuts the GaN-based semiconductor film 2. Therefore, in this comparative example, a phenomenon occurs in which the dicing blade having a narrow width on the second axis is clogged with a fragment of the hard GaN film, the sharpness of the dicing blade is reduced, and the back surface 1C of the silicon substrate 1 is finely chipped (back surface Chipping) 82 occurs.
　一例として、上記シリコン基板１の周辺部１Ａおよびこの周辺部１Ａ上に形成された上記ＧａＮ系半導体膜２の環状部分を切除する工程を行わない比較例では、１０枚のウエハのうちの８枚のウエハに割れが発生した。また、残り２枚のウエハに対してステップカット方式のダイシングを行ったところ、図８に示すような５０μｍ以上のチッピング(欠け)が生じた。 As an example, in the comparative example in which the step of cutting the peripheral portion 1A of the silicon substrate 1 and the annular portion of the GaN-based semiconductor film 2 formed on the peripheral portion 1A is not performed, eight of the ten wafers Cracks occurred in the wafer. Further, when the step cut type dicing was performed on the remaining two wafers, chipping of 50 μm or more as shown in FIG. 8 occurred.
　これに対して、本実施形態によれば、上述の如く、上記シリコン基板１の面取りされた周辺部１Ａおよびこの周辺部１Ａ上に形成された上記ＧａＮ系半導体膜２を切除して、シリコン基板１の側面１ＢにＧａＮ系半導体膜２が被さっていない状態にしてから、裏面研磨およびチップ化のためのダイシングを行っている。 On the other hand, according to the present embodiment, as described above, the chamfered peripheral portion 1A of the silicon substrate 1 and the GaN-based semiconductor film 2 formed on the peripheral portion 1A are excised to obtain a silicon substrate. After the side surface 1B of 1 is not covered with the GaN-based semiconductor film 2, dicing for back surface polishing and chip formation is performed.
　したがって、本実施形態では、一例として、１０枚のウエハのうちウエハの割れが発生したのは０枚でウエハの割れは発生しなかった。また、その後、上記１０枚のウエハに対してステップカット方式のダイシングを行ったところ、裏面チッピング量は３０μｍであり、素子特性上問題の無いレベルであった。 Therefore, in this embodiment, as an example, out of 10 wafers, no wafer cracking occurred and no wafer cracking occurred. After that, the step-cut type dicing was performed on the ten wafers. As a result, the back surface chipping amount was 30 μm, and there was no problem in terms of device characteristics.
　本実施形態では、面取りされた周辺部を有するシリコン基板を用いていたが、これに限らず、面取りされていない周辺部を有するシリコン基板を用いてもよい。 In this embodiment, a silicon substrate having a chamfered peripheral portion is used, but the present invention is not limited to this, and a silicon substrate having a peripheral portion that is not chamfered may be used.
　尚、この発明の製造方法におけるＧａＮ系半導体膜は、ＡlxＩnyＧa1-x-yＮ(ｘ≧０、ｙ≧０、０≦ｘ＋ｙ＜１)で表されるＧａＮ系半導体層を含むものでもよい。すなわち、この発明の製造方法におけるＧａＮ系半導体膜は、ＡｌＧａＮ、ＧａＮ、ＩｎＧａＮ等を含むものとしてもよい。また、この発明で製造するＧａＮ系半導体素子は、上記実施形態のＨＦＥＴに限らず、絶縁ゲート構造等の他の構造の電界効果トランジスタであってもよく、ＧａＮ系ダイオードでもよい。 Note that the GaN-based semiconductor film in the manufacturing method of the present invention includes a GaN-based semiconductor layer represented by Al x In y Ga 1-xy N (x ≧ 0, y ≧ 0, 0 ≦ x + y <1). Good. That is, the GaN-based semiconductor film in the manufacturing method of the present invention may include AlGaN, GaN, InGaN, and the like. Further, the GaN-based semiconductor device manufactured by the present invention is not limited to the HFET of the above embodiment, but may be a field effect transistor having another structure such as an insulated gate structure, or a GaN-based diode.
１　シリコン基板
１Ａ　周辺部
１Ｂ　側面
１Ｃ　裏面
２　ＧａＮ系半導体膜
３１　積層体
５１　回転ステージ
５２　ダイシングブレード
７１,８１　切れ込み
８２　裏面チッピング
９２　アンドープＡｌＧａＮバッファ層
９３　アンドープＧａＮチャネル層
９４　ＡｌＧａＮバリア層
９５　ソース電極
９６　ドレイン電極
９７　絶縁膜
９８　ゲート電極
９９　２次元電子ガス DESCRIPTION OF SYMBOLS 1 Silicon substrate 1A Peripheral part 1B Side surface 1C Back surface 2 GaN-type semiconductor film 31 Stack 51 Rotary stage 52 Dicing blade 71,81 Notch 82 Back surface chipping 92 Undoped AlGaN buffer layer 93 Undoped GaN channel layer 94 AlGaN barrier layer 95 Source electrode 96 Drain Electrode 97 Insulating film 98 Gate electrode 99 Two-dimensional electron gas

Claims (4)

  1. 　周辺部(１Ａ)を有するシリコン基板(１)上にＧａＮ系半導体膜(２)をエピタキシャル成長させ、
    　上記シリコン基板(１)上に上記ＧａＮ系半導体膜(２)を含む半導体素子を形成し、
    　上記シリコン基板(１)の周辺部(１Ａ)およびこの周辺部(１Ａ)上に形成された上記ＧａＮ系半導体膜(２)を切除してから、
    　上記シリコン基板(１)の裏面(１Ｃ)を研磨することを特徴とする半導体装置の製造方法。     A GaN-based semiconductor film (2) is epitaxially grown on a silicon substrate (1) having a peripheral portion (1A),
    Forming a semiconductor element including the GaN-based semiconductor film (2) on the silicon substrate (1);
    After cutting the peripheral portion (1A) of the silicon substrate (1) and the GaN-based semiconductor film (2) formed on the peripheral portion (1A),
    A method of manufacturing a semiconductor device, comprising polishing the back surface (1C) of the silicon substrate (1).
  2. 　請求項１に記載の半導体装置の製造方法において、
    　上記シリコン基板(１)は、
    　Ｇｅがドープされていることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 1,
    The silicon substrate (1)
    A method of manufacturing a semiconductor device, wherein Ge is doped.
  3. 　請求項１または２に記載の半導体装置の製造方法において、
    　上記ＧａＮ系半導体膜(２)がエピタキシャル成長されて上記半導体素子が形成されたシリコン基板(１)を回転ステージ(５１)上に載置し、
    　上記回転ステージ(５１)を回転させて上記シリコン基板(１)を回転させ、
    　上記回転ステージ(５１)の回転軸と略直交する回転軸周りに回転するダイシングブレード(５２)を、上記シリコン基板(１)の周辺部(１Ａ)上に形成された上記ＧａＮ系半導体膜(２)の上方から下方へ向けて下降させて、上記シリコン基板(１)の周辺部(１Ａ)およびこの周辺部(１Ａ)上に形成された上記ＧａＮ系半導体膜(２)を切除することを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 1 or 2,
    The silicon substrate (1) on which the semiconductor element is formed by epitaxially growing the GaN-based semiconductor film (2) is placed on a rotating stage (51),
    The silicon substrate (1) is rotated by rotating the rotary stage (51),
    The GaN-based semiconductor film (2) formed on the peripheral portion (1A) of the silicon substrate (1) is a dicing blade (52) that rotates about a rotation axis substantially orthogonal to the rotation axis of the rotation stage (51). ) From above to below, the peripheral portion (1A) of the silicon substrate (1) and the GaN-based semiconductor film (2) formed on the peripheral portion (1A) are cut off. A method for manufacturing a semiconductor device.
  4. 　請求項１から３のいずれか１つに記載の半導体装置の製造方法において、
    　上記シリコン基板(１)の裏面(１Ｃ)を研磨した後、
    　上記ＧａＮ系半導体膜(２)およびシリコン基板(１)をステップカット方式でダイシングして半導体素子が形成された複数の半導体チップを切り出すことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to any one of claims 1 to 3,
    After polishing the back surface (1C) of the silicon substrate (1),
    A method of manufacturing a semiconductor device, comprising: dicing the GaN-based semiconductor film (2) and the silicon substrate (1) by a step-cut method to cut out a plurality of semiconductor chips on which semiconductor elements are formed.
PCT/JP2013/072283 2012-09-10 2013-08-21 Semiconductor device producing method WO2014038374A1 (en)

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JP2011103389A (en) * 2009-11-11 2011-05-26 Disco Abrasive Syst Ltd Method of processing wafer
JP2012043825A (en) * 2010-08-12 2012-03-01 Disco Abrasive Syst Ltd Wafer processing method
JP2012066943A (en) * 2010-09-21 2012-04-05 Silicon Technology Co Ltd Substrate for forming nitride semiconductor, and nitride semiconductor
JP2012151412A (en) * 2011-01-21 2012-08-09 Disco Abrasive Syst Ltd Grinding method of hard substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011103389A (en) * 2009-11-11 2011-05-26 Disco Abrasive Syst Ltd Method of processing wafer
JP2012043825A (en) * 2010-08-12 2012-03-01 Disco Abrasive Syst Ltd Wafer processing method
JP2012066943A (en) * 2010-09-21 2012-04-05 Silicon Technology Co Ltd Substrate for forming nitride semiconductor, and nitride semiconductor
JP2012151412A (en) * 2011-01-21 2012-08-09 Disco Abrasive Syst Ltd Grinding method of hard substrate

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