WO2014036872A1 - Bipolar junction transistor and manufacturing method thereof - Google Patents
Bipolar junction transistor and manufacturing method thereof Download PDFInfo
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- WO2014036872A1 WO2014036872A1 PCT/CN2013/080674 CN2013080674W WO2014036872A1 WO 2014036872 A1 WO2014036872 A1 WO 2014036872A1 CN 2013080674 W CN2013080674 W CN 2013080674W WO 2014036872 A1 WO2014036872 A1 WO 2014036872A1
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- well region
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- junction transistor
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000007943 implant Substances 0.000 claims description 29
- 238000002513 implantation Methods 0.000 claims description 27
- 238000005468 ion implantation Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 230000003321 amplification Effects 0.000 abstract description 4
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 14
- 238000009826 distribution Methods 0.000 description 8
- 239000012535 impurity Substances 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
Definitions
- the present invention relates to a semiconductor device structure and a method of fabricating the same, and more particularly to a bipolar junction transistor and a method of fabricating the same, which are in the field of semiconductor device fabrication.
- Bipolar Junction Transistor also known as semiconductor triode, is a device that combines two PN junctions through a certain process.
- the basic structure can be divided into two types: PNP and NPN.
- Bipolar junction transistors have amplifying effects and are widely used in various circuit designs such as: detection, rectification, amplification, switching, voltage regulation, signal modulation, etc.
- bipolar junction transistors are limited by the need for amplification factor (Hfe).
- the base region concentration is not high or the base region is narrow.
- the collector-to-emitter breakdown voltage (BVceo) is about 10 ⁇ 30V, which limits the limit. Its application in the field of high pressure.
- BVceo breakdown voltage
- the invention patent application of the Chinese Patent Application No. CN200810147770.3 discloses a bipolar junction transistor which can be applied to fields such as high power converters.
- the bipolar junction transistor includes a substrate, a collector region, an emitter region, a base region, an emitter electrode, a base electrode, and a collector electrode, wherein a floating buried layer is disposed inside the base region, and The floating buried layer material is different from the base material.
- the BJT structure realizes a high breakdown voltage by fabricating a floating buried layer inside the base region.
- the structure requires a floating buried layer of different materials in the base region, which is complicated in process and high in cost.
- the technical problem to be solved by the present invention is to provide a bipolar junction transistor and a method for fabricating the same, which have better high voltage resistance performance under the condition of ensuring the magnification requirement, and the manufacturing method thereof Compatible with existing manufacturing processes.
- a bipolar junction transistor comprising:
- a first conductive well region respectively located on both sides of the second conductive type well region and on the first conductive type bottom well region;
- a second conductivity type implant region is disposed under the first conductivity type emitter region.
- the concentration of the second conductivity type implantation region is higher than the concentration of the second conductivity type well region.
- the number of the second conductivity type implantation regions is one or more.
- a second conductivity type base region implantation region is disposed around the second conductivity type base region, and the second conductivity type base region injection region portion extends below the first conductivity type emitter region.
- the concentration of the second conductivity type base region implantation region is higher than the concentration of the second conductivity type well region.
- the manufacturing method of the above bipolar junction transistor comprises the following steps:
- Step 1 forming a first conductivity type bottom well region, a second conductivity type well region, and a first guide on the semiconductor substrate An electric well region, the second conductive type well region and the first conductive type well region are located on the first conductive type bottom well region and the first conductive type well region is located on both sides of the second conductive type well region;
- Step 2 forming one or more second conductivity type implant regions on the second conductivity type well region;
- Step 3 forming a first conductivity type emitter region and a second conductivity type on the second conductivity type well region a base region, the second conductive type base region is located on both sides of the first conductive type emitter region, and the first conductive type emitter region is located above the one or more second conductivity type implant regions;
- Step 4 forming a first conductive type collector region on the first conductive type well region.
- the one or more second conductivity type implantation regions are formed by ion implantation.
- the concentration of the second conductivity type implantation region is higher than the concentration of the second conductivity type well region.
- a second conductivity type base region implantation region is formed while forming one or more second conductivity type implant regions, so that the second conductivity type base region is surrounded by the second conductivity type implant region. And the second conductive type base region implantation region partially extends below the first conductive type emitter region.
- the method of forming the second conductivity type base region implantation region by ion implantation is employed.
- the concentration of the second conductivity type base region implantation region is higher than the concentration of the second conductivity type well region.
- the bipolar junction transistor provided by the invention can adjust the impurity distribution under the emission region by adding an additional implantation region under the emission region, which can be obtained under the same Hfe as compared with the conventional bipolar junction transistor.
- the higher BVceo; its manufacturing process, the conditions are compatible with the typical CMOS / LDMOS integrated circuit manufacturing process.
- FIG. 1 is a schematic structural view of a high voltage bipolar junction transistor according to an embodiment of the present invention.
- 2 is a schematic structural view of a conventional bipolar junction transistor according to an embodiment of the present invention.
- FIG. 4 is a Gummel curve of Ic/Ib-Vbe of a high voltage bipolar junction transistor in an embodiment of the present invention.
- Figure 5 is a graph showing the Hfe-Ic curve of a high voltage bipolar junction transistor in accordance with an embodiment of the present invention.
- Figure 6 is a BVceo curve of a high voltage bipolar junction transistor in accordance with an embodiment of the present invention.
- Figure 7 is a graph showing current-voltage characteristics of Ic-Vc of a high voltage bipolar junction transistor in an embodiment of the present invention.
- the present invention improves the structure of the conventional bipolar junction transistor, and provides a high voltage resistant bipolar junction transistor structure, which is transmitted through An additional injection zone is added below the zone to adjust the impurity distribution below the emitter zone and a higher BVceo can be obtained under the same Hfe.
- FIG. 1 is a schematic structural view of a high voltage bipolar junction transistor according to an embodiment of the present invention. As shown in Figure 1, the bipolar junction transistor includes:
- the first conductivity type bottom well region 100 is usually fabricated on a semiconductor substrate
- first conductivity type well region 102 respectively located on both sides of the second conductivity type well region 101 and on the first conductivity type bottom well region 100; a first conductivity type emitter region 103 on the second conductivity type well region 101;
- a second conductive type base region 104 located on both sides of the first conductive type emitter region 103;
- a second conductivity type implant region 106 is provided under the first conductivity type emitter region 103.
- the concentration of the second conductivity type implant region 106 is higher than the concentration of the second conductivity type well region 101.
- the concentration of the second conductivity type well region 101 is Iel4 ⁇ lel6 cm- 3
- the concentration of the second conductivity type implantation region 106 is Iel6 ⁇ lel8 cm- 3 .
- only one second conductivity type implant region 106 is shown in FIG.
- the number of the second conductivity type implant regions 106 in the present invention is not limited to one, and may be two in other examples of the present invention.
- a second conductive type base region implant region 107 is further disposed around the second conductive type base region 104, and the second conductive type base region implant region 107 partially extends to the first conductive type emitter region 103.
- the concentration of the second conductivity type base region implantation region 107 is higher than the concentration of the second conductivity type well region 101.
- the concentration of the second conductivity type base region implantation region 107 may be the same as the second conductivity type implantation region.
- the concentration of 106 is the same, which is lel6 ⁇ lel8 cm- 3 .
- the number, shape (for example, circular or square) of the second conductive type implanted region 106 and the second conductive type base region implanted region 107, and the specific arrangement manner are not limited, and those skilled in the art can
- the device needs to be designed and adjusted to achieve optimal device characteristics by adjusting its concentration, width, number, and spacing.
- the BJT When the first conductivity type is N type and the second conductivity type is P type, the BJT is NPN type; when the first conductivity type is P type and the second conductivity type is N type, the BJT is PNP type.
- FIG. 2 shows a schematic structural diagram of a conventional bipolar junction transistor, including: a first conductivity type bottom well region 200, and a second conductivity type well region. 201.
- the ordinary BJT structure shown in FIG. 2 is not provided with the second conductivity type implant region and the second conductivity type base region implant region under the first conductivity type emitter region 203 as compared with the high voltage BJT structure shown in FIG. That is, the impurity distribution of the ordinary BJT structure of FIG.
- FIG. 2 is the same at A 2 A 2 and B 2 B 2 , and the high-pressure BJT shown in FIG. 1 is different from the impurity distribution at BiBi.
- the impurity distribution at A 2 A 2 is the same, and the impurity distribution at BiBi, and B 2 B 2 is shown in Fig. 3.
- the BVceo and Hfe of a conventional bipolar junction transistor are almost entirely determined by the second conductivity type well region 201 (PWell), and the second conductivity type well region 201 cannot be freely adjusted depending on the requirements of the device.
- the high voltage bipolar junction transistor provided by the invention can adjust the impurity distribution under the emission region by adding an additional implantation region under the emission region, so that the lower concentration well region can ensure the higher Hfe, and The higher concentration of the extra implant area guarantees a higher BVceo, so a higher BVceo can be achieved at the same Hfe compared to a conventional bipolar junction transistor, allowing it to be applied to higher input voltages. .
- FIG. 5, FIG. 6, and FIG. 7 are respectively a Gummel curve, a Hfe-Ic curve, a BVceo curve, and a current-voltage of Ic-Vc of a high voltage bipolar junction transistor according to an embodiment of the present invention.
- Characteristic curve, the Hfe of the high-voltage BJT is about 28, and the BVceo is about 60V. After experimental comparison, it can be seen that the breakdown voltage BVceo does have a large increase compared with the ordinary BJT.
- the method of making the high voltage BJT can include the following steps:
- Step 1 forming a first conductive type bottom well region, a second conductive type well region and a first conductive type well region on the semiconductor substrate, wherein the second conductive type well region and the first conductive type well region are located at the first conductive type
- the first well-type well region is located on both sides of the second conductivity type well region.
- the semiconductor village bottom can be selected as the silicon village.
- Forming the first conductive type bottom well region, the second conductive type well region, and the first conductive type well region may adopt an existing CMOS/LDMOS integrated circuit manufacturing process, which is a process known to those skilled in the art, and thus is not here. Narration.
- Step 2 forming one or more second conductivity type implant regions on the second conductivity type well region.
- the forming the one or more second conductivity type implantation regions may adopt an ion implantation method, and the concentration, the width, the number, and the spacing of the implantation regions may be adjusted by an ion implantation process, thereby obtaining the most according to the specific needs of different devices. Excellent Hfe and BVceo features.
- concentration of the injection zone is different, the width, the number, and the pitch may also be different.
- a second conductive type base region implant region may be formed while forming one or more second conductivity type implant regions, and the second conductivity type base region is formed by the second conductivity type implant region.
- the second conductive type base region implantation region partially extends below the first conductive type emitter region.
- forming the second conductivity type base region implantation region may adopt an ion implantation method, and the concentration, the width, the number, and the pitch of the implantation region may be adjusted by an ion implantation process, thereby obtaining an optimal according to specific requirements of different devices. Hfe and BVceo features. When the concentration of the injection zone is different, the width, the number, and the pitch may also be different.
- the concentration of the second conductivity type implant region should be higher than the concentration of the second conductivity type well region, and the concentration of the second conductivity type base region implant region should be higher than the concentration of the second conductivity type well region.
- Step 3 forming a first conductive type emitter region and a second conductive type base region on the second conductive type well region, wherein the second conductive type base region is located on both sides of the first conductive type emitter region, and makes the first The conductive emitter region is located above one or more second conductivity type implant regions.
- Step 4 forming a first conductive type collector region on the first conductive type well region.
- the collector is led out from the collector region, the emitter region leads to the emitter, and the base region leads to the base.
- the fabrication process of the high-voltage BJT structure is compatible with the typical CMOS/LDMOS integrated circuit manufacturing process except that one lithography and ion implantation are required.
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Abstract
Disclosed are a bipolar junction transistor and a manufacturing method thereof. The bipolar junction transistor comprises a first conductivity type bottom well region (100), a second conductivity type well region (101) located at the first conductivity type bottom well region (100), a first conductivity type well region (102) located respectively at two sides of the second conductivity type well region (101) and at the first conductivity type bottom well region (100), a first conductivity type emitter region (103) located at the second conductivity type well region (101), a second conductivity type base region (104) located at two sides of the first conductivity type emitter region (103), and a first conductivity type collector region (105) located at the first conductivity type well region (102). A second conductivity type injector region (106) is arranged under the first conductivity type emitter region (103). In the case of meeting requirements of an amplification factor, the bipolar junction transistor has good high-voltage resistance capabilities, and the manufacturing method of the bipolar junction transistor can be compatible with the existing manufacturing process.
Description
一种双极结型晶体管及其制作方法 Bipolar junction transistor and manufacturing method thereof
技术领域 本发明涉及一种半导体器件结构及制作方法，尤其涉及一种双极结型晶体管 及其制作方法， 属于半导体器件制造领域。 BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device structure and a method of fabricating the same, and more particularly to a bipolar junction transistor and a method of fabricating the same, which are in the field of semiconductor device fabrication.
背景技术 Background technique
双极结型晶体管 （ Bipolar Junction Transistor— BJT ) 又称为半导体三极管， 它是通过一定的工艺将两个 PN结结合在一起的器件， 基本结构可分为 PNP和 NPN 两种类型， 其外部引出有三个极： 集电极、 发射极和基极， 其中集电极从 集电区引出， 发射极从发射区引出， 基极从基区引出。 双极结型晶体管具有放大 作用， 广泛应用于各类电路设计中， 例如： 检波， 整流、 放大、 开关、 稳压、 信 号调制…等等。 Bipolar Junction Transistor (BJT), also known as semiconductor triode, is a device that combines two PN junctions through a certain process. The basic structure can be divided into two types: PNP and NPN. There are three poles: the collector, the emitter and the base, wherein the collector is led out of the collector, the emitter is led out of the emitter, and the base is led out of the base. Bipolar junction transistors have amplifying effects and are widely used in various circuit designs such as: detection, rectification, amplification, switching, voltage regulation, signal modulation, etc.
传统的双极结型晶体管受限于放大倍数 (Hfe)的需求， 基区浓度不高或基区 很窄， 集电极至发射极的击穿电压 (BVceo)约为 10~30V左右， 限制了其在高压 领域的应用。对于日渐兴起的高压半导体集成电路工艺而言，提高双极结型晶体 管的击穿电压 (BVceo)及其他耐高压性能， 以满足更多的芯片设计需求， 成为一 个研究课题。 Conventional bipolar junction transistors are limited by the need for amplification factor (Hfe). The base region concentration is not high or the base region is narrow. The collector-to-emitter breakdown voltage (BVceo) is about 10~30V, which limits the limit. Its application in the field of high pressure. For the emerging high-voltage semiconductor integrated circuit process, increasing the breakdown voltage (BVceo) and other high-voltage resistance of the bipolar junction transistor to meet more chip design requirements has become a research topic.
中国专利申请号为 CN200810147770.3的发明专利申请就公开了一种能够应 用于大功率变换器等领域的双极结型晶体管。 该双极结型晶体管包括村底、 集电 区、 发射区、 基区、 发射极电极、 基极电极和集电极电极， 其特征在于， 在基区 内部设置有浮空埋层， 且所述浮空埋层材料与基区材料相异。 该 BJT结构通过 在基区内部制作浮空埋层， 实现了较高的击穿电压， 然而该结构需要在基区内部 制作不同材料的浮空埋层， 工艺较为复杂， 成本也较高。 The invention patent application of the Chinese Patent Application No. CN200810147770.3 discloses a bipolar junction transistor which can be applied to fields such as high power converters. The bipolar junction transistor includes a substrate, a collector region, an emitter region, a base region, an emitter electrode, a base electrode, and a collector electrode, wherein a floating buried layer is disposed inside the base region, and The floating buried layer material is different from the base material. The BJT structure realizes a high breakdown voltage by fabricating a floating buried layer inside the base region. However, the structure requires a floating buried layer of different materials in the base region, which is complicated in process and high in cost.
为了满足更多高压半导体集成电路的设计需求，实有必要提供一种工艺筒单 的双极结型晶体管结构， 在保证 Hfe 满足需求的情况下， 提高器件的击穿电压
BVceo, 并与现有 CMOS制程兼容。 In order to meet the design requirements of more high-voltage semiconductor integrated circuits, it is necessary to provide a bipolar junction transistor structure with a single process, which improves the breakdown voltage of the device while ensuring that the Hfe meets the demand. BVceo, and is compatible with existing CMOS processes.
发明内容 本发明要解决的技术问题在于提供一种双极结型晶体管及其制作方法，该双 极结型晶体管在保证满足放大倍数的需求情况下， 具有较好的耐高压性能， 其制 作方法可与现有的制造工艺兼容。 SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to provide a bipolar junction transistor and a method for fabricating the same, which have better high voltage resistance performance under the condition of ensuring the magnification requirement, and the manufacturing method thereof Compatible with existing manufacturing processes.
为了解决上述技术问题， 本发明采用如下技术方案： In order to solve the above technical problem, the present invention adopts the following technical solutions:
一种双极结型晶体管， 包括： A bipolar junction transistor, comprising:
第一导电型底阱区； First conductivity type bottom well region;
位于所述第一导电型底阱区上的第二导电型阱区； a second conductivity type well region on the first conductivity type bottom well region;
分别位于所述第二导电型阱区两侧且在所述第一导电型底阱区上的第一导 电型阱区； a first conductive well region respectively located on both sides of the second conductive type well region and on the first conductive type bottom well region;
位于所述第二导电型阱区上的第一导电型发射区； a first conductivity type emitter region on the second conductivity type well region;
位于所述第一导电型发射区两侧的第二导电型基区； a second conductive type base region on both sides of the first conductive type emitter region;
位于所述第一导电型阱区上的第一导电型集电区； a first conductive type collector region on the first conductive type well region;
其中， 在第一导电型发射区下设有第二导电型注入区。 Wherein, a second conductivity type implant region is disposed under the first conductivity type emitter region.
作为本发明的优选方案，第二导电型注入区的浓度高于第二导电型阱区的浓 度。 As a preferred embodiment of the present invention, the concentration of the second conductivity type implantation region is higher than the concentration of the second conductivity type well region.
作为本发明的优选方案， 第二导电型注入区数量为 1个或多个。 As a preferred embodiment of the present invention, the number of the second conductivity type implantation regions is one or more.
作为本发明的优选方案，在第二导电型基区周围设置有第二导电型基区注入 区， 所述第二导电型基区注入区部分延伸至第一导电型发射区下方。 As a preferred embodiment of the present invention, a second conductivity type base region implantation region is disposed around the second conductivity type base region, and the second conductivity type base region injection region portion extends below the first conductivity type emitter region.
作为本发明的优选方案，所述第二导电型基区注入区的浓度高于第二导电型 阱区的浓度。 As a preferred embodiment of the present invention, the concentration of the second conductivity type base region implantation region is higher than the concentration of the second conductivity type well region.
上述双极结型晶体管的制作方法， 包括如下步骤： The manufacturing method of the above bipolar junction transistor comprises the following steps:
步骤一、在半导体村底上形成第一导电型底阱区、第二导电型阱区和第一导
电型阱区，所述第二导电型阱区和第一导电型阱区位于第一导电型底阱区上且第 一导电型阱区位于第二导电型阱区两侧； Step 1: forming a first conductivity type bottom well region, a second conductivity type well region, and a first guide on the semiconductor substrate An electric well region, the second conductive type well region and the first conductive type well region are located on the first conductive type bottom well region and the first conductive type well region is located on both sides of the second conductive type well region;
步骤二、 在所述第二导电型阱区上形成一个或多个第二导电型注入区； 步骤三、 在所述第二导电型阱区上形成第一导电型发射区和第二导电型基 区， 所述第二导电型基区位于第一导电型发射区两侧，且使第一导电型发射区位 于一个或多个第二导电型注入区之上； Step 2, forming one or more second conductivity type implant regions on the second conductivity type well region; Step 3, forming a first conductivity type emitter region and a second conductivity type on the second conductivity type well region a base region, the second conductive type base region is located on both sides of the first conductive type emitter region, and the first conductive type emitter region is located above the one or more second conductivity type implant regions;
步骤四、 在所述第一导电型阱区上形成第一导电型集电区。 Step 4, forming a first conductive type collector region on the first conductive type well region.
作为本发明的优选方案，形成所述一个或多个第二导电型注入区采用离子注 入的方法。 As a preferred embodiment of the present invention, the one or more second conductivity type implantation regions are formed by ion implantation.
作为本发明的优选方案，所述第二导电型注入区的浓度高于第二导电型阱区 的浓度。 As a preferred embodiment of the present invention, the concentration of the second conductivity type implantation region is higher than the concentration of the second conductivity type well region.
作为本发明的优选方案， 步骤二中，在形成一个或多个第二导电型注入区同 时形成第二导电型基区注入区，使第二导电型基区由第二导电型注入区包围，且 所述第二导电型基区注入区部分延伸至第一导电型发射区下方。 As a preferred embodiment of the present invention, in step 2, a second conductivity type base region implantation region is formed while forming one or more second conductivity type implant regions, so that the second conductivity type base region is surrounded by the second conductivity type implant region. And the second conductive type base region implantation region partially extends below the first conductive type emitter region.
作为本发明的优选方案，形成所述第二导电型基区注入区采用离子注入的方 法。 As a preferred embodiment of the present invention, the method of forming the second conductivity type base region implantation region by ion implantation is employed.
作为本发明的优选方案，所述第二导电型基区注入区的浓度高于第二导电型 阱区的浓度。 As a preferred embodiment of the present invention, the concentration of the second conductivity type base region implantation region is higher than the concentration of the second conductivity type well region.
本发明的有益效果在于： The beneficial effects of the invention are:
本发明提供的双极结型晶体管， 通过在发射区下方增设了额外的注入区，从 而可调整发射区下方的杂质分布， 与传统的双极结型晶体管相比， 在相同的 Hfe 下可以获得更高的 BVceo ; 其制作工艺筒单， 制成条件皆可与典型的 CMOS/LDMOS集成电路制造工艺兼容。 The bipolar junction transistor provided by the invention can adjust the impurity distribution under the emission region by adding an additional implantation region under the emission region, which can be obtained under the same Hfe as compared with the conventional bipolar junction transistor. The higher BVceo; its manufacturing process, the conditions are compatible with the typical CMOS / LDMOS integrated circuit manufacturing process.
附图说明 图 1为本发明实施例中高压双极结型晶体管的结构示意图。
图 2为本发明实施例中普通双极结型晶体管的结构示意图。 BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic structural view of a high voltage bipolar junction transistor according to an embodiment of the present invention. 2 is a schematic structural view of a conventional bipolar junction transistor according to an embodiment of the present invention.
图 3为本发明实施例中 BiBi，和 B2B2，处的杂质分布对比图。 3 is a comparison diagram of impurity distributions at BiBi, and B 2 B 2 in the examples of the present invention.
图 4为本发明实施例中高压双极结型晶体管的 Ic/Ib-Vbe的 Gummel曲线。 图 5为本发明实施例中高压双极结型晶体管的 Hfe-Ic曲线。 4 is a Gummel curve of Ic/Ib-Vbe of a high voltage bipolar junction transistor in an embodiment of the present invention. Figure 5 is a graph showing the Hfe-Ic curve of a high voltage bipolar junction transistor in accordance with an embodiment of the present invention.
图 6为本发明实施例中高压双极结型晶体管的 BVceo曲线。 Figure 6 is a BVceo curve of a high voltage bipolar junction transistor in accordance with an embodiment of the present invention.
图 7为本发明实施例中高压双极结型晶体管的 Ic-Vc的电流-电压特性曲线。 Figure 7 is a graph showing current-voltage characteristics of Ic-Vc of a high voltage bipolar junction transistor in an embodiment of the present invention.
具体实施方式 下面将结合附图， 对本发明实施例中的技术方案进行清楚、 完整地描述， 为 了示出的方便附图并未按照比例绘制。显然， 所描述的实施例仅是本发明一部分 实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在 没有做出创造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范 围。 The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings. It is apparent that the described embodiments are only a part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
正如背景技术部分所述， 传统的双极结型晶体管受限于放大倍数 (Hfe)的需 求，基区浓度不高或基区很窄， 集电极至发射极的击穿电压 (BVceo)约为 10~30V 左右， 限制了其在高压领域的应用。 为了在保证 Hfe满足需求的情况下， 提高器 件的击穿电压 BVceo, 本发明对传统双极结型晶体管结构进行改良，提供了一种 耐高压的双极结型晶体管结构， 该结构通过在发射区下方增设额外的注入区，从 而可调整发射区下方的杂质分布，在相同的 Hfe下可以获得更高的 BVceo。 下面 结合附图对本发明方案进行详细的描述。 As described in the background section, conventional bipolar junction transistors are limited by the need for amplification (Hfe), the base concentration is not high or the base region is narrow, and the collector to emitter breakdown voltage (BVceo) is approximately Around 10~30V, it limits its application in the high voltage field. In order to improve the breakdown voltage BVceo of the device while ensuring that the Hfe meets the demand, the present invention improves the structure of the conventional bipolar junction transistor, and provides a high voltage resistant bipolar junction transistor structure, which is transmitted through An additional injection zone is added below the zone to adjust the impurity distribution below the emitter zone and a higher BVceo can be obtained under the same Hfe. The solution of the present invention will be described in detail below with reference to the accompanying drawings.
图 1为本发明实施例中高压双极结型晶体管的结构示意图。如图 1所示， 该 双极结型晶体管包括： FIG. 1 is a schematic structural view of a high voltage bipolar junction transistor according to an embodiment of the present invention. As shown in Figure 1, the bipolar junction transistor includes:
第一导电型底阱区 100, 通常制作于半导体村底上； The first conductivity type bottom well region 100 is usually fabricated on a semiconductor substrate;
位于所述第一导电型底阱区 100上的第二导电型阱区 101 ; a second conductivity type well region 101 on the first conductivity type bottom well region 100;
分别位于所述第二导电型阱区 101两侧且在所述第一导电型底阱区 100上的 第一导电型阱区 102;
位于所述第二导电型阱区 101上的第一导电型发射区 103; a first conductivity type well region 102 respectively located on both sides of the second conductivity type well region 101 and on the first conductivity type bottom well region 100; a first conductivity type emitter region 103 on the second conductivity type well region 101;
位于所述第一导电型发射区 103两侧的第二导电型基区 104; a second conductive type base region 104 located on both sides of the first conductive type emitter region 103;
位于所述第一导电型阱区 102上的第一导电型集电区 105; a first conductive type collector region 105 on the first conductivity type well region 102;
其中， 在第一导电型发射区 103下设有第二导电型注入区 106。 Therein, a second conductivity type implant region 106 is provided under the first conductivity type emitter region 103.
优选地， 第二导电型注入区 106的浓度要高于第二导电型阱区 101的浓度。 例如， 第二导电型阱区 101的浓度为 Iel4~lel6 cm-3, 第二导电型注入区 106的 浓度为 Iel6~lel8 cm—3。 此外， 虽然图 1中仅示出一个第二导电型注入区 106, 但本发明中第二导电型注入区 106的数量不限制为 1个，在本发明的其他实例中 也可以是两个、 三个或者更多个。 作为本发明的优选实施例， 第二导电型基区 104周围还设置有第二导电型基区注入区 107, 所述第二导电型基区注入区 107 部分延伸至第一导电型发射区 103 下方。 优选地， 所述第二导电型基区注入区 107的浓度要高于第二导电型阱区 101的浓度，例如，第二导电型基区注入区 107 的浓度可以与第二导电型注入区 106的浓度相同， 为 lel6~lel8 cm-3。 Preferably, the concentration of the second conductivity type implant region 106 is higher than the concentration of the second conductivity type well region 101. For example, the concentration of the second conductivity type well region 101 is Iel4~lel6 cm- 3 , and the concentration of the second conductivity type implantation region 106 is Iel6~lel8 cm- 3 . In addition, although only one second conductivity type implant region 106 is shown in FIG. 1, the number of the second conductivity type implant regions 106 in the present invention is not limited to one, and may be two in other examples of the present invention.工具以上的As a preferred embodiment of the present invention, a second conductive type base region implant region 107 is further disposed around the second conductive type base region 104, and the second conductive type base region implant region 107 partially extends to the first conductive type emitter region 103. Below. Preferably, the concentration of the second conductivity type base region implantation region 107 is higher than the concentration of the second conductivity type well region 101. For example, the concentration of the second conductivity type base region implantation region 107 may be the same as the second conductivity type implantation region. The concentration of 106 is the same, which is lel6~lel8 cm- 3 .
需要说明的是，第二导电型注入区 106及第二导电型基区注入区 107的数量、 形状（例如圓形或者方形）及具体排列方式并不是限制性的， 本领域技术人员可 以根据具体器件的需要进行设计调整， 通过调整其浓度、 宽度、 数量以及间距可 获得最优的器件特性。 It should be noted that the number, shape (for example, circular or square) of the second conductive type implanted region 106 and the second conductive type base region implanted region 107, and the specific arrangement manner are not limited, and those skilled in the art can The device needs to be designed and adjusted to achieve optimal device characteristics by adjusting its concentration, width, number, and spacing.
当第一导电型为 N型， 第二导电型为 P型时， 该 BJT为 NPN型； 当第一导 电型为 P型， 第二导电型为 N型时， 该 BJT为 PNP型。 When the first conductivity type is N type and the second conductivity type is P type, the BJT is NPN type; when the first conductivity type is P type and the second conductivity type is N type, the BJT is PNP type.
为了对比传统 BJT与本发明的高压 BJT的耐高压性能， 图 2给出了一种普 通的双极结型晶体管的结构示意图， 包括： 第一导电型底阱区 200、 第二导电型 阱区 201、 第一导电型阱区 202、 第一导电型发射区 203、 第二导电型基区 204 和第一导电型集电区 205。图 2所示的普通 BJT结构与图 1所示的高压 BJT结构 相比，其在第一导电型发射区 203下没有设置第二导电型注入区和第二导电型基 区注入区。 即图 2的普通 BJT结构在 A2A2，和 B2B2，处的杂质分布是相同的， 而 图 1所示的高压 BJT在 ，和 BiBi，处的杂质分布是不同的，其中 ，与 A2A2， 处的杂质分布相同， BiBi，和 B2B2，处的杂质分布对比图如图 3所示。
普通双极结型晶体管的 BVceo 及 Hfe 几乎完全由第二导电型阱区 201 ( PWell ) 决定， 受限于器件的需求， 第二导电型阱区 201不可以随意调整。 即 使第二导电型阱区 201可以根据双极结型晶体管的高压需求做适当调整，在第二 导电型阱区 201浓度提高时， Hfe会迅速下降， 而 BVceo却提高的很緩慢。 而本 发明提供的高压双极结型晶体管，通过在发射区下方增设了额外的注入区，从而 可调整发射区下方的杂质分布， 这样较低浓度的阱区可以保证其较高的 Hfe, 而 较高浓度的额外注入区却可以保证其较高的 BVceo,因此与传统的双极结型晶体 管相比，在相同的 Hfe下可以获得更高的 BVceo,使其可以应用于更高的输入电 压。 In order to compare the high voltage resistance of the conventional BJT with the high voltage BJT of the present invention, FIG. 2 shows a schematic structural diagram of a conventional bipolar junction transistor, including: a first conductivity type bottom well region 200, and a second conductivity type well region. 201. The first conductive type well region 202, the first conductive type emitter region 203, the second conductive type base region 204, and the first conductive type collector region 205. The ordinary BJT structure shown in FIG. 2 is not provided with the second conductivity type implant region and the second conductivity type base region implant region under the first conductivity type emitter region 203 as compared with the high voltage BJT structure shown in FIG. That is, the impurity distribution of the ordinary BJT structure of FIG. 2 is the same at A 2 A 2 and B 2 B 2 , and the high-pressure BJT shown in FIG. 1 is different from the impurity distribution at BiBi. The impurity distribution at A 2 A 2 is the same, and the impurity distribution at BiBi, and B 2 B 2 is shown in Fig. 3. The BVceo and Hfe of a conventional bipolar junction transistor are almost entirely determined by the second conductivity type well region 201 (PWell), and the second conductivity type well region 201 cannot be freely adjusted depending on the requirements of the device. Even if the second conductivity type well region 201 can be appropriately adjusted according to the high voltage requirement of the bipolar junction transistor, when the concentration of the second conductivity type well region 201 is increased, the Hfe is rapidly decreased, and the BVceo is increased slowly. The high voltage bipolar junction transistor provided by the invention can adjust the impurity distribution under the emission region by adding an additional implantation region under the emission region, so that the lower concentration well region can ensure the higher Hfe, and The higher concentration of the extra implant area guarantees a higher BVceo, so a higher BVceo can be achieved at the same Hfe compared to a conventional bipolar junction transistor, allowing it to be applied to higher input voltages. .
图 4、 图 5、 图 6、 图 7 分别为本发明一实施例的高压双极结型晶体管的 Ic/Ib-Vbe的 Gummel曲线、 Hfe-Ic曲线、 BVceo曲线以及 Ic-Vc的电流-电压特 性曲线， 该高压 BJT的 Hfe约为 28, BVceo约为 60V, 经过实验对比， 可见其 击穿电压 BVceo与普通 BJT相比确实有较大幅度的提高。 4, FIG. 5, FIG. 6, and FIG. 7 are respectively a Gummel curve, a Hfe-Ic curve, a BVceo curve, and a current-voltage of Ic-Vc of a high voltage bipolar junction transistor according to an embodiment of the present invention. Characteristic curve, the Hfe of the high-voltage BJT is about 28, and the BVceo is about 60V. After experimental comparison, it can be seen that the breakdown voltage BVceo does have a large increase compared with the ordinary BJT.
制作该高压 BJT的方法可以包括以下步骤： The method of making the high voltage BJT can include the following steps:
步骤一、在半导体村底上形成第一导电型底阱区、第二导电型阱区和第一导 电型阱区，所述第二导电型阱区和第一导电型阱区位于第一导电型底阱区上且第 一导电型阱区位于第二导电型阱区两侧。 Step 1: forming a first conductive type bottom well region, a second conductive type well region and a first conductive type well region on the semiconductor substrate, wherein the second conductive type well region and the first conductive type well region are located at the first conductive type The first well-type well region is located on both sides of the second conductivity type well region.
其中， 半导体村底可选为硅村底。 形成第一导电型底阱区、 第二导电型阱区 和第一导电型阱区可采用现有的 CMOS/LDMOS集成电路制造工艺，此为本领域 技术人员习知的工艺， 故在此不赘述。 Among them, the semiconductor village bottom can be selected as the silicon village. Forming the first conductive type bottom well region, the second conductive type well region, and the first conductive type well region may adopt an existing CMOS/LDMOS integrated circuit manufacturing process, which is a process known to those skilled in the art, and thus is not here. Narration.
步骤二、 在所述第二导电型阱区上形成一个或多个第二导电型注入区。 Step 2, forming one or more second conductivity type implant regions on the second conductivity type well region.
其中， 形成所述一个或多个第二导电型注入区可采用离子注入的方法，通过 离子注入工艺可以调整该注入区的浓度、 宽度、 数量以及间距， 从而可以根据不 同器件的具体需求获得最优的 Hfe与 BVceo特性。 在该注入区的浓度不同时， 其宽度、 数量以及间距也可以不同。 The forming the one or more second conductivity type implantation regions may adopt an ion implantation method, and the concentration, the width, the number, and the spacing of the implantation regions may be adjusted by an ion implantation process, thereby obtaining the most according to the specific needs of different devices. Excellent Hfe and BVceo features. When the concentration of the injection zone is different, the width, the number, and the pitch may also be different.
作为本发明的优选实例， 步骤二中，在形成一个或多个第二导电型注入区同 时还可形成第二导电型基区注入区， 使第二导电型基区由第二导电型注入区包
围， 且所述第二导电型基区注入区部分延伸至第一导电型发射区下方。 其中， 形成所述第二导电型基区注入区可采用离子注入的方法，通过离子注 入工艺可以调整该注入区的浓度、 宽度、 数量以及间距， 从而可以根据不同器件 的具体需求获得最优的 Hfe与 BVceo特性。 在该注入区的浓度不同时， 其宽度、 数量以及间距也可以不同。 As a preferred example of the present invention, in step 2, a second conductive type base region implant region may be formed while forming one or more second conductivity type implant regions, and the second conductivity type base region is formed by the second conductivity type implant region. Package And the second conductive type base region implantation region partially extends below the first conductive type emitter region. Wherein, forming the second conductivity type base region implantation region may adopt an ion implantation method, and the concentration, the width, the number, and the pitch of the implantation region may be adjusted by an ion implantation process, thereby obtaining an optimal according to specific requirements of different devices. Hfe and BVceo features. When the concentration of the injection zone is different, the width, the number, and the pitch may also be different.
其中， 所述第二导电型注入区的浓度应高于第二导电型阱区的浓度， 所述第 二导电型基区注入区的浓度应高于第二导电型阱区的浓度。 The concentration of the second conductivity type implant region should be higher than the concentration of the second conductivity type well region, and the concentration of the second conductivity type base region implant region should be higher than the concentration of the second conductivity type well region.
步骤三、 在所述第二导电型阱区上形成第一导电型发射区和第二导电型基 区， 所述第二导电型基区位于第一导电型发射区两侧，且使第一导电型发射区位 于一个或多个第二导电型注入区之上。 Step 3: forming a first conductive type emitter region and a second conductive type base region on the second conductive type well region, wherein the second conductive type base region is located on both sides of the first conductive type emitter region, and makes the first The conductive emitter region is located above one or more second conductivity type implant regions.
步骤四、 在所述第一导电型阱区上形成第一导电型集电区。 Step 4, forming a first conductive type collector region on the first conductive type well region.
最后， 由集电区引出集电极， 发射区引出发射极， 基区引出基极。 Finally, the collector is led out from the collector region, the emitter region leads to the emitter, and the base region leads to the base.
可见， 该高压 BJT结构的制作工艺， 除了需增加一次光刻并进行离子注入 之外，其余的工艺流程、制成条件皆可与典型的 CMOS/LDMOS集成电路制造工 艺兼容。 It can be seen that the fabrication process of the high-voltage BJT structure is compatible with the typical CMOS/LDMOS integrated circuit manufacturing process except that one lithography and ion implantation are required.
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发 明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的， 本 文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施 例中实现。 因此， 本发明将不会被限制于本文所示的这些实施例， 而是要符合与 本文所公开的原理和新颖特点相一致的最宽的范围。
The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments are obvious to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein.
Claims
1. 一种双极结型晶体管， 其特征在于， 包括： A bipolar junction transistor, comprising:
第一导电型底阱区； First conductivity type bottom well region;
位于所述第一导电型底阱区上的第二导电型阱区； a second conductivity type well region on the first conductivity type bottom well region;
分别位于所述第二导电型阱区两侧且在所述第一导电型底阱区上的 第一导电型阱区； a first conductivity type well region respectively located on both sides of the second conductivity type well region and on the first conductivity type bottom well region;
位于所述第二导电型阱区上的第一导电型发射区； a first conductivity type emitter region on the second conductivity type well region;
位于所述第一导电型发射区两侧的第二导电型基区； a second conductive type base region on both sides of the first conductive type emitter region;
位于所述第一导电型阱区上的第一导电型集电区； a first conductive type collector region on the first conductive type well region;
其中， 在第一导电型发射区下设有第二导电型注入区。 Wherein, a second conductivity type implant region is disposed under the first conductivity type emitter region.
2. 根据权利要求 1 所述的双极结型晶体管， 其特征在于： 第二导电型注入 区的浓度高于第二导电型阱区的浓度。 The bipolar junction transistor according to claim 1, wherein the concentration of the second conductivity type implant region is higher than the concentration of the second conductivity type well region.
3. 根据权利要求 1 所述的双极结型晶体管， 其特征在于： 第二导电型注入 区数量为 1个或多个。 The bipolar junction transistor according to claim 1, wherein the number of the second conductivity type implantation regions is one or more.
4. 根据权利要求 1 所述的双极结型晶体管， 其特征在于： 在第二导电型基 区周围设置有第二导电型基区注入区，所述第二导电型基区注入区部分延 伸至第一导电型发射区下方。 4. The bipolar junction transistor according to claim 1, wherein: a second conductivity type base region implantation region is disposed around the second conductivity type base region, and the second conductivity type base region injection region is partially extended. Below the first conductivity type emitter region.
5. 根据权利要求 4所述的双极结型晶体管， 其特征在于： 所述第二导电型 基区注入区的浓度高于第二导电型阱区的浓度。 The bipolar junction transistor according to claim 4, wherein the concentration of the implantation region of the second conductivity type base region is higher than the concentration of the second conductivity type well region.
6. 一种双极结型晶体管的制作方法， 其特征在于， 包括如下步骤： 6. A method of fabricating a bipolar junction transistor, comprising the steps of:
步骤一、 在半导体村底上形成第一导电型底阱区、 第二导电型阱区 和第一导电型阱区， 所述第二导电型阱区和第一导电型阱区位于第一导 电型底阱区上且第一导电型阱区位于第二导电型阱区两侧；
步骤二、 在所述第二导电型阱区上形成一个或多个第二导电型注入 区； Step 1: forming a first conductive type bottom well region, a second conductive type well region and a first conductive type well region on the semiconductor substrate, wherein the second conductive type well region and the first conductive type well region are located at the first conductive type a type of bottom well region and the first conductivity type well region is located on both sides of the second conductivity type well region; Step 2, forming one or more second conductivity type implant regions on the second conductivity type well region;
步骤三、 在所述第二导电型阱区上形成第一导电型发射区和第二导 电型基区， 所述第二导电型基区位于第一导电型发射区两侧， 且使第一 导电型发射区位于一个或多个第二导电型注入区之上； Step 3: forming a first conductive type emitter region and a second conductive type base region on the second conductive type well region, wherein the second conductive type base region is located on both sides of the first conductive type emitter region, and is first The conductive type emitter region is located above one or more second conductivity type implant regions;
步骤四、 在所述第一导电型阱区上形成第一导电型集电区。 Step 4, forming a first conductive type collector region on the first conductive type well region.
7. 根据权利要求 6所述的双极结型晶体管的制作方法， 其特征在于： 形成 所述一个或多个第二导电型注入区采用离子注入的方法，所述第二导电型 注入区的浓度高于第二导电型阱区的浓度。 7 . The method of fabricating a bipolar junction transistor according to claim 6 , wherein: forming one or more second conductivity type implant regions by ion implantation, and the second conductivity type implant region The concentration is higher than the concentration of the second conductivity type well region.
8. 根据权利要求 6所述的双极结型晶体管的制作方法， 其特征在于： 步骤 二中，在形成一个或多个第二导电型注入区同时形成第二导电型基区注入 区，使第二导电型基区由第二导电型注入区包围， 且所述第二导电型基区 注入区部分延伸至第一导电型发射区下方。 8. The method of fabricating a bipolar junction transistor according to claim 6, wherein: in the second step, forming a second conductivity type base region implantation region while forming one or more second conductivity type implant regions; The second conductivity type base region is surrounded by the second conductivity type implant region, and the second conductivity type base region injection region portion extends below the first conductivity type emitter region.
9. 根据权利要求 8所述的双极结型晶体管的制作方法， 其特征在于： 形成 所述第二导电型基区注入区采用离子注入的方法，所述第二导电型基区注 入区的浓度高于第二导电型阱区的浓度。
9 . The method of fabricating a bipolar junction transistor according to claim 8 , wherein: forming a second conductivity type base region implantation region by ion implantation, and the second conductivity type base region implantation region The concentration is higher than the concentration of the second conductivity type well region.
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| KR20050108200A (en) * | 2004-05-12 | 2005-11-16 | 매그나칩 반도체 유한회사 | Method for manufacturing bipolar junction transistor |
| US20060131693A1 (en) * | 2004-12-17 | 2006-06-22 | Samsung Electronics Co., Ltd. | High-gain bipolar junction transistor compatible with complementary metal-oxide-semiconductor (CMOS) process and method for fabricating the same |
| US20070023866A1 (en) * | 2005-07-27 | 2007-02-01 | International Business Machines Corporation | Vertical silicon controlled rectifier electro-static discharge protection device in bi-cmos technology |
| GB2459695A (en) * | 2008-05-01 | 2009-11-04 | Lime Microsystems Ltd | CMOS compatible NPN bipolar transistors |
| CN102637743A (en) * | 2012-05-02 | 2012-08-15 | 杭州士兰微电子股份有限公司 | Power device and manufacturing method thereof |
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| KR20050108200A (en) * | 2004-05-12 | 2005-11-16 | 매그나칩 반도체 유한회사 | Method for manufacturing bipolar junction transistor |
| US20060131693A1 (en) * | 2004-12-17 | 2006-06-22 | Samsung Electronics Co., Ltd. | High-gain bipolar junction transistor compatible with complementary metal-oxide-semiconductor (CMOS) process and method for fabricating the same |
| US20070023866A1 (en) * | 2005-07-27 | 2007-02-01 | International Business Machines Corporation | Vertical silicon controlled rectifier electro-static discharge protection device in bi-cmos technology |
| GB2459695A (en) * | 2008-05-01 | 2009-11-04 | Lime Microsystems Ltd | CMOS compatible NPN bipolar transistors |
| CN102637743A (en) * | 2012-05-02 | 2012-08-15 | 杭州士兰微电子股份有限公司 | Power device and manufacturing method thereof |
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