GB2459695A - CMOS compatible NPN bipolar transistors - Google Patents

CMOS compatible NPN bipolar transistors Download PDF

Info

Publication number
GB2459695A
GB2459695A GB0807928A GB0807928A GB2459695A GB 2459695 A GB2459695 A GB 2459695A GB 0807928 A GB0807928 A GB 0807928A GB 0807928 A GB0807928 A GB 0807928A GB 2459695 A GB2459695 A GB 2459695A
Authority
GB
United Kingdom
Prior art keywords
forming
type
region
transistor
bjt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0807928A
Other versions
GB2459695B (en
GB0807928D0 (en
Inventor
Nebojsa Jankovic
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lime Microsystems Ltd
Original Assignee
Lime Microsystems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lime Microsystems Ltd filed Critical Lime Microsystems Ltd
Priority to GB0807928.7A priority Critical patent/GB2459695B/en
Publication of GB0807928D0 publication Critical patent/GB0807928D0/en
Publication of GB2459695A publication Critical patent/GB2459695A/en
Application granted granted Critical
Publication of GB2459695B publication Critical patent/GB2459695B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8228—Complementary devices, e.g. complementary transistors
    • H01L21/82285—Complementary vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A mask level for halo implants used for fabricating NMOST devices is also used to fabricate an intrinsic base of a vertical NPN transistor also formed using halo implantation. The base and emitter contacts 101,102 are formed directly over the extrinsic base region 111 and the emitter region 110 respectively giving reduced emitter and base parasitic resistance.

Description

I
CMOS COMPATIBLE VERTICAL NPN BIPOLAR JUNCTION
TRANSISTORS AND METHODS OF PRODUCING THEM
Field of the Invention
The invention is generally related to the field of integrated circuit bipolar junction transistors and more particularly to methods of constructing a high performance vertical bipolar junction transistor.
Background to the Invention
For mixed analog-digital circuit applications, an advanced Complementary Metal-Oxide Semi-conductor (CMOS) processes frequently offers the lateral PNP bipolar junction transistor (LPNP BJT) fabricated in the cost-effective way without additional masking steps on the same substrate with CMOS transistors. The bipolar transistor provides high current driver capabilities and is very useful as a constant current source and active load in many analog/digital applications. While the CMOS devices composed of P and N-channel field effect transistors (NFETs and PFETs) offers low power consumption, high packing density, and high-speed circuit applications, the LPNP BJT exhibits relatively poor performance such as low current gain and low speed. In contrast, the formation of vertical *NPN bipolar junction transistors (VNPN BJTs) with high current gains ( more then 100) and high speed requires more complex processing and new masking layers added to a generic CMOS process with increased manufacturing cost. Therefore, there is still a strong need in the semiconductor industry to make a high performance VNPN BJTs compatible with CMOS technology at a low manufacturing cost.
An advanced CMOS flow includes the following steps: 1. Pattern and implant N+ buried layer implant. 2. Thin layer epitaxial growth. 3.
Shallow Trench Isolation. 4. Pattern and implant p-well implants. 5.
I
Pattern and implant n-well implants. 6. Implant damage anneal. 7. Gate Module for split gate. 8. Drain extension patterns and implants as follows not necessarily in order: pattern and implant drain extensions and pocket for core nMOS; pattern and implant drain extensions and pocket for pMOS; pattern and implant drain extensions and pocket for I/O nMOS; and pattern and implant drain extensions and pocket for I/O pMOS. 9.
Sidewall deposit and etch. 10. Source/drain pattern and implant for nMOS. 11. Source/drain pattern and implant for pMOS. 12. Silicide module. 13. Contact module. 14. Dual Damascene Cu metalization module. 15. Protective Overcoat.
The key masking layers and the final LPNP BJT structure integrated with CMOS transistors in an advanced CMOS process using a P-type bulk/N-type epitaxial layer substrates are shown in FIG.1.A and FIG.B, respectively. Following the N+ buried implant and the low doped n-type epitaxial layer, the base region of LPNP BiT is formed by a separate deep implantation of n-type dopants (phosphorous) performed through the N + SINKER mask partially overlapping the N + buried layer.. A shallow trench (SHT) with oxide filling serves to isolate the N+ SINKER diffusion from the P+ collector regions. The P+ diffused emitter and collector regions of LPNP BJT are formed using the single p-type implantation trough the P + S/D mask followed by a silicon-nitride and the oxide layers deposition and subsequent rapid thermal annealing (RTA) steps. The emitter, the base and the collector ohmic contacts formation is performed by oxide etch using the FIRST METAL CONTACT mask. It exposes a bare silicon to the first metal layer deposition followed by the low temperature thermal annealing step. In order to increase emitter injection efficiency of shallow P+ diffused emitter, the LPNP BJT masking flow chart also incorporates a SILICIDE BLOCK mask (not shown in Fig.1) protecting the emitter contact areas from silicidation process thus avoiding the silicon consumption. Note that Fig. 1 A shows only the key masking layers of LPNP BiT fabrication that are important for understanding this disclosure. The rest of masking layers forming the complete LPNP BJT mask set are assumed generic as they are unchanged when used for processing a novel VNPN BJT.
The very short transistor gate length of CMOS transistors makes them susceptible to hot carrier injection. To reduce this effect, NMOS and PMOS drain extension implants (LDD) are utilized in an advanced CMOS process. The lower doped drain extensions typically extend the heavily doped source and drain regions further under the gate of the transistor.
There are two different kinds of LDD implants: a shallow LDD implant and a deep LDD implant used for the drain extensions of thin gate oxide and the thick gate oxide MOSTs, respectively. Another important implantation process is a pocket or halo implant used to reduce the effect of the short transistor gate length on transistor properties such as threshold voltage or punch-trough effect. The halo implants are of dopants that are of the same type as the channel and of opposite type as that in the source/drain. See Chatterjee et al. U.S. Pat. No. 6,287,920 Bi and Nandakurnar et al. U.S. Pat. No. 6,228,725 Bi. In this disclosure, the simple modification of the LPNP BJT layout will be used to incorporate NMOS LDD, HALO and/or P+ SID implants to create a high performance VNPN BJT within the CMOS integrated system.
A few CMOS designers have proposed the use the halo implants to create the base of various vertical bipolar transistor structures within the integrated system. For example, U.S. Pat. No. 6,303,420 and U.S.Pat.No.6,858,486 disclose a technique of using a halo implant to form an intrinsic base region of VNPN BiTs. However, both inventions are limited in their effectiveness because the intrinsic base region in their inventions must be connected to the outside base electrode via a side region of deep well diffusions. It ultimately results in an increased extrinsic base series resistance and low device dynamic performance. In addition, both inventions propose a non-isolate VNPN BJT structures where the collector region tied to CMOS substrate is permanently grounded which is known to greatly limits the application of such devices in mixed analog-digital signal integrated circuits.
Summary of the Invention
The present invention provides a method of forming a CMOS compatible vertical NPN bipolar junction transistor comprising: providing a p-type silicon body with an n-type top epitaxial layer; forming a collector region in the body using CMOS n-type sinker implants; forming an extrinsic base region in the body using CMOS p-type source-drain implants; forming an intrinsic base region in the body using CMOS p-type halo implants; and forming an emitter region over the intrinsic base region using CMOS n-type source-drain implants and/or CMOS n-type lightly doped drain extension (LDD) implants.
Some embodiments of the instant invention provide a method to achieve a high performance vertical NPN bipolar junction transistor (VNPN BJT) with isolated collector using a modified layout of existing lateral PNP bipolar junction transistor (LPNP BJT) integrated in an advanced CMOS process. The method may comprise: forming a collector region.of said VNPN BJT with the identical mask layer used for LPNP BJT base formation; forming a base region of said VNPN BJT using the mask layer for the NMOST pocket (halo) implant and the mask layer used for LPNP BJT collector implant; and forming the emitter region of said VNPN BJT with the mask layers used for shallow drain extension implant, the deep drain extension implant and/or the source/drain implant of NMOST forming the emitter, base and collector metal contacts of said VNPN BJT using the identical mask layers used for contacts and metal lines as for the
LPNP BJT
The main advantage of such a method is that it utilizes the simplicity of fabricating a high performance bipolar junction transistor with isolated collector together with MOS transistors in an advanced CMOS process without additional photolithographic masking steps. In comparison to the previously proposed similar methods of fabricating VNPN BJT in generic CMOS process, and a particular advantage of said method is the utilization of low doped epitaxial layer as the collector which effectively increases the final depth of the base/collector junction for a given range of p-type halo implant. It allows a subsequent formation of deeper emitter as well as the direct vertical metal contact to the emitter, which in turn improves the current gain and decreases the emitter series resistance, respectively.
Preferred embodiments of the present invention will now be described by way of example only with reference to the accompanying figures in which like reference numbers indicate like features and wherein the figures are not drawn to scale and are merely provided for illustrative purposes.
The present invention further provides a CMOS compatible vertical NPN bipolar junction transistor comprising a P-type substrate having a top n-type epitaxial layer surface, a buried N+ layer connected to the top surface by means of at least one sinker to form a collector, an N epitaxial layer extending over the N + layer, a P-type halo implant layer extending over the epitaxial layer and connected to a P + region which extends to the top surface to form a base, and an N+ layer extending over the halo implant layer to form an emitter. ( )
Brief Description of the Drawings
Figure 1A is a diagram of the prior art layout of LPNP BJT integrated in an advanced CMOS process, depicting only the key masking layers important for the description of present invention; Figure lB shows the key masking layers of Figure 1A shown individually for further reference; Figure 1C is a greatly enlarged schematic cross-sectional diagram of a prior art LPNP BJT device integrated in an advanced CMOS process; Figure 2A is a diagram of the layout of VNPN BJT integrated in an advanced CMOS process according to an embodiment of the present invention which depicts only the key masking layers; Figure ZB shows the key masking layers of Figure 2A shown individually; Figure 2C is a greatly enlarged schematic cross-sectional diagram of an integrated VNPN BJT device architecture according to an embodiment of the present invention; and Figure 3 is a graphical illustration of trough-emitter vertical dopant concentration profile associated with the VNPN BJT device architecture according to an embodiment of the present invention.
Description of the Preferred Embodiments
While the following description of an embodiment of the instant invention revolves around Figures land 2 showing the squared layout of BJTs, the instant invention can be utilized in any other layout shapes forming the BJT semiconductor device structures. The methodology of this embodiment of the instant invention provides a process to achieve the layout of high performance vertical NPN bipolar junction transistor (VNPN BJT) using the mask set of lateral PNP bipolar junction transistor integrated with advanced CMOS transistors.
It should be assumed that in all embodiments described the mask layer features and the device structures are integrated into the corresponding mask layer design and common substrate used for simultaneous CMOS transistors fabrication. Referring to Fig.1.A, a mask set (iOO)-(104) and (107) of prior art LPNP BJT is provided in advanced CMOS process, of which the key masking layers are: the N+ sinker mask (107), the P+ S/D mask (104) and the First Metal Contact mask (100)-(102). The Ni-sinker mask (107) is used in the CMOS process for region (107) to receive a deep phosphorous implant forming the N + sinker diffusion as a part of LPNP extrinsic base. The P+ S/D mask (104) ) is used for regions (103) and (104) of LPNP BJT to receive P+ boron implants forming the collector and the emitter of LPNP BJT simultaneously with forming the source and drain of NMOSTs in CMOS process. The First Metal Contact mask (100)-(102).is used for oxide etching step forming the contact openings (100), (101),(102) for the emitter, the base and the collector electrodes simultaneously with forming all other first metal layer contacts in CMOS process. After using a complete mask set of CMOS process, the final LPNP BJT structure is shown in Fig.1.C comprising the P-type substrate region (109), the N+ buried layer region (108), the N+ sinker region (107), the N-type epitaxial region (106), the shallow trench region (105), the P+ SID collector region (104), the P+ S/D emitter region (103), the emitter, the base an the collector contact regions (100)-(102) and the isolator (oxide, nitride) and metal layers (200) The embodiments of the instant invention described here are shown in Figs.2 A-2C. Referring to FIG.2.A, the new set (100)-(102), (104),(107), (110) and (111) of key masking layers of VNPN BJT is shown generated from the previous art mask set (100)-(104) and (107) of LPNP BJT of FIG.1.A. The mask level (107) used for N+ base sinker region (107) implants of LPNP BJT becomes the mask level used for the N + collector sinker region (107) implants of VNPN BJT. The mask level (104,103) used for P+ collector region (104) and emitter region (103) implants of LPNP BJT is modified by omitting the emitter area features (103) and used as the mask level (104) for the P+ extrinsic base region (104) implants of VNPN VBJT. The mask level (111) of VNPN BJT is introduced forming the intrinsic P-halo base region (111) which is the same mask level of CMOS process used for regions of n-type metal-oxide-semiconductor transistors ( NMOSTs) to receive the P-type halo (or pocket) implants. The mask level (104,103) used for P+ collector region (104) and emitter region (103) regions of LPNP BJT is modified by omitting the collector area features (104) and used as the emitter mask (110) for the N+ emitter region (110) implants of VNPN VBJT. The N+ emitter mask (110) of NPN VBJT is used for the emitter region (110) to receive either a low-voltage NMOST drain extension (LV LDD), a high-voltage NMOST drain extension (HV LDD) or the NMOST source/drain n-type implants (N + S/D) including any suitable combination of these three. All other mask layers forming VNPN BJT layout are identical to that of the mask layer set of LPNP BJT layout.
After using a complete mask set of CMOS process, the final VNPN LPNP BJT structure is shown in FIG.2.C. This comprises the P-type substrate region (109), with the N+ buried layer region (108) forming the collector region. The N� sinker region (107) connects the buried layer 108 to the upper surface of the substrate. The N-type epitaxial region (106) extends over the buried layer, and also forms part of the collector. The shallow trench region (105) is formed between the extrinsic base region 104 and the sinker 107. The P+ SID extrinsic base regioft (1a4)_is formed at the surface of the substrate, and the P halo intrinsic base region (111) extends over part of the epitaxial layer 106, and is in contact with the extrinsic base region 104. The N+ emitter region (110) is formed at the surface of the substrate and extends over part of the intrinsic base region 111. The metal emitter, base and collector contact regions 102, 101, 100 are formed on the surface of the substrate directly over, and in contact with, the emitter region 110, extrinsic base region 104 and sinker 107 respectively. Isolator (oxide, and nitride) layers (200) are also formed on the surface of the substrate.
Shown in FIG.3 is the graphical illustration of trough-emitter vertical dopant concentration profile associated with the VNPN BJT device architecture according to the embodiment of the present invention. It illustrates a main advantage of the instant invention in comparisons with other similar VNPN BiT structures as, for example, U.S. Pat. No. 6,303,420 and U.S.Pat.No.6,858,486 disclosing a technique of using a P-halo implant to form an intrinsic base region of VNPN BJTs. Our instant invention allows the formation of deeper intrinsic base-collector junction bellow the emitter region (110) with the same P-halo implant owing to the use of lower doped epitaxial layer (typically 10 5atoms/cm 3) as the collector region (106) in comparison with previous art using the N-well collector region with typical doping of 10' atoms/cm in CMOS process. It makes possible to place the emitter contact (102) and the base contact (101) directly over the emitter region (110) and the P+ SID base extrinsic region, respectively, resulting in a smaller emitter and base parasitic series resistances and, consequently, an improved device dynamic performance. In addition, the instant invention results in VNPN BJT with N-type collector regions (106)-(108) isolated from P-type substrate region (109) thus enabling a wider range of device application in CMOS mixed analog-digital signal integrated circuits.
Accordingly, although the present invention has been described in detail, it should be understood that any number of alterations, substitutions, or modifications may be made to the teachings described herein without departing from the scope of the present invention which is solely defined by the appended claims.

Claims (19)

  1. Claims 1. A method of forming a CMOS compatible vertical NPN bipolar junction transistor comprising: providing a p-type silicon body with an n-type top epitaxial layer; forming a collector region in the body using N+ type sinker implants; forming an extrinsic base region in the body using P + type source-drain implants; forming an intrinsic base region, in the body using P-type halo implants; and forming an emitter region over the intrinsic base region using N + type source-drain implants and/or lightly doped drain extension (LDD) implants.
  2. 2. A method according to claim 1 wherein the collector region is formed by forming a buried layer using N+ type implants, and forming an epitaxial layer over the buried layer.
  3. 3. A method according to claim 2 further comprising forming at least one N + sinker extending between the buried layer and an upper surface of the silicon body.
  4. 4. A method according to claim 3 further comprising forming a shallow trench between the extrinsic base region and the sinker.
  5. 5. A method according to any foregoing claim further comprising forming a metal emitter contact on the surface of the silicon body over a part of the emitter region.
  6. 6. A method according to any foregoing claim including forming a CMOS compatible lateral PNP bipolar transistor on the silicon body simultaneously with the formation of the vertical NPN bipolar transistor.
  7. 7. A method according to claim 6 wherein the collector region is formed using a mask layer which is also used for the formation of a base of tl1e CMOS compatible lateral PNP bipolar junction transistor.
  8. 8. A method according to claim 6 or claim 7 wherein the base region is formed with a mask layer which is also used for the formation of a collector of the CMOS compatible lateral PNP bipolar junction transistor.
  9. 9. A method according to any foregoing claim further comprising forming an N-type metal oxide semiconductor CMOS transistor on the body.
  10. 10. A method according to claim 9 wherein the intrinsic base region is formed with a mask layer also used for the formation of a halo region of the N-type metal oxide semiconductor CMOS transistor.
  11. 11. A method according to claim 9 or claim 10 wherein the emitter region is formed using at least one mask layer which is also used for the formation of at least one of the following in the N-type metal oxide semiconductor CMOS transistor: a shallow drain extension implant, a deep drain extension implant and/or a source-drain shallow implant. 0 0.
  12. 12. A method according to any foregoing claim further comprising forming a metal base contact on the upper surface of the body over the extrinsic base region.
  13. 13. A CMOS compatible vertical NPN bipolar junction transistor comprising a P-type substrate having a top surface, a buried N � layer connected to the top surface by means of at least one sinker to form a collector, an N epitaxial layer extending over the N+ layer, a P-type pocket implant layer extending over the epitaxial layer and connected to a P+ region which extends to the top surface to form a base, and an N+ layer extending over the pocket implant layer to form an emitter.
  14. 14. A transistor according to claim 13 further comprising an emitter contact formed on the top surface over the emitter.
  15. 15. A method of forming a CMOS compatible vertical NPN bipolar junction transistor (VNPN BJT) comprising: providing a mask set used for fabrication of CMOS compatible lateral PNP bipolar junction transistor (LPNP BJT) with an epitaxial layer collector grown on p-type silicon body in advanced CMOS process; forming a collector region of said VNPN BJT with the mask layer used for the base formation of LPNP BJT; forming an extrinsic base region of said VNPN BJT with the mask layer used for the collector formation of LPNP BJT; and forming an intrinsic base region of said VNPN BJT with the mask layer used for the formation of a pocket region of a N-type metal oxide semiconductor transistor; and forming a emitter region of said VNPN BJT with at least one of a plurality of mask layers used for the formation of at least one of: a N-type metal oxide semiconductor transistor shallow drain extension implant, a N-type metal oxide semiconductor transistor deep drain extension implant and a N-type metal oxide semiconductor transistor source-drain shallow drain implant.
  16. 16. The method of claim 15 wherein said metal oxide semiconductor transistor pocket implant is p-type.
  17. 17. The method of claim 15 or claim 16 wherein said metal oxide semiconductor transistor shallow drain extension implant is n-type.
  18. 18. The method of any of claims 15 to 17 wherein said metal oxide semiconductor transistor deep drain extension implant is n-type.
  19. 19. The method of any of claims 15 to 18 wherein said metal oxide semiconductor transistor source/drain implant is ri-type.
GB0807928.7A 2008-05-01 2008-05-01 CMOS compatible vertical NPN bipolar junction transistors and methods of producing them Active GB2459695B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0807928.7A GB2459695B (en) 2008-05-01 2008-05-01 CMOS compatible vertical NPN bipolar junction transistors and methods of producing them

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0807928.7A GB2459695B (en) 2008-05-01 2008-05-01 CMOS compatible vertical NPN bipolar junction transistors and methods of producing them

Publications (3)

Publication Number Publication Date
GB0807928D0 GB0807928D0 (en) 2008-06-11
GB2459695A true GB2459695A (en) 2009-11-04
GB2459695B GB2459695B (en) 2012-03-21

Family

ID=39537111

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0807928.7A Active GB2459695B (en) 2008-05-01 2008-05-01 CMOS compatible vertical NPN bipolar junction transistors and methods of producing them

Country Status (1)

Country Link
GB (1) GB2459695B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010089675A1 (en) * 2009-02-06 2010-08-12 Nxp B.V. Ic and ic manufacturing method
WO2014036872A1 (en) * 2012-09-05 2014-03-13 无锡华润上华半导体有限公司 Bipolar junction transistor and manufacturing method thereof
US9466579B2 (en) 2007-07-26 2016-10-11 Nxp B.V. Reinforced structure for a stack of layers in a semiconductor component
CN109841517A (en) * 2017-11-28 2019-06-04 德克萨斯仪器股份有限公司 Manufacture the dielectric transistor having on the side wall for being formed in grid material and gate oxide before forming silicide

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107946355B (en) * 2017-03-02 2024-04-05 重庆中科渝芯电子有限公司 Lateral high-voltage bipolar junction transistor and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091321A (en) * 1991-07-22 1992-02-25 Allegro Microsystems, Inc. Method for making an NPN transistor with controlled base width compatible with making a Bi-MOS integrated circuit
US5793085A (en) * 1993-02-26 1998-08-11 Sgs-Thomson Microelectronics S.R.L. Bipolar transistor compatible with CMOS processes
EP1119051A1 (en) * 1992-09-21 2001-07-25 SILICONIX Incorporated BiCDMOS process technology and structures
US6303420B1 (en) * 1999-08-13 2001-10-16 Texas Instruments Incorporated Integrated bipolar junction transistor for mixed signal circuits

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091321A (en) * 1991-07-22 1992-02-25 Allegro Microsystems, Inc. Method for making an NPN transistor with controlled base width compatible with making a Bi-MOS integrated circuit
EP1119051A1 (en) * 1992-09-21 2001-07-25 SILICONIX Incorporated BiCDMOS process technology and structures
US5793085A (en) * 1993-02-26 1998-08-11 Sgs-Thomson Microelectronics S.R.L. Bipolar transistor compatible with CMOS processes
US6303420B1 (en) * 1999-08-13 2001-10-16 Texas Instruments Incorporated Integrated bipolar junction transistor for mixed signal circuits

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9466579B2 (en) 2007-07-26 2016-10-11 Nxp B.V. Reinforced structure for a stack of layers in a semiconductor component
WO2010089675A1 (en) * 2009-02-06 2010-08-12 Nxp B.V. Ic and ic manufacturing method
US9443773B2 (en) 2009-02-06 2016-09-13 Nxp B.V. IC and IC manufacturing method
WO2014036872A1 (en) * 2012-09-05 2014-03-13 无锡华润上华半导体有限公司 Bipolar junction transistor and manufacturing method thereof
CN103681807A (en) * 2012-09-05 2014-03-26 无锡华润上华半导体有限公司 Bipolar junction transistor and manufacturing method thereof
CN103681807B (en) * 2012-09-05 2016-08-03 无锡华润上华半导体有限公司 A kind of bipolar junction transistor and preparation method thereof
CN109841517A (en) * 2017-11-28 2019-06-04 德克萨斯仪器股份有限公司 Manufacture the dielectric transistor having on the side wall for being formed in grid material and gate oxide before forming silicide
CN109841517B (en) * 2017-11-28 2023-12-01 德克萨斯仪器股份有限公司 Manufacturing a transistor with a dielectric formed on the sidewalls of the gate material and gate oxide prior to silicide formation

Also Published As

Publication number Publication date
GB2459695B (en) 2012-03-21
GB0807928D0 (en) 2008-06-11

Similar Documents

Publication Publication Date Title
JP5089529B2 (en) BiCMOS integrated circuit
US7449388B2 (en) Method for forming multiple doping level bipolar junctions transistors
US4507847A (en) Method of making CMOS by twin-tub process integrated with a vertical bipolar transistor
US8836043B2 (en) Lateral bipolar junction transistor
US5387552A (en) Method of fabrication of PNP structure in a common substrate containing NPN or MOS structures
US5661046A (en) Method of fabricating BiCMOS device
JPH05243584A (en) Manufacturing method of insulating vertical pnp transistor equipped with eeprom memory in complementary bicmos process
US7285830B2 (en) Lateral bipolar junction transistor in CMOS flow
US20050164439A1 (en) Low volt/high volt transistor
US5757052A (en) Bipolar transistor and method of forming BiCMOS circuitry
US10026730B2 (en) Single mask level including a resistor and a through-gate implant
US5231042A (en) Formation of silicide contacts using a sidewall oxide process
JPH04226064A (en) Interconnection body for semiconductor device use its manufacture
GB2459695A (en) CMOS compatible NPN bipolar transistors
US6303420B1 (en) Integrated bipolar junction transistor for mixed signal circuits
US6903424B2 (en) Semiconductor device and its manufacturing method
KR20100079381A (en) Semiconductor device and method for manufacturing thereof
US7772060B2 (en) Integrated SiGe NMOS and PMOS transistors
US6011283A (en) Pillar emitter for BiCMOS devices
JPS6255309B2 (en)
JPH0567735A (en) Manufacture of semiconductor integrated circuit
JPH02113567A (en) Manufacture of semiconductor device