WO2014035342A1 - Circuit de conversion de fréquences harmoniques - Google Patents

Circuit de conversion de fréquences harmoniques Download PDF

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Publication number
WO2014035342A1
WO2014035342A1 PCT/SG2013/000373 SG2013000373W WO2014035342A1 WO 2014035342 A1 WO2014035342 A1 WO 2014035342A1 SG 2013000373 W SG2013000373 W SG 2013000373W WO 2014035342 A1 WO2014035342 A1 WO 2014035342A1
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WO
WIPO (PCT)
Prior art keywords
transistor
electrode
conversion circuit
harmonic frequency
cell
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PCT/SG2013/000373
Other languages
English (en)
Inventor
Kai Xue Ma
Shou Xian MOU
Kiat Seng Yeo
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Nanyang Technological University
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Publication of WO2014035342A1 publication Critical patent/WO2014035342A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1433—Balanced arrangements with transistors using bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1466—Passive mixer arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1475—Subharmonic mixer arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16—Multiple-frequency-changing
    • H03D7/165—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature

Definitions

  • Embodiments relate generally to frequency converters, and more particularly to a harmonic frequency conversion circuit.
  • Frequency modulators, demodulators and mixers are key functional circuits to perform frequency conversion by multiplying two signals. As it is a multiplication in the time domain, these function circuits can carry both the phase and amplitude information.
  • Frequency converters using modulator, demodulator and mixer may take consideration of or use not only the frequency conversion, but also the phase and amplitude information.
  • the phase and amplitude modulation technique is one of the key techniques used in millimeter-wave communication system, especially for low power high-speed access systems. Normally, it is achieved by a complex and costly down-converter or up- converter chain, which includes baseband modulator, mixers, filters, and amplifiers etc.
  • this traditional system can be simplified by replacing up-converting mixers and associated filters with a vector modulator that directly modulates data onto a carrier signal using orthogonal I (in-phase) and Q (quadrature phase) input signal from baseband for simultaneous amplitude and phase conversion.
  • Sub-harmonic, fourth-harmonic, and image-reject type mixers could also be designed with proper arrangement or generation of multiple phases through the phase generation network connected to the local oscillator (LO).
  • the sub-harmonic or fourth- harmonic mixers design would lower down the required LO frequency to half or quarter of the LO frequency required by the traditional fundamental mixer. Therefore it will simplify the LO chain and system integration.
  • the image-reject mixer or modulator/demodulator can suppress the image frequency to certain level by using proper phase combination and thus improve the system linearity.
  • the harmonic and image rejection frequency conversion techniques are especially important for millimeter-wave and broadband communication and radar system.
  • the current technologies are mostly based on the fundamental operation, i.e. the fundamental carrier frequency is modulated with baseband signals, which are either IQ signals or differential IQ signals.
  • baseband signals which are either IQ signals or differential IQ signals.
  • the reason may be that the operating frequency of the carrier frequency is low and the fundamental modulator/demodulator are already very complex, which involve lots of amplitude and phase control of high frequency signals with good amplitude and phase balance characteristics.
  • the sub-harmonic or harmonic mixers have been reported in GaAs design and some on-board circuit implementation. Only recently, it becomes hot topic to be implemented on the low cost silicon chipset.
  • the sub-harmonic mixer and fourth- harmonic mixer having been reported, which is majorly based on the Gerber cell prototype with tail transistor or resistor to control the bias condition.
  • the harmonic frequency conversion circuit may include an inverter having a first terminal and a second terminal.
  • the inverter may include at least one of a resistor or a capacitor connected between the first terminal and the second terminal; a P-channel transistor having a first electrode, a second electrode and a third electrode; and a N-channel transistor having a first electrode, a second electrode and third electrode.
  • the first electrode of the P-channel transistor and the first electrode of the N-channel transistor are connected to the first terminal, and the second electrode of the P-channel transistor and the second electrode of the N-channel transistor are connected to the second terminal.
  • the harmonic frequency conversion circuit may further include a transistor pair connected to the inverter and including a first transistor and a second transistor; wherein the first transistor has a first electrode, a second electrode and a third electrode; and the second transistor has a first electrode, a second electrode and a third electrode.
  • the first electrode of the first transistor is connected to receive a first local oscillation signal and the first electrode of the second transistor is connected to receive a second local oscillation signal.
  • the second electrode of the first transistor and the second electrode of the second transistor are connected to each other at a third terminal.
  • the third electrode of the first transistor and the third electrode of the second transistor are connected to one of the first terminal or the second terminal of the inverter.
  • Fig. 1 shows a harmonic frequency conversion circuit 100 according to various embodiments.
  • Fig. 2A shows a harmonic frequency up-conversion circuit according to various embodiments.
  • Fig. 2B shows a harmonic frequency down-conversion circuit according to various embodiments.
  • Fig. 3A shows a harmonic frequency up-conversion circuit according to various embodiments.
  • Fig. 3B shows a harmonic frequency down-conversion circuit according to various embodiments.
  • Fig. 4A shows a harmonic frequency up-conversion circuit according to various embodiments.
  • Fig. 4B shows a harmonic frequency down-conversion circuit according to various embodiments.
  • Fig. 5A shows a harmonic frequency up-conversion circuit according to various embodiments.
  • Fig. 5B shows a harmonic frequency down-conversion circuit according to various embodiments.
  • Fig. 6A shows a harmonic frequency up-conversion circuit according to various embodiments.
  • Fig. 6B shows a harmonic frequency down-conversion circuit according to various embodiments.
  • Fig. 7 shows an exemplary layout of an up-conversion sub-harmonic IQ SSB (single sideband) modulator together with an IQ network according to various embodiments.
  • Fig. 8 shows a transceiver including a sub-harmonic IQ modulator/demodulator according to various embodiments.
  • Fig. 9 shows a differential IQ sub-harmonic up-conversion DSB (double sideband) mixer/modulator 900 according to various embodiments.
  • Fig. 10 shows an IQ fourth-harmonic down-conversion SSB mixer/demodulator according to various embodiments. Description
  • Various embodiments provide a harmonic frequency conversion circuit, which may be configured to be used or included in a modulator, a demodulator or a mixer for a transceiver.
  • a "circuit” in the context of this description may be understood as any kind of a logic implementing entity, which may be special purpose circuitry or a processor executing software stored in a memory, firmware, or any combination thereof.
  • a "circuit” may be a hard-wired logic circuit or a programmable logic circuit such as a programmable processor, e.g. a microprocessor (e.g. a Complex Instruction Set Computer (CISC) processor or a Reduced Instruction Set Computer (RISC) processor).
  • a “circuit” may also be a processor executing software, e.g. any kind of computer program, e.g. a computer program using a virtual machine code such as e.g. Java. Any other kind of implementation of the respective functions which will be described in more detail below may also be understood as a "circuit" in accordance with an alternative embodiment.
  • Fig. 1 shows a harmonic frequency conversion circuit 100 according to various embodiments.
  • the harmonic frequency conversion circuit 100 may include an inverter 1 10 having a first terminal 102 and a second terminal 104.
  • the inverter 110 may include at least one of a resistor 1 12 or a capacitor connected between the first terminal 102 and the second terminal 104; wherein the resistor 1 12 is shown in Fig. 1.
  • the inverter 110 may also include a P-channel transistor 114 having a first electrode 122, a second electrode 124 and a third electrode 126; and a N-channel transistor 116 having a first electrode 132, a second electrode 134 and a third electrode 136.
  • the first electrode 122 of the P-channel transistor 1 14 and the first electrode 132 of the N-channel transistor 1 16 are connected to the first terminal 102, and the second electrode 124 of the P-channel transistor 1 14 and the second electrode 134 of the N- channel transistor 1 16 are connected to the second terminal 104.
  • the harmonic frequency conversion circuit 100 may further include a transistor pair 140 connected to the inverter 110, wherein the transistor pair 140 includes a first transistor 142 and a second transistor 152.
  • the first transistor 142 has a first electrode 144, a second electrode 146 and a third electrode 148; and the second transistor 152 has a first electrode 154, a second electrode 156 and a third electrode 158.
  • the first electrode 144 of the first transistor 142 is coupled or connected to receive a first local oscillation signal LO 01 and the first electrode 154 of the second transistor 152 is coupled or connected to receive a second local oscillation signal LO_02.
  • the second electrode 146 of the first transistor 142 and the second electrode 156 of the second transistor 152 are connected to each other at a third terminal 106.
  • the first electrode 144 of the first transistor 142 may be configured to receive the first local oscillation signal LO_01.
  • the first electrode 144 of the first transistor 142 may be coupled or connected to a signal generator, e.g. a local oscillator (LO), to receive the first local oscillation signal LO 01.
  • the first electrode 154 of the second transistor 152 may be configured to receive the second local oscillation signal LO 02.
  • the first electrode 154 of the second transistor 152 may be coupled or connected to a signal generator, e.g. a local oscillator (LO), to receive the second local oscillation signal LO 02.
  • LO local oscillator
  • the third electrode 148 of the first transistor 142 and the third electrode 158 of the second transistor 152 are connected to one of the first terminal 102 or the second terminal 104 of the inverter 110.
  • the third electrode 148 of the first transistor 142 and the third electrode 158 of the second transistor 152 are connected to the second terminal 104, i.e. the transistor pair 140 is connected to the second terminal 104 of the inverter 110, so as to form a harmonic frequency up-conversion circuit 100.
  • the transistor pair 140 may be connected to the first terminal 102 of the inverter 110, to form a harmonic frequency down-conversion circuit.
  • the transistors of the harmonic frequency conversion circuit 100 may be various types of transistors, such as FET (field effect transistor, e.g. MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or JFET (Junction Gate Field Effect Transistor), BJT (bipolar junction transistor), IGBT (Insulated Gate Bipolar Transistor), and HEMT (High Electron Mobility Transistor), etc.
  • FET field effect transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • JFET Joint Gate Field Effect Transistor
  • BJT bipolar junction transistor
  • IGBT Insulated Gate Bipolar Transistor
  • HEMT High Electron Mobility Transistor
  • the P-channel transistor 1 14 may be a P-MOS, a P-BJT, or a P-HEMT transistor
  • the N-channel transistor 116 may be a N-MOS, a N-BJT, or a N-HEMT transistor.
  • the transistors in the harmonic frequency conversion circuit 100 may be same or different types of transistors.
  • the first transistor 142 and the second transistor 152 of the transistor pair 140 may be BJT transistors, while the transistors 114 and 1 16 in the inverter 1 10 may be CMOS (complementary metal-oxide-semiconductor) transistors.
  • the inverter 1 10 may include a resistor 1 12, or a capacitor (not shown), or a resistor connected with a capacitor in parallel, between the first terminal 102 and the second terminal 104.
  • the first electrode 122 of the P-channel transistor 114 and the first electrode 132 of the N-channel transistor 1 16 may be gate electrodes or base electrodes.
  • the first electrode 122 may be a gate electrode when the P- channel transistor 114 is a FET.
  • the second electrode 124 of the P-channel transistor and the second electrode 134 of the N-channel transistor may be one of drain electrode or collector electrode.
  • the third electrode 126 of the P-channel transistor and the third electrode 136 of the N-channel transistor may be one of source electrode or emitter electrode.
  • the third electrode 126 of the P-channel transistor 114 is coupled or connected to a DC supply (Vdd), and the third electrode 136 of the N- channel transistor 1 16 is connected to the ground.
  • the first electrode 144 of the first transistor and the first electrode 154 of the second transistor may be one of gate electrode or base electrode.
  • the second electrode 146 of the first transistor and the second electrode 156 of the second transistor may be one of drain electrode or collector electrode.
  • the third electrode 148 of the first transistor and the third electrode 158 of the second transistor may be one of source electrode or emitter electrode.
  • At least one DC source and necessary bias network may be included in the harmonic frequency conversion circuit 100 to provide a bias voltage for the operation of the transistors 114, 1 16, 142, 152.
  • the harmonic frequency conversion circuit 100 may further include a DC bias (not shown) coupled or connected to the third terminal 106.
  • the DC bias may be supplied to the third terminal 106 through a resistor or an inductor, e.g., to avoid RF leakage to DC.
  • the harmonic frequency conversion circuit 100 may further include at least one of a resistor, an inductor, a LC tank or transmission lines coupled or connected to the third terminal 106.
  • the first local oscillation signal LO 01 and the second local oscillation signal LO_02 may be the same signal or may be different signals.
  • the first local oscillation signal LO 01 and the second local oscillation signal LO ⁇ 02 may have the same amplitude.
  • the first local oscillation signal LO_01 and the second local oscillation signal LO_02 may have a 180-degree phase difference.
  • the third electrode 148 of the first transistor 142 and the third electrode 158 of the second transistor 152 are connected to the second terminal 104 of the inverter 1 10, i.e. the transistor pair 140 is connected to the second terminal 104 of the inverter 110.
  • the harmonic frequency conversion circuit 100 may be configured to receive an intermediate frequency (IF) signal at the first terminal 102 of the inverter, and configured to output a radio frequency (RF) signal from the third terminal 106.
  • IF intermediate frequency
  • RF radio frequency
  • the harmonic frequency conversion circuit 100 may include a further inverter and a further transistor pair forming a second sub-harmonic frequency up-conversion cell.
  • the first cell may be configured to receive a 0 degree phase shifted intermediate frequency (IF) signal (also referred to as an in-phase IF signal) at the first terminal thereof.
  • the second cell may be configured to receive a 90 degree phase shifted intermediate frequency (IF) signal (also referred to as an quadrature phase IF signal) at the first terminal thereof.
  • IF phase shifted intermediate frequency
  • the harmonic frequency conversion circuit formed thereof may be referred to as a sub-harmonic IQ frequency up-conversion circuit.
  • the harmonic frequency conversion circuit 100 may further include a second sub-harmonic frequency up-conversion cell, a third sub- harmonic frequency up-conversion cell, and a fourth sub-harmonic frequency up- conversion cell, wherein each of the second cell, the third cell and the fourth cell includes an inverter and a transistor pair similar to the inverter 1 10 and the transistor pair 140 of the first sub-harmonic frequency up-conversion cell described above.
  • the first cell and the second cell may be connected to each other at their third terminals, and the third cell and the fourth cell may be connected to each at their third terminals.
  • the first cell may be configured to receive a 0 degree phase shifted intermediate frequency signal at the first terminal thereof; the second cell may be configured to receive a 180 degree phase shifted intermediate frequency signal at the first terminal thereof, the third cell may be configured to receive a 270 degree phase shifted intermediate frequency signal at the first terminal thereof; and the fourth cell may be configured to receive a 90 degree phase shifted intermediate frequency signal at the first terminal thereof.
  • the harmonic frequency conversion circuit formed thereof may be referred to as a differential IQ sub- harmonic frequency up-conversion circuit.
  • the third electrode 148 of the first transistor 142 and the third electrode 158 of the second transistor 152 may be connected to the first terminal 102 of the inverter 1 10, i.e. the transistor pair 140 is connected to the first terminal 102 of the inverter 1 10.
  • the harmonic frequency conversion circuit 100 may be configured to receive a radio frequency (RF) signal at the third terminal 106, and configured to output an intermediate frequency (IF) signal from the second terminal 104 of the inverter 1 10.
  • RF radio frequency
  • IF intermediate frequency
  • the inverter 1 10 and the transistor pair 140 form a first sub-harmonic frequency down-conversion cell.
  • the harmonic frequency conversion circuit 100 may further include a further inverter and a further transistor pair forming a second sub- harmonic frequency down-conversion cell.
  • the first cell may be configured to receive a 0 degree phase shifted radio frequency signal (also referred to as an in-phase RF signal) at the third terminal thereof, and the second cell may be configured to receive a 90 degree phase shifted radio frequency signal (also referred to as a quadrature phase RF signal) at the third terminal thereof.
  • the harmonic frequency conversion circuit formed thereof may be referred to as a sub-harmonic IQ frequency down-conversion circuit.
  • the harmonic frequency conversion circuit 100 may further include a second sub-harmonic frequency down-conversion cell, a third sub- harmonic frequency down-conversion cell, and a fourth sub-harmonic frequency down- conversion cell, wherein each of the second cell, the third cell and the fourth cell includes an inverter and a transistor pair similar to the inverter 1 10 and the transistor pair 140 of the first sub-harmonic frequency down-conversion cell described above.
  • the first cell and the second cell may be connected to each other at their third terminals, and the third cell and the fourth cell may be connected to each at their third terminals.
  • the first cell and the second cell may be configured to receive a 180 degree phase shifted radio frequency signal at their third terminals
  • the third cell and the fourth cell may be configured to receive a 270 degree phase shifted radio frequency signal at their third terminals.
  • the harmonic frequency conversion circuit formed thereof may be referred to as a differential IQ sub-harmonic frequency down-conversion circuit.
  • the harmonic frequency conversion circuit 100 may include a further transistor pair connected to the inverter 1 10, wherein the transistor pair 140 and the further transistor pair are connected in parallel.
  • the first local oscillation signal received by the transistor pair 140 and the first local oscillation signal received by the further transistor pair may have a 90-degree phase difference
  • the second local oscillation signal received by the transistor pair 140 and the second local oscillation signal received by the further transistor pair may have a 90-degree phase difference.
  • the harmonic frequency conversion circuit 100 may include a second transistor pair, a third transistor pair and a fourth transistor pair, wherein the transistor pair 140, the second transistor pair, the third transistor pair and the fourth transistor pair are connected with each other in parallel and are connected to the inverter 1 10.
  • the first local oscillation signals received by the transistor pair 140, the second transistor pair, the third transistor pair and the fourth transistor pair may have a 45-degree phase difference in sequence.
  • the second local oscillation signals received by the transistor pair 140, the second transistor pair, the third transistor pair and the fourth transistor pair have a 45-degree phase difference in sequence.
  • the harmonic frequency conversion circuit 100 described in various embodiments above may be configured to be used in at least one of a modulator, a demodulator or a mixer. Especially for the harmonic conversion cells, we only use
  • the symmetrical transistor pair 140 may include more than two transistors, for example, the transistor pair 140 may be a transistor array having any even number of the transistors, such as 4, 6, 8, ...transistors.
  • the harmonic frequency conversion circuit 100 may include multiple inverter combination with the similar configuration as the inverter 110, or may include a single inverter 110 having multiple transistors inside of the inverter.
  • the transistor pair 140 and frequency inverter 110 show in Fig. 1 may be used as the fundamental blocks and may be combined in various manner to form various types of harmonic frequency conversion circuits, as will be described with regard to Figs. 2A-2B, 3A-3B, 4A-4B, 5A-5B, 6A-6B, 9 -10 below.
  • Various embodiments are based on the fundamental frequency conversion circuit including the transistor pair and the inverter in combination.
  • the fundamental frequency conversion circuit By using the fundamental frequency conversion circuit, different types of modulator, demodulator and mixer, including sub-harmonic, fourth-harmonic, 8th-harmonic conversions etc., are may be provided in various embodiments.
  • Various embodiments may simplify the harmonic circuits, in which the fundamental sub-harmonic frequency conversion circuit is formed by the confronted transistor pair together with the inverter.
  • the inverter may be used for both up and down frequency conversion or modulation, and the required signal with different phases may be input to or generated from the inverter. This may simplify the requirement for both the bias and I/O (input/output) matching circuit, and may also benefit the layout simplification.
  • the harmonic frequency conversion circuit of various embodiments may also provide better conversion gain and broad band input data or information, since the inverter inside of the frequency conversion circuit not only performs the function of impedance matching but also provides the necessary gain for the input or output IF signal or data.
  • the basic isolation among the carrier, the IF/data and RF may also be provided by the inverter.
  • the harmonic frequency conversion circuit of various embodiments may provide low power consumption, since the combination of the inverter and the harmonic transistor pair may provide good DC bias condition without using the folded structures. This combination may simplify the circuit and layout for tradeoff the power consumption reduction.
  • the harmonic frequency conversion circuit of various embodiments may lower down the requirements for the carrier, since the harmonic frequency conversion scheme or modulation scheme can reduce the requirement of the LO (local oscillator) operation frequency by the targeted number of the harmonic.
  • the sub- harmonic may require half of the LO frequency required by the fundamental scheme and the 4th harmonic may require one quarter of the LO frequency required by the fundamental frequency conversion scheme.
  • the performance of LO including power consumption, phase noise etc. may be decreased with the increase of the LO frequency, but the design complexity may be increased with the increase of the LO frequency.
  • various embodiments using the harmonic scheme may simplify the LO design.
  • the harmonic frequency conversion circuit of various embodiments may simplify the overall transceiver architecture, since the harmonic frequency conversion provides simplified LO for the mixer and modulator/demodulator operation.
  • baseband data may be directly modulated to RF/microwave/millimeter data without carrying out the frequency conversion using up-conversion mixer.
  • RF/ microwave/ Millimeter- wave data may be directly demodulated to baseband data without carrying out the frequency conversion using down-conversion mixer.
  • Figs. 2A-2B show harmonic frequency conversion circuits according to various embodiments.
  • Fig. 2A shows a harmonic frequency up-conversion circuit 200 according to various embodiments, which may be configured to be used in a up-conversion mixer or modulator.
  • the harmonic frequency up-conversion circuit 200 is similar to the harmonic frequency conversion circuit 100 of Fig. 1, and includes the inverter 1 10 and the transistor pair 140. In this embodiment, the transistor pair 140 is connected to the second terminal of the inverter 1 10. Various embodiments described with reference to Fig. 1 above are also valid for the harmonic frequency up-conversion circuit 200.
  • the P-transistor (Ql) 1 14, the N-transistor (Q2) 1 16 and the resistor (Rl) 112 form the inverter 1 10, which is connected with the transistor pair 140 including the first transistor (Q3) 142 and the second transistor (Q4) 152 at the second terminal 104, and is configured to receive IF signal or IF data at the first terminal 102.
  • the resistor (Rl) ,1 12 inside the inverter 110 may be used to tradeoff between the gain and input/output matching. Though the resistor Rl is shown in the embodiments of Fig. 2A, it is understood that a capacitor, or a resistor connected in parallel with a capacitor, may be provided between the first terminal 102 and the second terminal 104 of the inverter 1 10.
  • the "source” (or “emitter”) electrode 126 of the P-transistor Ql inside the inverter 110 may be coupled or connected to a DC supply (Vdd) directly or through lumped elements or transmission line.
  • the "source” (or “emitter”) electrode 136 of the N-transistor Q2 may be connected to the ground.
  • IF signal e.g., for an up-conversion mixer
  • IF data e.g., for an up-conversion modulator
  • the first transistor Q3 and the second transistor Q4 are connected in confront, with their "source” (or “emitter”) electrodes 148, 158 connected with each other and their “drain” (or “collector”) electrodes 146, 156 connected with each other as shown in Fig. 2A.
  • the "gate” (or “base”) electrodes 144, 154 of the transistors Q3 and Q4 are connected with the first LO signal LO-01 and the second LO signal LO-02 with or without DC 260, respectively.
  • the LO signals LO-01 and LO-02 may be anti-phase, i.e., may have a 180-degree phase difference.
  • the amplitude of the LO signals LO-01 and LO-02 may be equal.
  • the DC bias 206 may be applied together with the LO signals LO-01 and LO-02 for the transistor "gate" (or "base”) bias purpose.
  • the harmonic frequency up-conversion circuit 200 may convert the IF signal or data received at the first terminal 102 to a RF signal or data, and may output the RF signal or data from the third terminal 106.
  • the third terminal 106 may be coupled or connected to the DC bias 260, e.g. by connecting to a bias network or a DC supply network or both.
  • the third terminal 106 i.e. the common node connected with the "drain” or "collector” electrodes 146, 156 of the transistor Q3 and Q4 may be further connected to inductors, resistors, LC tank, transmission lines or their combination for matching and/or bias purpose.
  • Fig. 2B shows a harmonic frequency down-conversion circuit 290 according to various embodiments, which may be configured to be used in a down-conversion mixer or demodulator.
  • the harmonic frequency down-conversion circuit 290 is similar to the harmonic frequency up-conversion circuit 200 of Fig. 2A, with the difference that the transistor pair 140 is connected to the first terminal 102 of the inverter 110.
  • Various embodiments described with reference to Fig. 2A above are also valid for the harmonic frequency down-conversion circuit 290.
  • RF signal or data may be received at the third terminal 106 and may be converted to IF signal or data.
  • the IF signal (e.g., for down-conversion mixer) or data (e.g., for down-conversion demodulator) to baseband or other digital source may be output from the "drain" (or "collector") electrodes 124, 134 of the transistors Ql and Q2 at the second terminal 104, as shown in Fig. 2B.
  • the common node of "gate” (or “base”) electrodes 122, 132 of transistors Ql and Q2 are connected to the common node of "source” (or “emitter”) electrodes 148, 158 of the transistor Q3 and Q4 at the first terminal 102.
  • the other connections and signals, such as LO-01, LO-02, RF, DC, etc. are similar to the connections and signals for the up- conversion circuit 200.
  • the harmonic frequency conversion circuits 200, 290 of Figs. 2A-2B may be referred to as a sub-harmonic frequency up-conversion circuit and a sub-harmonic frequency down-conversion circuit, respectively.
  • Figs. 3A-3B show harmonic frequency conversion circuits according to various embodiments.
  • Fig. 3A shows a harmonic frequency up-conversion circuit 300 according to various embodiments, which may be configured to be used in an up-conversion mixer or modulator.
  • the harmonic frequency up-conversion circuit 300 may be referred to as a fourth-harmonic up-conversion circuit.
  • the fourth-harmonic up-conversion circuit 300 is similar to the sub-harmonic up-conversion circuit 200 of Fig. 2A, with the difference that the fourth-harmonic up-conversion circuit 300 includes a further transistor pair 340 connected in parallel with the transistor pair 140.
  • Various embodiments described with reference to Fig. 2A are also valid for the fourth-harmonic up-conversion circuit 300.
  • the inverter 1 10 is similar to the inverter 1 10 of the circuit 200.
  • the P-transistor transistor Ql, the N-transistor Q2 and the resistor Rl form the inverter 1 10, which is connected with IF signal or data at the first terminal 102.
  • the inverter 1 10 is further connected to the transistor pair 140 (Q3 & Q4) and the further transistor pair 340 (Q5 & Q6) at the second terminal 104.
  • the resistor Rl inside the inverter 1 10 may be used to tradeoff between the gain and input/output matching.
  • the "source” (or “emitter”) electrodes 126 of the P-transistor Ql is connected to the DC supply (Vdd) directly or through lumped elements or transmission line, and the “source” (or “emitter”) electrodes 136 of the N-transistor Q2 is connected to the ground.
  • the IF signal (for up- conversion mixer) or data (for up-conversion modulator) from baseband or other digital source is feed into the "gate” (or “base”) electrodes 122, 132 of the transistors Ql and Q2 as shown in Fig. 3A.
  • the transistor pair Q3 and Q4 are connected in confront with their "source” (or “emitter”) electrodes connected each other and their “drain” (or “collector”) electrodes connected each other.
  • the "gate” (or “base”) electrodes of the transistors Q3 and Q4 are connected with two LO signals LO-01 and LO-02 with or without DC respectively.
  • the further transistor pair 340 also includes a first transistor Q5 342 and a second transistor Q6 352.
  • the connection between the transistors Q5 and Q6 may be similar to the connection between the transistors Q3 and Q4 of the transistor pair 340 described above.
  • the first transistor Q5 and the second transistor Q6 of the further transistor pair 340 may be connected, with their "source” (or “emitter”) electrodes connected with each other and their “drain” (or “collector”) electrodes connected with each other as shown in Fig. 3A.
  • the "gate” (or “base”) electrodes of the transistors Q5 and Q6 are connected with a third LO signal LO-03 and a fourth LO signal LO-04 with or without DC 260, respectively.
  • the LO signals LO-01 and LO-02 of the transistor pair 140 may be anti-phase, i.e., may have a 180-degree phase difference, and the amplitude of the LO signals LO-01 and LO-02 may be equal.
  • the LO signals LO-03 and LO-04 of the transistor pair 340 may have a 180-degree phase difference, and the amplitude of the LO signals LO-03 and LO-04 may be equal.
  • the LO signals of different transistor pairs, e.g., LO-01 and LO-03 may have a 90-degree phase difference, and the LO signals LO-02 and LO-04 may have a 90-degree phase difference.
  • the LO signals of LO-01 , LO-03, LO-02 and LO- 04 may have the same amplitude and may have phase difference of 90 degrees in sequence.
  • LO-01 may be 0 degree phase shifted
  • LO-02 may be 180 degree phase shifted
  • LO-03 may be 90 degree phase shifted
  • LO-04 may be 270 degree phase shifted.
  • the DC 260 may be applied together with LO-01, LO-02, LO-03 and LO-04 for the transistor "gate" (or "base”) bias purpose.
  • the common node 106 connected with "drain” (or “collector”) electrodes of the transistors Q3, Q4, Q5 and Q6 may be coupled or connected to a RF connection node and/or a DC bias 260, and may be further connected to inductors, resistors, LC tank, transmission lines or their combination for matching and/or bias purpose.
  • Fig. 3B shows a harmonic frequency down-conversion circuit 390 according to various embodiments, which may be configured to be used in a down-conversion mixer or demodulator.
  • the harmonic frequency down-conversion circuit 390 (also referred to as a fourth-harmonic down-conversion circuit) is similar to the harmonic frequency up-conversion circuit 300 of Fig. 3 A, with the difference that the transistor pair 140 and the further transistor pair 340 are connected to the first terminal 102 ' of the inverter 1 10.
  • Various embodiments described with reference to Fig. 3 A above are also valid for the harmonic frequency down-conversion circuit 390.
  • the IF signal (e.g., for down-conversion mixer) or data (e.g. for down-conversion demodulator) to baseband or other digital source may be output from the "drain" (or “collector") electrodes 124, 134 of the transistors Ql and Q2 at the second terminal 104 as shown in Fig. 3B.
  • the common node of "gate” (or “base”) electrodes 122, 132 of transistors Ql and Q2 are connected to the common node of "source” (or “emitter”) electrodes of the transistors Q3, Q4, Q5 and Q6 at the first terminal 102.
  • the other connections and signals such as LO-01, LO-02, LO-03, LO- 04, RF, DC etc. are similar to the connections and signals for the up-conversion circuit 300.
  • Figs. 4A-4B show harmonic frequency conversion circuits according to various embodiments.
  • Fig. 4A shows a harmonic frequency up-conversion circuit 400 according to various embodiments, which may be configured to be used in an up-conversion mixer or modulator.
  • the harmonic frequency up-conversion circuit 400 may be referred to as a 8th-harmonic up-conversion circuit.
  • the 8th-harmonic up- conversion circuit 400 is similar to the sub-harmonic up-conversion circuit 200 of Fig. 2A and the fourth-harmonic up-conversion circuit 300 of Fig. 3 A, with the difference that the 8th-harmonic up-conversion circuit 400 includes four transistor pairs 140, 340, 440, 450 connected in parallel with each other.
  • 3A are also valid for the 8th-harmonic up-conversion circuit 400.
  • the circuit 400 shown in Fig. 4A includes four transistor pairs connected to the inverter to form the 8th-harmonic up-conversion circuit, it is understood that more than four transistor pairs may be connected to the inverter in the analogous manner to form various harmonic up-conversion circuit, such as 16th-harmonic and 32-th harmonic up- conversion circuit.
  • the harmonic conversion circuit of up to N-th harmonics may be formed, wherein N/2 transistor pairs may be provided to connect to one inverter, and N LO signals having the same amplitude but having phase difference by 360degree N in sequence may be provided to the N-th harmonic conversion circuit.
  • the inverter 1 10 is similar to the inverter 110 of the circuits 200, 300.
  • the P-transistor transistor Ql, the N-transistor Q2 and the resistor Rl form the inverter 110, which is connected with IF signal or data at the first terminal 102.
  • the inverter 1 10 is further connected to a first transistor pair 140 (Q3 & Q4), a second transistor pair 340 (Q5 & Q6), a third transistor pair 440 (Q3 & Q4) and a fourth transistor pair 450 (Q5 & Q6) at the second terminal 104.
  • the resistor Rl inside the inverter 1 10 may be used to tradeoff between the gain and input/output matching.
  • the "source” (or “emitter”) electrodes 126 of the P-transistor Ql is connected to the DC supply (Vdd) directly or through lumped elements or transmission line, and the “source” (or “emitter”) electrodes 136 of the N-transistor Q2 is connected to the ground.
  • the LO signals within the same transistor pair may have a 180-degree phase difference, and may have the same or substantially the same amplitude.
  • the first transistor pair 140 may receive LO signals LO O and LO l 80 having a 180-degree phase difference between each other.
  • the LO signals LO O, L0 45, LO 90, L0 135, LO 180, LO_225, LO 270, L0 315 may have the same amplitude, and may have phase difference of 45 degrees in sequence (i.e. 0, 45, 90, 135, 180, 225, 27Q, 315 degree phase shifted).
  • the first transistor pair 140 may receive LO signals LO O and LO 180
  • the second transistor pair 340 may receive LO signals LO 90 and LO 270
  • the third transistor pair 440 may receive LO signals L0 45 and L0 225
  • the fourth transistor pair 450 may receive LO signals L0 135 and L0 315, as shown in Fig. 4A.
  • the DC 260 may be applied together with the LO signals LO_0, LO_45, LO 90, LO_135, LO_180, LO_225, LO_270 and LO_315 for the transistor "gate" (or “base”) bias purpose.
  • the common node 106 connected with "drain” (or “collector”) electrodes of the transistor pairs 140, 340, 440, 450 may be coupled or connected to a RF connection node and/or the DC bias 260, and may be further connected to inductors, resistors, LC tank, transmission lines or their combination for matching and/or bias purpose.
  • Fig. 4B shows a harmonic frequency down-conversion circuit 490 according to various embodiments, which may be configured to be used in a down-conversion mixer or demodulator.
  • the harmonic frequency down-conversion circuit 490 (also referred to as a 8th-harmonic down-conversion circuit) is similar to the harmonic frequency up-conversion circuit 400 of Fig. 4A, with the difference that the transistor pairs 140, 340, 440, 450 are connected to the first terminal 102 of the inverter 110.
  • Various embodiments described with reference to Fig. 4A above are also valid for the harmonic frequency down-conversion circuit 490.
  • the IF signal (for down-conversion mixer) or data (for down-conversion demodulator) to baseband or other digital source may be output from the "drain” (or “collector”) electrodes 124, 134 of the transistors Ql and Q2 at the second terminal 104 as shown in Fig. 4B.
  • the common node of "gate” (or “base”) electrodes 122, 132 of transistors Ql and Q2 are connected to the common node of "source” (or “emitter”) electrodes of the transistor Q3, Q4, Q5 and Q6 at the first terminal 102.
  • connections and signals such as LO O, L0 45, LO 90, LO_135, LO 180, LO_225, LO 270 and LO_315, RF, DC etc. may be similar to the connections and signals for the up-conversion circuit 400.
  • the transistors with the same name may be different, for example, the transistors Q3, Q4 of the first transistor pair 140 may be different from the transistors Q3, Q4 of the third transistor pair 440.
  • Figs. 5A-5B show harmonic frequency conversion circuits according to various embodiments.
  • Fig. 5A shows a harmonic frequency up-conversion circuit 500 according to various embodiments, which may be configured to be used in an up-conversion mixer or modulator.
  • the harmonic frequency up-conversion circuit 500 may include the sub- harmonic up-conversion circuit 200 of Fig. 2 A having an inverter 110 and a transistor pair 140.
  • Various embodiments described with reference to Fig. 2 A are also valid for the harmonic frequency up-conversion circuit 500.
  • the harmonic frequency up-conversion circuit 500 may include a further sub- harmonic up-conversion circuit similar to the sub-harmonic up-conversion circuit 200, wherein the further sub-harmonic up-conversion circuit includes an inverter 510 and a transistor pair 540 having similar components and connections as those of the inverter 110 and the transistor pair 140.
  • the inverter 510 may include a P-transistor (Ql) 514, a N-transistor (Q2) 516 and a resistor (R) 512, and may be connected with the transistor pair 540 including a first transistor (Q3) 542 and a second transistor (Q4) 552 at the second terminal 504.
  • the inverter 510 may he configured to receive IF signal or IF data at the first terminal 502.
  • the resistor R 512 inside the inverter 510 may be used to tradeoff between the gain and input/output matching. Though the resistor Rl is shown in the embodiments of Fig. 5 A, if is understood that a capacitor, or a resistor connected in parallel with a capacitor, may be provided between the first terminal 502 and the second terminal 504 of the inverter 510.
  • the "source” (or “emitter”) electrode of the P-transistor 514 inside the inverter 510 may be coupled or connected to a DC supply (Vdd) directly or through lumped elements or transmission line.
  • the "source” (or “emitter”) electrode of the N-transistor 516 may be connected to the ground.
  • the inverter 110 may be configured to receive in- phase signal/data (i.e. "I" signal/data) and the inverter 512 may be configured to receive quadrature phase signal/data (i.e. "Q" signal/data).
  • the inverter 1 10 may receive 0 degree phase shifted IF signal (denoted by IF_0) or 0 degree, phase shifted IF data (denoted by Data O) at its first terminal 102; and may be connected to the transistor pair 140 at its second terminal 104.
  • the transistor pair 140 may output 0 degree phase shifted RF signal (denoted by RF 0) at the third terminal 106.
  • the inverter 510 may receive 90 degree phase shifted IF signal (denoted by IF 90) or 90 degree phase shifted IF data (denoted by Data_90) at its first terminal 502, and may be connected to the transistor pair 540 at its second terminal 504.
  • the transistor pair 540 may output 90 degree phase shifted RF signal (denoted by RF 90) at the third terminal 506.
  • the third terminal 106 of the transistor pair 140 and the third, terminal 506 of the transistor pair 540 may be connected to inductors, resistors, LC tank, transmission lines or their combination for matching and/or bias purpose.
  • the third terminals 106, 506 may be connected to inductors for DC bias and RF blocking. In the embodiments shown in Fig.
  • the common node 106 connected with "drain” (or “collector”) electrodes 146, 156 of the transistor pair 140 may be coupled or connected to a DC bias 560 (VDD) through an inductor LI 562, and the common node 506 connected with "drain” (or “collector") electrodes of the transistor pair 540 may be coupled or connected to the DC bias 560 (VDD) through an inductor L2 564.
  • the inductors LI and L2 may have the same or different values or parameters.
  • the harmonic frequency up- conversion circuit 500 may further include a 90 degree hybrid coupler 566, wherein the nodes 106, 506 for output RF 0 and RF 90 may be connected to two ports of the four- port 90 degree T ybrid coupler 566 through two capacitors CI and C2, respectively.
  • the other two ports i.e. output port and isolation port, of the 90 degree hybrid coupler 566 may be used for upper sideband (USB) frequency conversion signal or low sideband (LSB) frequency conversion signal.
  • the harmonic frequency up- conversion circuit 500 may be configured to generate upper side band (USB) mixed/modulated signal or low side band (LSB) mixed/modulated signal for conversion from in-phase and quadrature-phase IF signal/data.
  • the harmonic frequency up-conversion circuit 500 may be referred to or used as a sub-harmonic IQ frequency up- conversion SSB (single sideband) mixer/modulator.
  • SSB single sideband
  • Fig. 5B shows a harmonic frequency down-conversion circuit 590 according to various embodiments, which may be configured to be used in a down-conversion mixer or demodulator.
  • the harmonic frequency down-conversion circuit 590 is similar to the harmonic frequency up-conversion circuit 500 of Fig. 5A, with the difference that the transistor pairs 140, 540 are respectively connected to the first terminal 102, 502 of the inverters 110, 510.
  • Various embodiments described with reference to Fig. 5 A above are also valid for the harmonic frequency down-conversion circuit 590.
  • the inverter 1 10 may be configured to output in-phase signal/data (i.e. "I" signal/data) and the inverter 512 may be configured to output quadrature phase signal/data (i.e. "Q" signal/data).
  • the transistor pair 140 may receive 0 degree phase shifted RF signal (denoted by RF 0) at the third terminal 106, and the inverter 1 10 may output 0 degree phase shifted IF signal (denoted by IF 0) or 0 degree phase shifted IF data (denoted by Data O) at its second terminal 104.
  • the transistor pair 540 may receive 90 degree phase shifted RF signal (denoted by RF_90) at the third terminal 506, and the inverter 510 may output 90 degree phase shifted IF signal (denoted by IF_90) or 90 degree phase shifted IF data (denoted by Data_90) at its second terminal 504.
  • the third terminal 106 of the transistor pair 140 and the third terminal 506 of the transistor pair 540 may be connected to inductors, resistors, LC tank, transmission lines or their combination for matching and/or bias purpose. In the embodiments shown in Fig.
  • the common node 106 connected with "drain” (or “collector”) electrodes 146, 156 of the transistor pair 140 may be coupled or connected to the DC bias 560 (VDD) through the inductor LI 562, and the common node 506 connected with "drain” (or “collector") electrodes of the transistor pair 540 may be coupled or connected to the DC bias 560 (VDD) through the inductor L2 564.
  • the inductors LI and L2 may have the same or different values or parameters.
  • the nodes 106, 506 for output RF 0 and RF 90 may be connected to the 90 degree hybrid coupler 566 through two capacitors CI and C2, respectively.
  • the harmonic frequency down-conversion circuit 590 may be configured to add upper side band (USB) mixed/modulated signal or low side band (LSB) mixed/modulated signal for conversion to in-phase and quadrature-phase IF signal/data.
  • the harmonic frequency down-conversion circuit 590 may be referred to or used as a sub-harmonic IQ frequency down-conversion SSB (single sideband) mixer/demodulator.
  • SSB single sideband
  • Figs. 6A-6B show harmonic frequency conversion circuits according to various embodiments.
  • Fig. 6A shows a harmonic frequency up-conversion circuit 600 according to various embodiments, which may be configured to be used in an up-conversion mixer or modulator with image rejection.
  • the harmonic frequency up-conversion circuit 600 may include the sub-harmonic up-conversion circuit 200 of Fig. 2 A having an inverter 110 and a transistor pair 140, is similar to the harmonic frequency up-conversion circuit 500 of Fig. 5A.
  • Various embodiments described with reference to Fig. 2A and Fig. 5A are also valid for the harmonic frequency up-conversion circuit 600.
  • the harmonic frequency up-conversion circuit 600 may further include a second sub-harmonic up-conversion circuit 200B, a third sub-harmonic up-conversion circuit 200C and a fourth sub-harmonic up-conversion circuit 200D.
  • the circuits 200B, 200C, 200D are similar to the sub-harmonic up-conversion circuit 200, may each include an inverter and a transistor pair having similar components and connections as those of the inverter 1 10 and the transistor pair 140 of the sub-harmonic frequency up-conversion circuit 200.
  • a P-transistor Ql, a N-transistor Q2 and a resistor Rl/R forms an inverter, which may be configured to receive IF signal or data from baseband or other digital sources.
  • the common node of "gate” (or “base”) electrodes of transistors Ql and Q2 of the inverters may be connected to differential "I" signal/data or differential "Q" signal/data input from baseband or other sources.
  • the resistor Rl/R inside the inverters may be used to tradeoff between the gain and input/output matching.
  • the sub-harmonic up-conversion circuit 200, 200B may be configured to receive differential "I" signal/data, wherein the circuit 200 may receive 180 degree phase shifted IF signal/data (denoted by IF 180 or data_180) at its first terminal 102, and the circuit 200B may receive 0 degree phase shifted IF signal/data (denoted by IF_0 or data O) at its first terminal 102B.
  • the sub-harmonic up-conversion circuit 200C, 200D may be configured to receive differential "Q" signal/data, wherein the circuit 200C may receive 270 degree phase shifted IF signal/data (denoted by IF 270 or data_270) at its first terminal 102C, and the circuit 200D may receive 90 degree phase shifted IF signal/data (denoted by IF 90 or data_90) at its first terminal 102D.
  • LO signals of LO O, LO 90, LO 180 and LO 270 provided to the sub-harmonic up-conversion circuits 200, 200B may have the same amplitude, and may have a phase difference of 90 degrees in sequence (i.e. 0, 90, 180, 270 degrees).
  • the DC bias may be applied together with LO_0, LO 90, LO 180 and LO 270 for the transistor "gate" (or "base”) bias purpose.
  • the sub-harmonic up- conversion circuit 200 and the second sub-harmonic up-conversion circuit 200B are connected to each other at their third terminal 106.
  • the common node 106 connected with “drain” (or “collector”) electrodes of the transistor pairs in the circuits 200, 200B may output a 180 degree phase shifted RF signal (denoted by RF 180).
  • the common node 106 may be coupled or connected to the DC bias 560 through the inductor LI 562.
  • the common node 106 may also be connected to inductors, resistors, LC tank, transmission lines or their combination for matching and/or bias purpose.
  • LO signals of LO O, LO_90, LO 180 and LO 270 provided to the sub-harmonic up-conversion circuits 200C, 200D may have the same amplitude, and may have a phase difference of 90 degrees in sequence (i.e. 0, 90, 180, 270 degrees).
  • the DC bias may be applied together with LO O, LO_90, LO 180 and LO_270 for the transistor "gate" (or "base”) bias purpose.
  • the third sub-harmonic up-conversion circuit 200C and the fourth sub-harmonic up-conversion circuit 200D are connected to each other at their third terminal 606.
  • the common node 606 connected with "drain” (or “collector”) electrodes of the transistor pairs in the circuits 200C, 200D may output a 270 degree phase shifted RF signal (denoted by RF 270).
  • the common node 606 may be coupled or connected to the DC bias 560 through the inductor L2 564.
  • the common node 606 may also be connected to inductors, resistors, LC tank, transmission lines or their combination for matching and/or bias purpose.
  • the inductors LI and L2 may have the same or different values or parameters.
  • the harmonic frequency up-conversion circuit 600 may further include a 90 degree hybrid coupler 566, wherein the nodes 106, 606 for output RF 180 and RF 270 may be connected to the 90 degree hybrid coupler 566 through two capacitors CI and C2, respectively.
  • the harmonic frequency up-conversion circuit 600 may be configured to generate upper side band (USB) mixed/modulated signal or low side band (LSB) mixed/modulated signal for conversion from in-phase and quadrature-phase IF signal/data.
  • the IF signal or data input with different phases may be combined with the different LO phases for the frequency up- conversion operation with either LSB or USB.
  • the operation performs the function with image rejection frequency conversion.
  • necessary biases and the matching network may be included as described above.
  • the DC block capacitor-or matching capacitor may be included into the circuit 600.
  • the harmonic frequency up-conversion circuit 600 may be referred to or used as a differential IQ sub-harmonic frequency up-conversion SSB mixer/modulator with image rejection.
  • more than four sub-harmonic frequency conversion circuits 200 may be connected in parallel.
  • a power divider or a balun may be used to carry out frequency conversion with different phase combination of the IF/data and the LO signals for up-conversion, or with different phase combination of LO signal and RF signals for down-conversion.
  • both the passive network and transistor network may be used for the required signal generation.
  • the passive network such as transmission line, lumped coupler or poly phase filter, may be used.
  • active transistor network such as active balun or phase shifter may be used.
  • the differential or quadrature VCO voltage-controlled oscillator
  • Fig. 6B shows a harmonic frequency down-conversion circuit 690 according to various embodiments, which may be configured to be used in a down-conversion mixer or demodulator with image rejection.
  • the harmonic frequency down-conversion circuit 690 is similar to the harmonic frequency up-conversion circuit 600 of Fig. 6A, with the difference that the circuit 690 includes the harmonic down-conversion circuit 290 of Fig. 2B and additional three harmonic down-conversion circuits 290B, 290C, 290D having the similar configuration as the harmonic down-conversion circuit 290.
  • Various embodiments described with reference to Fig. 2B and Fig. 6A above are also valid for the harmonic frequency down-conversion circuit 690.
  • the common node of "gate” (or “base”) of transistors Ql and Q2 may be connected to the common node of "source” (or “emitter”) of the transistor Q3 and Q4, as shown in Fig. 6B.
  • the inverters of the harmonic down-conversion circuits 290, 290B, 290C, 290D may be configured to output differential "I" signal/data (e.g. differential "I” IF signal or data of 0 degree denoted by IF 0 or Data_0, and differential "I” IF signal or data of 180 degree denoted by IF 180 or Data_180), or output differential "Q" signal/data (e.g. differential "Q” IF signal or data of 90 degree denoted by IF 90 or Data_90, and differential "Q” IF signal or data of 270 degree denoted by IF_270 and Data_270).
  • differential "I" signal/data e.g. differential "I” IF signal or data of 0 degree denoted by IF 0 or Data_0, and differential "I” IF signal or data of 180 degree denoted by IF 180 or Data_180
  • differential "Q" signal/data e.g. differential "Q” IF signal or data of 90 degree denoted by
  • the resistors Rl/R inside the inverters may be used to tradeoff between the gain and input/output matching.
  • the "source” (or “emitter”) electrodes of the P-transistors inside of the inverters may be connected to Vdd (DC supply) directly or through lumped elements or transmission lines etc. '
  • LO signals of LO O, LO 90, LO l 80 and LO_270 may have the same amplitude and may have phase difference of 90 degrees in sequence (i.e. 0, 90, 180, 270 degrees), similar to the embodiments of Fig. 6 A above.
  • the DC can be applied together with LO O, LO 90, LO 180 and LO 270 for the transistor "gate” (or “base”) bias purpose.
  • the common node 106, 606 connected with “drain” (or “collector”) of the transistor pairs may be connected to inductors, resistors, LC tank, transmission lines or their combination for matching and/or bias purpose.
  • the harmonic frequency down-conversion circuit 690 may be referred to or used as a differential IQ sub-harmonic frequency down-conversion SSB mixer/demodulator with image rejection.
  • Fig. 7 shows an exemplary layout 700 of an up-conversion sub-harmonic Differential IQ SSB modulator together with a Differential IQ network according to various embodiments, which may be used in a transceiver.
  • a passive Differential IQ network 710 (also referred to as a DQ network) is provided to convert the input differential LO signal (LO O, LO 180) into differential quadrature output LO signals (LO-0, LO 180, LO 90 and LO_270) with phases of 0, 180, 90 and 270 degrees.
  • the output LO signals may be supplied to the sub- harmonic differential IQ modulator 600 (also referred to as sub-harmonic DQ modulator).
  • the sub-harmonic differential IQ modulator may be the harmonic frequency up- conversion circuit 600 described in Fig. 6A above, including four sub-harmonic frequency conversion cells 200 of Fig.
  • the 90 degree hybrid coupler is integrated with the core modulator 600 as in Fig. 6A.
  • the GSSGSSG pads 720 are used for probe touching for differential quadrature IF/data inputs.
  • the GSSG pads 730 at the bottom is to feed in differential LO signals LO O and LO_180.
  • the GSGSG Pads 740 on the top are used to obtain either LSB signal or USB signal.
  • the harmonic frequency conversion circuits of various embodiments may be capable of suppressing the sub-harmonic leakage and image signal to provide good linearity and spectrum purity for the modulator as well as for the transmitter.
  • Fig. 8 shows a transceiver 800 including a sub-harmonic Differential IQ modulator/ demodulator according to various embodiments.
  • Fig. 8 shows the application of the sub-harmonic Differential IQ modulator/demodulator (also referred to as sub-harmonic DQ modulator/demodulator) in the transceiver 800.
  • the use of the sub-harmonic Differential IQ modulator 810 e.g. IQ modulator 500, 600 of Figs. 5A and 6A
  • the sub-harmonic Differential IQ demodulator 820 e.g.
  • IQ demodulator 590, 690 of Figs. 5B and 6B) of various embodiments above may dramatically simplify the transceiver architecture by reducing the components and LO chain, and thus reducing the chip area and the total power consumption.
  • the required LO frequency may be reduced to half of that of the normal fundamental modulator.
  • a synthesizer 830 for LO drive may be shared by both the transmitter side and the receiver side.
  • the Differential IQ networks 832, 834 (also referred to as DQ networks) may be used to convert the differential LO signals (LO O and LO_180) from the synthesizer 830 to differential quadrature LO signals (LO O, LO 90, LO 180, LO 270), as shown in Fig. 8.
  • the Differential IQ networks 832, 834 may be integrated with the IQ modulator/demodulator, similar to the embodiment of Fig. 7.
  • the LSB When USB is needed for the transceiver system, the LSB may be connected to 50ohm load. At the transmitter side, the USB may be connected to a power amplifier 840. At the receiver side, the USB may be connected to a low-noise amplifier 850.
  • Fig. 9 shows a differential IQ sub-harmonic up-conversion DSB (double sideband) mixer/modulator 900 according to various embodiments.
  • the differential IQ sub-harmonic frequency conversion circuit of various embodiments may be used in a modulator or mixer with double side band.
  • the differential IQ sub-harmonic up-conversion DSB mixer/modulator 900 is similar to the circuit 600 of Fig. 6A, with the difference that the 90 degree hybrid 566 is replaced by a power combiner/divider 966 to collect both USB and LSB as the DSB.
  • the power combiner/divider 966 may also be replaced by a transformer for power combination.
  • the 90 degree hybrid coupler 566 in the circuits 500, 590, 690 of Figs. 5A, 5B, 6B may also be replaced by a power combiner/divider, to form the corresponding circuits for DSB modulator/demodulator.
  • Fig. 10 shows an IQ fourth-harmonic down-conversion SSB mixer/demodulator 1000 according to various embodiments.
  • the mixer/demodulator 1000 may include a fourth-harmonic frequency down-conversion circuit 390 described in Fig. 3B above for converting RF signal into in-phase IF signal (IF_I) or IF data (Data_I).
  • the mixer/demodulator 1000 may include a further fourth-harmonic frequency down-conversion circuit 390B similar to the circuit 390, for converting RF signal into quadrature-phase IF signal (IF Q) or IF data (Data Q). In this manner, I and Q signals may be generated from the RF signals received at the node 106 and 1006.
  • the mixer/demodulator 1000 may include a 90 degree hybrid 566 to input either USB or LSB for the SSB operation.
  • the up-conversion fourth-harmonic frequency up-conversion circuit 300 of Fig. 3A may be used to form the IQ fourth- harmonic frequency up-conversion modulator/mixer.
  • the single sideband (SSB) modulator/demodulator may be useful in the modulation applications wherein the desired and undesired RF sidebands are too close in frequency to be separated using a simple band pass filter or where minimum group delay is required.

Abstract

Un circuit de conversion de fréquences harmoniques, comprenant un inverseur et des premier et deuxième transistors, peut comporter au moins un élément parmi une résistance et un condensateur connecté entre une première borne et une deuxième borne. L'inverseur comprend un transistor à canal P et un transistor à canal N ayant chacun trois électrodes. Les première et deuxième électrodes du transistor à canal P et du transistor à canal N sont connectées aux première et deuxième bornes respectivement. Les premier et deuxième transistors ont chacun trois électrodes. La première électrode des premier et deuxième transistors est connectée de façon à recevoir un premier signal d'oscillation local et un deuxième signal d'oscillation local respectivement. Les deuxièmes électrodes des premier et deuxième transistors sont connectées l'une à l'autre au niveau d'une troisième borne. Les troisièmes électrodes des premier et deuxième transistors sont connectées à l'une ou l'autre des première et deuxième bornes de l'inverseur.
PCT/SG2013/000373 2012-08-27 2013-08-27 Circuit de conversion de fréquences harmoniques WO2014035342A1 (fr)

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WO2021133397A1 (fr) 2019-12-27 2021-07-01 Intel Corporation Procédés et dispositifs pour sélectionner un sous-harmonique souhaitée d'une horloge à haute fréquence
US11552596B2 (en) 2020-06-17 2023-01-10 Imec Vzw Odd harmonic generation device and method

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US20100029239A1 (en) * 2008-08-01 2010-02-04 Qualcomm Incorporated Upconverter and downconverter with switched transconductance and lo masking

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US20100029239A1 (en) * 2008-08-01 2010-02-04 Qualcomm Incorporated Upconverter and downconverter with switched transconductance and lo masking

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021133397A1 (fr) 2019-12-27 2021-07-01 Intel Corporation Procédés et dispositifs pour sélectionner un sous-harmonique souhaitée d'une horloge à haute fréquence
EP4082124A4 (fr) * 2019-12-27 2023-09-20 INTEL Corporation Procédés et dispositifs pour sélectionner un sous-harmonique souhaitée d'une horloge à haute fréquence
US11552596B2 (en) 2020-06-17 2023-01-10 Imec Vzw Odd harmonic generation device and method

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