WO2014035087A1 - Light-emitting module for surface lighting - Google Patents
Light-emitting module for surface lighting Download PDFInfo
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- WO2014035087A1 WO2014035087A1 PCT/KR2013/007413 KR2013007413W WO2014035087A1 WO 2014035087 A1 WO2014035087 A1 WO 2014035087A1 KR 2013007413 W KR2013007413 W KR 2013007413W WO 2014035087 A1 WO2014035087 A1 WO 2014035087A1
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- WIPO (PCT)
- Prior art keywords
- light emitting
- layer
- circuit board
- lens
- mesas
- Prior art date
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 18
- 238000003892 spreading Methods 0.000 claims description 60
- 239000004065 semiconductor Substances 0.000 claims description 57
- 238000000034 method Methods 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 11
- 230000003287 optical effect Effects 0.000 claims description 9
- 229920005989 resin Polymers 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 5
- 229920002050 silicone resin Polymers 0.000 claims description 3
- 239000006185 dispersion Substances 0.000 claims 2
- 239000010410 layer Substances 0.000 description 207
- 238000009826 distribution Methods 0.000 description 16
- 239000011247 coating layer Substances 0.000 description 8
- 229910002601 GaN Inorganic materials 0.000 description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000005286 illumination Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 229910003962 NiZn Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 229910008599 TiW Inorganic materials 0.000 description 1
- 230000004308 accommodation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- -1 gallium nitride compound Chemical class 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
- H01L33/60—Reflective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/50—Wavelength conversion elements
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0274—Optical details, e.g. printed circuits comprising integral optical means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10106—Light emitting diode [LED]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
Definitions
- the present invention relates to a light emitting module, and more particularly to a light emitting module for a surface illumination having a lens.
- a light emitting module for a surface illumination used in a light emitting module or a surface lighting apparatus for backlighting a liquid crystal display generally includes a lens for mounting a light emitting element on a circuit board and dispersing light emitted from the light emitting element at a wide angle. By uniformly dispersing the light emitted from the light emitting device by using the lens, a large area can be uniformly irradiated with a small number of light emitting devices.
- FIG. 1 is a schematic cross-sectional view for describing a light emitting module according to the prior art.
- the light emitting module includes a circuit board 100, a light emitting device 200, and a lens 300.
- the circuit board 100 is a printed circuit board on which a conductive pattern (not shown) is formed.
- the light emitting device 200 includes a main body 250 having a recess, a light emitting diode chip 210 mounted in the recess, and a molding part 230 covering the light emitting diode chip 210 in the recess.
- the molding part 230 includes a phosphor for wavelength converting light emitted from the light emitting diode chip 210.
- the light emitting device 200 is electrically connected to a conductive pattern (not shown) of the circuit board 100.
- the lens 300 has legs 310, and the legs 310 are attached to the circuit board 100 and disposed on the light emitting device 200.
- the lens 300 has an entrance surface 330 through which light is incident from the light emitting device 200 and an exit surface 350 through which the incident light is emitted.
- the incident surface 330 is provided in the form of a recess in the lower portion of the lens 300.
- the light emitting module according to the related art may implement uniform light over a large area by dispersing the light emitted from the light emitting device 200 through the lens 300.
- the light emitting device 200 disposed on the circuit board 100 and the lens 300 mounted on the circuit board 100 through the legs 310 have a limitation in slimming of the light emitting module.
- the main body 250 having the recess is adopted, the size of the light emitting device 200 is relatively large, and thus the size of the lens 300 is relatively increased.
- there is a limit in dispersing light through the lens 300 because the directivity angle of the light emitted through the main body 250 is relatively narrow.
- the light emitting diode chip 210, the light emitting device 200, and the lens 300 in the light emitting device 200 need to be precisely aligned.
- the light emitting module according to the prior art has a limitation in reducing alignment tolerance because all of the light emitting diode chip 210, the light emitting device 200, and the lens 300 must be precisely positioned.
- the problem to be solved by the present invention is to provide a light emitting module that can reduce the overall height.
- Another object of the present invention is to provide a light emitting module that can reduce alignment tolerances.
- Another object of the present invention is to provide a light emitting module capable of providing uniform light over a large area by adopting a light emitting diode suitable for a surface light source.
- a light emitting module includes a circuit board; A light emitting device flip-bonded to the circuit board; And a lens coupled to the circuit board and dispersing light emitted from the light emitting element.
- the light emitting device is a flip chip light emitting diode chip; And a wavelength conversion layer coated on the light emitting diode chip.
- the wavelength conversion layer may cover the top and side surfaces of the light emitting diode chip. In a particular embodiment, the wavelength conversion layer may cover only the top surface of the LED chip.
- the lens is coupled to the circuit board without employing conventional legs. Accordingly, the lower surface of the lens is closer to the upper surface of the circuit board, and the light emitting module is further slimmer.
- the circuit board may have a protrusion on an upper surface thereof, and the lens may have a receiving groove accommodating the protrusion, and the lens may be coupled to the circuit board by receiving the protrusion.
- a dam portion may be formed on the circuit board instead of the protrusion, and the lens may be coupled to the circuit board by receiving the dam portion.
- the dam portion may be formed of a silicone resin or an optical sheet.
- the light emitting module may further include an optical sheet attached to the circuit board and having an opening for exposing the light emitting device.
- the lens may be inserted into an opening of the optical sheet and coupled to the circuit board.
- the circuit board may include a recess, and the lens may be fitted into the recess and coupled to the circuit board.
- the lens has an incident surface on which light emitted from the light emitting element is incident and an exit surface on which incident light is emitted.
- the incident surface may be an inner surface of a recess located on the lower surface of the lens.
- the recess may include a first recess and a second recess positioned at an inlet side of the first recess and surrounding the first recess.
- the light emitting diode chip may include a first conductivity type semiconductor layer; A plurality of mesas spaced apart from each other on the first conductive semiconductor layer, each of the mesas including an active layer and a second conductive semiconductor layer; Reflective electrodes positioned on the plurality of mesas, respectively, for ohmic contact with a second conductivity-type semiconductor layer; And openings covering the plurality of mesas and the first conductivity type semiconductor layer, the openings being located in the upper region of each mesa and exposing the reflective electrodes, ohmic contacting the first conductivity type semiconductor layer, and the plurality of mesas. And a current spreading layer insulated from the light emitting diode chip, the light emitting diode chip being flip bonded to the circuit board.
- the current spreading layer covers the plurality of mesas and the first conductivity type semiconductor layer, the current spreading performance is improved through the current spreading layer.
- the first conductivity type semiconductor layer is continuous.
- the plurality of mesas may have an elongated shape extending in parallel to each other in one direction, and the openings of the current spreading layer may be located at the same end side of the plurality of mesas. Therefore, a pad connecting the reflective electrodes exposed to the openings of the current spreading layer can be easily formed.
- the current spreading layer may include a reflective metal such as Al. Accordingly, in addition to the light reflection by the reflective electrodes, the light reflection by the current spreading layer can be obtained, and thus, the light traveling through the plurality of mesas sidewalls and the first conductivity type semiconductor layer can be reflected.
- the reflective electrodes may each include a reflective metal layer and a barrier metal layer. Further, the barrier metal layer may cover the top and side surfaces of the reflective metal layer. As a result, the reflective metal layer can be prevented from being exposed to the outside, and deterioration of the reflective metal layer can be prevented.
- the light emitting diode chip may include: an upper insulating layer covering at least a portion of the current spreading layer and having openings exposing the reflective electrodes; And a second pad disposed on the upper insulating layer and connected to the reflective electrodes exposed through the openings of the upper insulating layer, and further comprising a first pad connected to the current spreading layer.
- the first pad and the second pad may be formed in the same shape and size, and thus flip chip bonding may be easily performed.
- the light emitting diode chip may further include a lower insulating layer positioned between the plurality of mesas and the current spreading layer to insulate the current spreading layer from the plurality of mesas.
- the lower insulating layer may have openings positioned in the upper mesas and exposing the reflective electrodes.
- each of the openings of the current spreading layer may have a wider width than the openings of the lower insulating layer so that all of the openings of the lower insulating layer are exposed. That is, sidewalls of the openings of the current spreading layer are located on the lower insulating layer.
- the LED chip may further include an upper insulating layer covering at least a portion of the current spreading layer and having openings exposing the reflective electrodes. The upper insulating layer may cover sidewalls of the openings of the current spreading layer.
- the lower insulating layer may be a reflective dielectric layer, such as a distributed Bragg reflector (DBR).
- DBR distributed Bragg reflector
- the LED chip may further include a growth substrate, and the growth substrate may be, for example, a sapphire substrate or a gallium nitride substrate.
- the wavelength conversion layer covers the growth substrate to convert wavelengths of light emitted from the growth substrate to the outside.
- the light emitting module can be made slim, and furthermore, the mounting tolerance of the light emitting module can be reduced by mounting the light emitting diode chip directly on the circuit board. Furthermore, the illumination intensity distribution can be improved by adopting a flip chip type light emitting diode chip having a relatively wide beam angle.
- FIG. 1 is a cross-sectional view illustrating a light emitting module according to the prior art.
- FIG. 2 is a cross-sectional view illustrating a light emitting module according to an embodiment of the present invention.
- FIG 3 is a cross-sectional view for describing a light emitting module according to another embodiment of the present invention.
- 4 to 7 are cross-sectional views illustrating various light emitting modules according to embodiments of the present invention.
- FIGS. 8 to 12 are views for explaining a method of manufacturing a light emitting diode chip according to an embodiment of the present invention, in each of the drawings (a) is a plan view and (b) is a cross-sectional view taken along the cutting line A-A.
- Figure 14 is a graph showing the directivity distribution of the conventional LED package 200 and the flip chip LED chip having a conformal coating layer of the present application (a) and (b), respectively.
- FIG. 15 is a graph illustrating directions of distribution of light emitting modules using a conventional LED package 200 and light emitting modules using a flip chip type LED chip having a conformal coating layer of the present application as (a) and (b), respectively.
- Figure 16 shows the illuminance distribution of the light emitting module combining 16 LED array and the lens
- (a) is a conventional LED package having a 120-degree directivity
- (b) is a flip-chip type light emitting diode to which the conformal coating layer according to the present application is applied The illuminance distribution of the light emitting module to which the chip is applied is shown.
- FIG. 2 is a cross-sectional view illustrating a light emitting module according to an embodiment of the present invention.
- the light emitting module includes a circuit board 100a, a dam unit 130, a light emitting diode chip 220, a conformal coated wavelength conversion layer 240, and a lens 300a.
- the circuit board 100a is a printed circuit board on which a printed circuit (not shown) is formed.
- the dam 130 is formed around the mounting area of the LED chip 220.
- the dam unit 130 may be formed by attaching the optical sheet to the circuit board 100a in a ring shape, or may be formed using a silicone resin.
- the light emitting diode chip 220 is mounted on the circuit board 100a.
- the LED chip 220 is flip-bonded without using a bonding wire and connected to the printed circuit on the direct circuit board 100a. Since the present invention does not use a wire when bonding the LED chip 220 on the circuit board 100a, the molding part for protecting the wire is not required, and the wavelength conversion layer 240 is used to expose the bonding pad. You don't even have to remove a part of). Therefore, by adopting the flip type light emitting diode chip 220, color deviation and luminance unevenness may be eliminated and the module manufacturing process may be simplified as compared with using the light emitting diode chip using the bonding wire.
- the light emitting diode chip 220 is a flip chip semiconductor chip formed of a gallium nitride-based compound semiconductor and may emit ultraviolet light or blue light.
- a flip chip type semiconductor according to an embodiment of the present invention will be described in detail later with reference to FIGS. 8 to 13.
- the wavelength conversion layer 240 covers the light emitting diode chip 220.
- the conformal coated wavelength conversion layer 240 for example, a phosphor layer, may be formed on the light emitting diode chip 220, and may convert the light emitted from the light emitting diode chip 220 to wavelength convert.
- the wavelength conversion layer 240 is coated on the LED chip 220 and may cover the top and side surfaces of the LED chip 220. In a particular embodiment, the wavelength conversion layer 240 may cover only the top surface of the LED chip 220.
- the light emitted from the light emitting diode chip 220 and the wavelength conversion layer 240 may be used to implement light of various colors, and in particular, may implement mixed light such as white light.
- the conformal coated wavelength conversion layer 240 may be previously formed on the LED chip 220 and mounted on the circuit board 100a together with the LED chip 220.
- the lens 300a has an entrance surface 330 through which light is incident from the LED chip 220 and an exit surface 350 through which light is emitted from the lens 300a to the outside.
- the incident surface 330 may be an inner surface of a bell shaped recess.
- the lens 300a disperses the light incident from the light emitting diode chip 220 by using the refraction of the light at the entrance surface 330 and the refraction of the light at the exit surface 350.
- the lens 300a also has an accommodating groove for accommodating the dam 130, and by accommodating the dam 130, the lens 300a may be coupled to the circuit board 100a. Since the lens 300a can be coupled to the circuit board 100a by using the dam 130 and the receiving groove of the lens 300a, the conventional leg portion 310 of FIG. 1 can be removed. Accordingly, the lower surface of the lens 300a is close to the upper surface of the circuit board 100a, and thus, the light emitting module may be further slimmed.
- FIG 3 is a cross-sectional view for describing a light emitting module according to another embodiment of the present invention.
- the light emitting module according to the present embodiment is generally similar to the light emitting module described with reference to FIG. 2, but there is a difference in the shape of the concave portion of the lens 300b.
- the incident surface of the lens 300b includes a longitudinally shaped first recessed inner surface 331 and an inner surface 333 of the second recessed portion surrounding the first recessed portion.
- the second recess is formed at the inlet side of the first recess and has a relatively wider width than the first recess.
- the inner surface 333 of the second concave portion changes the traveling path of the light incident from the light emitting diode chip 220 to the upper side to prevent the light from being absorbed and lost by the dam unit 130.
- FIG. 4 is a cross-sectional view for describing a light emitting module according to another embodiment of the present invention.
- the light emitting module according to the present embodiment is generally similar to the light emitting module described with reference to FIG. 2, except that the circuit board 100b has the protrusion 150. That is, in the light emitting module of FIG. 2, the dam part 110 is formed to couple the lens 300a to the circuit board 100a. However, in the present exemplary embodiment, the protrusion 150 is provided on the circuit board 100b to provide the lens 300a. ) Are being combined.
- the process of forming the dam unit 110 may be omitted by forming the protrusion 150 on the circuit board 100b instead of the dam unit 110, and the lens 300a may be more stably provided.
- the second concave portion may be formed at the entrance of the first concave portion to prevent light loss caused by the protrusion 150.
- FIG. 5 is a cross-sectional view for describing a light emitting module according to another embodiment of the present invention.
- the light emitting module according to the present embodiment is generally similar to the light emitting module described with reference to FIG. 2, but a recess 150 is formed in the circuit board 100c and the lens 300c is recessed. There is a difference between the fitting and the fitting.
- the dam unit 110 does not need to be formed, and the accommodation groove is formed in the lens 300c. no need.
- a second recessed portion as described with reference to FIG. 3 may be formed.
- FIG. 6 is a cross-sectional view for describing a light emitting module according to another embodiment of the present invention.
- the light emitting module according to the present embodiment is generally similar to the light emitting module described with reference to FIG. 5, but has an optical sheet having an opening 175 for coupling the lens 300c to the circuit board 100d. There is a difference in that the 170 is attached and the lens 300c is coupled to the opening 175.
- the opening 175 of the optical sheet 170 is used instead of the recess 150 in FIG. Therefore, it is not necessary to form the recess 150 in the circuit board 100d.
- FIG. 7 is a cross-sectional view for describing a light emitting module according to another embodiment of the present invention.
- the light emitting module according to the present embodiment is substantially similar to the light emitting module described with reference to FIG. 2, but further includes a transparent resin 260 covering the light emitting diode chip 220 and the wavelength conversion layer 240. There is a difference.
- the transparent resin 260 covers the light emitting device in the recess 330.
- the transparent resin 260 may also be applied to the embodiments of FIGS. 3 to 6.
- the transparent resin 260 protects the wavelength conversion layer 240 and the light emitting diode chip 220 from moisture.
- FIGS. 8 to 12 are views for explaining a flip chip type light emitting diode chip manufacturing method according to an embodiment of the present invention, (a) is a cross-sectional view taken along the cutting line A-A (b) in each of the drawings.
- a first conductive semiconductor layer 23 is formed on the growth substrate 21, and a plurality of mesas M spaced apart from each other on the first conductive semiconductor layer 23 are formed. Is formed.
- the plurality of mesas M may include an active layer 25 and a second conductivity type semiconductor layer 27, respectively.
- the active layer 25 is positioned between the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27.
- the reflective electrodes 30 are positioned on the plurality of mesas M, respectively.
- the plurality of mesas M may be formed on the growth substrate 21 by forming an epitaxial layer including the first conductive semiconductor layer 23, the active layer 25, and the second conductive semiconductor layer 27. After growing using the same, the second conductive semiconductor layer 27 and the active layer 25 may be formed by patterning the first conductive semiconductor layer 23 to expose the first conductive semiconductor layer 23. Sides of the plurality of mesas M may be formed to be inclined by using a technique such as photoresist reflow. The inclined profile of the mesa (M) side improves the extraction efficiency of the light generated in the active layer 25.
- the plurality of mesas M may have an elongated shape extending in parallel to each other in one direction as shown. This shape simplifies forming a plurality of mesas M of the same shape in the plurality of chip regions on the growth substrate 21.
- the reflective electrodes 30 may be formed on each mesa M after the plurality of mesas M are formed, but is not limited thereto.
- the second conductive semiconductor layer 27 may be grown and mesas. It may be formed in advance on the second conductivity-type semiconductor layer 27 before forming (M).
- the reflective electrode 30 covers most of the upper surface of the mesa M, and has a shape substantially the same as the planar shape of the mesa M.
- the reflective electrodes 30 may include a reflective layer 28 and may further include a barrier layer 29.
- the barrier layer 29 may cover the top and side surfaces of the reflective layer 28.
- barrier layer 29 can be formed to cover the top and side surfaces of reflective layer 28.
- the reflective layer 28 may be formed by depositing and patterning an Ag, Ag alloy, Ni / Ag, NiZn / Ag, TiO / Ag layer.
- the barrier layer 29 may be formed of Ni, Cr, Ti, Pt, Rd, Ru, W, Mo, TiW, or a composite layer thereof to prevent the metal material of the reflective layer from being diffused or contaminated.
- an edge of the first conductivity type semiconductor layer 23 may also be etched. Accordingly, the upper surface of the substrate 21 may be exposed. Side surfaces of the first conductivity-type semiconductor layer 23 may also be formed to be inclined.
- the plurality of mesas M may be formed to be located within the upper region of the first conductivity-type semiconductor layer 23. That is, the plurality of mesas M may be located in an island shape on the upper region of the first conductivity type semiconductor layer 23.
- mesas M extending in one direction may be formed to reach the upper edge of the first conductivity-type semiconductor layer 23. That is, one side edge of the bottom surface of the plurality of mesas M coincides with one side edge of the first conductive semiconductor layer 23. Accordingly, the top surface of the first conductivity type semiconductor layer 23 is partitioned by a plurality of mesas M.
- a lower insulating layer 31 covering the plurality of mesas M and the first conductive semiconductor layer 23 is formed.
- the lower insulating layer 31 has openings 31a and 31b to allow electrical connection to the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27 in a specific region.
- the lower insulating layer 31 may have openings 31a exposing the first conductivity type semiconductor layer 23 and openings 31b exposing the reflective electrodes 30.
- the openings 31a may be positioned near the edge between the mesas M and the edge of the substrate 21, and may have an elongated shape extending along the mesas M.
- the openings 31b are limited to the upper portion of the mesa (M), and are located on the same end side of the mesas.
- the lower insulating layer 31 may be formed of an oxide film such as SiO 2 , a nitride film such as SiN x, or an insulating film of SiON or MgF 2 using a technique such as chemical vapor deposition (CVD).
- the lower insulating layer 31 may be formed of a single layer, but is not limited thereto and may be formed of multiple layers.
- the lower insulating layer 31 may be formed of a distributed Bragg reflector (DBR) in which a low refractive material layer and a high refractive material layer are alternately stacked.
- DBR distributed Bragg reflector
- an insulating reflective layer having a high reflectance can be formed by laminating dielectric layers such as SiO 2 / TiO 2 or SiO 2 / Nb 2 O 5 .
- a current spreading layer 33 is formed on the lower insulating layer 31.
- the current spreading layer 33 covers the plurality of mesas M and the first conductive semiconductor layer 23.
- the current spreading layer 33 has openings 33a located in the upper region of each mesa M to expose the reflective electrodes.
- the current spreading layer 33 may be in ohmic contact with the first conductivity type semiconductor layer 23 through the openings 31a of the lower insulating layer 31.
- the current spreading layer 33 is insulated from the plurality of mesas M and the reflective electrodes 30 by the lower insulating layer 31.
- the openings 33a of the current spreading layer 33 have a larger area than the openings 31b of the lower insulating layer 31, respectively, to prevent the current spreading layer 33 from connecting to the reflective electrodes 30. Have Thus, sidewalls of the openings 33a are located on the lower insulating layer 31.
- the current spreading layer 33 is formed over almost the entire area of the substrate 31 except for the openings 33a. Thus, current can be easily dispersed through the current spreading layer 33.
- the current spreading layer 33 may include a high reflective metal layer such as an Al layer, and the high reflective metal layer may be formed on an adhesive layer such as Ti, Cr, or Ni.
- a protective layer of a single layer or a composite layer structure such as Ni, Cr, Au, or the like may be formed on the highly reflective metal layer.
- the current spreading layer 33 may have, for example, a multilayer structure of Ti / Al / Ti / Ni / Au.
- an upper insulating layer 35 is formed on the current spreading layer 33.
- the upper insulating layer 35 has openings 35b exposing the current spreading layer 33 and openings 35b exposing the reflective electrodes 30.
- the opening 35a may have an elongated shape in a direction perpendicular to the longitudinal direction of the mesa M, and has a relatively large area compared to the openings 35b.
- the openings 35b expose the reflective electrodes 30 exposed through the openings 33a of the current spreading layer 33 and the openings 31b of the lower insulating layer 31.
- the openings 35b may have a smaller area than the openings 33a of the current spreading layer 33, and may have a larger area than the openings 31b of the lower insulating layer 31. Accordingly, sidewalls of the openings 33a of the current spreading layer 33 may be covered by the upper insulating layer 35.
- the upper insulating layer 35 may be formed using an oxide insulating layer, a nitride insulating layer, a mixed layer or a cross layer of these insulating layers, or a polymer such as polyimide, teflon, parylene, or the like.
- a first pad 37a and a second pad 37b are formed on the upper insulating layer 35.
- the first pad 37a connects to the current spreading layer 33 through the opening 35a of the upper insulating layer 35
- the second pad 37b connects the openings 35b of the upper insulating layer 35. It is connected to the reflective electrodes 30 through.
- the first pad 37a and the second pad 37b may be connected to bumps or used as pads for SMT to mount the light emitting diode to a submount, package, or printed circuit board.
- the first and second pads 37a and 37b may be formed together in the same process, for example using photo and etching techniques or lift off techniques.
- the first and second pads 37a and 37b may include, for example, an adhesive layer such as Ti, Cr, or Ni, and a highly conductive metal layer such as Al, Cu, Ag, or Au.
- the first and second pads 37a and 37b may be formed so that the end ends thereof are coplanar, and thus the light emitting diode chip 220 may be formed on the conductive patterns having the same height on the circuit boards 100a to 100d. Can be flip bonded to.
- the growth substrate 21 is divided into individual light emitting diode chip units to complete the light emitting diode chip.
- the growth substrate 21 may be removed from the LED chip before or after it is divided into individual LED chip units.
- the light emitting diode chip includes a first conductive semiconductor layer 23, mesas M, reflective electrodes 30, and a current spreading layer 33, and includes a growth substrate 21 and a lower insulating layer 31.
- the upper insulating layer 35 may include a first pad 37a and a second pad 37b.
- the substrate 21 may be a growth substrate for growing gallium nitride-based epi layers, such as sapphire, silicon carbide, silicon, or gallium nitride substrate.
- the substrate 21 is, for example, a sapphire substrate, it may have a thickness of 200um or more, preferably 250um or more.
- the first conductive semiconductor layer 23 is continuous, and the plurality of mesas M are spaced apart from each other on the first conductive semiconductor layer 23.
- the mesas M include the active layer 25 and the second conductivity-type semiconductor layer 27 as described with reference to FIG. 8 and have an elongated shape extending toward one side.
- the mesas M may be a stacked structure of a gallium nitride compound semiconductor.
- the mesas M may be limitedly positioned in an upper region of the first conductivity-type semiconductor layer 23, as shown in FIG. 8.
- the mesas M may extend to one edge of the upper surface of the first conductivity-type semiconductor layer 23 in one direction, as shown in FIG. 6, and thus the first conductivity-type semiconductor layer 23.
- the upper surface of the can be divided into a plurality of areas. Accordingly, it is possible to alleviate the concentration of the current near the edge of the mesas (M) to further enhance the current distribution performance.
- the reflective electrodes 30 are respectively positioned on the plurality of mesas M to make ohmic contact with the second conductivity-type semiconductor layer 27.
- the reflective electrodes 300 may include a reflective layer 28 and a barrier layer 29, and the barrier layer 29 may cover the top and side surfaces of the reflective layer 28.
- the current spreading layer 33 covers the plurality of mesas M and the first conductive semiconductor layer 23.
- the current spreading layer 33 has openings 33a located in the upper region of each mesa M and exposing the reflective electrodes 30.
- the current spreading layer 33 is also ohmic contacted to the first conductivity type semiconductor layer 23 and insulated from the plurality of mesas M.
- the current spreading layer 33 may include a reflective metal such as Al.
- the current spreading layer 33 may be insulated from the plurality of mesas M by the lower insulating layer 31.
- the lower insulating layer 31 may be positioned between the plurality of mesas M and the current spreading layer 33 to insulate the current spreading layer 33 from the plurality of mesas M.
- the lower insulating layer 31 may have openings 31b disposed in the upper region of each mesa M to expose the reflective electrodes 30, and may expose the first conductivity-type semiconductor layer 23. It may have openings 31a.
- the current spreading layer 33 may be connected to the first conductivity type semiconductor layer 23 through the openings 31a.
- the openings 31b of the lower insulating layer 31 have a smaller area than the openings 33a of the current spreading layer 33 and are all exposed by the openings 33a.
- the upper insulating layer 35 covers at least a portion of the current spreading layer 33.
- the upper insulating layer 35 has openings 35b exposing the reflective electrodes 30.
- the upper insulating layer 35 may have an opening 35a exposing the current spreading layer 33.
- the upper insulating layer 35 may cover sidewalls of the openings 33a of the current spreading layer 33.
- the first pad 37a may be positioned on the current spreading layer 33, and may be connected to the current spreading layer 33 through, for example, an opening 35a of the upper insulating layer 35.
- the second pad 37b is connected to the reflective electrodes 30 exposed through the openings 35b.
- the first pad 37a and the second pad 37b may have upper ends disposed at the same height.
- the current spreading layer 33 covers almost the entire area of the mesas M and the first conductivity type semiconductor layer 23 between the mesas M. Thus, current can be easily dispersed through the current spreading layer 33.
- the current spreading layer 23 includes a reflecting metal layer such as Al, or the lower insulating layer is formed as an insulating reflecting layer so that the light not reflected by the reflecting electrodes 30 is reflected by the current spreading layer 23 or the lower insulating layer. (31) can be used to reflect, thereby improving light extraction efficiency.
- the flip chip light emitting diode chip according to the present embodiment may have a relatively wide directivity distribution.
- FIG. 14 is a graph illustrating a direct distribution of a flip chip type light emitting diode chip 240 having a conventional light emitting diode package 200 and a conformal coating layer 220 according to an embodiment of the present disclosure.
- the conventional LED package 200 has a directing angle of about 120 degrees as a substantially same directing angle with respect to the X and Y directions.
- the flip-chip type light emitting diode chip 240 of the present application exhibits a direction angle of about 140 degrees which is substantially the same with respect to the X direction and the Y direction, and when the conformal coating layer is applied, as shown in FIG. Indicates the orientation angle.
- Figure 15 (a) shows the directivity distribution of the light emitting module using a conventional light emitting diode package having a directivity angle of 120 degrees
- Figure 15 (b) is coated with a conformal coating layer 220 having a directivity angle of 145 degrees of the present application
- the directivity distribution of the light emitting module using the flip chip light emitting diode chip 240 is shown.
- the light directivity distribution in the uniaxial direction was simulated using a light emitting element and a lens having the same illuminance distribution in each direction.
- the light directivity distribution shows the luminous intensity according to the directivity angle at a point 5 m away from each light emitting element.
- FIG. 16 illustrates an illuminance distribution of a light emitting module in which 16 light emitting devices are arranged in a 4 ⁇ 4 matrix on a circuit board and a lens is coupled to each light emitting device.
- b) shows the illuminance distribution of the light emitting module in which the flip chip type light emitting diode chip 240 to which the conformal coating layer 220 is applied is arranged.
- the distance between the light sources was 100 mm and the illuminance distribution measurement distance was 23 mm.
- FIG. 16 (a) the light uniformity was 79.4%, and in FIG. 16 (b), the light uniformity was 84.6%. Even when comparing FIGS. 16 (a) and (b) with the naked eye, FIG. In this case, it can be seen that the light diffusivity of the outside is superior to that of FIG.
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Abstract
A light-emitting module for surface lighting is disclosed. The light-emitting module comprises: a circuit board; a light-emitting element which is flip-bonded to the circuit board; and a lens which is coupled to the circuit board and disperses light emitted from the light-emitting element. In addition, the light-emitting element comprises a flip-chip type light-emitting diode chip and a wavelength conversion layer coated on the light-emitting diode chip. The light-emitting module can be made to be slim by mounting the flip-chip type light-emitting diode chip on the circuit board.
Description
본 발명은 발광 모듈에 관한 것으로, 특히 렌즈를 구비하는 면 조명용 발광 모듈에 관한 것이다.The present invention relates to a light emitting module, and more particularly to a light emitting module for a surface illumination having a lens.
액정 디스플레이를 백라이팅하기 위한 발광 모듈이나 면 조명 장치에 사용되는 면 조명용 발광 모듈은 일반적으로 회로 기판 상에 발광 소자를 실장하고 상기 발광 소자에서 방출되는 광을 넓은 각도로 분산시키는 렌즈를 포함한다. 상기 렌즈를 이용하여 발광 소자에서 방출된 광을 고르게 분산시킴으로써 적은 개수의 발광소자로 넓은 영역을 균일하게 조사할 수 있다.BACKGROUND OF THE INVENTION A light emitting module for a surface illumination used in a light emitting module or a surface lighting apparatus for backlighting a liquid crystal display generally includes a lens for mounting a light emitting element on a circuit board and dispersing light emitted from the light emitting element at a wide angle. By uniformly dispersing the light emitted from the light emitting device by using the lens, a large area can be uniformly irradiated with a small number of light emitting devices.
도 1은 종래 기술에 따른 발광 모듈을 설명하기 위한 개략적인 단면도이다.1 is a schematic cross-sectional view for describing a light emitting module according to the prior art.
도 1을 참조하면, 상기 발광 모듈은 회로 기판(100), 발광 소자(200) 및 렌즈(300)를 포함한다. 상기 회로 기판(100)은 도전 패턴(도시하지 않음)이 형성된 인쇄회로 기판이다.Referring to FIG. 1, the light emitting module includes a circuit board 100, a light emitting device 200, and a lens 300. The circuit board 100 is a printed circuit board on which a conductive pattern (not shown) is formed.
상기 발광 소자(200)는 리세스를 갖는 본체(250)와 리세스 내에 실장된 발광 다이오드 칩(210) 및 상기 리세스 내에서 발광 다이오드 칩(210)을 덮는 몰딩부(230)를 포함한다. 상기 몰딩부(230)는 발광 다이오드 칩(210)에서 방출된 광을 파장변환시키는 형광체를 포함한다. 상기 발광 소자(200)는 회로 기판(100)의 도전 패턴(도시하지 않음)에 전기적으로 연결된다.The light emitting device 200 includes a main body 250 having a recess, a light emitting diode chip 210 mounted in the recess, and a molding part 230 covering the light emitting diode chip 210 in the recess. The molding part 230 includes a phosphor for wavelength converting light emitted from the light emitting diode chip 210. The light emitting device 200 is electrically connected to a conductive pattern (not shown) of the circuit board 100.
한편, 상기 렌즈(300)는 다리부들(310)을 가지며, 다리부들(310)이 회로 기판(100) 상에 부착되어 발광 소자(200) 상부에 배치된다. 상기 렌즈(300)는 발광소자(200)로부터 광이 입사되는 입사면(330)과 입사된 광이 출사되는 출사면(350)을 갖는다. 상기 입사면(330)은 렌즈(300)의 하부에 오목부 형태로 제공된다.Meanwhile, the lens 300 has legs 310, and the legs 310 are attached to the circuit board 100 and disposed on the light emitting device 200. The lens 300 has an entrance surface 330 through which light is incident from the light emitting device 200 and an exit surface 350 through which the incident light is emitted. The incident surface 330 is provided in the form of a recess in the lower portion of the lens 300.
종래기술에 따른 발광 모듈은 발광 소자(200)에서 방출된 광을 렌즈(300)를 통해 분산시킴으로써 넓은 면적에 걸쳐 균일한 광을 구현할 수 있다. 그러나 회로 기판(100) 상에 배치된 발광 소자(200)와, 다리부들(310)을 통해 회로 기판(100) 상에 장착된 렌즈(300)를 갖기 때문에, 발광 모듈의 슬림화에 한계가 있다. 더욱이, 리세스를 갖는 본체(250)를 채택하기 때문에 발광 소자(200)의 크기가 상대적으로 크고, 이에 따라 렌즈(300)의 크기도 상대적으로 증가된다. 더욱이, 본체(250)를 통해 방출되는 광의 지향각이 상대적으로 좁기 때문에 렌즈(300)를 통해 광을 분산시키는데 한계가 있다.The light emitting module according to the related art may implement uniform light over a large area by dispersing the light emitted from the light emitting device 200 through the lens 300. However, since the light emitting device 200 disposed on the circuit board 100 and the lens 300 mounted on the circuit board 100 through the legs 310 have a limitation in slimming of the light emitting module. Furthermore, since the main body 250 having the recess is adopted, the size of the light emitting device 200 is relatively large, and thus the size of the lens 300 is relatively increased. Moreover, there is a limit in dispersing light through the lens 300 because the directivity angle of the light emitted through the main body 250 is relatively narrow.
더욱이, 균일한 면 광원을 구현하기 위해 발광 소자(200) 내의 발광 다이오드 칩(210), 발광 소자(200) 및 렌즈(300)가 정밀하게 정렬될 필요가 있다. 그러나, 종래 기술에 따른 발광 모듈은 발광 다이오드 칩(210), 발광 소자(200) 및 렌즈(300)를 모두 정밀하게 위치시켜야 하므로 정렬 공차를 줄이는데 한계가 있다.Furthermore, in order to realize a uniform surface light source, the light emitting diode chip 210, the light emitting device 200, and the lens 300 in the light emitting device 200 need to be precisely aligned. However, the light emitting module according to the prior art has a limitation in reducing alignment tolerance because all of the light emitting diode chip 210, the light emitting device 200, and the lens 300 must be precisely positioned.
본 발명이 해결하고자 하는 과제는, 전체 높이를 감소시킬 수 있는 발광 모듈을 제공하는 것이다.The problem to be solved by the present invention is to provide a light emitting module that can reduce the overall height.
본 발명이 해결하고자 하는 또 다른 과제는, 정렬 공차를 줄일 수 있는 발광 모듈을 제공하는 것이다.Another object of the present invention is to provide a light emitting module that can reduce alignment tolerances.
본 발명이 해결하고자 하는 또 다른 과제는, 면 광원에 적합한 발광 다이오드를 채택하여 넓은 면적에 걸쳐 균일한 광을 제공할 수 있는 발광 모듈을 제공하는 것이다.Another object of the present invention is to provide a light emitting module capable of providing uniform light over a large area by adopting a light emitting diode suitable for a surface light source.
본 발명의 실시예들에 따른 발광 모듈은, 회로 기판; 상기 회로 기판에 플립 본딩된 발광 소자; 및 상기 회로 기판에 결합되고, 상기 발광 소자에서 방출된 광을 분산시키는 렌즈를 포함한다. 한편, 상기 발광 소자는 플립칩형 발광 다이오드 칩; 및 상기 발광 다이오드 칩에 코팅된 파장변환층을 포함한다. 회로 기판에 플립칩형 발광 다이오드 칩을 실장함으로써, 발광 모듈을 슬림화할 수 있다.A light emitting module according to embodiments of the present invention includes a circuit board; A light emitting device flip-bonded to the circuit board; And a lens coupled to the circuit board and dispersing light emitted from the light emitting element. On the other hand, the light emitting device is a flip chip light emitting diode chip; And a wavelength conversion layer coated on the light emitting diode chip. By mounting a flip chip type light emitting diode chip on a circuit board, the light emitting module can be made slim.
상기 파장변환층은 상기 발광 다이오드 칩의 상면 및 측면을 덮을 수 있다. 특정 실시예에 있어서, 상기 파장변환층은 발광 다이오드 칩의 상면만을 덮을 수 있다.The wavelength conversion layer may cover the top and side surfaces of the light emitting diode chip. In a particular embodiment, the wavelength conversion layer may cover only the top surface of the LED chip.
상기 렌즈는 종래의 다리부를 채택하지 않고 상기 회로 기판에 결합된다. 따라서, 상기 렌즈의 하부면은 상기 회로 기판의 상부면에 근접하고 이에 따라 발광 모듈이 더욱 슬림화된다.The lens is coupled to the circuit board without employing conventional legs. Accordingly, the lower surface of the lens is closer to the upper surface of the circuit board, and the light emitting module is further slimmer.
예를 들어, 상기 회로 기판은 상면에 돌출부를 갖고, 상기 렌즈는 상기 돌출부를 수용하는 수용홈을 가지며, 상기 렌즈는 상기 수용홈이 상기 돌출부를 수용하여 상기 회로 기판에 결합될 수 있다. 또는, 상기 돌출부 대신 상기 회로 기판 상에 댐부가 형성되고, 상기 렌즈는 상기 수용홈이 상기 댐부를 수용하여 상기 회로 기판에 결합될 수 있다. 상기 댐부는 실리콘 수지 또는 광학 시트로 형성될 수 있다.For example, the circuit board may have a protrusion on an upper surface thereof, and the lens may have a receiving groove accommodating the protrusion, and the lens may be coupled to the circuit board by receiving the protrusion. Alternatively, a dam portion may be formed on the circuit board instead of the protrusion, and the lens may be coupled to the circuit board by receiving the dam portion. The dam portion may be formed of a silicone resin or an optical sheet.
또 다른 실시예에 있어서, 상기 발광 모듈은, 상기 회로 기판 상에 부착되고 상기 발광 소자를 노출시키는 개구부를 갖는 광학 시트를 더 포함할 수 있다. 상기 렌즈는 상기 광학 시트의 개구부에 끼워져 상기 회로 기판에 결합될 수 있다.In another embodiment, the light emitting module may further include an optical sheet attached to the circuit board and having an opening for exposing the light emitting device. The lens may be inserted into an opening of the optical sheet and coupled to the circuit board.
또 다른 실시예에 있어서, 상기 회로 기판은 리세스를 포함하고, 상기 렌즈는 상기 리세스에 끼워져 상기 회로 기판에 결합될 수 있다.In another embodiment, the circuit board may include a recess, and the lens may be fitted into the recess and coupled to the circuit board.
한편, 상기 렌즈는 상기 발광 소자로부터 방출된 광이 입사되는 입사면과 입사된 입사광이 출사되는 출사면을 갖는다. 상기 입사면은 상기 렌즈의 하부면에 위치하는 오목부 내부면일 수 있다. 나아가, 상기 오목부는 제1 오목부 및 상기 제1 오목부의 입구측에 위치하여 상기 제1 오목부를 둘러싸는 제2 오목부를 포함할 수 있다.The lens has an incident surface on which light emitted from the light emitting element is incident and an exit surface on which incident light is emitted. The incident surface may be an inner surface of a recess located on the lower surface of the lens. Furthermore, the recess may include a first recess and a second recess positioned at an inlet side of the first recess and surrounding the first recess.
본 발명의 실시예들에 있어서, 상기 발광 다이오드 칩은, 제1 도전형 반도체층; 상기 제1 도전형 반도체층 상에 서로 이격되어 배치되고, 각각 활성층 및 제2 도전형 반도체층을 포함하는 복수의 메사들; 각각 상기 복수의 메사들 상에 위치하여 제2 도전형 반도체층에 오믹 콘택하는 반사 전극들; 및 상기 복수의 메사들 및 상기 제1 도전형 반도체층을 덮되, 상기 각각의 메사 상부 영역 내에 위치하고 상기 반사 전극들을 노출시키는 개구부들을 가지며, 상기 제1 도전형 반도체층에 오믹콘택하고 상기 복수의 메사들로부터 절연된 전류 분산층을 포함하며, 이 발광 다이오드 칩이 상기 회로 기판에 플립 본딩된다.In example embodiments, the light emitting diode chip may include a first conductivity type semiconductor layer; A plurality of mesas spaced apart from each other on the first conductive semiconductor layer, each of the mesas including an active layer and a second conductive semiconductor layer; Reflective electrodes positioned on the plurality of mesas, respectively, for ohmic contact with a second conductivity-type semiconductor layer; And openings covering the plurality of mesas and the first conductivity type semiconductor layer, the openings being located in the upper region of each mesa and exposing the reflective electrodes, ohmic contacting the first conductivity type semiconductor layer, and the plurality of mesas. And a current spreading layer insulated from the light emitting diode chip, the light emitting diode chip being flip bonded to the circuit board.
상기 전류 분산층이 복수의 메사들 및 제1 도전형 반도체층을 덮기 때문에, 전류 분산층을 통해 전류 분산 성능이 향상된다.Since the current spreading layer covers the plurality of mesas and the first conductivity type semiconductor layer, the current spreading performance is improved through the current spreading layer.
상기 제1 도전형 반도체층은 연속적이다. 나아가, 상기 복수의 메사들은 일측 방향으로 서로 평행하게 연장하는 기다란 형상을 갖고, 상기 전류 분산층의 개구부들은 상기 복수의 메사들의 동일 단부측에 치우쳐 위치할 수 있다. 따라서, 전류 분산층의 개구부들에 노출된 반사 전극들을 연결하는 패드를 용이하게 형성할 수 있다.The first conductivity type semiconductor layer is continuous. In addition, the plurality of mesas may have an elongated shape extending in parallel to each other in one direction, and the openings of the current spreading layer may be located at the same end side of the plurality of mesas. Therefore, a pad connecting the reflective electrodes exposed to the openings of the current spreading layer can be easily formed.
상기 전류 분산층은 Al과 같은 반사 금속을 포함할 수 있다. 이에 따라, 반사 전극들에 의한 광 반사에 더하여, 전류 분산층에 의한 광 반사를 얻을 수 있으며, 따라서, 복수의 메사들 측벽 및 제1 도전형 반도체층을 통해 진행하는 광을 반사시킬 수 있다.The current spreading layer may include a reflective metal such as Al. Accordingly, in addition to the light reflection by the reflective electrodes, the light reflection by the current spreading layer can be obtained, and thus, the light traveling through the plurality of mesas sidewalls and the first conductivity type semiconductor layer can be reflected.
한편, 상기 반사 전극들은 각각 반사 금속층과 장벽 금속층을 포함할 수 있다. 나아가, 상기 장벽 금속층이 상기 반사 금속층의 상면 및 측면을 덮을 수 있다. 이에 따라, 반사 금속층이 외부에 노출되는 것을 방지할 수 있어 반사 금속층의 열화를 방지할 수 있다.The reflective electrodes may each include a reflective metal layer and a barrier metal layer. Further, the barrier metal layer may cover the top and side surfaces of the reflective metal layer. As a result, the reflective metal layer can be prevented from being exposed to the outside, and deterioration of the reflective metal layer can be prevented.
상기 발광 다이오드 칩은, 상기 전류분산층의 적어도 일부를 덮되, 상기 반사 전극들을 노출시키는 개구부들을 갖는 상부 절연층; 및 상기 상부 절연층 상에 위치하고 상기 상부 절연층의 개구부들을 통해 노출된 반사 전극들에 접속하는 제2 패드를 더 포함할 수 있으며, 나아가, 상기 전류 분산층에 접속하는 제1 패드를 더 포함할 수 있다. 상기 제1 패드 및 제2 패드는 동일한 형상 및 크기로 형성될 수 있으며, 따라서 플립칩 본딩을 용이하게 수행할 수 있다.The light emitting diode chip may include: an upper insulating layer covering at least a portion of the current spreading layer and having openings exposing the reflective electrodes; And a second pad disposed on the upper insulating layer and connected to the reflective electrodes exposed through the openings of the upper insulating layer, and further comprising a first pad connected to the current spreading layer. Can be. The first pad and the second pad may be formed in the same shape and size, and thus flip chip bonding may be easily performed.
또한, 상기 발광 다이오드 칩은, 상기 복수의 메사들과 상기 전류 분산층 사이에 위치하여 상기 전류 분산층을 상기 복수의 메사들로부터 절연시키는 하부 절연층을 더 포함할 수 있다. 상기 하부 절연층은 상기 각각의 메사 상부 영역 내에 위치하고 상기 반사 전극들을 노출시키는 개구부들을 가질 수 있다.The light emitting diode chip may further include a lower insulating layer positioned between the plurality of mesas and the current spreading layer to insulate the current spreading layer from the plurality of mesas. The lower insulating layer may have openings positioned in the upper mesas and exposing the reflective electrodes.
나아가, 상기 전류 분산층의 개구부들은 각각 상기 하부 절연층의 개구부들이 모두 노출되도록 상기 하부 절연층의 개구부들보다 더 넓은 폭을 가질 수 있다. 즉, 상기 전류 분산층의 개구부들의 측벽은 상기 하부 절연층 상에 위치한다. 이에 더하여, 상기 발광 다이오드 칩은, 상기 전류분산층의 적어도 일부를 덮고, 상기 반사 전극들을 노출시키는 개구부들을 갖는 상부 절연층을 더 포함할 수 있다. 상기 상부 절연층은 상기 전류 분산층의 개구부들의 측벽들을 덮을 수 있다.Further, each of the openings of the current spreading layer may have a wider width than the openings of the lower insulating layer so that all of the openings of the lower insulating layer are exposed. That is, sidewalls of the openings of the current spreading layer are located on the lower insulating layer. In addition, the LED chip may further include an upper insulating layer covering at least a portion of the current spreading layer and having openings exposing the reflective electrodes. The upper insulating layer may cover sidewalls of the openings of the current spreading layer.
상기 하부 절연층은 반사성 유전층, 예컨대 분포 브래그 반사기(DBR)일 수 있다.The lower insulating layer may be a reflective dielectric layer, such as a distributed Bragg reflector (DBR).
한편, 상기 발광 다이오드 칩은 성장 기판을 더 포함할 수 있으며, 상기 성장 기판은 예컨대 사파이어 기판 또는 질화갈륨 기판일 수 있다. 상기 파장변환층은 상기 성장 기판을 덮어 성장 기판으로부터 외부로 방출되는 광의 파장을 변환시킨다.The LED chip may further include a growth substrate, and the growth substrate may be, for example, a sapphire substrate or a gallium nitride substrate. The wavelength conversion layer covers the growth substrate to convert wavelengths of light emitted from the growth substrate to the outside.
본 발명의 실시예들에 따르면, 발광 모듈을 슬림화할 수 있으며, 나아가 발광 다이오드 칩을 직접 회로 기판 상에 실장함으로써 발광 모듈의 정렬 공차를 줄일 수 있다. 나아가, 지향각이 상대적으로 넓은 플립칩형 발광 다이오드 칩을 채택함으로써 조도분포를 개선할 수 있다.According to the embodiments of the present invention, the light emitting module can be made slim, and furthermore, the mounting tolerance of the light emitting module can be reduced by mounting the light emitting diode chip directly on the circuit board. Furthermore, the illumination intensity distribution can be improved by adopting a flip chip type light emitting diode chip having a relatively wide beam angle.
도 1은 종래 기술에 따른 발광 모듈을 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a light emitting module according to the prior art.
도 2는 본 발명의 일 실시예에 따른 발광 모듈을 설명하기 위한 단면도이다.2 is a cross-sectional view illustrating a light emitting module according to an embodiment of the present invention.
도 3은 본 발명의 또 다른 실시예에 따른 발광 모듈을 설명하기 위한 단면도이다.3 is a cross-sectional view for describing a light emitting module according to another embodiment of the present invention.
도 4 내지 도 7은 본 발명의 실시예들에 따른 다양한 발광 모듈을 설명하기 위한 단면도들이다.4 to 7 are cross-sectional views illustrating various light emitting modules according to embodiments of the present invention.
도 8 내지 도 12는 본 발명의 일 실시예에 따른 발광 다이오드 칩 제조 방법을 설명하기 위한 도면들로서, 각 도면들에서 (a)는 평면도를 (b)는 절취선 A-A를 따라 취해진 단면도를 나타낸다.8 to 12 are views for explaining a method of manufacturing a light emitting diode chip according to an embodiment of the present invention, in each of the drawings (a) is a plan view and (b) is a cross-sectional view taken along the cutting line A-A.
도 13은 메사 구조의 변형예를 설명하기 위한 평면도이다.It is a top view for demonstrating the modified example of a mesa structure.
도 14는 종래의 발광 다이오드 패키지(200) 및 본원의 컨포멀 코팅층을 갖는 플립칩형 발광 다이오드 칩의 지향 분포를 각각 (a) 및 (b)로 나타낸 그래프이다.Figure 14 is a graph showing the directivity distribution of the conventional LED package 200 and the flip chip LED chip having a conformal coating layer of the present application (a) and (b), respectively.
도 15는 종래의 발광 다이오드 패키지(200)를 사용한 발광 모듈과 본원의 컨포멀 코팅층을 갖는 플립칩형 발광 다이오드 칩을 사용한 발광 모듈의 지향 분포를 각각 (a) 및 (b)로 나타낸 그래프이다.FIG. 15 is a graph illustrating directions of distribution of light emitting modules using a conventional LED package 200 and light emitting modules using a flip chip type LED chip having a conformal coating layer of the present application as (a) and (b), respectively.
도 16은 16개의 LED 어레이와 렌즈를 결합한 발광 모듈의 조도 분포를 나타낸 것으로 (a)는 종래의 120도 지향각을 갖는 발광 다이오드 패키지 (b)는 본원에 따른 컨포멀 코팅층이 적용된 플립칩형 발광 다이오드 칩을 적용한 발광 모듈의 조도 분포를 나타낸다. Figure 16 shows the illuminance distribution of the light emitting module combining 16 LED array and the lens (a) is a conventional LED package having a 120-degree directivity (b) is a flip-chip type light emitting diode to which the conformal coating layer according to the present application is applied The illuminance distribution of the light emitting module to which the chip is applied is shown.
이하, 첨부한 도면들을 참조하여 본 발명의 실시예들을 상세히 설명한다. 다음에 소개되는 실시예들은 당업자에게 본 발명의 사상이 충분히 전달될 수 있도록 하기 위해 예로서 제공되는 것이다. 따라서, 본 발명은 이하 설명되는 실시예들에 한정되지 않고 다른 형태로 구체화될 수도 있다. 그리고, 도면들에 있어서, 구성요소의 폭, 길이, 두께 등은 편의를 위하여 과장되어 표현될 수도 있다. 명세서 전체에 걸쳐서 동일한 참조번호들은 동일한 구성요소들을 나타낸다.Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention; The following embodiments are provided as examples to ensure that the spirit of the present invention can be fully conveyed to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, widths, lengths, thicknesses, and the like of components may be exaggerated for convenience. Like numbers refer to like elements throughout.
도 2는 본 발명의 일 실시예에 따른 발광 모듈을 설명하기 위한 단면도이다.2 is a cross-sectional view illustrating a light emitting module according to an embodiment of the present invention.
도 2를 참조하면, 발광 모듈은, 회로 기판(100a), 댐부(130), 발광 다이오드 칩(220), 컨포멀 코팅된 파장변환층(240), 렌즈(300a)를 포함한다. 회로 기판(100a)은 인쇄회로(도시하지 않음)가 형성된 인쇄회로기판이다.Referring to FIG. 2, the light emitting module includes a circuit board 100a, a dam unit 130, a light emitting diode chip 220, a conformal coated wavelength conversion layer 240, and a lens 300a. The circuit board 100a is a printed circuit board on which a printed circuit (not shown) is formed.
댐부(130)는 발광 다이오드 칩(220) 실장 영역 주위에 형성된다. 댐부(130)는 광학 시트를 링 형상으로 회로 기판(100a)에 부착하여 형성할 수도 있고, 실리콘 수지를 이용하여 형성할 수도 있다. The dam 130 is formed around the mounting area of the LED chip 220. The dam unit 130 may be formed by attaching the optical sheet to the circuit board 100a in a ring shape, or may be formed using a silicone resin.
발광 다이오드 칩(220)이 회로 기판(100a) 상에 실장된다. 발광 다이오드 칩(220)은 본딩 와이어를 사용함이 없이 플립 본딩되어 직접 회로 기판(100a) 상의 인쇄회로에 연결된다. 본 발명은 발광 다이오드 칩(220)을 상기 회로 기판(100a) 상에 본딩시 와이어를 사용하지 않기 때문에, 와이어를 보호하기 위한 몰딩부를 필요로 하지 않으며, 본딩 패드를 노출하기 위해 파장변환층(240)의 일부를 제거할 필요도 없다. 따라서, 플립형 발광 다이오드 칩(220)을 채택함으로써 본딩 와이어를 사용하는 발광 다이오드 칩을 사용하는 것에 비해 색편차나 휘도 얼룩 현상을 제거하고, 모듈 제조 공정을 단순화할 수 있다.The light emitting diode chip 220 is mounted on the circuit board 100a. The LED chip 220 is flip-bonded without using a bonding wire and connected to the printed circuit on the direct circuit board 100a. Since the present invention does not use a wire when bonding the LED chip 220 on the circuit board 100a, the molding part for protecting the wire is not required, and the wavelength conversion layer 240 is used to expose the bonding pad. You don't even have to remove a part of). Therefore, by adopting the flip type light emitting diode chip 220, color deviation and luminance unevenness may be eliminated and the module manufacturing process may be simplified as compared with using the light emitting diode chip using the bonding wire.
발광 다이오드 칩(220)은 질화갈륨계열의 화합물 반도체로 형성된 플립칩형 반도체 칩으로 자외선 또는 청색 계열의 광을 방출할 수 있다. 본 발명의 일 실시예에 따른 플립칩형 반도체에 대해 도 8 내지 도 13을 참조하여 뒤에서 상세히 설명하도록 한다. The light emitting diode chip 220 is a flip chip semiconductor chip formed of a gallium nitride-based compound semiconductor and may emit ultraviolet light or blue light. A flip chip type semiconductor according to an embodiment of the present invention will be described in detail later with reference to FIGS. 8 to 13.
한편, 파장변환층(240)은 발광 다이오드 칩(220)을 덮는다. 도시한 바와 같이, 컨포멀 코팅된 파장변환층(240), 예컨대 형광체층이 발광 다이오드 칩(220) 상에 형성될 수 있으며, 발광 다이오드 칩(220)에서 방출된 광을 파장변환할 수 있다. 파장변환층(240)은 발광 다이오드 칩(220)에 코팅되며, 발광 다이오드 칩(220)의 상면 및 측면을 덮을 수 있다. 특정 실시예에 있어서, 파장변환층(240)은 발광 다이오드 칩(220)의 상면만을 덮을 수도 있다. 발광 다이오드 칩(220)에서 방출된 광과 파장변환층(240)을 이용하여 다양한 색상의 광을 구현할 수 있으며, 특히 백색광과 같은 혼합광을 구현할 수 있다.Meanwhile, the wavelength conversion layer 240 covers the light emitting diode chip 220. As shown, the conformal coated wavelength conversion layer 240, for example, a phosphor layer, may be formed on the light emitting diode chip 220, and may convert the light emitted from the light emitting diode chip 220 to wavelength convert. The wavelength conversion layer 240 is coated on the LED chip 220 and may cover the top and side surfaces of the LED chip 220. In a particular embodiment, the wavelength conversion layer 240 may cover only the top surface of the LED chip 220. The light emitted from the light emitting diode chip 220 and the wavelength conversion layer 240 may be used to implement light of various colors, and in particular, may implement mixed light such as white light.
본 실시예에 있어서, 컨포멀 코팅된 파장변환층(240)은 발광 다이오드 칩(220) 상에 미리 형성되어 발광 다이오드 칩(220)과 함께 회로 기판(100a) 상에 실장될 수 있다.In the present exemplary embodiment, the conformal coated wavelength conversion layer 240 may be previously formed on the LED chip 220 and mounted on the circuit board 100a together with the LED chip 220.
한편, 렌즈(300a)는 발광 다이오드 칩(220)으로부터 광이 입사되는 입사면(330)과 렌즈(300a)로부터 외부로 광이 출사되는 출사면(350)을 갖는다. 입사면(330)은 도시한 바와 같이 종 모양의 오목부 내부면일 수 있다. 렌즈(300a)는 입사면(330)에서의 광의 굴절과 출사면(350)에서의 광의 굴절을 이용하여 발광 다이오드 칩(220)에서 입사된 광을 분산시킨다.On the other hand, the lens 300a has an entrance surface 330 through which light is incident from the LED chip 220 and an exit surface 350 through which light is emitted from the lens 300a to the outside. As illustrated, the incident surface 330 may be an inner surface of a bell shaped recess. The lens 300a disperses the light incident from the light emitting diode chip 220 by using the refraction of the light at the entrance surface 330 and the refraction of the light at the exit surface 350.
렌즈(300a)는 또한, 댐부(130)를 수용하는 수용홈을 가지며, 댐부(130)를 수용함으로써 렌즈(300a)가 회로 기판(100a)에 결합될 수 있다. 댐부(130)와 렌즈(300a)의 수용홈을 이용하여 렌즈(300a)를 회로 기판(100a)에 결합할 수 있기 때문에 종래의 다리부(도 1의 310)를 제거할 수 있다. 따라서, 렌즈(300a)의 하부면은 회로 기판(100a)의 상부면에 근접하고 이에 따라 발광 모듈을 더욱 슬림화할 수 있다.The lens 300a also has an accommodating groove for accommodating the dam 130, and by accommodating the dam 130, the lens 300a may be coupled to the circuit board 100a. Since the lens 300a can be coupled to the circuit board 100a by using the dam 130 and the receiving groove of the lens 300a, the conventional leg portion 310 of FIG. 1 can be removed. Accordingly, the lower surface of the lens 300a is close to the upper surface of the circuit board 100a, and thus, the light emitting module may be further slimmed.
도 3은 본 발명의 또 다른 실시예에 따른 발광 모듈을 설명하기 위한 단면도이다.3 is a cross-sectional view for describing a light emitting module according to another embodiment of the present invention.
도 3을 참조하면, 본 실시예에 따른 발광 모듈은 도 2를 참조하여 설명한 발광 모듈과 대체로 유사하나, 렌즈(300b)의 오목부 형상에 차이가 있다.Referring to FIG. 3, the light emitting module according to the present embodiment is generally similar to the light emitting module described with reference to FIG. 2, but there is a difference in the shape of the concave portion of the lens 300b.
즉, 본 실시예에 따른 렌즈(300b)의 입사면은 종 모양의 제1 오목부 내부면(331)과 제1 오목부를 둘러싸는 제2 오목부의 내부면(333)을 포함한다. 제2 오목부는 제1 오목부의 입구측에 형성되어 제1 오목부에 비해 상대적으로 넓은 폭을 갖는다.That is, the incident surface of the lens 300b according to the present exemplary embodiment includes a longitudinally shaped first recessed inner surface 331 and an inner surface 333 of the second recessed portion surrounding the first recessed portion. The second recess is formed at the inlet side of the first recess and has a relatively wider width than the first recess.
제2 오목부의 내부면(333)은 발광 다이오드 칩(220)에서 입사되는 광의 진행 경로를 상측으로 변경하여 광이 댐부(130)에 흡수되어 손실되는 것을 방지한다. The inner surface 333 of the second concave portion changes the traveling path of the light incident from the light emitting diode chip 220 to the upper side to prevent the light from being absorbed and lost by the dam unit 130.
도 4는 본 발명의 또 다른 실시예에 따른 발광 모듈을 설명하기 위한 단면도이다.4 is a cross-sectional view for describing a light emitting module according to another embodiment of the present invention.
도 4를 참조하면, 본 실시예에 따른 발광 모듈은 도 2를 참조하여 설명한 발광 모듈과 대체로 유사하나, 회로 기판(100b)이 돌출부(150)를 갖는 것에 차이가 있다. 즉, 도 2의 발광 모듈은 렌즈(300a)를 회로 기판(100a)에 결합시키기 위해 댐부(110)를 형성하였지만, 본 실시예에서는 회로 기판(100b)에 돌출부(150)를 마련하여 렌즈(300a)를 결합시키고 있다.Referring to FIG. 4, the light emitting module according to the present embodiment is generally similar to the light emitting module described with reference to FIG. 2, except that the circuit board 100b has the protrusion 150. That is, in the light emitting module of FIG. 2, the dam part 110 is formed to couple the lens 300a to the circuit board 100a. However, in the present exemplary embodiment, the protrusion 150 is provided on the circuit board 100b to provide the lens 300a. ) Are being combined.
본 실시예에 따르면, 댐부(110) 대신에 회로 기판(100b)에 돌출부(150)를 형성함으로써 댐부(110) 형성 공정을 생략할 수 있으며, 렌즈(300a)를 더 안정하게 회로 기판(100b)에 결합시킬 수 있다.According to the present exemplary embodiment, the process of forming the dam unit 110 may be omitted by forming the protrusion 150 on the circuit board 100b instead of the dam unit 110, and the lens 300a may be more stably provided. Can be bound to
한편, 도 3을 참조하여 설명한 바와 같이, 돌출부(150)에 의한 광 손실을 방지하기 위해 제1 오목부의 입구에 제2 오목부를 형성할 수 있다.Meanwhile, as described with reference to FIG. 3, the second concave portion may be formed at the entrance of the first concave portion to prevent light loss caused by the protrusion 150.
도 5는 본 발명의 또 다른 실시예에 따른 발광 모듈을 설명하기 위한 단면도이다.5 is a cross-sectional view for describing a light emitting module according to another embodiment of the present invention.
도 5를 참조하면, 본 실시예에 따른 발광 모듈은 도 2를 참조하여 설명한 발광 모듈과 대체로 유사하나, 회로 기판(100c)에 리세스(150)가 형성되고, 렌즈(300c)가 리세스(150)에 끼워 결합된 것에 차이가 있다.Referring to FIG. 5, the light emitting module according to the present embodiment is generally similar to the light emitting module described with reference to FIG. 2, but a recess 150 is formed in the circuit board 100c and the lens 300c is recessed. There is a difference between the fitting and the fitting.
즉, 도 2의 댐부(110) 대신에 리세스(150)를 이용하여 렌즈(300c)를 결합하기 때문에, 댐부(110)를 형성할 필요가 없으며, 또한 렌즈(300c)에 수용홈을 형성할 필요가 없다.That is, since the lens 300c is coupled using the recess 150 instead of the dam unit 110 of FIG. 2, the dam unit 110 does not need to be formed, and the accommodation groove is formed in the lens 300c. no need.
더욱이, 렌즈(300c)의 바깥 측면이 리세스(150)의 내벽에 끼워지므로, 렌즈(300c) 내부에서 광이 손실되는 것을 방지할 수 있다. 나아가, 리세스(150)의 내벽에 의해 광이 손실되는 것을 방지하기 위해 도 3에서 설명한 바와 같은 제2 오목부가 형성될 수도 있다.Furthermore, since the outer side surface of the lens 300c is fitted to the inner wall of the recess 150, it is possible to prevent the light from being lost inside the lens 300c. Further, in order to prevent light from being lost by the inner wall of the recess 150, a second recessed portion as described with reference to FIG. 3 may be formed.
도 6은 본 발명의 또 다른 실시예에 따른 발광 모듈을 설명하기 위한 단면도이다.6 is a cross-sectional view for describing a light emitting module according to another embodiment of the present invention.
도 6을 참조하면, 본 실시예에 따른 발광 모듈은 도 5를 참조하여 설명한 발광 모듈과 대체로 유사하나, 회로 기판(100d)에 렌즈(300c)를 결합할 수 있는 개구부(175)를 갖는 광학 시트(170)가 부착되고, 개구부(175)에 렌즈(300c)가 결합된 것에 차이가 있다.Referring to FIG. 6, the light emitting module according to the present embodiment is generally similar to the light emitting module described with reference to FIG. 5, but has an optical sheet having an opening 175 for coupling the lens 300c to the circuit board 100d. There is a difference in that the 170 is attached and the lens 300c is coupled to the opening 175.
즉, 광학 시트(170)의 개구부(175)가 도 5의 리세스(150) 대신에 사용된다. 따라서, 회로 기판(100d)에 리세스(150)를 형성할 필요가 없다.That is, the opening 175 of the optical sheet 170 is used instead of the recess 150 in FIG. Therefore, it is not necessary to form the recess 150 in the circuit board 100d.
도 7은 본 발명의 또 다른 실시예에 따른 발광 모듈을 설명하기 위한 단면도이다.7 is a cross-sectional view for describing a light emitting module according to another embodiment of the present invention.
도 7을 참조하면, 본 실시예에 따른 발광 모듈은 도 2를 참조하여 설명한 발광 모듈과 대체로 유사하나, 발광 다이오드 칩(220) 및 파장변환층(240)을 덮는 투명 수지(260)를 더 포함하는 것에 차이가 있다. 상기 투명 수지(260)는 오목부(330) 내에서 발광 소자를 덮는다. 상기 투명 수지(260)는 도 3 내지 도 6의 실시예에도 적용될 수 있다.Referring to FIG. 7, the light emitting module according to the present embodiment is substantially similar to the light emitting module described with reference to FIG. 2, but further includes a transparent resin 260 covering the light emitting diode chip 220 and the wavelength conversion layer 240. There is a difference. The transparent resin 260 covers the light emitting device in the recess 330. The transparent resin 260 may also be applied to the embodiments of FIGS. 3 to 6.
투명 수지(260)는 파장변환층(240) 및 발광 다이오드 칩(220)을 수분 등으로부터 보호한다.The transparent resin 260 protects the wavelength conversion layer 240 and the light emitting diode chip 220 from moisture.
(발광 다이오드 칩)(Light emitting diode chip)
이하에서는, 발광 다이오드 칩(220)에 대한 이해를 돕기 위해 그 제조 방법을 설명한다.Hereinafter, a manufacturing method thereof will be described in order to help the understanding of the LED chip 220.
도 8 내지 도 12는 본 발명의 일 실시예에 따른 플립칩형 발광 다이오드 칩 제조 방법을 설명하기 위한 도면들로서, 각 도면들에서 (a)는 평면도를 (b)는 절취선 A-A를 따라 취해진 단면도이다.8 to 12 are views for explaining a flip chip type light emitting diode chip manufacturing method according to an embodiment of the present invention, (a) is a cross-sectional view taken along the cutting line A-A (b) in each of the drawings.
우선, 도 8을 참조하면, 성장 기판(21) 상에 제1 도전형 반도체층(23)이 형성되고, 제1 도전형 반도체층(23) 상에 서로 이격된 복수의 메사들(M)이 형성된다. 복수의 메사들(M)은 각각 활성층(25) 및 제2 도전형 반도체층(27)을 포함한다. 활성층(25)이 제1 도전형 반도체층(23)과 제2 도전형 반도체층(27) 사이에 위치한다. 한편, 복수의 메사들(M) 상에는 각각 반사 전극들(30)이 위치한다.First, referring to FIG. 8, a first conductive semiconductor layer 23 is formed on the growth substrate 21, and a plurality of mesas M spaced apart from each other on the first conductive semiconductor layer 23 are formed. Is formed. The plurality of mesas M may include an active layer 25 and a second conductivity type semiconductor layer 27, respectively. The active layer 25 is positioned between the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27. Meanwhile, the reflective electrodes 30 are positioned on the plurality of mesas M, respectively.
복수의 메사(M)들은 성장 기판(21) 상에 제1 도전형 반도체층(23), 활성층(25) 및 제2 도전형 반도체층(27)을 포함하는 에피층을 금속 유기화학 기상 성장법 등을 이용하여 성장시킨 후, 제1 도전형 반도체층(23)이 노출되도록 제2 도전형 반도체층(27) 및 활성층(25)을 패터닝함으로써 형성될 수 있다. 복수의 메사들(M)의 측면은 포토레지스트 리플로우와 같은 기술을 사용함으로써 경사지게 형성될 수 있다. 메사(M) 측면의 경사진 프로파일은 활성층(25)에서 생성된 광의 추출 효율을 향상시킨다. The plurality of mesas M may be formed on the growth substrate 21 by forming an epitaxial layer including the first conductive semiconductor layer 23, the active layer 25, and the second conductive semiconductor layer 27. After growing using the same, the second conductive semiconductor layer 27 and the active layer 25 may be formed by patterning the first conductive semiconductor layer 23 to expose the first conductive semiconductor layer 23. Sides of the plurality of mesas M may be formed to be inclined by using a technique such as photoresist reflow. The inclined profile of the mesa (M) side improves the extraction efficiency of the light generated in the active layer 25.
복수의 메사들(M)은 도시한 바와 같이 일측 방향으로 서로 평행하게 연장하는 기다란 형상을 가질 수 있다. 이러한 형상은 성장 기판(21) 상에서 복수의 칩 영역에 동일한 형상의 복수의 메사들(M)을 형성하는 것을 단순화시킨다.The plurality of mesas M may have an elongated shape extending in parallel to each other in one direction as shown. This shape simplifies forming a plurality of mesas M of the same shape in the plurality of chip regions on the growth substrate 21.
한편, 반사 전극들(30)은 복수의 메사(M)들이 형성된 후, 각 메사(M) 상에 형성될 수 있으나, 이에 한정되는 것은 아니며, 제2 도전형 반도체층(27)을 성장시키고 메사(M)들을 형성하기 전에 제2 도전형 반도체층(27) 상에 미리 형성될 수도 있다. 반사 전극(30)은 메사(M)의 상면을 대부분 덮으며, 메사(M)의 평면 형상과 대체로 동일한 형상을 갖는다.Meanwhile, the reflective electrodes 30 may be formed on each mesa M after the plurality of mesas M are formed, but is not limited thereto. The second conductive semiconductor layer 27 may be grown and mesas. It may be formed in advance on the second conductivity-type semiconductor layer 27 before forming (M). The reflective electrode 30 covers most of the upper surface of the mesa M, and has a shape substantially the same as the planar shape of the mesa M. FIG.
반사전극들(30)은 반사층(28)을 포함하며, 나아가 장벽층(29)을 포함할 수 있다. 장벽층(29)은 반사층(28)의 상면 및 측면을 덮을 수 있다. 예컨대, 반사층(28)의 패턴을 형성하고, 그 위에 장벽층(29)을 형성함으로써, 장벽층(29)이 반사층(28)의 상면 및 측면을 덮도록 형성될 수 있다. 예를 들어, 반사층(28)은 Ag, Ag 합금, Ni/Ag, NiZn/Ag, TiO/Ag층을 증착 및 패터닝하여 형성될 수 있다. 한편, 장벽층(29)은 Ni, Cr, Ti, Pt, Rd, Ru, W, Mo, TiW 또는 그 복합층으로 형성될 수 있으며, 반사층의 금속 물질이 확산되거나 오염되는 것을 방지한다.The reflective electrodes 30 may include a reflective layer 28 and may further include a barrier layer 29. The barrier layer 29 may cover the top and side surfaces of the reflective layer 28. For example, by forming a pattern of reflective layer 28 and forming barrier layer 29 thereon, barrier layer 29 can be formed to cover the top and side surfaces of reflective layer 28. For example, the reflective layer 28 may be formed by depositing and patterning an Ag, Ag alloy, Ni / Ag, NiZn / Ag, TiO / Ag layer. Meanwhile, the barrier layer 29 may be formed of Ni, Cr, Ti, Pt, Rd, Ru, W, Mo, TiW, or a composite layer thereof to prevent the metal material of the reflective layer from being diffused or contaminated.
복수의 메사들(M)이 형성된 후, 제1 도전형 반도체층(23)의 가장자리 또한 식각될 수 있다. 이에 따라, 기판(21)의 상부면이 노출될 수 있다. 제1 도전형 반도체층(23)의 측면 또한 경사지게 형성될 수 있다.After the plurality of mesas M are formed, an edge of the first conductivity type semiconductor layer 23 may also be etched. Accordingly, the upper surface of the substrate 21 may be exposed. Side surfaces of the first conductivity-type semiconductor layer 23 may also be formed to be inclined.
복수의 메사들(M)은 도 8에 도시한 바와 같이 제1 도전형 반도체층(23)의 상부 영역 내부에 한정되어 위치하도록 형성될 수 있다. 즉, 복수의 메사들(M)이 제1 도전형 반도체층(23)의 상부 영역 상에 아일랜드 형태로 위치할 수 있다. 이와 달리, 도 13에 도시한 바와 같이, 일측방향으로 연장하는 메사들(M)은 제1 도전형 반도체층(23)의 상부 가장자리에 도달하도록 형성될 수 있다. 즉, 복수의 메사들(M) 하부면의 일측방향 가장자리는 제1 도전형 반도체층(23)의 일측방향 가장자리와 일치한다. 이에 따라, 제1 도전형 반도체층(23)의 상부면은 복수의 메사들(M)에 의해 구획된다.As illustrated in FIG. 8, the plurality of mesas M may be formed to be located within the upper region of the first conductivity-type semiconductor layer 23. That is, the plurality of mesas M may be located in an island shape on the upper region of the first conductivity type semiconductor layer 23. Alternatively, as shown in FIG. 13, mesas M extending in one direction may be formed to reach the upper edge of the first conductivity-type semiconductor layer 23. That is, one side edge of the bottom surface of the plurality of mesas M coincides with one side edge of the first conductive semiconductor layer 23. Accordingly, the top surface of the first conductivity type semiconductor layer 23 is partitioned by a plurality of mesas M.
도 9를 참조하면, 복수의 메사들(M) 및 제1 도전형 반도체층(23)을 덮는 하부 절연층(31)이 형성된다. 하부 절연층(31)은 특정 영역에서 제1 도전형 반도체층(23) 및 제2 도전형 반도체층(27)에 전기적 접속을 허용하기 위한 개구부들(31a, 31b)을 갖는다. 예컨대, 하부 절연층(31)은 제1 도전형 반도체층(23)을 노출시키는 개구부들(31a)과 반사전극들(30)을 노출시키는 개구부들(31b)을 가질 수 있다.Referring to FIG. 9, a lower insulating layer 31 covering the plurality of mesas M and the first conductive semiconductor layer 23 is formed. The lower insulating layer 31 has openings 31a and 31b to allow electrical connection to the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27 in a specific region. For example, the lower insulating layer 31 may have openings 31a exposing the first conductivity type semiconductor layer 23 and openings 31b exposing the reflective electrodes 30.
개구부들(31a)은 메사들(M) 사이의 영역 및 기판(21) 가장자리 근처에 위치할 수 있으며, 메사들(M)을 따라 연장하는 기다란 형상을 가질 수 있다. 한편, 개구부들(31b)은 메사(M) 상부에 한정되어 위치하며, 메사들의 동일 단부 측에 치우쳐 위치한다.The openings 31a may be positioned near the edge between the mesas M and the edge of the substrate 21, and may have an elongated shape extending along the mesas M. On the other hand, the openings 31b are limited to the upper portion of the mesa (M), and are located on the same end side of the mesas.
하부 절연층(31)은 화학기상증착(CVD) 등의 기술을 사용하여 SiO2 등의 산화막, SiNx 등의 질화막, SiON, MgF2의 절연막으로 형성될 수 있다. 하부 절연층(31)은 단일층으로 형성될 수 있으나, 이에 한정되는 것은 아니며 다중층으로 형성될 수도 있다. 나아가, 하부 절연층(31)은 저굴절 물질층과 고굴절 물질층이 교대로 적층된 분포 브래그 반사기(DBR)로 형성될 수 있다. 예컨대, SiO2/TiO2나 SiO2/Nb2O5 등의 유전층을 적층함으로써 반사율이 높은 절연 반사층을 형성할 수 있다.The lower insulating layer 31 may be formed of an oxide film such as SiO 2 , a nitride film such as SiN x, or an insulating film of SiON or MgF 2 using a technique such as chemical vapor deposition (CVD). The lower insulating layer 31 may be formed of a single layer, but is not limited thereto and may be formed of multiple layers. Further, the lower insulating layer 31 may be formed of a distributed Bragg reflector (DBR) in which a low refractive material layer and a high refractive material layer are alternately stacked. For example, an insulating reflective layer having a high reflectance can be formed by laminating dielectric layers such as SiO 2 / TiO 2 or SiO 2 / Nb 2 O 5 .
도 10을 참조하면, 하부 절연층(31) 상에 전류 분산층(33)이 형성된다. 전류 분산층(33)은 복수의 메사들(M) 및 제1 도전형 반도체층(23)을 덮는다. 또한, 전류 분산층(33)은 각각의 메사(M) 상부 영역 내에 위치하고 반사 전극들을 노출시키는 개구부들(33a)을 갖는다. 전류 분산층(33)은 하부 절연층(31)의 개구부들(31a)을 통해 제1 도전형 반도체층(23)에 오믹콘택할 수 있다. 전류 분산층(33)은 하부 절연층(31)에 의해 복수의 메사들(M) 및 반사 전극들(30)로부터 절연된다.Referring to FIG. 10, a current spreading layer 33 is formed on the lower insulating layer 31. The current spreading layer 33 covers the plurality of mesas M and the first conductive semiconductor layer 23. In addition, the current spreading layer 33 has openings 33a located in the upper region of each mesa M to expose the reflective electrodes. The current spreading layer 33 may be in ohmic contact with the first conductivity type semiconductor layer 23 through the openings 31a of the lower insulating layer 31. The current spreading layer 33 is insulated from the plurality of mesas M and the reflective electrodes 30 by the lower insulating layer 31.
전류 분산층(33)의 개구부들(33a)은 전류 분산층(33)이 반사 전극들(30)에 접속하는 것을 방지하도록 각각 하부 절연층(31)의 개구부들(31b)보다 더 넓은 면적을 갖는다. 따라서, 개구부들(33a)의 측벽은 하부 절연층(31) 상에 위치한다.The openings 33a of the current spreading layer 33 have a larger area than the openings 31b of the lower insulating layer 31, respectively, to prevent the current spreading layer 33 from connecting to the reflective electrodes 30. Have Thus, sidewalls of the openings 33a are located on the lower insulating layer 31.
전류 분산층(33)은 개구부들(33a)을 제외한 기판(31)의 거의 전 영역 상부에 형성된다. 따라서, 전류 분산층(33)을 통해 전류가 쉽게 분산될 수 있다. 전류 분산층(33)은 Al층과 같은 고반사 금속층을 포함할 수 있으며, 고반사 금속층은 Ti, Cr 또는 Ni 등의 접착층 상에 형성될 수 있다. 또한, 고반사 금속층 상에 Ni, Cr, Au 등의 단층 또는 복합층 구조의 보호층이 형성될 수 있다. 전류 분산층(33)은 예컨대, Ti/Al/Ti/Ni/Au의 다층 구조를 가질 수 있다. The current spreading layer 33 is formed over almost the entire area of the substrate 31 except for the openings 33a. Thus, current can be easily dispersed through the current spreading layer 33. The current spreading layer 33 may include a high reflective metal layer such as an Al layer, and the high reflective metal layer may be formed on an adhesive layer such as Ti, Cr, or Ni. In addition, a protective layer of a single layer or a composite layer structure such as Ni, Cr, Au, or the like may be formed on the highly reflective metal layer. The current spreading layer 33 may have, for example, a multilayer structure of Ti / Al / Ti / Ni / Au.
도 11을 참조하면, 전류 분산층(33) 상에 상부 절연층(35)이 형성된다. 상부 절연층(35)은 전류 분산층(33)을 노출시키는 개구부(35a)와 함께, 반사 전극들(30)을 노출시키는 개구부들(35b)을 갖는다. 개구부(35a)는 메사(M)의 길이 방향에 수직한 방향으로 기다란 형상을 가질 수 있으며, 개구부들(35b)에 비해 상대적으로 넓은 면적을 갖는다. 개구부들(35b)은 전류 분산층(33)의 개구부들(33a) 및 하부 절연층(31)의 개구부들(31b)을 통해 노출된 반사 전극들(30)을 노출시킨다. 개구부들(35b)은 전류 분산층(33)의 개구부들(33a)에 비해 더 좁은 면적을 갖고, 한편, 하부 절연층(31)의 개구부들(31b)보다 넓은 면적을 가질 수 있다. 이에 따라, 전류 분산층(33)의 개구부들(33a)의 측벽들은 상부 절연층(35)에 의해 덮일 수 있다.Referring to FIG. 11, an upper insulating layer 35 is formed on the current spreading layer 33. The upper insulating layer 35 has openings 35b exposing the current spreading layer 33 and openings 35b exposing the reflective electrodes 30. The opening 35a may have an elongated shape in a direction perpendicular to the longitudinal direction of the mesa M, and has a relatively large area compared to the openings 35b. The openings 35b expose the reflective electrodes 30 exposed through the openings 33a of the current spreading layer 33 and the openings 31b of the lower insulating layer 31. The openings 35b may have a smaller area than the openings 33a of the current spreading layer 33, and may have a larger area than the openings 31b of the lower insulating layer 31. Accordingly, sidewalls of the openings 33a of the current spreading layer 33 may be covered by the upper insulating layer 35.
상부 절연층(35)은 산화물 절연층, 질화물 절연층, 이들 절연층의 혼합층 또는 교차층, 또는 폴리이미드, 테플론, 파릴렌 등의 폴리머를 이용하여 형성될 수 있다.The upper insulating layer 35 may be formed using an oxide insulating layer, a nitride insulating layer, a mixed layer or a cross layer of these insulating layers, or a polymer such as polyimide, teflon, parylene, or the like.
도 12를 참조하면, 상부 절연층(35) 상에 제1 패드(37a) 및 제2 패드(37b)가 형성된다. 제1 패드(37a)는 상부 절연층(35)의 개구부(35a)를 통해 전류 분산층(33)에 접속하고, 제2 패드(37b)는 상부 절연층(35)의 개구부들(35b)을 통해 반사 전극들(30)에 접속한다. 제1 패드(37a) 및 제2 패드(37b)는 발광 다이오드를 서브마운트, 패키지 또는 인쇄회로보드 등에 실장하기 위해 범프를 접속하거나 SMT를 위한 패드로 사용될 수 있다.Referring to FIG. 12, a first pad 37a and a second pad 37b are formed on the upper insulating layer 35. The first pad 37a connects to the current spreading layer 33 through the opening 35a of the upper insulating layer 35, and the second pad 37b connects the openings 35b of the upper insulating layer 35. It is connected to the reflective electrodes 30 through. The first pad 37a and the second pad 37b may be connected to bumps or used as pads for SMT to mount the light emitting diode to a submount, package, or printed circuit board.
제1 및 제2 패드(37a, 37b)는 동일 공정으로 함께 형성될 수 있으며, 예컨대 사진 및 식각 기술 또는 리프트 오프 기술을 사용하여 형성될 수 있다. 제1 및 제2 패드(37a, 37b)는 예컨대 Ti, Cr, Ni 등의 접착층과 Al, Cu, Ag 또는 Au 등의 고전도 금속층을 포함할 수 있다. 제1 및 제2 패드(37a, 37b)는 끝 단부가 동일 평면상에 위치하도록 형성될 수 있으며, 따라서 발광 다이오드 칩(220)이 회로기판(100a 내지 100d) 상에 동일한 높이로 형성된 도전 패턴 상에 플립 본딩될 수 있다.The first and second pads 37a and 37b may be formed together in the same process, for example using photo and etching techniques or lift off techniques. The first and second pads 37a and 37b may include, for example, an adhesive layer such as Ti, Cr, or Ni, and a highly conductive metal layer such as Al, Cu, Ag, or Au. The first and second pads 37a and 37b may be formed so that the end ends thereof are coplanar, and thus the light emitting diode chip 220 may be formed on the conductive patterns having the same height on the circuit boards 100a to 100d. Can be flip bonded to.
그 후, 성장 기판(21)을 개별 발광 다이오드 칩 단위로 분할함으로써 발광 다이오드 칩이 완성된다. 성장 기판(21)은 개별 발광 다이오드 칩 단위로 분할되기 전 또는 후에 발광 다이오드 칩에서 제거될 수도 있다.Thereafter, the growth substrate 21 is divided into individual light emitting diode chip units to complete the light emitting diode chip. The growth substrate 21 may be removed from the LED chip before or after it is divided into individual LED chip units.
이하, 본 발명의 일 실시예에 따른 발광 다이오드 칩의 구조에 대해 도 12를 참조하여 상세히 설명한다.Hereinafter, a structure of a light emitting diode chip according to an embodiment of the present invention will be described in detail with reference to FIG. 12.
발광 다이오드 칩은, 제1 도전형 반도체층(23), 메사들(M), 반사 전극들(30), 전류 분산층(33)을 포함하며, 성장 기판(21), 하부 절연층(31), 상부 절연층(35) 및 제1 패드(37a)와 제2 패드(37b)를 포함할 수 있다.The light emitting diode chip includes a first conductive semiconductor layer 23, mesas M, reflective electrodes 30, and a current spreading layer 33, and includes a growth substrate 21 and a lower insulating layer 31. The upper insulating layer 35 may include a first pad 37a and a second pad 37b.
기판(21)은 질화갈륨계 에피층들을 성장시키기 위한 성장기판, 예컨대 사파이어, 탄화실리콘, 실리콘, 질화갈륨 기판일 수 있다. 상기 기판(21)은 예컨대 사파이어 기판으로, 200um 이상의 두께, 바람직하게 250um 이상의 두께를 가질 수 있다.The substrate 21 may be a growth substrate for growing gallium nitride-based epi layers, such as sapphire, silicon carbide, silicon, or gallium nitride substrate. The substrate 21 is, for example, a sapphire substrate, it may have a thickness of 200um or more, preferably 250um or more.
제1 도전형 반도체층(23)은 연속적이며, 제1 도전형 반도체층(23) 상에 복수의 메사들(M)이 서로 이격되어 위치한다. 메사들(M)은 도 8을 참조하여 설명한 바와 같이 활성층(25) 및 제2 도전형 반도체층(27)을 포함하며, 일측을 향해 연장하는 기다란 형상을 갖는다. 여기서 메사들(M)은 질화갈륨계 화합물 반도체의 적층 구조이다. 메사들(M)은, 도 8에 도시한 바와 같이, 제1 도전형 반도체층(23)의 상부 영역 내에 한정되어 위치할 수 있다. 이와 달리, 메사들(M)은, 도 6에 도시한 바와 같이, 일측방향을 따라 제1 도전형 반도체층(23)의 상부면 가장자리까지 연장할 수 있으며, 따라서 제1 도전형 반도체층(23)의 상부면을 복수의 영역으로 구획할 수 있다. 이에 따라, 메사들(M)의 모서리 근처에 전류가 집중되는 것을 완화하여 전류 분산 성능을 더 강화할 수 있다.The first conductive semiconductor layer 23 is continuous, and the plurality of mesas M are spaced apart from each other on the first conductive semiconductor layer 23. The mesas M include the active layer 25 and the second conductivity-type semiconductor layer 27 as described with reference to FIG. 8 and have an elongated shape extending toward one side. The mesas M may be a stacked structure of a gallium nitride compound semiconductor. The mesas M may be limitedly positioned in an upper region of the first conductivity-type semiconductor layer 23, as shown in FIG. 8. In contrast, the mesas M may extend to one edge of the upper surface of the first conductivity-type semiconductor layer 23 in one direction, as shown in FIG. 6, and thus the first conductivity-type semiconductor layer 23. The upper surface of the can be divided into a plurality of areas. Accordingly, it is possible to alleviate the concentration of the current near the edge of the mesas (M) to further enhance the current distribution performance.
반사 전극들(30)은 각각 복수의 메사들(M) 상에 위치하여 제2 도전형 반도체층(27)에 오믹 콘택한다. 반사 전극들(300은 도 8을 참조하여 설명한 바와 같이 반사층(28)과 장벽층(29)을 포함할 수 있으며, 장벽층(29)이 반사층(28)의 상면 및 측면을 덮을 수 있다.The reflective electrodes 30 are respectively positioned on the plurality of mesas M to make ohmic contact with the second conductivity-type semiconductor layer 27. As described with reference to FIG. 8, the reflective electrodes 300 may include a reflective layer 28 and a barrier layer 29, and the barrier layer 29 may cover the top and side surfaces of the reflective layer 28.
전류 분산층(33)은 복수의 메사들(M) 및 제1 도전형 반도체층(23)을 덮는다. 전류 분산층(33)은 각각의 메사(M) 상부 영역 내에 위치하고 반사 전극들(30)을 노출시키는 개구부들(33a)을 갖는다. 전류 분산층(33)은 또한, 제1 도전형 반도체층(23)에 오믹콘택하고 복수의 메사들(M)로부터 절연된다. 전류 분산층(33)은 Al과 같은 반사 금속을 포함할 수 있다.The current spreading layer 33 covers the plurality of mesas M and the first conductive semiconductor layer 23. The current spreading layer 33 has openings 33a located in the upper region of each mesa M and exposing the reflective electrodes 30. The current spreading layer 33 is also ohmic contacted to the first conductivity type semiconductor layer 23 and insulated from the plurality of mesas M. FIG. The current spreading layer 33 may include a reflective metal such as Al.
전류 분산층(33)은 하부 절연층(31)에 의해 복수의 메사들(M)로부터 절연될 수 있다. 예컨대, 하부 절연층(31)은 복수의 메사들(M)과 전류 분산층(33) 사이에 위치하여 전류 분산층(33)을 복수의 메사들(M)로부터 절연시킬 수 있다. 또한, 하부 절연층(31)은 각각의 메사(M) 상부 영역 내에 위치하고 반사 전극들(30)을 노출시키는 개구부들(31b)을 가질 수 있으며, 제1 도전형 반도체층(23)을 노출시키는 개구부들(31a)을 가질 수 있다. 전류 분산층(33)은 개구부들(31a)을 통해 제1 도전형 반도체층(23)에 접속할 수 있다. 하부 절연층(31)의 개구부들(31b)은 전류 분산층(33)의 개구부들(33a)보다 좁은 면적을 가지며, 개구부들(33a)에 의해 모두 노출된다.The current spreading layer 33 may be insulated from the plurality of mesas M by the lower insulating layer 31. For example, the lower insulating layer 31 may be positioned between the plurality of mesas M and the current spreading layer 33 to insulate the current spreading layer 33 from the plurality of mesas M. FIG. In addition, the lower insulating layer 31 may have openings 31b disposed in the upper region of each mesa M to expose the reflective electrodes 30, and may expose the first conductivity-type semiconductor layer 23. It may have openings 31a. The current spreading layer 33 may be connected to the first conductivity type semiconductor layer 23 through the openings 31a. The openings 31b of the lower insulating layer 31 have a smaller area than the openings 33a of the current spreading layer 33 and are all exposed by the openings 33a.
상부 절연층(35)은 전류분산층(33)의 적어도 일부를 덮는다. 또한, 상부 절연층(35)은 반사 전극들(30)을 노출시키는 개구부들(35b)을 갖는다. 나아가, 상부 절연층(35)은 전류 분산층(33)을 노출시키는 개구부(35a)를 가질 수 있다. 상부 절연층(35)은 전류 분산층(33)의 개구부들(33a)의 측벽들을 덮을 수 있다.The upper insulating layer 35 covers at least a portion of the current spreading layer 33. In addition, the upper insulating layer 35 has openings 35b exposing the reflective electrodes 30. Furthermore, the upper insulating layer 35 may have an opening 35a exposing the current spreading layer 33. The upper insulating layer 35 may cover sidewalls of the openings 33a of the current spreading layer 33.
제1 패드(37a)는 전류 분산층(33) 상에 위치할 수 있으며, 예컨대 상부 절연층(35)의 개구부(35a)를 통해 전류 분산층(33)에 접속할 수 있다. 또한, 제2 패드(37b)는 개구부들(35b)을 통해 노출된 반사전극들(30)에 접속한다. 제1 패드(37a) 및 제2 패드(37b)는 도 12에 도시한 바와 같이, 상단부가 동일 높이에 위치할 수 있다.The first pad 37a may be positioned on the current spreading layer 33, and may be connected to the current spreading layer 33 through, for example, an opening 35a of the upper insulating layer 35. In addition, the second pad 37b is connected to the reflective electrodes 30 exposed through the openings 35b. As illustrated in FIG. 12, the first pad 37a and the second pad 37b may have upper ends disposed at the same height.
본 발명에 따르면, 전류 분산층(33)이 메사들(M) 및 메사들(M) 사이의 제1 도전형 반도체층(23)의 거의 전 영역을 덮는다. 따라서, 전류 분산층(33)을 통해 전류가 쉽게 분산될 수 있다.According to the present invention, the current spreading layer 33 covers almost the entire area of the mesas M and the first conductivity type semiconductor layer 23 between the mesas M. Thus, current can be easily dispersed through the current spreading layer 33.
나아가, 전류 분산층(23)이 Al과 같은 반사 금속층을 포함하거나, 하부 절연층을 절연 반사층으로 형성함으로써 반사 전극들(30)에 의해 반사되지 않는 광을 전류 분산층(23) 또는 하부 절연층(31)을 이용하여 반사시킬 수 있어 광 추출 효율을 향상시킬 수 있다.Furthermore, the current spreading layer 23 includes a reflecting metal layer such as Al, or the lower insulating layer is formed as an insulating reflecting layer so that the light not reflected by the reflecting electrodes 30 is reflected by the current spreading layer 23 or the lower insulating layer. (31) can be used to reflect, thereby improving light extraction efficiency.
본 실시예에 따른 플립칩형 발광 다이오드 칩은 상대적으로 넓은 지향분포를 가질 수 있다.The flip chip light emitting diode chip according to the present embodiment may have a relatively wide directivity distribution.
도 14는 종래의 발광 다이오드 패키지(200) 및 본원의 일 실시예에 따른 컨포멀 코팅층(220)을 갖는 플립칩형 발광 다이오드 칩(240)의 지향 분포를 나타내는 그래프이다. 14 is a graph illustrating a direct distribution of a flip chip type light emitting diode chip 240 having a conventional light emitting diode package 200 and a conformal coating layer 220 according to an embodiment of the present disclosure.
도 14(a)를 참조하면, 종래의 발광 다이오드 패키지(200)는 X방향 및 Y방향에 대해 대체로 동일한 지향각으로서 약 120도의 지향각을 갖는다. 한편, 본원의 플립칩형 발광 다이오드 칩(240)은 X방향 및 Y방향에 대해 대체로 동일한 약 140도의 지향각을 나타내며, 컨포멀 코팅층을 적용할 경우, 도 14(b)에 나타나듯이 140~150도의 지향각을 나타낸다.Referring to FIG. 14A, the conventional LED package 200 has a directing angle of about 120 degrees as a substantially same directing angle with respect to the X and Y directions. On the other hand, the flip-chip type light emitting diode chip 240 of the present application exhibits a direction angle of about 140 degrees which is substantially the same with respect to the X direction and the Y direction, and when the conformal coating layer is applied, as shown in FIG. Indicates the orientation angle.
도 15(a)는 120도의 지향각을 갖는 종래의 발광 다이오드 패키지를 사용한 발광 모듈의 지향 분포를 나타내고, 도 15(b)는 본원의 145도의 지향각을 갖는 컨포멀 코팅층(220)이 코팅된 플립칩형 발광 다이오드 칩(240)을 사용한 발광 모듈의 지향 분포를 나타낸다. 여기서, 각 방향으로 조도 분포가 동일한 발광 소자와 렌즈를 사용하여 일축 방향의 광 지향 분포를 시뮬레이션하였다. 광 지향 분포는 각 발광 소자로부터 5m 이격된 지점에서의 지향각에 따른 광도를 나타낸 것이다.Figure 15 (a) shows the directivity distribution of the light emitting module using a conventional light emitting diode package having a directivity angle of 120 degrees, Figure 15 (b) is coated with a conformal coating layer 220 having a directivity angle of 145 degrees of the present application The directivity distribution of the light emitting module using the flip chip light emitting diode chip 240 is shown. Here, the light directivity distribution in the uniaxial direction was simulated using a light emitting element and a lens having the same illuminance distribution in each direction. The light directivity distribution shows the luminous intensity according to the directivity angle at a point 5 m away from each light emitting element.
이 그래프에서 최대 광도값 사이의 각도가 클수록, 그리고 최대 광도값에 대한 중심에서의 광도의 비율(C/P)이 작을수록, 광이 더 넓고 균일하게 분산된다. 도 15 (a)의 경우, 최대 광도값 사이의 각도는 146도이고, 최대 광도에 대한 중심에서의 광도의 비율은 10%이며, 도 15 (b)의 경우, 이들 값들은 각각 152도 및 4.5%이었다. 따라서, 본원의 컨포멀 코팅층(220)이 형성된 플립칩형 발광 다이오드 칩(240)을 사용하여 발광 모듈을 제작할 경우, 종래의 발광 모듈에 비해 더 넓고 균일하게 광을 분산시킬 수 있다.In this graph, the greater the angle between the maximum luminous intensity values, and the smaller the ratio of luminous intensity at the center to the maximum luminous intensity value (C / P), the wider and more uniformly the light is distributed. In the case of Fig. 15 (a), the angle between the maximum luminous intensity values is 146 degrees, and the ratio of the luminous intensity at the center to the maximum luminous intensity is 10%, and in Fig. 15 (b) these values are 152 degrees and 4.5, respectively. It was%. Therefore, when the light emitting module is manufactured using the flip chip type light emitting diode chip 240 in which the conformal coating layer 220 of the present application is formed, light can be dispersed more widely and uniformly than the conventional light emitting module.
도 16은 회로 기판 상에 4×4 행렬로 16개의 발광 소자를 배열하고 각 발광 소자에 렌즈를 결합한 발광 모듈의 조도 분포를 나타낸 것으로 (a)는 종래의 120도 지향각을 갖는 발광 다이오드 패키지 (b)는 본원에 따른 컨포멀 코팅층(220)이 적용된 플립칩형 발광 다이오드 칩(240)을 배열한 발광 모듈의 조도 분포를 나타낸다. 광원들 사이의 간격은 100mm이고, 조도 분포 측정 거리는 23mm로 하여 시뮬레이션을 하였다.FIG. 16 illustrates an illuminance distribution of a light emitting module in which 16 light emitting devices are arranged in a 4 × 4 matrix on a circuit board and a lens is coupled to each light emitting device. b) shows the illuminance distribution of the light emitting module in which the flip chip type light emitting diode chip 240 to which the conformal coating layer 220 is applied is arranged. The distance between the light sources was 100 mm and the illuminance distribution measurement distance was 23 mm.
도 16(a)의 경우, 광 균일도는 79.4%이었고, 도 16(b)의 경우 광 균일도는 84.6%이었으며, 도 16(a) 및 (b)를 육안으로 비교해도, 도 16(b)의 경우 바깥쪽의 광 확산성이 도 16(a)의 경우에 비해 더 우수한 것을 알 수 있다.In the case of FIG. 16 (a), the light uniformity was 79.4%, and in FIG. 16 (b), the light uniformity was 84.6%. Even when comparing FIGS. 16 (a) and (b) with the naked eye, FIG. In this case, it can be seen that the light diffusivity of the outside is superior to that of FIG.
이상에서 다양한 실시예들에 대해 설명하였지만, 본 발명은 특정 실시예에 한정되는 것은 아니다. 또한 특정 실시예에서 설명한 구성요소는 본원 발명의 사상을 벗어나지 않는 한 다른 실시예에서 동일하거나 유사하게 적용될 수 있다.Although various embodiments have been described above, the present invention is not limited to the specific embodiments. In addition, the components described in a specific embodiment may be applied to the same or similar in other embodiments without departing from the spirit of the present invention.
Claims (22)
- 회로 기판;A circuit board;상기 회로 기판에 플립 본딩된 발광 소자; 및A light emitting device flip-bonded to the circuit board; And상기 회로 기판에 결합되고, 상기 발광 소자에서 방출된 광을 분산시키는 렌즈를 포함하고,A lens coupled to the circuit board, the lens dispersing light emitted from the light emitting element;상기 발광 소자는 플립칩형 발광 다이오드 칩; 및The light emitting device includes a flip chip light emitting diode chip; And상기 발광 다이오드 칩에 코팅된 파장변환층을 포함하는 발광 모듈.Light emitting module comprising a wavelength conversion layer coated on the light emitting diode chip.
- 청구항 1에 있어서,The method according to claim 1,상기 파장변환층은 상기 발광 다이오드 칩의 상면 및 측면을 덮는 발광 모듈.The wavelength conversion layer covers a top surface and a side surface of the light emitting diode chip.
- 청구항 1에 있어서,The method according to claim 1,상기 회로 기판은 상면에 돌출부를 갖고,The circuit board has a protrusion on the upper surface,상기 렌즈는 상기 돌출부를 수용하는 수용홈을 가지며,The lens has a receiving groove for receiving the protrusion,상기 렌즈는 상기 수용홈이 상기 돌출부를 수용하여 상기 회로 기판에 결합된 발광 모듈.The lens is a light emitting module in which the receiving groove is coupled to the circuit board by receiving the protrusion.
- 청구항 1에 있어서,The method according to claim 1,상기 회로 기판 상에 형성된 댐부를 더 포함하고,Further comprising a dam formed on the circuit board,상기 렌즈는 댐부를 수용하는 수용홈을 가지며,The lens has a receiving groove for receiving the dam,상기 렌즈는 상기 수용홈이 상기 댐부를 수용하여 상기 회로 기판에 결합된 발광 모듈.The lens is a light emitting module, the receiving groove is coupled to the circuit board by receiving the dam.
- 청구항 4에 있어서,The method according to claim 4,상기 댐부는 실리콘 수지 또는 광학 시트로 형성된 발광 모듈.The dam unit is a light emitting module formed of a silicone resin or an optical sheet.
- 청구항 1에 있어서,The method according to claim 1,상기 회로 기판 상에 부착되고 상기 발광 소자를 노출시키는 개구부를 갖는 광학 시트를 더 포함하고,An optical sheet attached to the circuit board and having an opening for exposing the light emitting element;상기 렌즈는 상기 광학 시트의 개구부에 끼워져 상기 회로 기판에 결합된 발광 모듈.And the lens is coupled to the circuit board by being inserted into the opening of the optical sheet.
- 청구항 1에 있어서,The method according to claim 1,상기 회로 기판은 리세스를 포함하고,The circuit board comprises a recess,상기 렌즈는 상기 리세스에 끼워져 상기 회로 기판에 결합된 발광 모듈.Wherein the lens is fitted into the recess and coupled to the circuit board.
- 청구항 1에 있어서,The method according to claim 1,상기 발광 소자를 덮는 투명 수지를 더 포함하는 발광 모듈.The light emitting module further comprises a transparent resin covering the light emitting element.
- 청구항 1 내지 8의 어느 한 항에 있어서,The method according to any one of claims 1 to 8,상기 렌즈는 상기 발광 소자로부터 방출된 광이 입사되는 입사면과 입사된 입사광이 출사되는 출사면을 갖는 발광 모듈.The lens has a light emitting module having an incident surface on which light emitted from the light emitting element is incident and an exit surface on which incident light is emitted.
- 청구항 9에 있어서,The method according to claim 9,상기 입사면은 상기 렌즈의 하부면에 위치하는 오목부 내부면인 발광 모듈.The incident surface is a light emitting module inner surface of the recess located on the lower surface of the lens.
- 청구항 10에 있어서,The method according to claim 10,상기 오목부는 제1 오목부 및 상기 제1 오목부의 입구측에 위치하여 상기 제1 오목부를 둘러싸는 제2 오목부를 포함하는 발광 모듈.The concave portion includes a first concave portion and a second concave portion positioned at an inlet side of the first concave portion and enclosing the first concave portion.
- 청구항 1 내지 8의 어느 한 항에 있어서,The method according to any one of claims 1 to 8,상기 발광 다이오드 칩은,The light emitting diode chip,제1 도전형 반도체층;A first conductivity type semiconductor layer;상기 제1 도전형 반도체층 상에 서로 이격되어 배치되고, 각각 활성층 및 제2 도전형 반도체층을 포함하는 복수의 메사들;A plurality of mesas spaced apart from each other on the first conductive semiconductor layer, each of the mesas including an active layer and a second conductive semiconductor layer;각각 상기 복수의 메사들 상에 위치하여 제2 도전형 반도체층에 오믹 콘택하는 반사 전극들; 및Reflective electrodes positioned on the plurality of mesas, respectively, for ohmic contact with a second conductivity-type semiconductor layer; And상기 복수의 메사들 및 상기 제1 도전형 반도체층을 덮되, 상기 각각의 메사 상부 영역 내에 위치하고 상기 반사 전극들을 노출시키는 개구부들을 가지며, 상기 제1 도전형 반도체층에 오믹콘택하고 상기 복수의 메사들로부터 절연된 전류 분산층을 포함하고,Covering the plurality of mesas and the first conductivity type semiconductor layer, the openings being located in the upper region of each mesa and exposing the reflective electrodes, ohmic contacting the first conductivity type semiconductor layer, and the plurality of mesas. A current spreading layer insulated from the상기 발광 다이오드 칩은 상기 회로 기판 상에 플립 본딩되어 있는 발광 모듈.And the light emitting diode chip is flip bonded to the circuit board.
- 청구항 12에 있어서,The method according to claim 12,상기 복수의 메사들은 일측 방향으로 서로 평행하게 연장하는 기다란 형상을 갖고, 상기 전류 분산층의 개구부들은 상기 복수의 메사들의 동일 단부측에 치우쳐 위치하는 발광 모듈.The plurality of mesas have an elongated shape extending in parallel to each other in one direction, the opening of the current dispersion layer is located on the same end side of the plurality of mesas.
- 청구항 12에 있어서,The method according to claim 12,상기 전류 분산층은 반사 금속을 포함하는 발광 모듈.The current dispersion layer is a light emitting module comprising a reflective metal.
- 청구항 12에 있어서,The method according to claim 12,상기 반사 전극들은 각각 반사 금속층과 장벽 금속층을 포함하되, 상기 장벽 금속층이 상기 반사 금속층의 상면 및 측면을 덮는 발광 모듈.Each of the reflective electrodes includes a reflective metal layer and a barrier metal layer, wherein the barrier metal layer covers the top and side surfaces of the reflective metal layer.
- 청구항 12에 있어서,The method according to claim 12,상기 전류분산층의 적어도 일부를 덮되, 상기 반사 전극들을 노출시키는 개구부들을 갖는 상부 절연층; 및An upper insulating layer covering at least a portion of the current spreading layer and having openings exposing the reflective electrodes; And상기 상부 절연층 상에 위치하고 상기 상부 절연층의 개구부들을 통해 노출된 반사 전극들에 접속하는 제2 패드를 더 포함하는 발광 모듈.And a second pad disposed on the upper insulating layer and connected to the reflective electrodes exposed through the openings of the upper insulating layer.
- 청구항 16에 있어서,The method according to claim 16,상기 전류 분산층에 접속하는 제1 패드를 더 포함하는 발광 모듈.And a first pad connected to the current spreading layer.
- 청구항 12에 있어서,The method according to claim 12,상기 복수의 메사들과 상기 전류 분산층 사이에 위치하여 상기 전류 분산층을 상기 복수의 메사들로부터 절연시키는 하부 절연층을 더 포함하되,A lower insulating layer disposed between the plurality of mesas and the current spreading layer to insulate the current spreading layer from the plurality of mesas,상기 하부 절연층은 상기 각각의 메사 상부 영역 내에 위치하고 상기 반사 전극들을 노출시키는 개구부들을 갖는 발광 모듈.And the lower insulating layer has openings disposed in the respective mesa upper regions and exposing the reflective electrodes.
- 청구항 18에 있어서,The method according to claim 18,상기 전류 분산층의 개구부들은 각각 상기 하부 절연층의 개구부들이 모두 노출되도록 상기 하부 절연층의 개구부들보다 더 넓은 폭을 갖는 발광 모듈.Each of the openings of the current spreading layer has a wider width than the openings of the lower insulating layer such that all of the openings of the lower insulating layer are exposed.
- 청구항 19에 있어서,The method according to claim 19,상기 전류분산층의 적어도 일부를 덮고, 상기 반사 전극들을 노출시키는 개구부들을 갖는 상부 절연층을 더 포함하되,A top insulating layer covering at least a portion of the current spreading layer and having openings exposing the reflective electrodes,상기 상부 절연층은 상기 전류 분산층의 개구부들의 측벽들을 덮는 발광 모듈.The upper insulating layer covers the sidewalls of the openings of the current spreading layer.
- 청구항 18에 있어서,The method according to claim 18,상기 하부 절연층은 반사성 유전층인 발광 모듈.The lower insulating layer is a light emitting module is a reflective dielectric layer.
- 청구항 12에 있어서,The method according to claim 12,상기 발광 다이오드 칩은 성장 기판을 더 포함하고,The light emitting diode chip further includes a growth substrate,상기 파장변환층은 상기 성장 기판을 덮는 발광 모듈.The wavelength conversion layer covers the growth substrate.
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