WO2014025615A1

WO2014025615A1 - Methods for graphene fabrication on patterned catalytic metal

Info

Publication number: WO2014025615A1
Application number: PCT/US2013/053237
Authority: WO
Inventors: Feng Liu
Original assignee: University Of Utah Research Foundation
Priority date: 2012-08-07
Filing date: 2013-08-01
Publication date: 2014-02-13
Also published as: KR20150038579A

Abstract

A method for making thin films from layered materials and band gap devices formed therefrom. One aspect of the present disclosure provides a method for fabricating one or more graphene based nanostructures. The method comprises depositing a catalytic material onto a substrate thereby forming a catalytic material layer on the substrate. The method further comprises nanopatterning the catalytic material layer thereby forming a nanotemplate. Still, the method further comprises depositing graphene onto the nanotemplate thereby forming the one or more graphene based nanostructures.

Description

METHODS FOR GRAPHENE FABRICATION ON PATTERNED CATALYTIC

METAL

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to United States Provisional Application No.

61/680,650, filed August 7, 2012, which is hereby incorporated by reference herein in its entirety.

1. FIELD OF THE DISCLOSURE

[0002] Methods for fabricating thin films and band gap devices formed therefrom are provided. More particularly, methods for fabricating thin films from deposition onto catalytic substrates are provided.

2. BACKGROUND

[0003] A thin layer of a material, typically nanometers thick, can exhibit enhanced properties for various promising applications. A graphene sheet and a thin graphitic layer comprising a plurality of graphene sheets are good examples. Compared to its bulk three-dimensional counterpart, a graphene sheet and a thin graphitic layer have demonstrated many exceptional chemical, mechanical, electronic and optical properties, including high carrier mobility, high Young's elastic modulus, and excellent thermoconductivity. Such materials are well suited for applications in electronic devices, super-strong composite materials, and energy generation and storage.

[0004] Despite their desirable properties, fabrication of such a thin layer is mainly limited to laboratories because of imposing challenges in the development of a simple and cost- effective method that can be scaled up and at the same time can produce controllable and reliable thin layers. These laboratory methods can be broadly classified as epitaxial growth, colloidal suspension, unconventional methods and exfoliation (See, Jayasen and Subbiah, 2011, Nanoscale Research Letter, 6:95). The exfoliation method essentially involves separation of a thin layer from the bulk material. This technique can be further classified into thermal, chemical and mechanical methods. [0005] Mechanical exfoliation methods under development include the use of an ultrasharp single crystal diamond wedge (See, Jayasen and Subbiah, 2011, Nanoscale Research Letter, 6:95), an atomic force microscope (See, Liu et al, 2005, Applied Physics Letters 86, 073104), and adhesive tapes (See, Liu et al., 2010, Applied Physics Letters 96, 201909 and Chang et al, 2010, Applied Physics Letters 97, 211102) to cleave a highly ordered pyrolytic graphite (HOPG) sample. The use of adhesive tapes for mechanical cleavage is the popular method because it is simple and cost-effective. However, using current mechanical exfoliation methods, it is difficult to predict the number of peels required to obtain the desired thickness of the thin layer (See, Jayasen and Subbiah, 2011, Nanoscale Research Letter, 6:95). Microstructure damage, such as stripes and corrugated kinks, have also been observed in the thin layers produced by current mechanical exfoliation methods (See, Liu et al., 2010, Applied Physics Letters, 96, 201909).

[0006] In the last few years, various methods have been developed in an attempt to fabricate graphene based nanostructures, e.g. graphene nanoribbons (GNRs) and graphene

nanonetworks (GNNs) or graphene nanohole superlattices, while achieving desired size, specified geometries, and characterized electronic properties of the graphene based nanostructures. These methods include (1) the combination of e-beam lithography and oxygen plasma etching; (2) stripping of graphite that is sonochemically processed; (3) bottom-up chemical synthesis, e.g., by cyclodehydrogenation of l,4-diiodo-2, 3,5,6- tetraphenylbenzene6, or 10,10'-dibromo-9,9'-bianthryl7, polyanthrylene oligomers8 self- assembed on Au(l 11), Ag(l 11) or silica substrates; (4) electrochemical etching of graphene by scanning tunneling microscopy (STM) with high bias potential; (5) catalytic unzipping using metal nanoparticles on graphene; (6) chemical unzipping of carbon nanotubes, e.g., by Ar plasma etching or oxidation; (7) etching with a nanowire mask; and (8) oxidative unzipping and cutting large scale graphene into GNRs.

[0007] In order to obtain adequate band gaps for operation at room temperature, graphene based nanostructure width is required to be within a few nanometers due to the inverse relationship between the band gap and the width of the graphene based nanostructures.

Based on current technology, a width of a few tens of nanometers can be achieved using e- beam lithography from the combination of e-beam lithography and oxygen plasma etching.

While nanostructure widths can be reduced to be within sub- 10 nanometers using fabrication methods 2-7, referenced above, there are many drawbacks to using such methods. For example, the stripping of graphite that is sonochemically processed yields a large distribution of ribbon width, random edge directions, and a percentage yield around 0.5%. Similarly, bottom-up chemical synthesis suffers from difficulties in controlling edge geometry and size. Electrochemical etching of graphene by scanning tunneling microscopy (STM) with high bias potential is expensive and time-consuming. Methods 5 and 6, referenced above, are limited by the availability of carbon nanotubes. Etching with a nanowire mask is hindered by the complexity and difficulty in the positioning of nanowires. In addition, oxidative unzipping and cutting large scale graphene into GNRs (method 8) is limited by a lack of control in the initial cutting position, the direction of cutting, and the spacing between different cuts.

[0008] On the other hand, various methods have attempted to synthesize large-scale graphene sheets. One particular method is characterized by epitaxial growth of graphene on metal substrates. Different metal substrates have been used to grow graphene via chemical vapor deposition (CVD), such as Pt, Ir, Ru, Ni, and Cu. Copper is a particularly attractive substrate due to the success in etching away the substrate, the success in transferring the epitaxial graphene from the cooper, the low solubility of carbon in copper, and the relative low cost of copper.

[0009] Given the above background, there is a need in the art for thin layer fabrication methods that are simple and cost-effective, can be scaled up, and at the same time can produce controllable and reliable thin layers.

3. SUMMARY

[0010] The present disclosure provides methods for making thin films from layered materials and band gap devices formed therefrom. One aspect of the present disclosure provides a method for fabricating one or more graphene based nanostructures. The method comprises depositing a catalytic material onto a substrate thereby forming a catalytic material layer on the substrate. The method further comprises nanopatterning the catalytic material layer thereby forming a nanotemplate. Still, the method further comprises depositing carbon onto the nanotemplate thereby forming the one or more graphene based nanostructures.

[0011] Another aspect of the present disclosure provides another method for fabricating one or more graphene based nanostructures. The method comprises depositing a layer of a catalytic material onto a substrate thereby forming a catalytic material layer on the substrate. The method further comprises depositing a layer of spacer film onto the layer of catalytic material. The spacer film comprises material unsuitable for graphene growth. In addition, the method comprises nanopatterning the spacer film such that a portion of the catalytic material layer is exposed thereby forming a nanotemplate. Still further, the method comprises depositing carbon onto the nanotemplate thereby forming the one or more graphene based nanostructures.

4. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present application and, together with the detailed description, serve to explain the principles and implementations of the application.

[0013] FIG. 1 A provides a flow chart of an exemplary method for forming graphene nanoribbons and graphene nanonetworks on a nanopatterned catalytic metal substrate in accordance with an embodiment of the present disclosure.

[0014] FIG. IB provides a flow chart of another exemplary method for forming graphene nanoribbons and graphene nanonetworks on a nanopatterned catalytic metal substrate in accordance with an embodiment of the present disclosure.

[0015] FIG. 2 A is a detailed graphical representation of an exemplary method for forming graphene nanoribbons and graphene nanonetworks on a nanopatterned catalytic metal substrate with a positive setup in accordance with an embodiment of the present disclosure.

[0016] FIG. 2B is a detailed graphical representation of an exemplary method for forming graphene nanoribbons and graphene nanonetworks on a nanopatterned catalytic metal substrate with a negative setup in accordance with an embodiment of the present disclosure.

[0017] FIG. 3 depicts a two-dimensional view of one layer of a graphene nanoribbon in accordance with the prior art.

[0018] FIG. 4 illustrates an exemplary multiple band gap device that is made using the methods of the present disclosure.

[0019] FIG. 5 illustrates an additional exemplary multiple band gap device that is made in accordance with an aspect of the present disclosure. [0020] FIG. 6 depicts a schematic electrical diagram of a multiple band gap photovoltaic device that is made in accordance with an aspect of the present disclosure.

[0021] FIG. 7 depicts a schematic electrical diagram of a multiple band gap photodetector that is made in accordance with an aspect of the present disclosure.

[0022] FIG. 8 depicts a schematic electrical diagram of a multiple band gap light emitting diode that is made in accordance with an aspect of the present disclosure.

[0023] FIG. 9A-B depicts a schematic top view of a semiconducting nanohole superlattice that is made in accordance with an aspect of the present disclosure.

[0024] FIG. 10 depicts a schematic top view of a multiple band gap device comprising a nanohole superlattice that is made in accordance with an aspect of the present disclosure.

DETAILED DESCRIPTION

[0025] Embodiments of the present application are described in the context of methods for fabricating thin films from layered materials and in the context of thin films made therefrom. In this specification and claims, layered materials can refer to a material comprising a plurality of sheets, with each sheet having a substantially planar structure. The term "thin films" can refer to a thin layer comprising one such sheet; it can also refer to several, several tens, several hundreds or several thousands of such sheets. The thickness of the thin films can range from a nanometer to several micrometers, or to several tens of micrometers. Final thin films produced by the processes disclosed in this application can have a thickness in nanometers, and preferably less than fifty nanometers. The term "substrate" refers to one layer or multiple layers. In some embodiments, a substrate is glass, Si, Si02, SiC, or another material. When referring to multiple layers, the term "substrate" is equivalent to and interchangeable with the term "substrate stack". The term "catalytic material" will refer to any material that is suitable for growing graphene. Examples of catalytic materials are Pt, Ir, Ru, Ni, and Cu.

[0026] Those of ordinary skill in the art will realize that the following detailed description of the present application is illustrative only and is not intended to be in any way limiting. Other embodiments of the present application will readily suggest themselves to such skilled persons having benefit of this disclosure. Reference will now be made in detail to implementations of the present application as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts.

[0027] In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer's specific goals, such as compliance with application- and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.

[0028] Due to its many exceptional chemical, mechanical, electronic and optical properties, thin films, e.g. graphene nanoribbons (GNR) and graphene nanonetworks (G N), are very desirable for use in electronic devices, super-strong composite materials, and energy generation and storage. However, current methods for fabrication of GNRs and GNNs is complicated, expensive, inefficient and highly inconsistent. Thus, there is a need for a method to fabricate GNRs and GNNs in a much more efficient and consistent manner.

[0029] FIG. 1 A provides a flow chart of an exemplary method for forming graphene on a nanopatterned catalytic metal substrate in accordance with an embodiment of the present disclosure. In step 10, a catalytic material is deposited onto a substrate, such as silicon or glass, thereby forming a catalytic material layer on the substrate. As discussed above, the catalytic material can be any metal material, such as Pt, Ir, Ru, Ni, and Cu, as long as the material is conducive to growing or depositing graphene on the surface of the material. In some embodiments, the catalytic material used is not a metal at all, so long as the condition of catalyzing graphene formation on the surface of the material is met. The catalytic layer can be deposited onto the substrate via any standard clean room technology, e.g. sputtering, spin coating, or chemical vapor deposition.

[0030] In step 20, the catalytic material layer is nanopatterned, thereby forming a

nanotemplate. As discussed later and in more detail with regard to Fig. 2A, nanopatterning of the catalytic material layer can be achieved using standard lithography techniques, including depositing a layer of photoresist, nanopatterning by shining light onto the photoresist layer over a mask, and chemical etching exposed areas. It should be noted that any technique that results in the catalytic nanotemplate, e.g. e-beam lithography, can be used for step 20.

[0031] In step 30, graphene is formed on the nanotemplate thereby forming the one or more graphene based nanostructures or thin films for use in band gap devices. While the graphene layer can be deposited using any standard deposition technique, one embodiment of the present disclosure utilizes chemical vapor deposition.

[0032] The method depicted in Fig. 1 A patterns the catalytic material directly. This is referred to as using a "positive" setup. As will be seen with reference to Fig. IB, a method of depositing graphene according to an embodiment of the present disclosure can also be achieved using a "negative" setup. In a "negative" setup, the catalytic material is not patterned directly, but rather an additional layer of material, called a "spacer film," is patterned, exposing catalytic material for graphene deposition. A negative setup can be useful where the catalytic material itself is more difficult to pattern than the spacer film.

[0033] Fig. IB provides a flow chart of another exemplary method for depositing graphene onto nanopattemed catalytic metal substrate in accordance with an embodiment of the present disclosure. As described above, the method depicted in Fig. IB uses a negative setup. Step 40 is analogous to step 10 in Fig. 1A.

[0034] In Fig. IB, step 40 is identical to step 10 of Fig. 1A and therefore will not be further described. In step 50, a layer of spacer film is deposited onto the layer of catalytic material. The spacer film comprises material that is unsuitable for graphene growth or deposition. In one embodiment, the spacer film comprises Au. Gold is effective as a spacer film material because of its inert properties with respect to graphene growth. Like the catalytic material layer, the spacer film layer can be deposited using standard clean room technologies.

[0035] In step 60, the spacer film is nanopattemed such that a portion of the catalytic material layer is exposed thereby forming a nanotemplate. The nanopatteming can be achieved using standard lithography techniques. While the patterned catalytic material is made directly in Fig. 1 A, the pattern of the catalytic material is made indirectly through exposure from etching away of the spacer film.

[0036] In step 70, carbon is deposited onto the exposed catalytic material nanotemplate through standard deposition techniques. Since the spacer film layer comprises material inert with respect to graphene growth, graphene nanostructures are formed on the exposed portions of catalytic nanotemplate as the carbon deposited onto the exposed portions of catalytic nanotemplate.

[0037] FIG. 2A is a detailed graphical representation of an exemplary method for depositing graphene onto nanopatterned catalytic metal substrate with a positive setup in accordance with an embodiment of the present disclosure. Initial step 200 demonstrates a clean substrate 220. In some embodiments, substrate 220 is a material that facilitates deposition of one or more layers of a catalytic material. In one embodiment, substrate 220 is glass. The substrate 220 is typically planar and can be either rigid or flexible. In some embodiments, the substrate 220 is made of aluminosilicate glass, borosilicate glass, dichroic glass,

germanium/semiconductor glass, glass ceramic, silicate/fused silica glass, soda lime glass, quartz glass, chalcogenide/sulphide glass, fluoride glass, a glass-based phenolic, flint glass, or cereated glass. In some embodiments, the substrate 220 is made of a urethane polymer, an acrylic polymer, a fiuoropolymer, polybenzamidazole, polymide, polytetrafluoroethylene, polyetheretherketone, polyamide-imide, glass-based phenolic, polystyrene, cross-linked polystyrene, polyester, polycarbonate, polyethylene, polyethylene, acrylonitrile-butadiene- styrene, polytetrafiuoro-ethylene, polymethacrylate, nylon 6,6, cellulose acetate butyrate, cellulose acetate, rigid vinyl, plasticized vinyl, or polypropylene.

[0038] In step 202, catalytic material layer 230 is deposited onto substrate 220 using, for example, any of the deposition methods described in Section 7 below, in order to form catalytic material layer 230. Catalytic material layer 230 is any material that facilitates graphene growth through deposition. In one embodiment, catalytic material layer 230 is Cu.

[0039] Steps 204-210 represent a detailed implementation, e.g. photolithography, of step 20 from Fig. 1 A. As discussed above, other lithography methods, such as e-beam lithography, can also be used in other embodiments of the present disclosure.

[0040] Step 204 shows a layer of a positive photoresist 240 deposited onto the catalytic material layer 230. Exemplary properties of positive photoresist 240 are described in

Section 8.1 below.

[0041] After the resist layer has been applied, the density of the resist layer 240 is often insufficient to support later processing. Accordingly, in some embodiments of the present disclosure, a bake is used to densify the resist layer and drive off residual solvent. This bake is referred to as a softbake, prebake, or post-apply bake. Examples of such bake processes are described in Section

[0042] After the spacer has been coated with a resist layer, the next step is alignment and exposure of the resist layer. Alignment and exposure is, as the name implies, a two-purpose photomasking step. The first part of the alignment and exposure step is the positioning or alignment of the required image on the material surface. The image is found on a mask. The second part is the encoding of the image in the resist layer from an exposing light or radiation source. In step 206, a light (not shown) is shined onto photoresist layer 240 through the mask (not shown), exposing portions of the catalytic material 230 in accordance with the features of the mask. That is, the mask is made such that the mask itself obstructs light, but the apertures in the mask allows light to shine through. The apertures in the mask are arranged in such a way as to form the nanopattern from which the nanotemplate will be formed. More details on alignment and exposure of a mask are provided in Section 8.3, below.

[0043] After exposure through a mask, the pattern is coded as a latent image in resist as regions of exposed and unexposed resist. In some embodiments, the pattern is optionally developed in the resist by chemical dissolution of the unpolymerized resist regions. There are several methods in which a developer is applied to resist in order to develop the latent image. Such methods include, but are not limited to, immersion, spray development, and puddle development. Details on developing a resist layer are disclosed in Section 8.4, below. In some embodiments of the present disclosure, resist is optionally hard baked after it has been developed. The purpose of the hard bake is to achieve good adhesion of the resist layer to the underlying layer to be patterned. Details on hard baking a resist layer after chemical development are disclosed in Section 8.4, below.

[0044] In step 208, the exposed portions of catalytic material layer 230 are etched away using a plasma etcher. A plasma etcher uses energized ions to chemically dissolve away either exposed or unexposed portions of the resist layer. The etching process can be any etching process that etches away only the exposed catalytic material layer. It is important to note that the etching process should not affect the patterned photoresist layer 240, the portions of catalytic material layer 230 that are directly under and covered by photoresist layer 240, or the substrate 220. Section 8.6, below, provides exemplary etching techniques, including wet etching, plasma etching, ion beam etching, and reactive ion etching. [0045] In step 210, the remaining portions of the photoresist layer 240 are removed by any of a number of residual layer removal techniques. For example, in one embodiment of the present disclosure light (not shown) is once again shined onto photoresist layer 240, but this time without the mask, in order to remove the remaining portions of photoresist layer 240, thereby exposing a patterned catalytic material layer 230. In some embodiments, the resist layer 240 is stripped off with a strong acid such as H2SO4 or an acidoxidant combination, such as H₂S04-Cr₂03, attacking the resist but not the groove to yield the fully patterned structure. Additional residual layer removal techniques that can be applied in step 210 are described in Section 8.7, below.

[0046] Finally, in step 212, carbon is deposited onto the catalytic layer 230 to form graphene nanostructures 250. The graphene can be deposited in a variety of methods, e.g. chemical vapor deposition, some of which are described in Section 7.0 below. For instance, in some embodiments of step 212, chemical vapor deposition as described for example in Section 7.1 below, is used to deposit carbon onto the catalytic layer 230 to form graphene nanostructures 250. In some embodiments of step 212, reduced pressure chemical vapor deposition as described for example in Section 7.2 below, is used to deposit carbon onto the catalytic layer 230 to form graphene nanostructures 250. In some embodiments of step 212, any of the techniques described for example in any of Sections 7.3 through 7.21 below, is used to deposit carbon onto the catalytic layer 230 to form graphene nanostructures 250.

[0047] FIG. 2B is a detailed graphical representation of an exemplary method for depositing graphene onto nanopatterned catalytic metal substrate with a negative setup in accordance with an embodiment of the present disclosure. The method depicted in Fig. 2B starts the exact same way as the method in Fig. 2A. Thus, the method begins with step 200 and step 202 as in Fig. 2A. In step 203, a spacer film layer 260 is deposited onto thecatalytic material layer 230. The spacer film layer 260 can comprise any material that allows for

nanopatterning and is unsuitable for growing graphene upon the surface of the spacer film layer 260. In one embodiment, Au is used for spacer film layer 260.

[0048] Steps 205-211 are analogous to steps 204-210 in Fig. 2A, except the nanopatterned layer is the spacer film layer 260 rather than catalytic metal layer 230. In step 205, a layer of photoresist 240 is deposited onto spacer film layer 260. In step 207, light (not shown) is shined onto the photoresist layer 240 through a mask (not shown) such that the photoresist is nanopatterned. In step 209, the spacer film layer 260 is selectively etched such that the spacer film layer 260 forms the same nanopattern as the photoresist layer 240. In step 211 , the remaining photoresist layer 260 is removed through light exposure. Although steps 205- 211 are similar to steps 204-210 in Fig. 2A, the fundamental difference is that the mask defines the nanotemplate via the apertures in the mask. In other words, the graphene nanostructures are formed in the areas defined by the holes in the mask, rather than the areas covered by the mask, as in the method in Fig. 2A.

[0049] In step 213, carbon is deposited onto the exposed portions of the catalytic material layer 230 thereby forming the desired graphene nanostructures 250. As discussed above, the spacer film layer 260 comprises material that is unreactive to graphene growth. Therefore, graphene only grows on the exposed regions of catalytic material layer 230.

[0050] FIG. 3 depicts a two-dimensional view of one layer of a graphene nanoribbon (GNR) 300 in accordance with the prior art. GNR 300 comprises a thin strip of graphene, or an unrolled carbon nanotube. As is evident from Fig. 3, graphene comprises carbon atoms sp2- bonded to form a honeycomb like lattice. In Fig. 3, each of the plurality of vertices 302 represents a carbon atom. GNRs, such as GNR 300, can have two edge structures that characterize their electronic properties: armchair and zigzag. Edge 310 depicts the armchair edge structure, while edge 320 depicts the zigzag edge structure. More details about GNRs and their electronic properties can be found in Motohiko Ezawa's Peculiar Band Gap Structure of Graphene Nanoribbons, Physica Status Solidi (c) 4, No. 2, 489 (2007), which is hereby incorporated by reference herein in its entirety.

[0051] FIG. 4 illustrates an exemplary embodiment 400 of a multiple band gap device arranged on a substrate 102 in accordance with the present disclosure. Instead of arranging nanoribbons or stacks in one row, exemplary embodiment 400 comprises a plurality of rows, with each row having a first common lead 406 and a second common lead 408. Graphene structures 404-i and 404-j represent either a single ribbon or a stack of GNR 300. Graphene structures 404-i and 404-j are either identical or have different characteristics. Each row can be electrically connected in series or parallel for a desired output.

[0052] FIG. 5 illustrates an additional exemplary multiple band gap device 500 in accordance with an aspect of the present disclosure, where 504 represents either a single ribbon or a stack of GNR 300, and GNN 506 represents a nanohole superlattice or a vertical stack of multiple nanohole superlattices. Nanoribbons, nanohole superlattices or stacks (formed with either nanoribbons or nanohole superlattices) in exemplary embodiment 500 are nanopatterned and arranged into a plurality of clusters (000-1, 000-2, ..., 000-N) on substrate 102. Each cluster is spatially separated from each other, and has its own first lead 510 and second lead 512. With respect to structure and function, 000-1, 000-2, ..., 000-N can represent embodiments for either nanoribbons or nanoholes superlattices. Exemplary embodiment 500 is a conglomerate that comprises a plurality of multiple band gap devices.

[0053] In some embodiments, cluster 000-i has the same structure as cluster 000-j. In other embodiments, cluster 000-i has the same structure as cluster 000-j, but both of them are different from cluster 000-k. In yet other embodiments, cluster 000-i has the same structure as cluster 000-j, but nanoribbons or stacks of cluster 000-i have different characteristics than nanoribbons or stacks of cluster 000-j. In some embodiments, cluster 000-i is a device comprising a plurality of lateral spaced nanoribbons, whereas in other embodiments, cluster 000-i is a device comprising a plurality of vertically stacked nanoribbons. In some embodiments, cluster 000-i is a device comprising a plurality of lateral spaced nanohole superlattices, whereas in other embodiments, cluster 000-i is a device comprising a plurality of vertically stacked nanohole superlattices. In some embodiments, cluster 000-i is a device comprising one single nanohole superlattice, whereas in other embodiments, cluster 000-i is a device comprising one single stack formed by a plurality of vertically stacked nanohole superlattices.

[0054] In some embodiments, the plurality of multiple band gap devices, or clusters 000-1 , 000-2, ..., 000-N, is geometrically arranged in a planar array, preferably with each cluster parallel or near parallel to adjacent clusters. In some embodiments, however, some clusters are displaced or tilted as shown in FIG. 5. In other embodiments, one cluster is placed on top of another cluster in the plurality of clusters. Depending on the desired application, the plurality of multiple band gap devices, or clusters 000-1, 000-2, ..., 000-N, are electrically connected in parallel, in series, or in combination of parallel and series.

[0055] In general, each device in plurality of multiple band gap devices or each cluster in the plurality of clusters has a width that is between 1 μιη to 10 mm and a length that is between 1 μιη to 10 mm. In some embodiments, each cluster in the plurality of clusters has a width that is between 10 μιη to 1 mm and a length that is between 10 μιη to 1 mm. In some embodiments, each cluster in the plurality of clusters has a width that is between 50 μιη to 500 μιη and a length that is between 50 μιη to 500 μιη.

[0056] In some instance, exemplary embodiments 400 and 500 respectively depicted in FIGS. 4 and 5 comprise an optical splitter and can be used, for example, as photovoltaic devices or photodetectors.

[0057] FIGS. 6-8 provide exemplary schematic electric diagrams for a multiple band gap device in accordance with the present disclosure. In Figs. 6-8, element 602 represents all the embodiments previously described, such as embodiments 400 and 500, and equivalents within the scope of the present disclosure. Through the first lead 604 and the second lead 606, embodiment 602 can be electrically connected to a selective external circuit, creating a multiple band gap photovoltaic device 600 (Fig. 6), a multiple band gap photodetector 700 (Fig. 7), or a multiple band gap LED 900 (Fig. 8).

[0058] A multiple band gap photovoltaic device 600 is created by connecting embodiment 602 to an external load, a schematic electrical diagram of which is illustrated in Fig. 7. Represented by the resistor 608, the load is an electricity generator, a water heater, a battery, or other appliances. In some embodiments, the load is an electrical grid when embodiment 602 is connected to a main electrical grid. In some embodiments, upon receiving incident sunlight, photovoltaic device 700 produces power at 50 W/m2 or higher without a solar concentrator. In some embodiments, photovoltaic device 700 includes a solar concentrator and the power output is higher. For example, using a lOOx solar concentrator, a power of 5000 W/m2 is achieved in some embodiments.

[0059] Connecting embodiment 602 to an electrometer produces a multiple band gap photodetector 700, a schematic electrical diagram of which is illustrated in Fig. 7. The electrometer is any type of electrometer, including vibrating reed electrometers, valve electrometers, and solid-state electrometers, and measures either electric charge or electrical potential difference. By tuning and controlling the band gaps of embodiment 602, photodetector 700 is designed to measure infrared radiation, visible light, and/or ultraviolet radiation, in wavelength ranges anywhere between 10 nm and 100 μιη.

[0060] When embodiment 602 is connected to an external current, such as a battery, a multiple band gap LED 800 is generated. Fig. 8 provides a schematic electrical diagram of a multiple band LED 900 in accordance with the present disclosure. By tuning and controlling the band gaps of embodiment 602, the multiple band gap LED 800 can emit light in a wide wavelength spectrum in the range of between 10 nm to 100 μιη. In some embodiments, the multiple band LED 900 emits a hybrid light, such as a white light.

[0061] In addition, present photovoltaic device 600, photodetector 700, and LED 800 can be integrated into more complex electronic devices to facilitate desired applications. For instance, in some embodiments the photovoltaic device 600 is combined with the LED 800 for a variety of self-sustained solar lighting applications examples of which include outdoor lighting at night. During the daytime, the photovoltaic device 600 absorbs solar energy, converts solar energy into electricity and stores electricity, for example, in a battery. At night, stored electricity powers the LED 800 causing it to light.

[0062] FIGS. 9 A and 9B depict a semiconducting nanohole superlattice 930 with triangular nanoholes 932 and with rectangular nanoholes 934 respectively. Other shapes of nanoholes or combination of different shapes of nanoholes can be patterned within a layered crystalline material to make a semiconducting nanohole superlattice. As used herein the term

"semiconducting nanohole superlattice" refers to a layered crystalline material having an array of nanoholes defined therein. In some embodiments, the nanohole superlattice comprises one sheet of the layered crystalline material or multiple vertically stacked sheets of the layered crystalline material. Layered crystalline materials include, but not limited to, graphite (C), boron nitride (BN), molybdenum disulfide (MoS2), tungsten disulfide (WS2), zinc oxide (ZnO), and titanium dioxide (Ti02). The array of nanoholes can be produced using any suitable fabrication known in the art. For example, in some embodiments, a nanohole superlattice structure is patterned with one or more nanohole arrays using conventional photolithography techniques.

[0063] Effectively, a nanohole superlattice is a two-dimensional network of crossing nanoribbons, in which the size, shape, and density of the nanoholes define the shape and dimensions of the nanoribbons. Thus, nanohole superlattices have similar characteristics to nanoribbons. For example, while not wishing to be bound by any particular theory, the tight- binding model indicates that band gaps of graphene nanohole superlattices increase linearly with the product of nanohole size and density. This is because the width of a nanoribbon in the two-dimensional network of crossing nanoribbons can be decreased by either increasing the sizes of nanoholes or increasing the number of nanoholes in one fixed unit. Other similar characteristics include larger mean free paths for charge carriers in nanohole superlattices and dependence or weak dependence of the work functions of nanohole superlattices on the size, shape, density of the nanoholes. These characteristics make it possible to design a device with nanohole superlattices in a similar way as nanoribbons.

[0064] In addition to having similar characteristics, a nanohole superlattice in general has several advantages compared to an individual nanoribbon. For example, a signal nanoribbon is typically fragile and harder to transfer from one substrate to another. A nanohole superlattice, however, is mechanically stronger and more stable due to the crossing network structure, thus easier to transfer to another substrate if needed. In addition, a nanohole superlattice usually provides more surface area for absorbing or omitting light, and hence potentially higher efficiency for any device comprising such a nanohole superlattice.

Furthermore, a nanohole superlattice tolerates defects better than an individual nanoribbon.

5. Multiple Band Gap Devices

[0065] Using semiconducting nanoribbons or nanohole superlattices as a photon-absorbing or light-emitting material, the present disclosure provides a multiple band gap device that can efficiently convert photon energy to electricity, or vice versa, across all or a portion of a wide wavelength spectrum. In the case of semiconducting nanoribbons, the basic architecture of the multiple band gap device in accordance with the present disclosure includes a plurality of semiconducting nanoribbons that have multiple band gaps. The plurality of semiconducting nanoribbons are configured so that a nanoribbon with a first band gap absorbs a photon or emits a light within a first spectrum range and a nanoribbon with a second band gap absorbs a photon or emits a light within a second spectrum range. In one example, the plurality of semiconducting nanoribbons is arranged vertically by stacking one on top of another or arranged laterally by placing one next to another side by side.

[0066] In the case of semiconducting nanohole superlattices, the basic architecture of the multiple band gap device in accordance with the present disclosure includes one or more semiconducting nanohole superlattices. Each semiconducting nanohole superlattice is characterized by a band gap range, which can span a few meV or a few eV by control of nanohole patterns. In one example, the band gap range of a nanohole superlattice is configured to be in the range of between 0.1 eV to 2 eV for absorbing solar radiation, or is configured at or near a desired single band gap value for detecting a light signal at a specific wavelength. In some embodiments, within the one or more nanohole superlattices, a nanohole superlattice has a different band gap range or value from other nanohole superlattices. Similar to nanoribbons, the one or more nanohole superlattices is arranged vertically in some embodiments by stacking one on top of another or arranged laterally by placing one next to another side by side.

[0067] In addition to a plurality of semiconducting nanoribbons or one or more nanohole superlattices, the basic architecture of the multiple band gap devices in accordance with the present disclosure includes a first lead and a second lead, which are typically made of electrically conductive materials such as metals. In the case of nanoribbons, the first lead electrically contacts one end of each nanoribbon in the plurality of nanoribbons, and the second lead electrically contacts the other end of each nanoribbon in the plurality of nanoribbons. In the case of nanohole superlattices, the first lead electrically contacts one edge of each nanohole superlattice in one or more nanohole superlattices and the second lead electrically contacts the opposite edge of each nanohole superlattice in one or more nanohole superlattices. Depending on the application, the first lead or the second lead forms a

Schottky barrier or ohmic contact at the interface between the lead and one end of the nanoribbons or between the lead and one edge of the nanohole superlattices in some embodiments.

[0068] FIG. 10 depicts a schematic top view of a multiple band gap device comprising a nanohole superlattice 930 in accordance with an aspect of the present disclosure. As in embodiments comprising nanoribbons, the nanohole superlattice is disposed on a substrate 102. There are also two leads, the first lead 1006 and the second lead 1008, electrically contact two opposite edges of the nanohole superlattice. Patterned within the nanohole superlattice is an array of rectangular nanoholes 1034. By way of illustration, rectangular nanoholes 1034 depicted in FIG. 10 have different sizes and spacing, rendering the analogous nanoribbons within the nanohole superlattice 930 having different widths. Thus the nanohole superlattice 930 is expected to have multiple band gaps.

[0069] Depending on the application and the desired band gap range, an array of nanoholes having different shapes, sizes, densities, or any combination thereof is used, or is distributed differently within the nanohole superlattice. In addition, in some embodiments, the nanohole superlattice is doped, in bulk or on edges, with different dopants or concentrations, to further tune the band gap range. Other parameters, such as the thickness of the nanohole

superlattice, are varied as well to modify the band gap in some embodiments of the present disclosure.

[0070] Like nanoribbon based embodiments, the first lead 1006 or the second lead 1008 forms a Schottky barrier or ohmic contact at the interface between the lead and the edge of the nanohole superlattice, depending on the application, in some embodiments. Also, as is the case with the disclosed nanoribbon based embodiments, embodiments using nanohole superlattices may or may not comprise an optical splitter depending on the application. For applications in which incident light is converted into electricity or detectable signals, a multiple band gap device in accordance with the present disclosure further comprises an optical splitter in optical communication with the nanohole superlattice. For light emission applications, however, a multiple band gap device in accordance with the present disclosure does not need an optical splitter.

[0071] Similar to nanoribbons, in some embodiments, the one or more nanohole superlattices are arranged vertically by stacking one on top of another or arranged laterally by placing one next to another side by side. In some embodiments, the architecture of devices having semiconducting nanohole superlattices is essentially the same as those described above when using nanoribbons, whether it is vertically stacked or lateral spaced. In fact, all the structures, parameters, figures, materials, etc. described above for nanoribbons can be easily modified to describe the architectures, parameters, figures, materials, etc for nanohole superlattices by simply replacing nanoribbons with nanohole superlattices. Other optional features, such as antireflection layer and optical splitter, can be incorporated in essentially the same way into the architectures using semiconducting nanohole superlattices.

[0072] As an example to illustrate the similarity, a vertically stacked structure using semiconducting nanohole superlattices includes a substrate and a nanohole superlattice stack defined by a first edge and a second edge. The nanohole superlattice stack comprises a plurality of nanohole superlattices, including (i) a first nanohole superlattice in the plurality of nanohole superlattices characterized by a first band gap range and patterned with a first array of nanoholes, and the first nanohole superlattice overlaying the substrate, (ii) a first optically transparent insulator overlaying the first nanohole superlattice, and (iii) a second nanohole superlattice in the plurality of nanohole superlattices characterized by a second band gap range and patterned with a second array of nanoholes, and the second nanohole superlattice overlaying the first insulator. The first band gap range is characterized by at least one band gap within the first band gap range that is smaller than band gaps within the second band gap range. In addition, the vertically stacked structure using semiconducting nanohole superlattices includes a first lead electrically contacting the first edge of the nanohole superlattice stack, and a second lead electrically contacting the second edge of the nanohole superlattice stack.

[0073] In some embodiments, a nanohole superlattice in the plurality of nanohole

superlattices has a characteristic dimension that is in between 1 μιη and 10 mm. In some embodiments, the characteristic dimension of a nanohole superlattice is between 50 μιη and 500 μιη, or between 100 μιη and 300 μιη. In some embodiments, a nanohole in the array of nanoholes patterned in a nanohole superlattice in the plurality of nanohole superlattices has a characteristic dimension that is less than 5000 nm. In some embodiments, a nanohole in the array of nanoholes has a characteristic dimension that is less than 1000 nm, less than 500 nm, less than 100 nm, or less than 50 nm. In some embodiments, a nanohole superlattice in the plurality of nanohole superlattices has a nanohole density that is in between 1 nanohole^m2 and 106 nanoholes^m2, while in other embodiments, a nanohole superlattice in the plurality of nanohole superlattices has a nanohole density that is in between 10 nanoholes/ μιη2 and 105 nanoholes^m2, or between 100 nanoholes^m2 and 104 nanoholes^m2.

[0074] In some embodiments, a first junction between the first lead and the first edge of the nanohole superlattice stack forms a Schottky barrier with respect to a carrier while the second junction between the second lead and the second edge of the nanohole superlattice stack either forms no Schottky barrier at all with respect to the carrier or forms a smaller Schottky barrier for the carrier, where the carrier is either electrons or wholes. Electrically connecting the first lead and the second lead to a selective circuit produces a multiple band gap photovoltaic device, a multiple band gap photodetector, or a multiple band gap light emitting diode.

[0075] Some devices in accordance with the present disclosure comprise a nanohole superlattice device having a plurality of nanohole superlattices stacked on top of each other, the device having a first edge and a second edge. The first edge is in electrical communication with a first lead and the second edge is in electrical communication with a second lead. The device is arranged on a substrate, more specifically on a surface of the substrate. The substrate serves as a support for the device. The substrate is typically planar and can be either rigid or flexible. In some embodiments, the substrate is made of aluminosilicate glass, borosilicate glass, dichroic glass, germanium/semiconductor glass, glass ceramic, silicate/fused silica glass, soda lime glass, quartz glass, chalcogenide/sulphide glass, fluoride glass, a glass-based phenolic, flint glass, or cereated glass. In some embodiments, the substrate is made of a urethane polymer, an acrylic polymer, a

fluoropolymer, polybenzamidazole, polymide, polytetrafluoroethylene, polyetheretherketone, polyamide-imide, glass-based phenolic, polystyrene, cross-linked polystyrene, polyester, polycarbonate, polyethylene, polyethylene, acrylonitrile-butadiene-styrene, polytetrafluoroethylene, polymethacrylate, nylon 6,6, cellulose acetate butyrate, cellulose acetate, rigid vinyl, plasticized vinyl, or polypropylene.

[0076] The device comprises a plurality of nanohole superlattices and an optically

transparent insulator in between adjacent nanohole superlattices. In some embodiments, the nanohole superlattice device comprises two nanohole superlattices, whereas in other embodiments, the nanohole superlattice device comprises three nanohole superlattices. In yet other embodiments, the nanohole superlattice device comprises more than three nanohole superlattices.

[0077] Generally, the band gaps of the nanohole superlattices are tuned to be between 0.1 eV to 2.2 eV. In some embodiments where a nanohole superlattice stack comprises two nanohole superlattice, the first band gap is tuned and controlled to be between 0.1 eV to 1.2 eV, between 0.5 eV and 1.5 eV, or between 0.8 eV and 1.8 eV; the second band gap is configured to be between 0.8 eV and 1.9 eV, or between 1.2 eV and 2.2 eV, or between 1.5 eV and 2.2 eV. In some embodiments where a nanohole superlattice stack comprises three nanohole superlattices, the first band gap is tuned and controlled to be between 0.1 eV and 1.1 eV, between 0.4 eV and 1.3 eV, or between 0.6 eV and 1.5 eV; the second band gap is configured to be between 0.7 eV and 1.5 eV, between 1 eV and 1.7 eV, or between 1.2 and 2.1 eV; and the third band gap is configured to be between 1.4 eV to 2 eV, between 1.5 eV to 2.1 eV, or between 1.6 eV to 2.2 eV. [0078] In some embodiments, a first nanohole superlattice has a band gap of between 0.1 eV and 1.0 eV, between 0.4 eV and 1.4 eV, between 0.6 eV and 1.8 eV, or between 0.8 eV and 2.2 eV. In some embodiments a first nanohole superlattice has a band gap between 0.1 eV and 0.4 eV, between 0.4 eV and 0.8 eV, between 0.8 eV and 1.2 eV, between 1.2 eV and 1.6 eV, between 1.6 eV and 2.0 eV or between 2.0 eV and 2.2 eV.

[0079] In some embodiments, a first nanohole superlattice has a band gap of between 0.1 eV and 1.0 eV, between 0.4 eV and 1.4 eV, between 0.6 eV and 1.8 eV, or between 0.8 eV and 2.2 eV and a second nanohole superlattice has a band gap, different than the band gap of the first nanohole superlattice, in the range of between 0.1 eV and 1.0 eV, between 0.4 eV and 1.4 eV, between 0.6 eV and 1.8 eV, or between 0.8 eV and 2.2 eV. In some embodiments a first nanohole superlattice has a band gap between 0.1 eV and 0.4 eV, between 0.4 eV and 0.8 eV, between 0.8 eV and 1.2 eV, between 1.2 eV and 1.6 eV, between 1.6 eV and 2.0 eV or between 2.0 eV and 2.2 eV and a second nanohole superlattice has a band gap, different than the band gap of the first nanohole superlattice, in the range of between 1 nm and 10 nm, between 10 nm and 20 nm, between 20 nm and 30 nm, between 30 nm and 40 nm, or between 40 nm and 50 nm.

[0080] Band gaps for a multiple band gap photodetector in accordance with the present disclosure depend on the spectrum of the incident light that needs to be measured. If the spectrum of the incident light is within the infrared range, the band gaps of the nanohole superlattice stack can be set at lower values, for instance, below 1.0 eV. On the other hand, nanohole superlattices must have larger band gaps, for instance, above 1.5 eV, if the spectrum of the incident light is within the ultraviolet range. For measuring a spectral range within the visible light, band gaps have the same values as a multiple band gap photovoltaic device. In applications where the spectrum of the incident light spans a broader range, for instance, from infrared to ultraviolet where a wavelength ranges in between 10 nm to 100 μιη, a nanohole superlattice stack comprise more than three layers of nanohole superlattices, with each nanohole superlattice tuned to selectively absorb photons in a specifically targeted spectral range.

[0081] Similarly, for a multiple band gap LED in accordance with the present disclosure, the number of nanohole superlattices in a stack and the band gap for each nanohole superlattice is application dependent. For instance, in some embodiments in which a white light is desired, the multiple band gap LED comprises a plurality of nanohole superlattice stacks, with each nanohole superlattice stack having three nanohole superlattices. The band gaps of each nanohole superlattice is tuned and controlled so that the first nanohole superlattice at the bottom has the smallest band gap, the third nanohole superlattice on the top has the largest band gap, and the second nanohole superlattice in the middle has a band gap between the largest and smallest band gaps. Upon application of an electric source, the first, second, and third nanohole superlattice emit a red light, a green light, and a blue light, respectively. If in the right proportion, the red, green and blue lights collectively emit a white light thus creating a white light LED.

[0082] The thickness of a nanohole superlattice can have a wide range spanning from nanometers to micrometers, corresponding to a nanohole superlattice that contains a monolayer graphene nanohole superlattice sheet to several hundred graphene nanohole superlattice sheets. In some embodiments, a nanohole superlattice comprises between 1 and 300 graphene nanohole superlattice sheets. In some embodiments, a nanohole superlattice comprises between 100 and 300 graphene nanohole superlattice sheets.

[0083] In some embodiments, however, the architecture using semiconducting nanohole superlattices comprises only one single nanohole superlattice. This is different from the architectures using nanoribbons, which require a plurality of nanoribbons to provide multiple band gaps. Unlike an individual nanohole superlattice with a restricted band gap at or near a band gap value, a single nanohole superlattice can have multiple band gaps or a band gap range because it is equivalent to a crossing network of a plurality of nanoribbons. By control of nanohole size, shape, density, and/or other parameters, one single nanohole superlattice can have multiple band gaps spanning a broad range, for example, from 0.1 eV to 2.2 eV. Likewise, by control of nanohole size, shape, and/or density, a nanohole superlattice can be tuned to a specific band gap value. To control the band gaps, a single nanohole superlattice can be selectively patterned with triangles, rectangles, hexagons, rhombuses, etc., or any combination thereof. The band gaps of the nanohole superlattice can be further tuned by variations of its thickness or doping. 6. Advantages

[0084] There are many advantages to fabricating GNRs and GNNs in the manner described above. One advantage is ease of fabrication. Currently, cutting graphene sheets into desired GNRs and GNNs is a difficult task, due to the novelty graphene and the techniques of cutting the same. However, cutting or etching metal and semiconductors is a much more mature technology and can be achieved with much more ease.

[0085] Another advantage to the methods described in the present disclosure is more consistency. Cutting GNRs and GNNs from graphene sheets numerous times has proven to yield unpredictable shapes and erratic edge structures. Because the methods described above cut metal or semiconductor materials using masks, the exact structures and patterns desired can be reproduced consistently because the same masks can be used repeatedly.

[0086] Yet another advantage to the methods described in the present disclosure is the ability to mass produce graphene nanostructures. Current techniques produce a dissatisfactory yield in the best cases. However, because the methods described above use nanotemplates, the percentage yield is improved. This means that GNRs and GNNs can be produced much more efficiently using the methods described in the present disclosure.

7. Deposition Methods

[0087] The following subsections describe individual fabrication techniques that can be used to deposit layers of material, e.g. catalytic material layer 230, spacer film 260, resist layer 240, or graphene layer 250, hereinafter referred to collectively as "deposit materials," in accordance with embodiments of the present disclosure.

7.1 Chemical vapor deposition

[0088] In some embodiments, one or more layers of the deposit materials are deposited by chemical vapor deposition. In chemical vapor deposition (CVD), the constituents of a vapor phase, often diluted with an inert carrier gas, react at a hot surface (typically higher than 300°C) to deposit a solid film. Generally, chemical vapor deposition reactions require the addition of energy to the system, such as heating the chamber or the wafer. For more information on chemical vapor deposition, exemplary devices used to perform chemical vapor deposition, and process conditions are used to perform chemical vapor deposition of silicon nitride, see Van Zant, Microchip Fabrication, Fourth Edition, McGraw-Hill, New York, 2000, pp. 363-393; and Madou, Fundamentals of Microfabrication, Second Edition, 2002, pp. 144-154, CRC Press, each of which are hereby incorporated by reference herein in their entireties.

7.2 Reduced pressure chemical vapor deposition

[0089] In some embodiments, one or more layers of the deposit materials are deposited by reduced pressure chemical vapor deposition (RPCVD). RPCVD is typically performed at below 10 Pa and at temperatures in the range of (550°C - 600°C). The low pressure used in RPCVD results in a large diffusion coefficient, which leads to growth of a layer that is limited by the rate of surface reactions rather than the rate of mass transfer to the substrate. In RPCVD, reactants can typically be used without dilution. RPCVD is performed, for example, in some embodiments, in a horizontal tube hot wall reactor.

7.3 Low pressure chemical vapor deposition

[0090] In some embodiments, one or more layers of the deposit materials are deposited by low pressure chemical vapor deposition (LPCVD) or very low pressure CVD. LPCVD is typically performed at below 1 Pa.

7.4 Atmospheric chemical vapor deposition

[0091] In some embodiments, one or more layers of the deposit materials are deposited by atmospheric to slightly reduced pressure chemical vapor deposition. Atmospheric pressure to slightly reduced pressure CVD (APCVD) is used, for example, to grow APCVD is a relatively simplistic process that has the advantage of producing layers at high deposition rates and low temperatures (350°C - 400°C).

7.5 Plasma enhanced chemical vapor deposition

[0092] In some embodiments, one or more layers of the deposit materials are deposited by plasma enhanced (plasma assisted) chemical vapor deposition (PECVD). PECVD systems feature a parallel plate chamber operated at a low pressure (e.g., 2-5 Torr) and low temperature (300°C - 400°C). A radio-frequency-induced glow discharge, or other plasma source is used to induce a plasma field in the deposition gas. PECVD systems that are used include, but are not limited to, horizontal vertical flow PECVD, barrel radiant-heated PECVD, and horizontal-tube PECVD. In some embodiments, remote plasma CVD (RPCVD) is used. Remote plasma CVD is described, for example, in United States Patent No. 6,458,715 to Sano et al, which is hereby incorporated by reference in its entirety.

7.6 Anodization

[0093] In some embodiments, one or more layers of the deposit materials are deposited by anodization. Anodization is an oxidation process performed in an electrolytic cell. The material to be anodized becomes the anode (+) while a noble metal is the cathode (-).

Depending on the solubility of the anodic reaction products, an insoluble layer (e.g., an oxide) results. If the primary oxidizing agent is water, the resulting oxides generally are porous, whereas organic electrolytes lead to very dense oxides providing excellent passivation. See, e.g., Madou et al, 1982, J. Electrochem. Soc. 129, pp. 2749-2752, which is hereby incorporated by reference in its entirety.

7.7 Sol-gel deposition techniques

[0094] In some embodiments, one or more layers of thedeposit materials are deposited by a sol-gel process. In a sol-gel process solid particles, chemical precursors, in a colloidal suspension in a liquid (a sol) forms a gelatinous network (a gel). Upon removal of the solvent by heating a glass or ceramic layer. Both sol and gel formation are low-temperature processes. For sol formation, an appropriate chemical precursor is dissolved in a liquid, for example, tetraethylsiloxane (TEOS) in water. The sol is then brought to its gel-point, that is, the point in the phase diagram where the sol abruptly changes from a viscous liquid to a gelatinous, polymerized network. In the gel state the material is shaped (e.g., a fiber or a lens) or applied onto a substrate by spinning, dipping, or spraying. In the case of TEOS, a silica gel is formed by hydrolysis and condensation using hydrochloric acid as the catalyst. Drying and sintering at temperatures between 200°C to 600°C transforms the gel into a glass and ultimately into silicon dioxide.

7.8 Plasma spraying techniques

[0095] In some embodiments, one or more layers of the deposit materials are deposited by a plasma spraying process. With plasma spraying, almost any material can be coated on many types of substrates. Plasma spraying is a particle deposition method. Particles, a few microns to 100 microns in diameter, are transported from source to substrate. In plasma spraying, a high-intensity plasma arc is operated between a sticktype cathode and a nozzle-shaped water- cooled anode. Plasma gas, pneumatically fed along the cathode, is heated by the arc to plasma temperatures, leaving the anode nozzle as a plasma jet or plasma flame. Argon and mixtures of argon with other noble (He) or molecular gases (H₂, N₂, 0₂, etc.) are frequently used for plasma spraying. Fine powder suspended in a carrier gas is injected into the plasma jet where the particles are accelerated and heated. The plasma jet reaches temperatures of 20,000 K and velocities up to 1000 ms^"1 in some embodiments. The temperature of the particle surface is lower than the plasma temperature, and the dwelling time in the plasma gas is very short. The lower surface temperature and short duration prevent the spray particles from being vaporized in the gas plasma. The particles in the plasma assume a negative charge, owing to the different thermal velocities of electrons and ions. As the molten particles splatter with high velocities onto a substrate, they spread, freeze, and form a more or less dense coating, typically forming a good bond with the substrate. Plasma spraying equipment is available from Sulzer Metco (Winterthur Switzerland). For more information on plasma spraying, see, for example, Madou, Fundamentals of Micro fabrication, Second Edition, 2002, pp. 157-159, CRC Press, which is hereby incorporated by reference in its entirety.

7.9 Ink jet printing

[0096] In some embodiments, one or more layers of the deposit materials are deposited by ink-jet printing. Ink-jet printing is based on the same principles of commercial ink-jet printing. The ink-jet nozzle is connected to a reservoir filled with the chemical solution and placed above a computer-controlled x-y stage. The target object is placed on the x-y stage and, under computer control, liquid drops (e.g., 50 microns in diameter) are expelled through the nozzle onto a well-defined place on the object. Different nozzles print different spots in parallel. In one embodiment of the present disclusre, a bubble jet, with drops as small as a few picoliters, is used to form a layer of a deposit material. In another embodiment, a thermal ink jet (Hewlett Packard, Palo Alto, California) is used to form a layer of a deposit material. In a thermal ink jet, resistors are used to rapidly heat a thin layer of liquid ink. A superheated vapor explosion vaporizes a tiny fraction of the ink to form an expanding bubble that ejects a drop of ink from the ink cartridge onto the substrate. In still another embodiment of the present disclosure, a piezoelectric ink-jet head is used for ink-jet printing. A piezoelectric ink-jet head includes a reservoir with an inlet port and a nozzle at the other end. One wall of the reservoir consists of a thin diaphragm with an attached piezoelectric crystal. When voltage is applied to the crystal, it contracts laterally, thus deflecting the diaphragm and ejecting a small drop of fluid from the nozzle. The reservoir then refills via capillary action through the inlet. One, and only one, drop is ejected for each voltage pulse applied to the crystal, thus allowing complete control over the when a drop is ejected. In yet another embodiment of the present disclosure, an epoxy delivery system is used to deposit a layer of a solar cell. An example of an epoxy delivery system is the Ivek Digispense 2000 (Ivek Corporation, North Springfield, Vermont). For more information on jet spraying, see, for example, Madou, Fundamentals of Micro fabrication, Second Edition, 2002, pp. 164-167, CRC Press, which is hereby incorporated by reference herein in its entirety.

7.10 Vacuum evaporation

[0097] In one embodiment of the present disclosure, one or more layers of the deposit materials are deposited by vacuum evaporation. Vacuum evaporation takes place inside an evacuated chamber. The chamber can be, for example, a quartz bell jar or a stainless steal enclosure. Inside the chamber is a mechanism that evaporates the metal source, a wafer holder, a shutter, thickness and rate monitors, and heaters. The chamber is connected to a vacuum pump. There are any number of different ways in which the metal is evaporated within the chamber, including filament evaporation, E-beam gun evaporation, and hot plate evaporation. See, for example, Van Zant, Microchip Fabrication, Fourth Edition, McGraw- Hill, New York, 2000, pp. 407-411, which is hereby incorporated by reference herein in its entirety.

7.11 Sputter deposition / physical vapor deposition

[0098] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by sputtering. Sputtering, like evaporation, takes place in a vacuum. However, it is a physical not a chemical process (evaporation is a chemical process), and is referred to as physical vapor deposition. Inside the vacuum chamber is a slab, called a target, of the desired film material. The target is electrically grounded. An inert gas such as argon is introduced into the chamber and is ionized to a positive charge. The positively charged argon atoms are attracted to the grounded target and accelerate toward it.

[0099] During the acceleration they gain momentum, and strike the target, causing target atoms to scatter. That is, the argon atoms "knock off atoms and molecules from the target into the chamber. The sputtered atoms or molecules scatter in the chamber with some coming to rest on the wafer. A principal feature of a sputtering process is that the target material is deposited on the wafer with chemical or compositional change. In some embodiments of the present disclosure, direct current (DC) diode sputtering, radio frequency (RF) diode sputtering, triode sputtering, DC magnetron sputtering or RF magnetron sputtering is used. See, for example, Van Zant, Microchip Fabrication, Fourth Edition, McGraw-Hill, New York, 2000, pp. 411-415; United States Patent 5,203,977; United States Patent 5,486,277; and United States Patent 5,742,471, each of which is hereby incorporated by reference herein in its entirety.

[00100] RF diode sputtering is a vacuum coating process where an electrically isolated cathode is mounted in a chamber that can be evacuated and partially filled with an inert gas. If the cathode material is an electrical conductor, a direct-current high-voltage power supply is used to apply the high voltage potential. If the cathode is an electrical insulator, the polarity of the electrodes is reversed at very high frequencies to prevent the formation of a positive charge on the cathode that would stop the ion bombardment process. Since the electrode polarity is reversed at a radio frequency, this process is referred to as 133 sputtering. Magnetron sputtering is different form of sputtering. Magnetron sputtering uses a magnetic field to trap electrons in a region near the target surface thus creating a higher probability of ionizing a gas atom. The high density of ions created near the target surface causes material to be removed many times faster than in diode sputtering. The magnetron effect is created by an array of permanent magnets included within the cathode assembly that produce a magnetic field normal to the electric field.

7.12 Collimated sputtering

[00101] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by collimated sputtering. Collimated sputtering is a sputtering process where the arrival of metal occurs at an angel normal to the wafer surface. The metal is collimated by a thick honeycomb grid that effectively blocks off angle metal atoms in some embodiments. Alternatively, ionizing the metal atoms and attracting them towards the wafer collimates the metal. Collimated sputtering improves filling of high aspect ratio contacts.

7.13 Laser Ablated deposition

[00102] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by laser ablated deposition. In one form of laser ablated deposition, a rotating cylindrical target surface is provided for the laser ablation process. The target is mounted in a vacuum chamber so that it is rotated about the longitudinal axis of the cylindrical surface target and simultaneously translated along the longitudinal axis. A laser beam is focused by a cylindrical lens onto the target surface along a line that is at an angle with respect to the longitudinal axis to spread a plume of ablated material over a radial arc. The plume is spread in the longitudinal direction by providing a concave or convex lateral target surface. The angle of incidence of the focused laser beam is other than normal to the target surface to provide a glancing geometry in some embodiments. Simultaneous rotation about and translation along the longitudinal axis produce a smooth and even ablation of the entire cylindrical target surface and a steady evaporation plume. Maintaining a smooth target surface is useful in reducing undesirable splashing of particulates during the laser ablation process and thereby depositing high quality thin films. See, for example, United States Patent Number 5,049,405, which is hereby incorporated by reference herein in its entirety.

7.14 Molecular beam deposition

[00103] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by molecular beam deposition. Molecular beam deposition is a method of growing films, under vacuum conditions, by directing one or more molecular beams at a substrate. In some instances, molecular beam deposition involves epitaxial film growth on single crystal substrates by a process that typically involves either the reaction of one or more molecular beams with the substrate or the deposition on the substrate of the beam particles. The term "molecular beam" refers to beams of monoatomic species as well as polyatomic species. The term molecular beam deposition includes both epitaxial growth and nonepitaxial growth processes. Molecular beam deposition is a variation of simple vacuum evaporation. However, molecular beam deposition offers better control over the species incident on the substrate than does vacuum evaporation. Good control over the incident species, coupled with the slow growth rates that are possible, permits the growth of thin layers having compositions (including dopant concentrations) that are precisely defined. Compositional control is aided by the fact that growth is generally at relatively low substrate temperatures, as compared to other growth techniques such as liquid phase epitaxy or chemical vapor deposition, and diffusion processes are very slow.

[00104] Essentially arbitrary layer compositions and doping profiles are obtained with precisely controlled layer thickness. In fact, layers as thin as a monolayer are grown by

MBE. Furthermore, the relatively low growth temperature permits growth of materials and use of substrate materials that could not be used with higher temperature growth techniques. See for example, United States Patent 4,681,773, which is hereby incorporated by reference herein in its entirety.

7.15 Ionized physical vapor deposition

[00105] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by ionized physical vapor deposition (I-PVD), also known as ionized metal plasma (IMP). In I-PVD, metal atoms are ionized in an intense plasma. Once ionized, the metal is directed by electric fields perpendicular to the wafer surface. Metal atoms are introduced into the plasma by sputtering from the target. A high density plasma is generated in the central volume of the reactor by an inductively coupled plasma (ICP) source. This electron density is sufficient to ionize approximately 80% of the metal atoms incident at the wafer surface. The ions from the plasma are accelerated and collimated at the surface of the wafer by a plasma sheath. The sheath is a region of intense electric field that is directed toward the wafer surface. The field strength is controlled by applying a radio frequency bias.

7.16 Ion beam deposition

[00106] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by ion beam deposition (IBD). IBD uses an energetic, broad beam ion source carefully focused on a grounded metallic or dielectric sputtering target. Material sputtered from the target deposits on a nearby substrate to create a film. Most applications also use a second ion source, termed an ion assist source (IAD), that is directed at the substrate to deliver energetic noble or reactive ions at the surface of the growing film. The ion sources are "gridded" ion sources and are typically neutralized with an independent electron source. IBD processing yields excellent control and repeatability of film thickness and properties. Process pressures in IBD systems are approximately 10^"4 Torr. Hence, there is very little scattering of either ions delivered by the ion sources or material sputtered from the target of the surface. Compared to sputter deposition using magnetron or diode systems, sputter deposition by IBD is highly directional and more energetic. In combination with a substrate fixture that rotates and changes angle, IBD systems deliver a broad range of control over sidewall coatings, trench filling and liftoff profiles. 7.17 Atomic layer deposition

[00107] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by atomic layer deposition. Atomic layer deposition is also known as atomic layer epitaxy, sequential layer deposition, and pulsed-gas chemical vapor deposition. Atomic layer deposition involves use of a precursor based on self-limiting surface reactions. Generally, an object is exposed to a first species that deposits as a monolayer on the object. Then, the monolayer is exposed to a second species to form a fully reacted layer plus gaseous byproducts. The process is typically repeated until a desired thickness is achieved. Atomic layer deposition and various methods to carry out the same are described in United States Patent Number 4,058,430 to Suntola et al., entitled "Method for Producing Compound Thin Films," United States Patent Number 4,413,022 to Suntola et al., entitled "Method for Performing Growth of Compound Thin Films," to Ylilammi, and George et al., 1996, J. Phys. Chem. 100, pp. 13121-13131, each of which is hereby incorporated by reference herein in its entirety. Atomic layer deposition has also been described as a chemical vapor deposition operation performed under controlled conditions that cause the deposition to be self-limiting to yield deposition of, at most, a monolayer. The deposition of a monolayer provides precise control of film thickness and improved compound material layer uniformity. Atomic layer deposition is performed using equipment such as the Endura Integrated Cu Barrier/Seed system (Applied Materials, Santa Clara, California).

7.18 Hot filament chemical vapor deposition

[00108] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by hot filament chemical vapor deposition (HFCVD). In HFCVD, reactant gases are flowed over a heated filament to form precursor species that subsequently impinge on the substrate surface, resulting in the deposition of high quality films. HFCVD has been used to grow a wide variety of films, including diamond, boron nitride, aluminum nitride, titanium nitride, boron carbide, as well as amorphous silicon nitride. See, for example, Deshpande et al., 1995, J. Appl. Phys. 77, pp. 6534-6541, which is hereby incorporated by reference herein in its entirety.

7.19 Screen printing

[00109] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by a screen printing (also known as silk-screening) process.

A paste or ink is pressed onto portions of an underlying structure through openings in the emulsion on a screen. See, for example, Lambrechts and Sansen, Biosensors:

Microelectrochemical Devices, The Institute of Physics Publishing, Philadelphia, 1992, which is hereby incorporated by reference in its entirety. The paste consists of a mixture of the material of interest, an organic binder, and a solvent. The organic binder determines the flow properties of the paste. The bonding agent provides adhesion of particles to one another and to the substrate. The active particles make the ink a conductor, a resistor, or an insulator. The lithographic pattern in the screen emulsion is transferred onto portions of the underlying structure by forcing the paste through the mask openings with a squeegee. In a first step, paste is put down on the screen. Then the squeegee lowers and pushes the screen onto the substrate, forcing the paste through openings in the screen during its horizontal motion.

During the last step, the screen snaps back, the thick film paste that adheres between the screening frame and the substrate shears, and the printed pattern is formed on the substrate. The resolution of the process depends on the openings in the screen and the nature of the paste. With a 325-mesh screen {i.e., 325 wires per inch or 40 μΜ holes) and a typical paste, a lateral resolution of ΙΟΟμΜ can be obtained.

[00110] For difficult-to-print pastes, a shadow mask, such as a thin metal foil with openings, complements the process. However, the resolution of this method is inferior (>500 μΜ). After printing, the wet films are allowed to settle for a period of time {e.g., fifteen minutes) to flatten the surface while drying. This removes the solvents from the paste. Subsequent firing burns off the organic binder, metallic particles are reduced or oxidized, and glass particles are sintered. Typical temperatures range from 500°C to 1000°C. After firing, the thickness of the resulting layer ranges from 10μΜ to 50μΜ. One silk-screening setup is the DEK 4265 (Universal Instrument Corporation, Binghamton, New York). Commercially available inks (pastes) that can be used in the screen printing include conductive {e.g., Au, Pt, Ag/Pd, etc.), resistive {e.g., Ru0₂, Ir0₂), overglaze, and dielectric (e.g., A1₂0₃, Zr0₂). The conductive pastes are based on metal particles, such as Ag, Pd, Au, or Pt, or a mixture of these combined with glass. Resistive pastes are based on Ru0₂ or Bi₂Ru₂0₇ mixed with glass {e.g., 65% PBO, 25% Si0₂, 10% Bi₂0₃).

[00111] The resistivity is determined by the mixing ratio. Overglaze and dielectric pastes are based on glass mixtures. Different melting temperatures can be achieved by adjusting the paste composition. See, for example, Madou, Fundamentals of Microfabrication, Second Edition, CRC Press, Boca Raton, Florida, 2002, pp. 154-156, which is hereby incorporated by reference herein in its entirety.

7.20 Electroless metal deposition

[00112] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by electroless metal deposition. In electroless plating a layer is built by chemical means without applying a voltage. Electroless plating baths can be used to form Au, Co-P, Cu, Ni-Co, Ni-P, Pd, or Pt layers. See, for example, Madou,

Fundamentals of Microfabrication, Second Edition, CRC Press, Boca Raton, Florida, 2002, pp. 344-345, which is hereby incorporated by reference herein in its entirety.

7.21 Electroplating

[00113] In another embodiment of the present disclosure, one or more layers of the deposit materials are deposited by electroplating. Electroplating takes place in an electrolytic cell. The reactions that take place in electroplating involve current flow under an imposed bias. In some embodiments, a layer is deposited as part of a damascene process. See, for example, Madou, Fundamentals of Microfabrication, Second Edition, CRC Press, Boca Raton, Florida, 2002, pp. 346-357, which is hereby incorporated herein by reference in its entirety.

8. Lithographic Etching Methods

[00114] The following subsections describe lithographic etching techniques that can be used in the fabrication methods described above.

8.1 Resist properties

[00115] One form of photolithographic processing in accordance with the present disclosure begins with the coating of a resist layer over the layer of material to be patterned. Resists used to form this resist layer are typically comprised of organic polymers applied from a solution. In some embodiments, this resist layer has a thickness in the range of 0.1 μιη to 2.0 um. Furthermore, in some embodiments, the resist layer has a uniformity of plus or minus 0.01 μιη. In some embodiments, the resist layer is applied using a spin technique such as a static spin process or a dynamic dispense process. In some embodiments, the resist layer is applied using a manual spinner, a moving-arm resist dispenser, or an automatic spinner. See, for example, Van Zant, Microchip Fabrication, Forth Edition, McGraw-Hill, New York, 2000, pp. 217-222, which is hereby incorporated by reference herein in its entirety.

[00116] Negative resists. In some embodiments, the resist layer is an optical resist that is designed to react with ultraviolet or laser sources. In some embodiments, the resist layer is a negative resist in which polymers in the resist form a cross-linked material that is etch resistant upon exposure to light. Examples of negative resists that can be used to make the resist layer include, but are not limited to, azidelisoprene negative resists,

polymethylmethacrylate (PMMA), polymethylisopropyl ketone (PMIPK), poly-butene-1- sulfone (PBS), poly-(trifluoroethyl chloroacrylate) TFECA, copolymer-(V-cyano ethyl acrylate-V-amido ethyl acrylate) (COP), poly-(2 -methyl pentene-l-sulfone) (PMPS) and the like.

[00117] Positive resists. In other embodiments, the resist layer {e.g., positive resist layer of Fig. 2A) is a positive resist. The positive resist is relatively unsoluble. After exposure to the proper light energy, the resist converts to a more soluble state. This reaction is called photosobulization. One positive photoresist in accordance with the present disclosure is the phenol-formaldehyde polymer, also called phenol-formaldehyde novolak resin. See, for example, DeForest, Photoresist: Materials and Processes, McGraw-Hill, New York, 1975, which is hereby incorporated by reference herein in its entirety. In some embodiments, the resist layer is LOR OSA, LOR 5 0.7A, LOR 1A, LOR 3A, or LOR 5A (MICROCHEM, Newton, Massachusetts). LOR lift-off resists use polydimethylglutarimide.

8.2 Baking

[00118] After the resist layer has been applied, the density is often insufficient to support later processing. Accordingly, in some embodiments of the present disclosure, a bake is used to densify the resist layer and drive off residual solvent. This bake is referred to as a softbake, prebake, or post-apply bake. Several methods of baking the resist layer are contemplated by the present disclosure including, but not limited to, convection ovens, infrared ovens, microwave ovens, or hot plates. See, e.g, Levinson, Principles of

Lithography, SPIE Press, Bellingham, Washington, 2001, pp. 68-70, which is hereby incorporated by reference herein in its entirety. 8.3 Alignment and exposure of the mask

[00119] After the spacer has been coated with a resist layer, the next step is alignment and exposure of the resist layer. Alignment and exposure is, as the name implies, a two- purpose photomasking step. The first part of the alignment and exposure step is the positioning or alignment of the required image on the material surface. The image is found on a mask. The second part is the encoding of the image in the resist layer from an exposing light or radiation source. In the present disclosure, any conventional alignment system can be used to align the mask with the resist layer, including but not limited to, contact aligners, proximity aligners, scanning projection aligners, steppers, step and scan aligners, x-ray aligners, and electron beam aligners. For a review of aligners that can be used in the present disclosure, see, e.g., Solid State Technology, April 1993, p. 26; and Van Zant, Microchip Fabrication, Fourth Edition, McGraw-Hill, New York, 2000, pp. 232-241, each of which in incorporated herein by reference in its entirety. Masks can be negative or positive.

[00120] A positive mask (not shown) used to develop a positive resist would have the opposite pattern of a negative mask. Both negative masks and positive masks used in the methods of the present disclosure are fabricated with techniques similar to those used in wafer processing. A photomask blank, consisting of an opaque film (usually chromium) deposited on glass substrates, is covered with resist. The resist is exposed according to the desired pattern, is then developed, and the exposed opaque material etched. Mask patterning is accomplished primarily by means of beam writers, which are tools that expose mask blanks according to suitably formatted biosensor electrode patterns. In some embodiments, electron or optical beam writers are used to pattern negative masks or positive masks. See, e.g., Levison, Principles of Lithography, SPIE Press, Bellingham, Washington, 200 1, pp. 229- 256, which is hereby incorporated by reference herein in its entirety.

[00121] In one embodiment of the present disclosure, the tool used to project the pattern of a mask onto a solar cell unit is a wafer stepper. Wafer steppers exist in two configurations, step-and-repeat and step-and-scan. In a step-and-repeat system, the entire area of the mask to be exposed is illuminated when a shutter is opened. In a step-and scan system, only part of the mask, and therefore only part of the exposure field on the device unit, is exposed when a shutter is opened. The entire field is exposed by scanning mask and the device being patterned synchronously. See, e.g., Levison, Principles of Lithography, SPIE Press, Bellingham, Washington, 200 1, pp. 1 33- 174, which is hereby incorporated by reference herein in its entirety.

8.4 Development

[00122] After exposure through a mask, the pattern is coded as a latent image in resist as regions of exposed and unexposed resist. The pattern is developed in the resist by chemical dissolution of the unpolymerized resist regions. A number of development techniques can be used to develop the resist. Development techniques are designed to leave in the resist layer an exact copy of the pattern that was on the mask or reticle. The successful development of the image coded in resist is dependent on the nature of the resist's exposure mechanisms.

[00123] Negative resist, upon exposure to light, goes through a process of

polymerization which renders the resist resistant to dissolution in the developer chemical. The dissolving rate between the two regions is high enough so that little of the layer is lost from the polymerized regions. The chemical preferred for many negative -resist-developing situations is xylene or Stoddart solvent. The development step is done with a chemical developer followed by a rinse. For negative resists, the rinse chemical is n-butyl acetate in some embodiments.

[00124] Positive resists present a different developing condition. The two regions, polymerized and unpolymerized, have a different dissolving rate. This means that during the developing step some resist is always lost from the polymerized region. Use of developers that are too aggressive or that have overly long developing times result in an unacceptable thinning of the resist. Two types of chemical developers used with positive resists in accordance with the present disclosure are alkaline-water solutions and nonionic solutions. The alkaline -water solutions can be sodium hydroxide or potassium hydroxide. Typical nonionic solutions include, but are not limited to, tetramethylamrnonimurn hydroxide (TMAH). The rinse chemical for positive-resist developers is water. A rinse is used for both positive and negative resists. This rinse is used to rapidly dilute the developer chemical to stop the developing action.

[00125] There are several methods in which a developer is applied to resist in order to develop the latent image. Such methods include, but are not limited to, immersion, spray development, and puddle development. In some embodiments of the present disclosure, wet development methods are not used. Rather, a dry (or plasma) development is used. In such dry processes, a plasma etcher uses energized ions to chemically dissolve away either exposed or unexposed portions of the resist layer without first developing the resist layer using wet chemical techniques.

8.5 Hard baking

[00126] In some embodiments of the present disclosure, resist is hard baked after it has been developed. The purpose of the hard bake is to achieve good adhesion of the resist layer to the underlying layer to be patterned. In some embodiments, a hard bake is accomplished using a convection oven, in-line or manual hot plates, infrared tunneling ovens, moving-belt convection ovens, vacuum ovens and the like. General baking temperature and baking times are provided by the resist manufacture. Therefore, specific baking temperatures and times is application dependent. Nominal hard bake temperatures are from 130°C to 200°C for thirty minutes in a convection oven.

8.6 Etching

[00127] After development, an etching step is used for patterning. A number of etching methods are available.

[00128] Wet etching. In one embodiment of the present disclosure, the structure to be patterned is immersed in a tank of an etchant for a specific time. Then the structure is transferred to a rinse station for acid removal, and transferred to a station for final rinse and a spin dry step.

[00129] Wet spray etching or vapor etching. In some embodiments of the present disclosure, wet spray etching or vapor etching is used for patterning. Wet spray etching offers several advantages over immersion etching including the added definition gained from the mechanical pressure of the spray. In vapor etching, the wafer is exposed to etchant vapors such as hydro flowic acid vapors.

[00130] Plasma etching. In some embodiments of the present disclosure, plasma etching is used. Plasma etching is a chemical process that uses gases and plasma energy to cause the chemical reaction. Plasma etching is performed using a plasma etcher. Physically, a plasma etcher comprises a chamber, vacuum system, gas supply, and a power supply. The structure to be etched is loaded into the chamber and the pressure inside is reduced by the vacuum system. After the vacuum is established, the chamber is filled with the reactive gas. For the etching of silicon dioxide, for example, the gas is usually CF4 that is mixed with oxygen. A power supply creates a radio frequency (RF) field through electrodes in the chamber. The field energizes the gas mixture to a plasma state. In the energized state, the fluorine attacks the silicon dioxide, converting it into volatile components that are removed from the system by the vacuum system.

[00131] Any of a wide variety of plasma etchers is used to perform etching, in accordance with various embodiments of the present disclosure. Such etchers include, but are not limited to, barrel etchers, plasma planar systems, electron cyclotron resonance sources, high density reflected electron sources, helicon wave sources, inductively coupled plasma sources, and transformer coupled plasma sources.

[00132] Ion beam etching. Another type of etcher that is used to perform the etching of spacer 140 in accordance with various aspects of the present disclosure is ion beam etching. Unlike chemical plasma systems, ion beam etching is a physical process. The structure to be etched is placed on a holder in a vacuum chamber and a stream of argon is introduced into the chamber. Upon entering the chamber, the argon is subjected to a stream of high-energy electrons from a set of cathode (-)-anode (+) electrodes. The electrons ionize the argon atoms to a high-energy state with a positive charge. The wafers are held on a negatively grounded holder that attracts the ionized argon atoms. As the argon atoms travel to the wafer holder they accelerate, picking up energy. At the wafer surface, they crash into the exposed wafer layer and blast small amounts from the wafer surface. No chemical reaction takes place between the argon atoms and the wafer material. The material removal (etching) is highly directional (anisotropic), resulting in good definition in small openings.

[00133] Reactive ion etching. Yet another type of etcher that is used to perform the etching in some embodiments is a reactive ion etcher. A reactive ion etcher system combines plasma etching and ion beam etching principles. The systems are similar in construction to the plasma systems but have a capability of ion milling. The combination brings the benefits of chemical plasma etching along with the benefits of directional ion milling. See, e.g., Van Zant, Microchip Fabrication, Fourth Edition, McGraw-Hill, New York, 2000, pp. 256-270, for more information on etching techniques and etching equipment that can be used in accordance with the present disclosure. 8.7 Residual layer removal

[00134] The result of the etching process described above is the formation of grooves. Next, the residual layer is removed in a process known as resist stripping in order to yield the patterned structure. In some embodiments, the resist is stripped off with a strong acid such as H2SO4 or an acidoxidant combination, such as H₂S04-Cr₂03, attacking the resist but not the groove to yield the fully patterned structure. Other liquid strippers include organic solvent strippers (e.g., phenolic organic strippers and solventlamine strippers) and alkaline strippers (with or without oxidants). In some embodiments of the present disclosure, a dry plasma process is applied to remove a resist. In such embodiments, the device is placed in a chamber and oxygen is introduced. The plasma field energizes the oxygen to a high energy state, which, in turn, oxidizes the resist components to gases that are removed from the chamber by the vacuum pump. In dry strippers, the plasma is generated by microwave, radio frequency, or ultraviolet-ozone sources. More information on photolithographic processes that can be used to pattern devices is found in Madou, Fundamentals of Microfabrication, Second Edition, CRC Press, Boca Raton, Florida, 2002, pp. 2-65; and Van Zant, Microchip

Fabrication, Fourth Edition, McGraw-Hill, New York, 2000, each of which are hereby incorporated by reference herein in their entireties. Such methods include the use of a positive photoresist rather than a negative photoresist as well as extreme ultraviolet lithography, x-ray lithography, charged-particle-beam lithography, scanning probe lithography, soft lithography, and three-dimensional lithographic methods.

9. REFERENCES CITED

[00135] All references cited herein are incorporated herein by reference in their entirety and for all purposes to the same extent as if each individual publication or patent or patent application was specifically and individually indicated to be incorporated by reference in its entirety for all purposes.

[00136] Many modifications and variations of this disclosure can be made without departing from its spirit and scope, as will be apparent to those skilled in the art. The specific embodiments described herein are offered by way of example only, and the disclosure is to be limited only by the terms of the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

WHAT IS CLAIMED IS:

1. A method for fabricating a graphene based nanostructure comprising:

depositing a catalyst onto a substrate thereby forming a catalytic layer;

nanopatterning the catalytic layer thereby forming a nanotemplate; and

depositing graphene onto the nanotemplate thereby forming the graphene based nanostructure.

2. The method of claim 1, wherein the nanopatterning comprises:

depositing a layer of spacer film onto the catalytic layer, wherein the spacer film comprising a material unsuitable for graphene growth;

patterning the spacer film thereby exposing portions of the catalytic material layer.

3. The method of claim 1, wherein nanopatterning the catalytic layer comprises patterning the catalytic layer thereby exposing portions of the substrate.

4. The method of any one of claims 1-3, wherein the catalyst is platinum, iridium, ruthenium, nickel, or copper.

5. The method of any one of claims 1-4, wherein the graphene based nanostructure is a graphene nanoribbon or a graphene nanonetwork.

6. The method of any one of claims 1-5, wherein the substrate is glass, silocon, SiC, Si0₂ or SiC/Si.

7. The method of any one of claims 1-6, wherein the step of depositing graphene occurs through chemical vapor deposition.

8. The method of any one of claims 1-6, wherein the step of depositing graphene occurs through a process selected from the group consisting of molecular beam deposition, laser ablated deposition, collimated sputtering, vacuum evaporation, ionized physical vapor deposition, and ion beam deposition.

9. The method of any one of claims 1-8, wherein the graphene based structure comprises a nanohole superlattice comprising a plurality of sheets arranged on the catalytic layer, the plurality of sheets having an array of holes defined therein, wherein the graphene based structure is characterized by a band gap or a band gap range.

10. The method of claim 9, wherein the band gap range is between 0.1 eV and 2.2 eV.

11. The method of claim 9, wherein the first band gap range is between 0.1 eV and 0.8 eV.

12. The method of claim 9, wherein the first band gap range is between 0.5 eV and 2.2 eV.

13. The method of any one of claim 9-12, wherein a hole in the array of holes has a characteristic dimension that is in between 1 μιη and 10 mm.

14. The method of any one of claims 9-12, wherein a hole in the array of holes has a characteristic dimension that is between 50 μιη and 500 μιη.

15. The method of any one of claims 9-12, wherein a hole in the array of holes has a characteristic dimension that is between 100 μιη and 300 μιη.

16. The method of any one of claims 9-12, wherein a hole in the array of holes has a characteristic dimension that is less than 5000 nm.

17. The method of any one of claims 9-12, wherein a hole in the array of holes has a characteristic dimension that is less than 1000 nm.

18. The method of any one of claims 9-12, wherein a hole in the array of holes has a characteristic dimension that is less than 500 nm.

19. The method of any one of claims 9-12, wherein a hole in the array of holes has a characteristic dimension that is less than 100 nm.

20. The method of any one of claims 9-12, wherein a hole in the array of holes has a characteristic dimension that is less than 50 nm.

21. The method of any one of claims 9-20, wherein a hole in the array of holes is

characterized by a cross-section that is circular, ovoid, triangular, rectangular, pentangular, or hexagonal.

22. The method of any one of claims 9-20, wherein a hole in the array of holes is

characterized by a cross-section that includes any combination of a linear portion, an arcuate portion, or a curved portion.

23. The method of any one of claims 9-22, wherein the array of holes has a nanohole density that is between 1 nanohole/ um² and 10⁶ nanoholes/μηι² in the plurality of sheets.

24. The method of any one of claims 9-22, wherein the array of holes has a nanohole density that is between 100 nanohole/ um² and 10⁵ nanoholes/μηι² in the plurality of sheets.

25. The method of any one of claims 9-22, wherein the array of holes has a nanohole density that is between 500 nanohole/ um² and 10⁵ nanoholes/μηι² in the plurality of sheets.

26. The method of any one of claims 9-22, wherein the array of holes has a nanohole density that is between 10 nanoholes/μηι² and 10⁵ nanoholes/μηι² in the plurality of sheets.

27. The method of any one of claims 9-22, wherein the array of holes has a nanohole density that is between 100 nanoholes/μηι² and 10⁴ nanoholes/μηι² in the plurality of sheets.

28. The method of any one of claims 1-8, wherein the graphene based structure comprises a plurality of stacks, the plurality of stacks lengthwise arranged on the catalytic layer, wherein each respective stack in the plurality of stacks comprises a corresponding plurality of graphene nanoribbons wherein (i) a first graphene nanoribbon in the corresponding plurality of nanoribbons is characterized by a first band gap or a first band gap range, the first graphene nanoribbon overlaying on a first portion of the catalytic layer,

(ii) a first optically transparent insulator overlaying the first nanoribbon, and

(iii) a second nanoribbon in the respective plurality of nanoribbons is characterized by a second band gap, the second nanoribbon overlaying the first insulator, wherein the first band gap is smaller than the second band gap.

29. The method of claim 28, wherein a nanoribbon of a stack in the plurality of stacks has a band gap that is between 0.1 eV and 2.2 eV.

30. The method of claim 28, wherein a first nanoribbon of a stack in the plurality of stacks has a band gap that is between 0.1 eV and 1.2 eV and a second nanoribbon of the stack has a band gap that is between 0.8 eV and 1.9 eV.

31. The method of claim 28, wherein a first nanoribbon of a stack in the plurality of stacks has a band gap that is between 0.5 eV and 1.5 eV, and a second nanoribbon of the stack has a band gap that is between 1.2 eV and 2.2 eV.

32. The method of claim 28, wherein the first nanoribbon of a stack in the plurality of stacks has a band gap that is between 0.8 eV and 1.8 eV, and a second nanoribbon of the stack has a band gap that is between 1.5 eV and 2.2 eV.

33. The method of any one of claims 28-32, wherein a nanoribbon of a stack in the plurality of stacks has a width that is between 1 nm and 60 nm.

34. The method of any one of claims 28-32, wherein a first nanoribbon of a stack in the plurality of stacks has a width that is between 20 nm and 50 nm, and a second nanoribbon of the stack has a width that is between 1 nm to 30 nm.

35. The method of any one of claims 28-32, wherein a first nanoribbon of a stack in the plurality of stacks has a width that is between 30 nm and 40 nm, and a second nanoribbon of the stack has a width that is between 10 nm to 20 nm.

36. The method of any one of claims 28-32, wherein a first nanoribbon of a stack in the plurality of stacks has a width that is between 5 nm and 20 nm, and a second nanoribbon of the stack has a width that is between 1 nm to 10 nm.

37. The method of claim any one of claims 28-32, wherein the plurality of graphene nanoribbons in a stack in the plurality of stacks consists of between 1 and 300 graphene nanoribbon sheets.

38. The method of claim any one of claims 28-32, wherein the plurality of graphene nanoribbons in a stack in the plurality of stacks consists of between 100 and 300 graphene nanoribbon sheets.

39. The method of claim 28, wherein

the first graphene nanoribbon in the corresponding plurality of nanoribbons has a width that is between 25 nm and 50 nm,

the second nanoribbon in the respective plurality of nanoribbons has a width that is between 15 nm to 40 nm, and

a third nanoribbon in the respective plurality of nanoribbons has a width that is between 1 nm to 20 nm.

40. The method of claim 28, wherein

the first graphene nanoribbon in the corresponding plurality of nanoribbons has a width that is between 35 nm and 45 nm,

the second nanoribbon in the respective plurality of nanoribbons has a width that is between 20 nm to 30 nm, and

a third nanoribbon in the respective plurality of nanoribbons has a width that is 5 nm to 15 nm.

41. The method of any one of claims 1-40, further comprising

depositing an antireflection layer on all or a portion of the graphene based nanostructure.

42. The method of claim 41, wherein the antireflection layer comprises Si0₂ or Ti0₂.