WO2014019071A1 - Émetteur numérique doherty avec largeur de bande étendue - Google Patents

Émetteur numérique doherty avec largeur de bande étendue Download PDF

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Publication number
WO2014019071A1
WO2014019071A1 PCT/CA2013/000678 CA2013000678W WO2014019071A1 WO 2014019071 A1 WO2014019071 A1 WO 2014019071A1 CA 2013000678 W CA2013000678 W CA 2013000678W WO 2014019071 A1 WO2014019071 A1 WO 2014019071A1
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WIPO (PCT)
Prior art keywords
digital
output
doherty
input
signal
Prior art date
Application number
PCT/CA2013/000678
Other languages
English (en)
Inventor
Fadhel Ghannouchi
Ramzi Darraji
Original Assignee
Fadhel Ghannouchi
Ramzi Darraji
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/563,621 external-priority patent/US8837629B2/en
Application filed by Fadhel Ghannouchi, Ramzi Darraji filed Critical Fadhel Ghannouchi
Priority to CN201380051036.6A priority Critical patent/CN104704747B/zh
Priority to SE1550180A priority patent/SE541265C2/en
Priority to CA2880734A priority patent/CA2880734A1/fr
Publication of WO2014019071A1 publication Critical patent/WO2014019071A1/fr
Priority to HK15112168.4A priority patent/HK1211391A1/xx

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B1/0475—Circuits with means for limiting noise, interference or distortion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B1/0483—Transmitters with multiple parallel paths
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/36—Modulator circuits; Transmitter circuits
    • H04L27/366—Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator
    • H04L27/367—Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator using predistortion
    • H04L27/368—Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator using predistortion adaptive predistortion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B2001/0408—Circuits with power amplifiers
    • H04B2001/0425—Circuits with power amplifiers with linearisation using predistortion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2614—Peak power aspects
    • H04L27/2623—Reduction thereof by clipping

Definitions

  • the present invention relates generally to digital Doherty transmitters, and, more particularly to an extended bandwidth digital Doherty transmitter.
  • a popular power amplification architecture for enhancing the efficiency at backed-off output power region is the Doherty amplifier architecture.
  • a Doherty amplifier is composed of: 1) one main amplifier (commonly denoted as carrier amplifier) that is operating in class- AB and performing signal amplification for all input signal levels, 2) at least one auxiliary amplifier (commonly denoted as peaking amplifier) that is operating in class-C and performing signal amplification starting from a predefined signal level, 3) an input analog power divider for splitting the input signal between the carrier amplifier and the peaking amplifier(s), 4) a non-isolated Doherty output power combiner for combining the outputs of the carrier amplifier and the peaking amplifier(s) which includes quarter wavelength transformers, and 5) 50 Ohms lines inserted at the input of the peaking amplifiers and/or carrier amplifier to balance the delay between the branches of the Doherty amplifier.
  • a non-isolated power combiner initiates an active load modulation mechanism that is based on dynamically changing the load presented to the carrier amplifier through the impedance modulation triggered by the peaking amplifier(s). This allows the carrier amplifier to operate efficiently until it reaches its optimal load while the peaking amplifier(s) is/are simultaneously contributing to the output power of the Doherty amplifier.
  • the two-stage Doherty amplifier which consists of one carrier amplifier and one peaking amplifier; and, the three-stage Doherty amplifier which consists of one carrier amplifier and two peaking amplifiers are the most used architectures in Doherty based RF transmitters.
  • Practical implantations of four-stage and higher order-stage Doherty amplifiers are rare and not fully convincing in their performance. The main reasons are the rather complex design and the excessive costs of implementation for no significant performance improvement as compared to the two or three-stage Doherty amplifier architecture.
  • two-stage (three-stage) Doherty amplifier has two (three) maximum efficiency points located within a range of up-to 6 dB (12 dB) of output power back-off relatively to the saturation output power point.
  • This feature makes the two-stage and three-stage Doherty amplifiers the most suitable architectures for power amplification in 3rd generation and beyond wireless communications applications where the PAPR of the modulated signals is typically ranging between 6 and 12 dB.
  • two-stage Doherty amplifiers are more suitable when the PAPR is about or slightly higher than 6 dB and three-stage Doherty amplifiers when the PAPR of the signal is significantly higher that than 6 dB.
  • the achievement of such a superior performance requires a quasi-perfect load modulation mechanism which is not likely to happen in fully-analog implementations due to limitations related to inherent hardware impairments in the RF blocks of two-stage or three-stage Doherty amplifiers.
  • HEMT high electron-mobility transistor
  • GaN gallium nitride
  • Another problem related to the Doherty PA is the narrow bandwidth performance. Indeed, due to the need for using quarter-wavelength impedance transformers to design the output power combiner, the efficiency of the Doherty PA drops significantly as the frequency of operation shifts away from the design frequency of the Doherty PA ( o), which greatly limits its bandwidth.
  • a digital Doherty transmitter has a baseband signal processing block, the baseband signal processing block including a digital predistortion unit, an adaptive digital signal distribution unit and a digital phase alignment unit; a signal up-conversion block, an RF power amplification block, the RF power amplification block including the carrier amplifier and one or two peaking amplifiers; and an RF Doherty combining network, the topology of the RF Doherty combining network is predefined and it depends on the number of stages and the settings of turn-on points of the peaking amplifiers of the Doherty amplifier system .
  • a three-stage Doherty amplifier will be used. It is noted that a two-stage Doherty amplifier which includes one peaking amplifier may be considered in one sense a simple and special case of three-stage Doherty amplifier architecture that has two peaking amplifiers.
  • a digital Doherty transmitter includes a baseband signal processing block, the baseband signal processing block including a digital predistortion unit, an adaptive digital signal distribution unit and a digital phase alignment unit; a signal up-conversion block; a signal up-conversion block, the signal up-conversion block including three digital-to-analog converters (DACs) and a tri-channel up-converter or three single-channel up-converter; an RF power amplification block, the RF power amplification block including the carrier amplifier and two peaking amplifiers; and an RF Doherty combining network which includes quarter wavelength impedance transformers, the topology of the RF Doherty combining network is predefined and it depends on the number of stage , mode and order of operation of the Doherty amplifier.
  • DACs digital-to-analog converters
  • Figure 1 is a block diagram of the digital Doherty transmitter architecture according to an exemplary embodiment of the present invention.
  • Figure 2 is one embodiment illustrating a detailed block diagram of the architecture of Figure 1 , using a single tri-channel up-converter.
  • Figure 3 is an alternate embodiment illustrating a detailed block diagram of the architecture of Figure 1, using three single channel up-converters.
  • Figure 4 is an example of a possible signal distribution scheme of an exemplary embodiment of the present invention.
  • Figure 5 is an example of a possible phase alignment mechanism of an exemplary embodiment of the present invention.
  • Figure 6 is a block diagram of the prior art.
  • Figure 7 is an electrical diagram of the prior art.
  • Figure 8 is a graph illustrating the ideal output currents profile at the fundamental frequency of the circuit of Figure 7.
  • Figure 9 is an electrical diagram according to an exemplary embodiment of the present invention shown in Figure 2.
  • Figure 10 is a block diagram of the architecture according to an exemplary embodiment of the present invention where the RF power amplification block has only one peaking amplifier.
  • Figure 11 is another embodiment of the invention architecture shown in Figure 10, where the RF power amplification block has only one peaking amplifier, and a dual-channel up-converter.
  • Figure 12 is an electrical diagram according to an exemplary embodiment of the present invention shown in Figure 1 1.
  • Figure 13 is another possible block diagram of the architecture of Figure 10 where the RF power amplification block has only one peaking amplifier, and two single channel up- converters.
  • Figure 14 is a flowchart illustrating the steps of the execution of the digital adaptive signal distribution algorithm performed by Digital Signal Distribution Unit of the Baseband Processing Block.
  • Figure 15 is a flowchart illustrating the steps of the execution of the digital phase alignment algorithm for the Digital Phase Alignment Unit of the Baseband Processing Block.
  • FIG. 16 is a flowchart illustrating the steps of the execution of the digital predistortion (DPD) algorithm for the Digital Predistortion Unit of the Baseband Processing Block.
  • DPD digital predistortion
  • Figure 17 is a flowchart illustrating the steps of the Baseband Signal Processing Block of the present invention.
  • Figure 18 is a block diagram of the architecture when used in adaptive mode according to an embodiment of the present invention where high directivity couplers are used at the output of the RF power amplification block.
  • Figure 19 is a block diagram of the architecture of Figure 10, where high directivity couplers are used at the output of the RF power amplification block.
  • Figure 20 is the measured performance of the prior art compared to a practical implementation of an exemplary embodiment of the present invention.
  • Figure 21 is another measured performance of the prior art compared to a practical implementation of an exemplary embodiment of the present invention.
  • Figure 22 is a simulated performance of the prior art compared to a practical implementation of an exemplary embodiment of the present invention.
  • Figure 23 is the measured performance, in terms of spectrum, of a practical implementation of an exemplary embodiment of the present invention.
  • an embodiment of the present invention provides a multiple branch digital Doherty transmitter architecture and digital signal processing algorithms for impairments- free operation and linearized three-stage Doherty amplifier.
  • the baseband processing Block 20 For a given mode of operation of the digital Doherty transmitter and starting from an initial baseband signal, shown at QIN, corresponding to a given communication standard, the baseband processing Block 20 generates three different input baseband signals (II ,C/QI ,C , IIN, PI/QIN. PI , IIN, P2/Q1N, P2) so that, after up-conversion via Signal Up-Conversion Block 28 and RF power amplification via RF Power Amplification Block 44, the magnitudes of the currents at the input of the RF Doherty Combining Network 52 follow the ideal currents profile that is predefined depending on the mode of operation of the multiple stage Doherty transmitter.
  • the digital signal distribution unit 24 is implanted to adaptively distribute the available power between the input branches of the power amplification block 44 according to a specific power distribution scheme that is derived to ensure the quasi-ideal load modulation behavior at and beyond the nominal design frequency of Doherty PA.
  • Figure 4 shows an example of a possible signal distribution scheme executed at the digital signal distribution unit 24 of an exemplary embodiment of the present invention where the RF power amplification block has only one peaking amplifier.
  • the "Present Invention" graph line illustrates the digital Doherty transmitter, while the “Prior Art” graph line illustrates the state of the prior art.
  • the baseband signals generated at the digital signal distribution unit 24 are further updated to compensate for any phase misalignment resulting from the non-linear behavior of the devices.
  • the phase misalignment behavior is identified from the amplitude-dependent phase distortion (AM/PM) of the carrier amplifier and the (AM/PM) responses of the peaking amplifiers.
  • the characterization can be achieved by only driving one amplifier at a time with its specific input signal generated at the digital signal distribution unit 24 and collecting its corresponding amplified signal at the output of the digital Doherty transmitter.
  • the output RF signal is down-converted to baseband and benchmarked against the known driving input baseband signal which permits obtaining the AM/PM of the amplifier under test.
  • a static digital phase alignment is applied to the input baseband data at the input of each peaking branch to align the AM/PM response of the peaking amplifiers with that of the carrier amplifier.
  • an adaptive digital phase alignment is applied to the baseband data at the input of each branch to ensure that the AM/PM response of the carrier amplifier and those of the peaking amplifiers are overlapping at all time.
  • phase digital predistortion PDPD
  • PDPD phase digital predistortion
  • the digital phase alignment mechanism ensures the quasi-perfect active load modulation behavior (when the input signal is properly distributed at the digital signal distribution unit 24) and prevents the destructive power summation at the RF Doherty combining network.
  • the digital phase alignment mechanism prevents the destructive power summation at the RF Doherty combining network.
  • Both digital signal distribution unit and digital phase alignment unit ensure the quasi-perfect active load modulation behavior and impairments-free operation of the multiple (three) stage digital Doherty transmitter.
  • the digital predistortion is required. This can be achieved by considering the system that consists of ⁇ digital adaptive signal distribution unit + digital phase alignment unit 26+ signal up-conversion block 28+ RF power amplification block 44+ RF Doherty combining network 52 ⁇ as device-under-test (DUT). As such, the initial characterization and DPD model identification of the digital Doherty transmitter can be derived based on the initial input baseband signal and the equivalent baseband version of the RF signal at the output of the RF Doherty combining network 52.
  • a digital predistortion technique consisting of pre-processing an input baseband signal according to the complement of the transmitter response to compensate for its nonlinearity effects.
  • a complex function of the predistorter is determined while satisfying the following conditions:
  • / and g represent the complex nonlinear functions of the predistorter and the PA/transmitter, respectively.
  • G represents the small-signal gain of the Doherty amplifier.
  • the variables x, supplement and x out denote the input and output signals respectively. Both / and g are determined using baseband records at the input and output of the Doherty transmitter.
  • the digital Doherty amplifier/transmitter architecture includes a baseband signal processing block 20; a signal up-conversion block 28; an RF power amplification block 44; and an RF Doherty combining network 52, the topology of the RF Doherty combining network is predefined topologies and is depending on the mode of operation of the multiple branch digital Doherty amplifier/transmitter of the present invention.
  • the specific number of multiple branches n of the digital Doherty amplifier/transmitter of the present invention architecture is equal to one (carrier amplifier branch) plus the value n-1 which value equals the number of peaking amplifiers in a particular circuit.
  • the baseband signal processing block 20 includes a digital predistortion unit 22, an adaptive digital signal distribution unit 24 and a digital phase alignment unit 26.
  • the baseband signal processing block 20 is a set of digital signal processing algorithms best shown in Figure 17 that are implemented to ensure impairments-free and linear operation of multiple-stage Doherty amplifiers/transmitters at a given frequency of operation.
  • the baseband signal processing block 20 is a set of digital signal processing algorithms best shown in Figure 17 that are implemented to ensure impairments-free and linear operation of multiple-stage Doherty amplifiers/transmitters at a given frequency of operation.
  • the baseband signal processing block 20 is a set of digital signal processing algorithms best shown in Figure 17 that are implemented to ensure impairments-free and linear operation of multiple-stage Doherty amplifiers/transmitters at a given frequency of operation.
  • the baseband signal processing block 20 is a set of digital signal processing algorithms best shown in Figure 17 that are implemented to ensure impairments-free and linear operation of multiple-stage Doherty amplifiers/transmitters
  • digital predistortion unit 22 is best shown in Figure 16; the implementation of digital signal distribution unit 24 is best shown in Figure 14; the implementation of digital phase alignment unit 26 is best shown in Figure 15.
  • baseband signal processing block 20 allow for digital processing of digital signals, and for a digital signal output.
  • the digital predistortion unit 22 is an algorithm that takes the initial input digital baseband in-phase/ quadrature ( QIN) signal to generate the predistorted baseband digital signal (Ip re d/Qpred) intended to feed the digital adaptive signal separation unit 24 according to the equations stated above (see Figure 16).
  • the digital signal distribution unit 24 is an algorithm that is applied (according to Figure 14) to the digital baseband signal (Ipre d /Qpred) obtained from the digital predistortion unit 24 to generate the digital baseband signals (Ic/Qc), (IPI/QPI) and ( Qp 2 ) to ensure that, after up- conversion and RF power amplification, the magnitudes of the currents at the input of the RF Doherty combining network follow the ideal currents profile for the mode of operation of the multiple branch digital Doherty transmitter at and beyond the original design frequency of Doherty PA.
  • the baseband signal (7p re d/O.Pred) is adaptively split to compensate for the output RF power loss due to the frequency response of the output combiner for carrier frequencies of the baseband signal that are different from the original design frequency of the Doherty PA; and to ensure the quasi-ideal load modulation behavior at and beyond the original design frequency of the Doherty PA.
  • the digital signal distribution unit 24 can be implemented based on a set of finite impulse response (FIR) linear phase digital filters that are designed to ensure execution of the optimal signal separation at each frequency component of the transmit signal.
  • FIR finite impulse response
  • the digital phase alignment unit 26 is an algorithm (according to Figure 15) that is applied to the baseband signal (Ic/Qc), (Ipi/Qpi) and ( Qp2) to generate the baseband signals (IIN,C/QIN,C), ( ⁇ , ⁇ /QIN.PI) and (IIN,P2/QIN,P2) in order to compensate in digital domain for the phase imbalance problem.
  • the signal up-conversion block 28 may include first, second and third digital-to-analog converters (DACs) 30, 32, and 34, respectively, and a tri-channel up- converter 36.
  • the DACs 30, 32, 34 and the tri-channel up-converter 36 may be any digital-to-analog converters (DACs) 30, 32, and 34, respectively, and a tri-channel up- converter 36.
  • the DACs 30, 32, 34 and the tri-channel up-converter 36 may be any combination of the signals from the signal up-conversion block 28.
  • Each DAC 30, 32, 34 is an electrical device that converts the baseband streams (IIN,C/QIN,C), (IIN,PI/QIN,PI) and (IINWQIN.PI) obtained at the output of the baseband signal processing block 20 into continuous analog signals.
  • the tri-channel up-converter 30 is an electrical device that takes the low frequency input analog signals from the DACs 30, 32, 34 to produce the RF signals RF IN .
  • C from first single-channel up-converter 38
  • RF I ,PI from second single-channel up-converter 40
  • RF IN,P 2 from third single-channel up-converter 42
  • the signal up-conversion block 28 may include three digital-to-analog converters (DACs) 30, 32, 34, respectively, and first, second, and third single- channel up-converters 38, 40, 42, respectively.
  • the DACs 30, 32, 34 and the single-channel up- converter 38, 40, 42 may be any commercially available parts.
  • Each DAC 30, 32, 34 is an electrical device that converts the baseband streams (IIN,C/QIN,C), (IrN,pi/QiN,pi) and (I[N,PI/QIN,PI) obtained at the output of the baseband signal processing block 20 into continuous analog signals.
  • the up-converter 36 is an electrical device that takes the low frequency input analog signals from the DACs 30, 32, 34 to produce the RF signals RFr ⁇ c RFIN.PI and RF[N,p 2 that are feeding the input of the RF power amplification block 44.
  • the RF power amplification block 44 includes the carrier amplifier 46 and two peaking amplifiers 48 and 50.
  • the carrier amplifier 46 is an electrical device that amplifies the input radio frequency signal RF[N , C-
  • the two peaking amplifiers 48 and 50 are electrical devices that amplify the input radio frequency signals RFIN , PI and RF[N , P2-
  • the carrier amplifier 46 and peaking amplifiers 48 and 50 are implemented based on transistors and input and output matching networks.
  • the matching networks may be
  • the transistor of the carrier amplifier 46 and the transistors of the peaking amplifiers 48 and 50 are identical in size. In other possible configurations of the multiple stage/branch Doherty amplifier, the transistors of the carrier amplifier 46 and the transistors of the peaking amplifiers 48 and 50 have different sizes. For a given configuration of device's size ratio between the carrier device and peaking devices, there is predefined mode of operation and ideal output fundamental current profile describing the proper operation of the multiple stage/branch Doherty amplifier.
  • the Doherty combining network 52 compromises passive structures including quarter wavelength ⁇ /4)-transmission line impedance transformers as well as ⁇ /4-transmission line impedance inverters that are arranged according to a predefined configuration depending on the mode of operation of the multiple branch Doherty transmitter.
  • a three-stage digital Doherty transmitter shown generally at 18 includes an input analog power divider 43 which may be physically located in signal up conversion unit 28 or an RF power amplification unit 44, one carrier amplifier 46 and two peaking amplifiers 48 and 50 and an RF Doherty combining network 52.
  • the RF Doherty combining network 52 when the identical devices are used to implement the carrier amplifier and the peaking amplifiers includes four ⁇ /4- transmission lines 54, 56 (with characteristic impedances Zo 58 (with characteristic impedances Z 0 /2) and 60 (with characteristic impedances 1.73Z 0 ).
  • Z 0 62 is the output load impedance of the three-stage Doherty amplifier.
  • the ideal currents profile of a three-stage Doherty amplifier, the carrier amplifier 46 and the peaking amplifiers 48 and 50 of which are implemented using identical devices, are such that all output currents are aligned at peak power drive; and, the output current from the carrier amplifier is as twice as the output current of peaking amplifier 48 when peaking amplifier 50 turns ON.
  • Figure 9 shows an electrical diagram according to an exemplary embodiment of the present invention in which the carrier amplifier 46 and the peaking amplifiers 48 and 50 are built using identical devices.
  • the digital Doherty transmitter may further or alternatively include a first, second, and/or third high-directivity coupler 68, 70, 72, respectively, at the out of the carrier amplifier 46 and at the output of each of the peaking amplifiers 48 and 50.
  • the high directivity coupler 68, 70, 72 may be built using passive coupling based structure and embedded within the output matching network of each of the amplifiers of the RF power amplification block 44.
  • the high directivity coupler 68, 70, 72 is used to probe a sample of the output signals of amplifiers in order to: first, continuously monitor their AM PM responses that may vary with time; and, second, update the input signals as needed.
  • Figure 20 shows the measured power efficiency performance of a practical implementation of an exemplary embodiment of the Present Invention operating at the nominal design frequency where the RF power amplification block has only one peaking amplifier and where only digital phase alignment is applied.
  • Figure 21 shows the measured power efficiency performance of the analog Doherty prior art compared to a practical implementation of an exemplary embodiment of the Present Invention (the digital Doherty transmitter of the present invention) operating at the nominal design frequency where the RF power amplification block has only one peaking amplifier and where only digital adaptive power distribution was applied.
  • Figure 22 shows the simulated power efficiency versus frequency performance of the analog Doherty prior art compared to an implementation of an exemplary embodiment of the Present Invention (the digital Doherty transmitter of the present invention) where the RF power amplification block has only one peaking amplifier and where digital adaptive power distribution and digital phase alignment was are applied.
  • Figure 23 shows the measured performance, in terms of spectrum of a practical implementation of an exemplary embodiment of the present invention operating at the original design frequency where the RF power amplification block has only one peaking amplifier and where digital predistortion and digital adaptive power distribution are applied.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)

Abstract

Un émetteur numérique Doherty avec largeur de bande étendue comprend un bloc de traitement de signaux de bande de base comprenant une unité numérique de pré-distorsion. Il comprend également une unité numérique de distribution de signaux et une unité numérique d'alignement de phase, un bloc de sur-conversion de signaux, un bloc d'amplification de puissance RF comprenant l'amplificateur de porteuse et un ou deux amplificateurs de crête ; et un réseau de combinaison Doherty RF. Dans un autre aspect, un émetteur numérique Doherty comprend un bloc de signaux de bande de base comprenant une unité numérique de pré-distorsion, une unité numérique de distribution de signaux et une unité numérique adaptative d'alignement de phase. Dans cet aspect, un bloc de sur-conversion de signaux comprend trois convertisseurs numériques-analogiques (CNA) et un sur-convertisseur à trois canaux ou trois sur-convertisseurs à un seul canal. Ledit émetteur comprend également un bloc d'amplification de puissance RF comprenant l'amplificateur de porteuse et deux amplificateurs de crête, et un réseau de combinaison Doherty RF qui comprend des transformateurs d'impédance en quart d'onde.
PCT/CA2013/000678 2012-07-31 2013-07-31 Émetteur numérique doherty avec largeur de bande étendue WO2014019071A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201380051036.6A CN104704747B (zh) 2012-07-31 2013-07-31 扩展带宽的数字多尔蒂发射机
SE1550180A SE541265C2 (en) 2012-07-31 2013-07-31 Extended bandwidth digital doherty transmitter
CA2880734A CA2880734A1 (fr) 2012-07-31 2013-07-31 Emetteur numerique doherty avec largeur de bande etendue
HK15112168.4A HK1211391A1 (en) 2012-07-31 2015-12-09 Extended bandwidth digital doherty transmitter

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/563,621 US8837629B2 (en) 2011-05-11 2012-07-31 Extended bandwidth digital Doherty transmitter
US13/563,621 2012-07-31

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WO2014019071A1 true WO2014019071A1 (fr) 2014-02-06

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SE541265C2 (en) 2019-05-28
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CA2880734A1 (fr) 2014-02-06
CN104704747B (zh) 2017-08-25

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