WO2014008678A1 - 太阳能电池及其制作方法 - Google Patents

太阳能电池及其制作方法 Download PDF

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Publication number
WO2014008678A1
WO2014008678A1 PCT/CN2012/078820 CN2012078820W WO2014008678A1 WO 2014008678 A1 WO2014008678 A1 WO 2014008678A1 CN 2012078820 W CN2012078820 W CN 2012078820W WO 2014008678 A1 WO2014008678 A1 WO 2014008678A1
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substrate
solar cell
doped region
region
doped
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PCT/CN2012/078820
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English (en)
French (fr)
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陈芃
梁硕玮
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友达光电股份有限公司
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Publication of WO2014008678A1 publication Critical patent/WO2014008678A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H01L31/022458—Electrode arrangements specially adapted for back-contact solar cells for emitter wrap-through [EWT] type solar cells, e.g. interdigitated emitter-base back-contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/065—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the graded gap type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a solar cell and a method of fabricating the same, and more particularly to an interdigitated back electrode solar cell (ICC solar cell) having a selective emitter and a method of fabricating the same.
  • ICC solar cell interdigitated back electrode solar cell
  • a solar cell is a photoelectric conversion component that converts solar energy into electrical energy.
  • Today when petroleum resources are depleted, it is expected to be the most potential alternative energy source.
  • solar energy technology is still limited by high production cost, complicated process and poor photoelectric conversion efficiency, so the development of solar energy is still waiting for a breakthrough. Summary of the invention
  • One of the objects of the present invention is to provide a solar cell and a method of fabricating the same to improve photoelectric conversion efficiency.
  • a preferred embodiment of the present invention provides a method of fabricating a solar cell comprising the following steps.
  • a substrate is provided, wherein the substrate has a first surface and a second surface, and the first surface is opposite the second surface.
  • the first exposed area has a first size.
  • the first patterned doped stack structure includes a first dielectric layer, a first doped layer and a second dielectric layer stacked on each other, and the first doped layer includes a plurality of first doping types
  • a dopant layer is disposed between the first dielectric layer and the second dielectric layer, the first dielectric layer has a gap, and the first doped layer is in contact with the second surface of the substrate via the gap.
  • the second doped layer contacts the second surface exposed by the first exposed region, the second doped layer includes a plurality of second dopants having a second doping type, and the first doping type is opposite to the second doping Miscellaneous type.
  • Performing a diffusion process driving the first dopant of the first doped layer into the second surface of the substrate to form a first lightly doped region and a first heavily doped region in the first masking region, and The second dopant of the second doped layer is driven into the second surface of the substrate to form a second heavily doped region in at least a portion of the first exposed region.
  • Removing a portion of the first patterned doped stack structure to form a storm A first contact hole of the first heavily doped region is exposed, and a portion of the second doped layer is removed to form a second contact hole exposing the second heavily doped region.
  • the resistance of the first lightly doped region is substantially greater than ⁇ ⁇ ⁇ /port
  • the resistance of the first heavily doped region is substantially less than 50 ⁇ / ⁇
  • the second heavily doped region is substantially less than 50 ⁇ / mouth.
  • the method further includes performing a roughening process to form the roughened surface of the first surface of the substrate.
  • the method further includes forming an anti-reflection layer on the first surface of the substrate.
  • the substrate has the second doping type or the first doping type.
  • the thickness of the first dielectric layer is between 1 nm and 20 nm, and the thickness of the second dielectric layer is greater than 100 nm.
  • the method further includes forming a third dielectric layer on the second doped layer before performing the diffusion process.
  • the thickness of the third dielectric layer is greater than 100 nanometers.
  • the method further includes forming a fourth dielectric layer on the first patterned doped stack structure and the second surface of the substrate before forming the second doped layer, wherein the fourth dielectric layer package Covering the first patterned doped stack structure and shielding a portion of the first exposed region to form at least one second masking region and at least one second exposed region having a second dimension, the second doped layer contacting the The second surface of the substrate exposed by the second exposed area, and the second size is smaller than the first size.
  • the method further includes performing the diffusion process to drive the second dopants of the second doped layer into the second surface of the substrate to form a second lightly doped region in the second mask region, and The first heavily doped region is formed in the second exposed region.
  • the thickness of the fourth dielectric layer is between 1 nm and 20 nm.
  • a piece of resistance of the second lightly doped region is greater than 80 ⁇ / port.
  • a solar cell including a substrate, a first lightly doped region, a first heavily doped region, a second heavily doped region, and a first patterned doping.
  • a stack structure a second doped layer, a first electrode, and a second electrode.
  • the substrate has a first surface and a second surface, wherein the first surface is opposite to the second surface, and the first surface is a light incident surface.
  • the first lightly doped region is located within the substrate and adjacent to the second surface.
  • a first heavily doped region is located within the substrate and adjacent to the second surface, wherein the first The lightly doped region and the first heavily doped region have a first doping type.
  • the second heavily doped region is located within the substrate and adjacent to the second surface, wherein the second heavily doped region has a second doping type and the first doping type is opposite to the second doping type.
  • the first patterned doped stack structure is disposed on the second surface of the substrate and corresponds to the first lightly doped region and exposes the first heavily doped region and the second heavily doped region, wherein the first patterned doped stack structure A first dielectric layer, a first doped layer and a second dielectric layer are stacked on each other.
  • the second doped layer is on the first patterned doped stack structure and the second surface of the substrate, wherein the second doped layer exposes a portion of the first heavily doped region and a portion of the second heavily doped region.
  • the first electrode and the first patterned doped stack structure are electrically connected to the first heavily doped region exposed by the second doped layer.
  • the second electrode and the first patterned doped stack structure are electrically connected to the second heavily doped region exposed by the second doped layer.
  • a resistance of the first lightly doped region is greater than ⁇ ⁇ ⁇ / port
  • a resistance of the first heavily doped region is less than 50 ⁇ / ⁇
  • the second heavily doped region is less than 50 ⁇ / port.
  • the substrate has the second doping type or the first doping type.
  • the first surface of the substrate has a roughened surface.
  • the method further includes an anti-reflection layer disposed on the first surface of the substrate.
  • the thickness of the first dielectric layer is between 1 nm and 20 nm, and the thickness of the second dielectric layer is greater than 100 nm.
  • the method further includes a third dielectric layer disposed on the second doped layer.
  • the thickness of the third dielectric layer is greater than 100 nanometers.
  • the method further includes: a second lightly doped region located in the substrate adjacent to the second surface, wherein the second lightly doped region has the second doping type; and a fourth dielectric layer, coated
  • the first patterned doped stack structure covers the second lightly doped region.
  • the thickness of the fourth dielectric layer is between 1 nm and 20 nm.
  • a piece of resistance of the second lightly doped region is greater than 80 ⁇ / port.
  • the solar cell of the present invention is an interdigitated back electrode solar cell having a selective emitter structure, wherein the electrode is in contact with the heavily doped region of the substrate, thereby having a lower contact resistance, and the lightly doped region not in contact with the electrode has
  • the lower saturation current can reduce the recombination of electron-hole pairs while increasing the absorption of infrared rays, and increasing the photoelectric conversion efficiency.
  • the photoelectric conversion efficiency of the solar cell of the preferred embodiment of the present invention can be substantially increased by 0.5% to 0.6% after comparison with the photoelectric conversion efficiency of the conventional solar cell.
  • FIG. 1 to 7 are schematic views showing a method of fabricating a solar cell according to a first preferred embodiment of the present invention.
  • FIGS. 8 to 11 are schematic views showing a method of fabricating a solar cell according to a second preferred embodiment of the present invention.
  • Figure 12 is a schematic illustration of a solar cell of a comparative embodiment of the present invention.
  • substrate 101 first surface
  • second surface 12 first patterned doped stack junction
  • first dielectric layer 121A gap
  • first doped layer 123 second dielectric layer
  • first electrode 262 second electrode
  • a substrate 10 is first provided.
  • the substrate 10 may include a silicon substrate such as a single crystal silicon substrate or a polycrystalline silicon substrate or the like, and the thickness of the substrate 10 is, for example, between about 50 micrometers and 300 micrometers, but not limited thereto.
  • Substrate 10 can be other various types of semiconductor substrates.
  • the substrate 10 has a first surface 101 and a second surface 102, wherein the first surface 101 and the second surface 102 are opposite each other, and the first surface 101 is a light incident surface.
  • the substrate 10 can be subjected to a saw damage removal (SDR) process, such as cleaning the substrate 10 with an acidic solution or an alkaline solution to remove the minor damage caused by the cutting to the substrate 10.
  • SDR saw damage removal
  • a first patterned doped stack structure 12 is formed on the second surface 102 of the substrate 10 and exposes a portion of the second surface 102 of the substrate 10, as shown in FIG.
  • the method of forming the first patterned doped stack structure 12 is as shown in the method disclosed in FIG. 2 to FIG. 4, but is not limited thereto.
  • a first dielectric layer 121 is formed on the second surface 102 of the substrate 10, and the first dielectric layer 121 is patterned so that the first dielectric layer 121 has a notch 121A, which is exposed.
  • the first dielectric layer 121 may be a single layer or a multilayer structure, and its material may include silicon oxide, silicon oxynitride, or silicon nitride, but may also be, for example, alumina or other organic or inorganic dielectric material.
  • the thickness of the first dielectric layer 121 may be, for example, substantially between 1 nm and 20 nm, but is not limited thereto.
  • the first dielectric layer 121 can be formed by a chemical vapor deposition (CVD) process, such as an atmospheric pressure chemical vapor deposition (APCVD) process, and patterned by, for example, an etching process, but is not limited thereto.
  • CVD chemical vapor deposition
  • APCVD atmospheric pressure chemical vapor deposition
  • the first dielectric layer 121 can also be fabricated by, for example, a physical vapor deposition process, a spin coating process, an inkjet printing process, a screen printing process, or the like. As shown in FIG. 3, a first doped layer 122 is formed on the first dielectric layer 121 and the exposed second surface 102 of the substrate 10, wherein the first doped layer 122 is via the first dielectric layer
  • the notch 121A of the electrical layer 121 is in contact with the second surface 102 of the substrate 10. That is, the first doping layer 122 will cover the first dielectric layer 121 in addition to the second surface 102 in the notch 121A.
  • the first doped layer 122 includes a plurality of first dopants (different dopants or diffusers) having a first doping type.
  • the first doping type is p-type
  • the first doping layer 122 is borosilicate glass BSG
  • the first dopant is boron, but is not limited thereto.
  • a second dielectric layer 123 is formed on the first doping layer 122. That is, the second dielectric layer 123 covers the first doped layer 122.
  • the thickness of the second dielectric layer 123 is, for example, substantially greater than 100 nanometers, but is not limited thereto.
  • the second dielectric layer 123 may be a single layer or a multilayer structure, and its material includes silicon oxide, silicon oxynitride or silicon nitride, but may also be, for example, alumina or other organic or inorganic dielectric material.
  • the second dielectric layer 123 can be fabricated by a chemical vapor deposition process, such as an atmospheric pressure chemical vapor deposition process. However, it is not limited thereto, such as a physical vapor deposition process, a spin coating process, an inkjet printing process, a screen printing process, and the like. As shown in FIG.
  • the second dielectric layer 123, the first doping layer 122, and the first dielectric layer 121 are patterned, and a portion of the second dielectric layer 123, the first doping layer 122, and the first dielectric layer are removed.
  • Electrical layer 121 forms a first patterned doped stack structure 12.
  • the step of patterning the second dielectric layer 123, the first doping layer 122 and the first dielectric layer 121 can be implemented by an etching process, but is not limited thereto. In other embodiments, the steps of patterning the second dielectric layer 123, the first doping layer 122, and the first dielectric layer 121 can be formed by a screen printing method or an inkjet method without requiring exposure and development. Step.
  • the first patterned doped stack structure 12 exposes a portion of the second surface 102 of the substrate 10 and covers a portion of the second surface 102 of the substrate 10, wherein the second surface 102 of the first patterned doped stack structure 12 forms at least A first masking region 12S, and the second surface 102 exposed by the first patterned doped stack structure 12 forms at least one first exposed region 12E, and the first exposed region 12E has a first size. It should be noted that the notch 121A is substantially located in the first shielding area 12S.
  • a second doped layer 14 is formed and covered on the first patterned doped stacked structure 12 and the second surface 102 of the substrate 10, wherein the second doped layer 14 contacts the first exposed region 12E.
  • the second doped layer 14 includes a plurality of second dopants having a second doping type, and the first doping type is opposite to the second doping type.
  • the second doping type is n-type
  • the second doping layer 14 is a phosphosilicate glass (PSG)
  • the second dopant is phosphorus, but is not limited thereto.
  • a third dielectric layer 16 can be selectively formed on the second doped layer 14.
  • the third dielectric layer 16 may be a single layer or a multilayer structure, and its material may include silicon oxide, silicon oxynitride, or silicon nitride, but may be, for example, aluminum oxide or other organic or inorganic dielectric material.
  • the thickness of the third dielectric layer 16 is, for example, substantially greater than 100 nanometers, but is not limited thereto.
  • the third dielectric layer 16 can be fabricated by a chemical vapor deposition process, such as an atmospheric pressure chemical vapor deposition process, but can also be fabricated by other suitable processes, such as physical vapor deposition processes, spin coating processes, inkjet printing. Process, screen printing process, etc.
  • the third dielectric layer 16 is used to provide good insulation of the solar cell, and to avoid the poor performance of the solar cell due to the leakage current of the positive and negative electrodes. Therefore, the selection of the material, process and thickness of the third dielectric layer 16 should be based on its insulating effect. Further, a roughening process is performed to form a textured surface of the first surface 101 of the substrate 10 to increase the amount of light incident.
  • a diffusion process is subsequently performed to drive the first dopant of the first doped layer 122 into the second surface 102 of the substrate 10 to form a first doping type in the first masking region 12S.
  • a first lightly doped region 18L and a first heavily doped region 18H, and a second dopant of the second doped layer 14 are driven into the substrate
  • a second heavily doped region 20H having a second doping type is formed in the second surface 102 of the bottom 10 in at least a portion of the first exposed region 12E.
  • the diffusion process referred to herein means that the substrate 10 is located in a high temperature environment, and the first dopant and the second dopant in the above structure are respectively diffused into a predetermined region in the substrate 10.
  • this diffusion process can be referred to as tempering or annealing.
  • the first dielectric layer 121 can slow down the diffusion speed and have a diffusion barrier effect. Therefore, in the diffusion process, the substrate 10 corresponding to the notch 121A of the first dielectric layer 121 forms the first heavily doped region 18H. That is, in the diffusion process, more of the first dopant enters the substrate 10 not covered by the first dielectric layer 121, thereby forming the first heavily doped region 18H having a higher doping concentration. In addition, under the diffusion barrier effect of the first dielectric layer 121, less first dopants may enter the substrate 10 covered by the first dielectric layer 121, thereby forming a first light having a lower doping concentration. Doped region 18L.
  • the surface doping concentration of the first heavily doped region 18H is generally preferably between 10 19 atoms/cm 3 and 10 21 atoms/cm 3
  • the first lightly doped region 18L The surface doping concentration is generally preferably between 10 18 atoms/cm 3 and 10 19 atoms/cm 3 , but is not limited thereto.
  • the sheet resistance of the first heavily doped region 18H or the sheet resistance is generally less than 50 ⁇ / ⁇ , and the sheet resistance of the first lightly doped region 18L is generally greater than ⁇ ⁇ ⁇ / ⁇ , but not This is limited to this.
  • the main function of the first dielectric layer 121 of the first patterned doped stack structure 12 is to control the sheet resistance of the first heavily doped region 18H and the sheet resistance of the first lightly doped region 18L, thus
  • the first dielectric layer 121 may be formed by a suitable material and process, and the thickness of the first dielectric layer 121 may be adjusted to ensure that the first heavily doped region 18H and the first lightly doped region 18L have a predetermined after diffusion process. Chip resistance.
  • the first patterned doped stack structure 12 also has the effect of a diffusion barrier, so in the diffusion process, the substrate 10 corresponding to the first exposed region 12E not covered by the first patterned doped stacked structure 12 A second heavily doped region 20 ⁇ is formed therein.
  • the second dopant enters the substrate 10 of the first exposed region 12E that is not covered by the first patterned doped stacked structure 12, thereby forming a second heavily doped with a higher doping concentration. Miscellaneous area 20 ⁇ .
  • the second dielectric layer 123 of the first patterned doped stacked structure 12 is used to avoid mutual doping between the first doped layer 122 and the second doped layer 14, and therefore the material, process and thickness should be selected. It is considered that the effect of avoiding mutual doping of the first doping layer 122 and the second doping layer 14 is achieved.
  • the second dielectric layer 123 in the diffusion process, no second dopant or only a second dopant having a negligible amount/concentration may enter the first patterned doped stack structure 12
  • the first masking region 12S covered, that is, the second dopant does not enter the first heavily doped region 18H and the first lightly doped region 18L as much as possible, so the first heavily doped region 18H and the first Doping concentration ratio of a lightly doped region 18L It is less affected by the influence of the second dopant.
  • the surface doping concentration of the second heavily doped region 20H is generally preferably between 10 19 atoms/cm 3 and 10 21 atoms/cm 3 , and the second heavily doped region 20H
  • the sheet resistance is generally less than 50 ⁇ / port, but not limited to this.
  • the first lightly doped region 18L and the first heavily doped region 18H have a first doping type
  • the second heavily doped region 20H has a second doping type.
  • the substrate 10 can be either a first doping type or a second doping type depending on the design of the solar cell.
  • the method for fabricating a solar cell of the present embodiment can simultaneously form the first lightly doped region 18L having the first doping type and the first heavily doped region 18H, and have the second doping, using only a single diffusion process.
  • an anti-reflection layer 22 is formed on the first surface 101 of the substrate 10.
  • the anti-reflection layer 22 is formed on the first surface 101 of the substrate 10 in a conformal conformal manner; therefore, the anti-reflection layer 22 also has a roughened surface.
  • the anti-reflection layer 22 increases the amount of light entering the solar cell.
  • the anti-reflective layer 22 may be a single layer or a multilayer structure, and the material thereof may be, for example, silicon nitride, silicon oxide, or silicon oxynitride, or other suitable materials, and may be, for example, a plasma enhanced chemical vapor deposition (PECVD). The process is formed, but not limited to this.
  • a portion of the third dielectric layer 16 and a portion of the first patterned doped stack structure 12 are then removed to form a first contact hole 241 exposing the first heavily doped region 18H, and A portion of the third dielectric layer 16 and a portion of the second doped layer 14 are formed to form a second contact hole 242 exposing the second heavily doped region 20H.
  • a first electrode eg, an anode
  • a second electrode electrically connected to the solar cell 30 of the present embodiment is fabricated.
  • the first electrode 261 and the first heavily doped region 18H form a selective emitter structure
  • the second electrode 262 and the second heavily doped region 20H also form a selective emitter structure.
  • the material of the first electrode 261 and the second electrode 262 may be, for example, a metal or an alloy, or other suitable electrically conductive material.
  • the solar cell of the present invention and the method of fabricating the same are not limited to the above embodiments.
  • solar cells of other preferred embodiments of the present invention and a method of fabricating the same will be sequentially described, and in order to facilitate comparison of the differences of the embodiments and simplify the description, the same symbols are used to mark the same in the following embodiments.
  • the components are mainly described with respect to the differences of the embodiments, and the repeated portions are not described again.
  • FIG. 8 to FIG. 11 are schematic views showing a method of fabricating a solar cell according to a second preferred embodiment of the present invention.
  • the method of fabricating a solar cell of this embodiment is carried out following the method of FIG. As shown in FIG. 8, forming a first patterned doping stack After the structure 12, a fourth dielectric layer 15 is formed on the first patterned doped stacked structure 12 and the second surface 102 of the substrate 10, and the fourth dielectric layer 15 is patterned such that the fourth dielectric layer 15 is packaged.
  • the first patterned doped stack structure 12 is covered and a portion of the first exposed region 12E is shielded to form at least one second masking region 12S' and at least one second exposed region 12E'.
  • the second exposed area 12E' has a second size, and the second size of the second exposed area 12E' is substantially smaller than the first size of the first exposed area 12E. That is, the second exposed region 12E' is located within the first exposed region 12E.
  • the fourth dielectric layer 15 may be a single layer or a multilayer structure, and its material includes silicon oxide, silicon oxynitride or silicon nitride, but may also be, for example, alumina or other organic or inorganic dielectric material.
  • the thickness of the second dielectric layer 123 is, for example, substantially greater than 100 nanometers, and the thickness of the fourth dielectric layer 15 is, for example, substantially between 1 nanometer and 20 nanometers, but not limited thereto.
  • the fourth dielectric layer 15 can be fabricated by a chemical vapor deposition process, such as an atmospheric pressure chemical vapor deposition process, but can also be fabricated by other suitable processes, such as physical vapor deposition processes, spin coating processes, inkjet printing. Process, screen printing process, etc.
  • a chemical vapor deposition process such as an atmospheric pressure chemical vapor deposition process
  • suitable processes such as physical vapor deposition processes, spin coating processes, inkjet printing. Process, screen printing process, etc.
  • a second doped layer 14 is formed over the second dielectric layer 15 and the second surface 102 of the substrate 10, wherein the second doped layer 14 is exposed to the second exposed region 12E'.
  • a third dielectric layer 16 is formed on the second doped layer 14. Further, a roughening process is performed to form the roughened surface of the first surface 101 of the substrate 10 to increase the amount of light incident.
  • a diffusion process is subsequently performed to drive the first dopant of the first doped layer 122 into the second surface 102 of the substrate 10 to form at least two first lightly doped layers in the first masking region 12S.
  • the impurity region 18L and the at least one first heavily doped region 18H drive the second dopant of the second doped layer 14 into the second surface 102 of the substrate 10 to form at least one second in the second exposed region 12E'
  • the heavily doped region 20H, and the second dopant of the second doped layer 14 are driven into the second surface 102 of the substrate 10 to form at least two second portions in the first exposed region 12E other than the second exposed region 12E' Lightly doped area 20L.
  • the above heavily doped region is located between the two light miscellaneous regions, but is not limited thereto.
  • the description of the name of the diffusion process for this embodiment can be referred to the aforementioned embodiment.
  • the fourth dielectric layer 15 of the embodiment covers a portion of the first exposed region 12, and the fourth dielectric layer 15 also has a diffusion barrier function, and thus is diffused.
  • a second heavily doped region 20H having a higher doping concentration is formed in the substrate 10 corresponding to the second exposed region 12E', and the second exposed region 12E' covered by the fourth dielectric layer 15 is formed.
  • a second lightly doped region 20L having a lower doping concentration is formed in the substrate 10 of the first exposed region 12E.
  • the surface doping concentration of the first heavily doped region 18H is generally preferably between 10 19 atoms/cm 3 and 10 21 atoms/cm 3
  • the first lightly doped region 18L Surface doping concentration
  • from 10 18 atom / cm 3 ⁇ 10 19 atom / cm 3 between the surface of the second heavily-doped region 20H generally preferred doping concentration between 10 19 atom / cm 3 ⁇ 10 21 atom / cm 3 of
  • the surface doping concentration of the second lightly doped region 20L is preferably between 10 18 atoms/cm 3 and 10 19 atoms/cm 3 , but not limited thereto.
  • the sheet resistance of the first heavily doped region 18H is generally less than 50 ⁇ / ⁇
  • the sheet resistance of the first lightly doped region 18L is generally greater than 80 ⁇ / ⁇
  • the sheet resistance of the second heavily doped region 20 ⁇ is substantially It needs to be less than 50 ⁇ / port
  • the sheet resistance of the second lightly doped region 20L is generally greater than 80 ⁇ / port, but not limited thereto.
  • the main function of the fourth dielectric layer 15 is to control the sheet resistance of the second heavily doped region 20A and the sheet resistance of the second lightly doped region 20L, so that a suitable material and process can be selected to produce the fourth.
  • Dielectric layer 15 is selected and a suitable thickness is selected to ensure that the second heavily doped region 20A and the second lightly doped region 20L will have a predetermined sheet resistance after the diffusion process.
  • an anti-reflection layer 22 is formed on the first surface 101 of the substrate 10. It can be seen from the above that the method for fabricating a solar cell of the present embodiment can simultaneously form the first lightly doped region 18L having the first doping type and the first heavily doped region 18H, and have the second doping, using only a single diffusion process. The second type of heavily doped region 20 ⁇ and the second lightly doped region 20L.
  • a portion of the third dielectric layer 16, a portion of the fourth dielectric layer 15 and a portion of the first patterned doped stack structure 12 are removed to form a first heavily doped region 18H.
  • Two contact holes 242. Then, a first electrode 261 electrically connected to the first heavily doped region 18H is formed in the first contact hole 241, and a first electrode is electrically connected to the second heavily doped region 20H.
  • the second electrode 262, that is, the solar cell 40 of the present embodiment was fabricated.
  • Figure 12 is a schematic illustration of a solar cell of a comparative embodiment of the present invention.
  • the solar cell 50 of the comparative embodiment does not include a selective emitter structure
  • the first electrode 261 is in contact with the first lightly doped region 18L
  • the second electrode 262 is in contact with the second lightly doped region. 20L contact, therefore with a high contact resistance.
  • the solar cell of the present invention is an interdigitated back electrode solar cell having a selective emitter structure. Since the first electrode 261 and the second electrode 262 are both disposed on the second surface 102 of the substrate 10, the amount of light entering the first surface 101 of the substrate 10 can be increased. Further, the first electrode 261 is in contact with the heavily doped first heavily doped region 18H, and the second electrode 262 is in contact with the heavily doped second heavily doped region 20H, thus having a lower contact resistance.
  • the first lightly doped region 18L and the second lightly doped region 20L having light doping have a lower saturation current, thereby reducing the recombination of electron-hole pairs (recombination), at the same time, can increase the absorption of infrared rays, and can increase the photoelectric conversion efficiency.
  • the photoelectric conversion efficiency of the solar cell of the preferred embodiment of the present invention can be substantially increased by about 0.5% to 0.6%.
  • the method for fabricating a solar cell of the present invention utilizes a patterned doped stack structure as a diffusion barrier, and the first lightly doped region having the first doping type and the first heavily doped region can be formed by only one diffusion process. The region and the second lightly doped region and the second heavily doped region having the second doping type can thus simplify the process and save cost.
  • the solar cell of the present invention is an interdigitated back electrode solar cell having a selective emitter structure, wherein the electrode is in contact with the heavily doped region of the substrate, thereby having a lower contact resistance, and the lightly doped region not in contact with the electrode has
  • the lower saturation current can reduce the recombination of electron-hole pairs while increasing the absorption of infrared rays, and increasing the photoelectric conversion efficiency.
  • the photoelectric conversion efficiency of the solar cell of the preferred embodiment of the present invention can be substantially increased by 0.5% to 0.6% after comparison with the photoelectric conversion efficiency of the conventional solar cell.

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Abstract

本发明提供一种太阳能电池及其制作方法。太阳能电池的基底具有重掺杂区与轻掺杂区。阳极与阴极均设置于基底的背面，因此，可增加基底的正面的入光量。阳极与阴极与重掺杂区接触而形成选择性射极结构，因此具有较低的接触电阻。另外，未与电极接触的轻掺杂区具有较低的饱和电流，因此，可减少电子-空穴对的复合，同时并可增加对于红外线的吸收。本发明的太阳能电池为具有选择性射极结构的交指背电极太阳能电池，其中电极与基底的重掺杂区接触，因此具有较低的接触电阻，而未与电极接触的轻掺杂区具有较低的饱和电流，因此可减少电子-空穴对的复合，同时并可增加对于红外线的吸收，而可增加光电转换效率。

Description

太阳能电池及其制作方法 技术领域
本发明关于一种太阳能电池及其制作方法， 尤指一种具有选择性射极 (selective emitter)的交指背电极太阳能电池 (interdigitated back electrode solar cell IBC solar cell)及其制作方法。 背景技术
太阳能电池是一种可将太阳光能转换成电能的光电转换组件， 在石油资源 面临枯竭的今日， 可望成为最具发展潜力的替代能源。 然而， 目前太阳能技术 仍受限于高制作成本、 工艺复杂与光电转换效率不佳等问题， 因此太阳能的发 展仍待进一歩的突破。 发明内容
本发明的目的之一在于提供一种太阳能电池及其制作方法， 以提升光电转 换效率。
本发明的一较佳实施例提供一种制作太阳能电池的方法， 包括下列歩骤。 提供一基底， 其中基底具有一第一表面与一第二表面， 且第一表面相对于第二 表面。 形成一第一图案化掺杂堆栈结构于基底的第二表面上并暴露出基板的部 份第二表面， 以形成至少一第一遮蔽区与至少一第一暴露区。 第一暴露区具有 一第一尺寸。 第一图案化掺杂堆栈结构包括相互堆栈的一第一介电层、 一第一 掺杂层与一第二介电层，第一掺杂层包括多个具有一第一掺杂类型的第一掺质， 第一掺杂层设置于第一介电层与第二介电层之间， 第一介电层具有一缺口， 且 第一掺杂层经由缺口与基底的第二表面接触。 形成且覆盖一第二掺杂层于第一 图案化掺杂堆栈结构与基底的第二表面上。 第二掺杂层接触第一暴露区所暴露 出的第二表面， 第二掺杂层包括多个具有一第二掺杂类型的第二掺质， 且第一 掺杂类型相反于第二掺杂类型。 进行一扩散工艺， 将第一掺杂层的第一掺质驱 入基底的第二表面内以于第一遮蔽区中形成一第一轻掺杂区与一第一重掺杂 区， 以及将第二掺杂层的第二掺质驱入基底的第二表面内以于至少一部份第一 暴露区中形成一第二重掺杂区。 移除部分的第一图案化掺杂堆栈结构以形成暴 露出第一重掺杂区的一第一接触洞， 以及移除部分的第二掺杂层以形成暴露出 第二重掺杂区的一第二接触洞。 于第一接触洞内形成一与第一重掺杂区电性连 接的第一电极， 以及于第二接触洞内形成一与第二重掺杂区电性连接的第二电 极。
其中， 该第一轻掺杂区的一片电阻大体上大于 δΟ Ω /口， 该第一重掺杂区 的一片电阻大体上小于 50 Ω /□， 且该第二重掺杂区大体上小于 50 Ω /口。
其中， 另包括进行一粗糙化工艺， 使该基底的该第一表面形成一粗糙化表 面。
其中， 另包括于该基底的该第一表面形成一抗反射层。
其中， 该基底具有该第二掺杂类型或第一掺杂类型。
其中，该第一介电层的厚度介于 1纳米至 20纳米之间，且该第二介电层的 厚度大于 100纳米。
其中， 另包括于进行该扩散工艺之前， 先于该第二掺杂层上形成一第三介 电层。
其中， 该第三介电层的厚度大于 100纳米。
其中， 另包括于形成该第二掺杂层之前， 先形成一第四介电层于该第一图 案化掺杂堆栈结构以及该基底的该第二表面上， 其中该第四介电层包覆该第一 图案化掺杂堆栈结构并遮蔽部份该第一暴露区以形成至少一第二遮蔽区及具有 一第二尺寸的至少一第二暴露区， 该第二掺杂层系接触该第二暴露区所暴露出 的该基板的该第二表面， 且该第二尺寸小于该第一尺寸。
其中， 更包括进行该扩散工艺将该第二掺杂层的该等第二掺质驱入该基底 的该第二表面内以于该第二遮蔽区内形成一第二轻掺杂区， 以及于该第二暴露 区内形成该第一重掺杂区。
其中， 该第四介电层的厚度介于 1纳米至 20纳米之间。
其中， 该第二轻掺杂区的一片电阻大于 80 Ω /口。
本发明的另一较佳实施例提供一种太阳能电池， 包括一基底、 一第一轻掺 杂区、 一第一重掺杂区、 一第二重掺杂区、 一第一图案化掺杂堆栈结构、 一第 二掺杂层、 一第一电极以及一第二电极。 基底具有一第一表面与一第二表面， 其中第一表面相对于第二表面， 且第一表面系为一入光面。 第一轻掺杂区位于 基底内并邻近第二表面。 第一重掺杂区位于基底内并邻近第二表面， 其中第一 轻掺杂区与第一重掺杂区具有一第一掺杂类型。 第二重掺杂区位于基底内并邻 近第二表面， 其中第二重掺杂区具有一第二掺杂类型， 且第一掺杂类型相反于 第二掺杂类型。 第一图案化掺杂堆栈结构设置于基底的第二表面且对应于第一 轻掺杂区并暴露出第一重掺杂区与第二重掺杂区， 其中第一图案化掺杂堆栈结 构包括相互堆栈的一第一介电层、 一第一掺杂层与一第二介电层。 第二掺杂层 位于第一图案化掺杂堆栈结构与基底的第二表面上， 其中第二掺杂层暴露出部 份第一重掺杂区以及部分的第二重掺杂区。 第一电极与第一图案化掺杂堆栈结 构与第二掺杂层所暴露出的第一重掺杂区电性连接。 第二电极与第一图案化掺 杂堆栈结构与第二掺杂层所暴露出的第二重掺杂区电性连接。
其中， 该第一轻掺杂区的一片电阻大于 δΟ Ω /口， 该第一重掺杂区的一片 电阻小于 50 Ω /Ο， 且该第二重掺杂区小于 50 Ω /口。
其中， 该基底具有该第二掺杂类型或该第一掺杂类型。
其中， 该基底的该第一表面具有一粗糙化表面。
其中， 另包括一抗反射层， 设置于该基底的该第一表面。
其中，该第一介电层的厚度介于 1纳米至 20纳米之间，且该第二介电层的 厚度大于 100纳米。
其中， 另包括一第三介电层， 设置于该第二掺杂层上。
其中， 该第三介电层的厚度大于 100纳米。
其中， 另包括： 一第二轻掺杂区， 位于该基底内并邻近该第二表面， 其中 该第二轻掺杂区具有该第二掺杂类型； 以及一第四介电层， 包覆该第一图案化 掺杂堆栈结构并覆盖该第二轻掺杂区。
其中， 该第四介电层的厚度介于 1纳米至 20纳米之间。
其中， 该第二轻掺杂区的一片电阻大于 80 Ω /口。
本发明的太阳能电池为具有选择性射极结构的交指背电极太阳能电池， 其 中电极与基底的重掺杂区接触， 因此具有较低的接触电阻， 而未与电极接触的 轻掺杂区具有较低的饱和电流， 因此可减少电子-空穴对的复合， 同时并可增加 对于红外线的吸收， 而可增加光电转换效率。 本发明的较佳实施例的太阳能电 池的光电转换效率跟传统的太阳能电池的光电转换效率比较后， 大体上可再多 提升 0.5% ~ 0.6%。
以下结合附图和具体实施例对本发明进行详细描述， 但不作为对本发明的 限定。 附图说明
图 1至图 7绘示了本发明的一第一较佳实施例的制作太阳能电池的方法示 意图。
图 8至图 11绘示了本发明的一第二较佳实施例的制作太阳能电池的方法示 意图。
图 12绘示了本发明的一比较实施例的太阳能电池的示意图。
其中， 附图标记：
10： 基底 101： 第一表面
102： 第二表面 12： 第一图案化掺杂堆栈结
121： 第一介电层 121A: 缺口
122： 第一掺杂层 123： 第二介电层
12S: 第一遮蔽区 12E: 第一暴露区
14： 第二掺杂层 16： 第三介电层
18L: 第一轻掺杂区 18H: 第一重掺杂区
20H: 第二重掺杂区 22： 抗反射层
241： 第一接触洞 242： 第二接触洞
261： 第一电极 262： 第二电极
30： 太阳能电池 15： 第四介电层
12S' : 第二遮蔽区 12E' : 第二暴露区
20L: 第二轻掺杂区 40： 太阳能电池
50： 太阳能电池 具体实施方式
为使本领域技术人员能更进一歩了解本发明， 下文特列举本发明的较佳实 施例， 并配合所附图式， 详细说明本发明的构成内容及所欲达成的功效。 在文 中使用例如 "第一"与 "第二"等叙述， 仅用以区别不同的元件， 并不对其产生 顺序有所限制。
请参考图 1至图 7。图 1至图 7绘示了本发明的一第一较佳实施例的制作太 阳能电池的方法示意图。 如图 1所示， 首先提供一基底 10。 基底 10可包括一 硅基底例如单晶硅基底或多晶硅基底等等， 且基底 10的厚度例如约为 50微米 至 300微米之间， 但不以此为限。基底 10可为其它各种类型的半导体基底。基 底 10具有一第一表面 101与一第二表面 102，其中第一表面 101与第二表面 102 彼此相对， 且第一表面 101为入光面。 随后， 可对基底 10进行一切割损伤移除 (saw damage remove, SDR)工艺， 例如利用酸性溶液或碱性溶液清洗基底 10， 以去除切割对基底 10造成的细微损伤。
接着，形成一第一图案化掺杂堆栈结构 12于基底 10的第二表面 102上并暴 露出基板 10的部分第二表面 102， 如图 7所示。 在本实施例中， 形成第一图案 化掺杂堆栈结构 12的方法如图 2至图 4所揭示的方法所示，但不以此为限。如 图 2所示， 首先， 形成一第一介电层 121于基底 10的第二表面 102上， 并图案 化第一介电层 121以使第一介电层 121具有一缺口 121A, 暴露出基板 10的部 分第二表面 102。 第一介电层 121可为单层或多层结构， 且其材料可包括氧化 硅、 氮氧化硅、 或氮化硅， 但亦可为例如氧化铝或其它有机或无机介电材料。 另外，第一介电层 121的厚度例如大体上可介于 1纳米至 20纳米之间，但不以 此为限。 第一介电层 121可利用一化学气相沉积 (CVD)工艺， 例如一常压化学 气相沉积 (APCVD)工艺加以制作， 并利用例如一蚀刻工艺进行图案化， 但不以 此为限。 第一介电层 121亦可利用例如物理气相沉积工艺、 旋转涂布工艺、 喷 墨印刷程制、 网版印刷工艺等加以制作。 如图 3所示， 随后， 形成一第一掺杂 层 122于第一介电层 121上及其所暴露出的基底 10的第二表面 102上，其中第 一掺杂层 122经由第一介电层 121的缺口 121A与基底 10的第二表面 102接触。 也就是说， 第一掺杂层 122除了会接触缺口 121A中的第二表面 102外， 也会 包覆住第一介电层 121。 第一掺杂层 122包括多个具有一第一掺杂类型的第一 掺质 (； dopant or implant or diffuser)。 例如在本实施例中， 第一掺杂类型为 p型， 第一掺杂层 122为硼硅玻璃BSG), 且第一掺质为硼， 但不以此为限。 接着， 形成一第二介电层 123于第一掺杂层 122上。 也就是说， 第二介电层 123覆盖 于第一掺杂层 122上。 第二介电层 123的厚度例如大体上系大于 100纳米， 但 不以此为限。 第二介电层 123可为单层或多层结构， 且其材料包括氧化硅、 氮 氧化硅或氮化硅， 但也可为例如氧化铝或其它有机或无机介电材料。 第二介电 层 123可利用一化学气相沉积工艺， 例如一常压化学气相沉积工艺加以制作， 但不以此为限， 例如物理气相沉积工艺、 旋转涂布工艺、 喷墨印刷工艺、 网版 印刷工艺等。 如图 4， 对第二介电层 123、 第一掺杂层 122与第一介电层 121 进行图案化， 移除部分的第二介电层 123、 第一掺杂层 122与第一介电层 121 以形成第一图案化掺杂堆栈结构 12。 图案化第二介电层 123、 第一掺杂层 122 与第一介电层 121的歩骤可利用一蚀刻工艺加以实现， 但不以此为限。 于其它 实施例中， 图案化第二介电层 123、 第一掺杂层 122与第一介电层 121的歩骤 皆可用网版印刷方式或喷墨方法形成， 而不需要曝光显影的歩骤。 第一图案化 掺杂堆栈结构 12暴露出基板 10的部份第二表面 102并覆盖基板 10的部份第二 表面 102，其中被第一图案化掺杂堆栈结构 12的第二表面 102形成至少一第一 遮蔽区 12S ,而被第一图案化掺杂堆栈结构 12所暴露出的第二表面 102形成至 少一第一暴露区 12E, 且第一暴露区 12E具有一第一尺寸。 必需说明的是， 缺 口 121A实质上是位于第一遮蔽区 12S内。
如图 5所示， 形成且覆盖一第二掺杂层 14于第一图案化掺杂堆栈结构 12 与基底 10的第二表面 102上， 其中第二掺杂层 14接触第一暴露区 12E所暴露 出的第二表面 102。 第二掺杂层 14包括多个具有一第二掺杂类型的第二掺质， 且第一掺杂类型相反于第二掺杂类型。 例如在本实施例中， 第二掺杂类型为 n 型， 第二掺杂层 14为磷硅玻璃PSG), 且第二掺质为磷， 但不以此为限。 另外， 可选择性地于第二掺杂层 14上形成一第三介电层 16。第三介电层 16可为单层 或多层结构， 且其材料包括氧化硅、 氮氧化硅、 或氮化硅， 但也可为例如氧化 铝或其它有机或无机介电材料。 另外， 第三介电层 16 的厚度例如大体上大于 100纳米， 但不以此为限。 第三介电层 16可利用一化学气相沉积工艺， 例如一 常压化学气相沉积工艺加以制作， 但也可为其它适合的工艺加以制作， 例如物 理气相沉积工艺、 旋转涂布工艺、 喷墨印刷程制、 网版印刷工艺等。 第三介电 层 16用以为提供太阳能电池良好的绝缘性，避免太阳能电池因正负极的漏电流 造成其效能表现不佳。 因此， 第三介电层 16的材料、工艺与厚度的选择应以其 绝缘效果作为主要考虑的一。此外， 进行一粗糙化工艺， 使基底 10的第一表面 101形成一粗糙化 (textured)表面， 以增加入光量。
如图 6所示， 随后进行一扩散工艺，将第一掺杂层 122的第一掺质驱入基底 10的第二表面 102内以于第一遮蔽区 12S中形成具有第一掺杂类型的一第一轻 掺杂区 18L与一第一重掺杂区 18H, 以及将第二掺杂层 14的第二掺质驱入基 底 10的第二表面 102内以于至少一部份的第一暴露区 12E中形成具有第二掺 杂类型的一第二重掺杂区 20H。这边所说的扩散工艺是指基底 10位于高温环境 中， 将上述结构中的第一掺质及第二掺质分别扩散进入基底 10 中所预定的区 域。 因此， 此种扩散工艺又可称为回火或退火工艺 ( tempering or annealing)。 第 一介电层 121可减缓扩散速度而具有扩散阻障的作用， 因此在扩散工艺中， 对 应于第一介电层 121的缺口 121A的基底 10会形成第一重掺杂区 18H。也就是 说， 在扩散工艺中， 较多的第一掺质会进入没有被第一介电层 121所覆盖的基 底 10 内， 因而形成掺杂浓度较高的第一重掺杂区 18H。 此外， 在第一介电层 121 的扩散阻障效应下， 较少的第一掺质会进入被第一介电层 121所覆盖的基 底 10内， 因而形成掺杂浓度较低的第一轻掺杂区 18L。举例而言， 在扩散工艺 之后 ， 第一重掺杂区 18H 的表面掺杂浓度大体上较佳介于 1019atom/cm3~1021atom/cm3之间， 而第一轻掺杂区 18L的表面掺杂浓度大体上 较佳介于 1018atom/cm3~1019atom/cm3之间， 但不以此为限。 第一重掺杂区 18H 的片电阻或称为方块电阻 (sheet resistance)大体上需小于 50 Ω /Ο，而第一轻掺杂 区 18L的片电阻大体上需大于 δΟ Ω /口， 但不以此为限。 在本实施例中， 第一 图案化掺杂堆栈结构 12的第一介电层 121 的主要作用在于控制第一重掺杂区 18H的片电阻与第一轻掺杂区 18L的片电阻， 因此可选择适当的材料与工艺制 作第一介电层 121， 并调整第一介电层 121 的厚度， 以确保于扩散工艺后第一 重掺杂区 18H与第一轻掺杂区 18L会具有预定的片电阻。另一方面， 第一图案 化掺杂堆栈结构 12也具有扩散阻障的作用， 因此在扩散工艺中，对应于未被第 一图案化掺杂堆栈结构 12覆盖的第一暴露区 12E的基底 10内会形成第二重掺 杂区 20Η。 也就是说， 在扩散工艺中， 第二掺质会进入没有被第一图案化掺杂 堆栈结构 12覆盖的第一暴露区 12E的基底 10内， 因而形成掺杂浓度较高的第 二重掺杂区 20Η。第一图案化掺杂堆栈结构 12的第二介电层 123用以避免第一 掺杂层 122与第二掺杂层 14产生互相掺杂， 因此在材料、工艺与厚度的选择上 应以可达到避免第一掺杂层 122与第二掺杂层 14产生互相掺杂的效果作为考 虑。 藉由第二介电层 123的设置， 在扩散工艺中， 不会有第二掺质或是仅有数 量 /浓度可被忽略的第二掺质会进入被第一图案化掺杂堆栈结构 12所覆盖的第 一遮蔽区 12S, 也就是说， 第二掺质尽可能的不会进入第一重掺杂区 18H与第 一轻掺杂区 18L内，因此第一重掺杂区 18H与第一轻掺杂区 18L的掺杂浓度比 较不会受到第二掺质的影响而改变。 举例而言， 在扩散工艺之后， 第二重掺杂 区 20H的表面掺杂浓度大体上较佳介于 1019atom/cm3 〜 1021 atom/cm3之间， 且 第二重掺杂区 20H的片电阻大体上需小于 50 Ω /口， 但不以此为限。 在本实施 例中， 第一轻掺杂区 18L与第一重掺杂区 18H具有第一掺杂类型， 第二重掺杂 区 20H具有第二掺杂类型。 基底 10则可视太阳能电池的设计而为第一掺杂类 型或第二掺杂类型。 由上述可知， 本实施例的制作太阳能电池的方法仅利用单 一扩散工艺即可同时形成具有第一掺杂类型的第一轻掺杂区 18L与第一重掺杂 区 18H, 以及具有第二掺杂类型的第二重掺杂区 20H。
另外， 于基底 10的第一表面 101形成一抗反射层 22。 在本实施例中， 抗反 射层 22是以共形conformai;)方式形成于基板 10的第一表面 101上， 因此抗反 射层 22也具有粗糙化表面。 抗反射层 22可增加太阳能电池的入光量。 抗反射 层 22可为单层或多层结构， 且其材料可为例如氮化硅、 氧化硅、 或氮氧化硅、 或其它合适的材料，并可利用例如一电浆增强化学气相沉积 (PECVD)工艺形成， 但不以此为限。
如图 7所示， 接着移除部分的第三介电层 16与部分的第一图案化掺杂堆栈 结构 12以形成暴露出第一重掺杂区 18H的一第一接触洞 241，以及移除部分的 第三介电层 16与部分的第二掺杂层 14以形成暴露出第二重掺杂区 20H的一第 二接触洞 242。 随后， 于第一接触洞 241内形成与第一重掺杂区 18H电性连接 的一第一电极 (：例如阳极 )261， 以及于第二接触洞 242 内形成与第二重掺杂区 20H 电性连接的一第二电极 (：例如阴极 )262， 即制作出本实施例的太阳能电池 30。第一电极 261与第一重掺杂区 18H会形成选择性射极结构，而第二电极 262 与第二重掺杂区 20H也会形成选择性射极结构。 第一电极 261与第二电极 262 的材料可为例如金属或合金， 或其它适合的导电材料。
本发明的太阳能电池及其制作方法并不以上述实施例为限。下文将依序介绍 本发明的其它较佳实施例的太阳能电池及其制作方法， 且为了便于比较各实施 例的相异处并简化说明，在下文的各实施例中使用相同的符号标注相同的组件， 且主要针对各实施例的相异处进行说明， 而不再对重复部分进行赘述。
请参考图 8至图 11， 并一并参考图 1至图 4。 图 8至图 11绘示了本发明的 一第二较佳实施例的制作太阳能电池的方法示意图。 本实施例的制作太阳能电 池的方法系接续图 4的方法后进行。 如图 8所示， 于形成第一图案化掺杂堆栈 结构 12之后， 形成一第四介电层 15于第一图案化掺杂堆栈结构 12以及基底 10的第二表面 102上，并图案化第四介电层 15以使得第四介电层 15包覆第一 图案化掺杂堆栈结构 12并遮蔽部份的第一暴露区 12E以形成至少一第二遮蔽 区 12S'及至少一第二暴露区 12E'。 第二暴露区 12E'具有一第二尺寸， 且第二 暴露区 12E'的第二尺寸实质上小于第一暴露区 12E的第一尺寸。也就是说， 第 二暴露区 12E'系位于第一暴露区 12E的内。 第四介电层 15可为单层或多层结 构， 且其材料包括氧化硅、 氮氧化硅或氮化硅， 但也可为例如氧化铝或其它有 机或无机介电材料。 第二介电层 123的厚度例如大体上系大于 100纳米， 第四 介电层 15的厚度例如大体上可介于 1纳米至 20纳米之间， 但不以此为限。 第 四介电层 15可利用一化学气相沉积工艺，例如一常压化学气相沉积工艺加以制 作， 但也可为其它适合的工艺加以制作， 例如物理气相沉积工艺、 旋转涂布工 艺、 喷墨印刷程制、 网版印刷工艺等。
如图 9所示， 形成且覆盖第二掺杂层 14于第四介电层 15与基底 10的第二 表面 102上， 其中第二掺杂层 14接触第二暴露区 12E'所暴露出的基板 10的第 二表面 102。接着， 于第二掺杂层 14上形成一第三介电层 16。此外， 进行一粗 糙化工艺， 使基底 10的第一表面 101形成一粗糙化表面， 以增加入光量。
如图 10所示， 随后进行一扩散工艺， 将第一掺杂层 122的第一掺质驱入基 底 10的第二表面 102内以于第一遮蔽区 12S中形成至少二个第一轻掺杂区 18L 与至少一个第一重掺杂区 18H、 将第二掺杂层 14的第二掺质驱入基底 10的第 二表面 102内以于第二暴露区 12E'中形成至少一个第二重掺杂区 20H, 以及第 二掺杂层 14的第二掺质驱入基底 10的第二表面 102内以于第二暴露区 12E' 以外的第一暴露区 12E内形成至少二个第二轻掺杂区 20L。 较佳地， 上述的重 掺杂区是位于上述二个轻杂区之间， 但不限于此。 此实施例对于扩散工艺的名 称说明可参阅前述的实施例。 不同于第一较佳实施例的处在于， 本实施例的第 四介电层 15覆盖了部分的第一暴露区 12，而第四介电层 15也具有扩散阻障的 作用， 因此在扩散工艺中， 对应于第二暴露区 12E'的基底 10 内会形成掺杂浓 度较高的第二重掺杂区 20H, 而被第四介电层 15所覆盖的第二暴露区 12E'以 外的第一暴露区 12E的基底 10内则会形成掺杂浓度较低的第二轻掺杂区 20L。 举例而言， 在扩散工艺之后， 第一重掺杂区 18H的表面掺杂浓度大体上较佳介 于 1019atom/cm3〜 1021 atom/cm3之间，第一轻掺杂区 18L的表面掺杂浓度大体上 较佳介于 1018atom/cm3 〜 1019atom/cm3之间， 第二重掺杂区 20H的表面掺杂浓 度大体上较佳介于 1019atom/cm3 〜 1021atom/cm3之间，且第二轻掺杂区 20L的表 面掺杂浓度大体上较佳介于 1018atom/cm3 〜 1019atom/cm3之间， 但不以此为限。 第一重掺杂区 18H的片电阻大体上需小于 50 Ω /Ο， 第一轻掺杂区 18L的片电 阻大体上需大于 80 Ω /口， 第二重掺杂区 20Η的片电阻大体上需小于 50 Ω /口， 而第二轻掺杂区 20L的片电阻大体上需大于 80 Ω /口， 但不以此为限。 在本实 施例中， 第四介电层 15的主要作用在于控制第二重掺杂区 20Η的片电阻与第 二轻掺杂区 20L的片电阻， 因此可选择适当的材料与工艺制作第四介电层 15， 并选择适当的厚度， 以确保于扩散工艺后第二重掺杂区 20Η 与第二轻掺杂区 20L会具有预定的片电阻。 另外， 于基底 10的第一表面 101形成一抗反射层 22。 由上述可知， 本实施例的制作太阳能电池的方法仅利用单一扩散工艺即可 同时形成具有第一掺杂类型的第一轻掺杂区 18L与第一重掺杂区 18H, 以及具 有第二掺杂类型的第二重掺杂区 20Η与第二轻掺杂区 20L。
如图 11所示， 接着移除部分的第三介电层 16、 部分的第四介电层 15与部 分的第一图案化掺杂堆栈结构 12以形成暴露出第一重掺杂区 18H的一第一接 触洞 241， 以及移除部分的第三介电层 16、部分的第四介电层 15与部分的第二 掺杂层 14以形成暴露出第二重掺杂区 20H的一第二接触洞 242。随后，于第一 接触洞 241内形成与第一重掺杂区 18H电性连接的一第一电极 261， 以及于第 二接触洞 242内形成与第二重掺杂区 20H电性连接的一第二电极 262， 即制作 出本实施例的太阳能电池 40。
请参考图 12。 图 12绘示了本发明的一比较实施例的太阳能电池的示意图。 如图 12所示， 本比较实施例的太阳能电池 50未包括选择性射极结构， 第一电 极 261系与第一轻掺杂区 18L接触，而第二电极 262系与第二轻掺杂区 20L接 触， 因此具有较高的接触电阻。
本发明的太阳能电池为具有选择性射极结构的交指背电极太阳能电池。由于 第一电极 261与第二电极 262均设置于基底 10的第二表面 102， 因此可增加基 底 10的第一表面 101的入光量。此外，第一电极 261与具有重度掺杂的第一重 掺杂区 18H接触， 且第二电极 262与具有重度掺杂的第二重掺杂区 20H接触， 因此具有较低的接触电阻。 另一方面， 具有轻度掺杂的第一轻掺杂区 18L与第 二轻掺杂区 20L 具有较低的饱和电流， 因此可减少电子-空穴对的复合 (recombination), 同时并可增加对于红外线的吸收， 而可增加光电转换效率。相 较于比较实施例的太阳能电池， 本发明的较佳实施例的太阳能电池的光电转换 效率大体上可再多提升约 0.5% ~ 0.6%。另外，本发明的制作太阳能电池的方法 利用图案化掺杂堆栈结构作为扩散阻障， 仅需利用一道扩散工艺即可形成具有 第一掺杂类型的第一轻掺杂区与第一重掺杂区以及具有第二掺杂类型的第二轻 掺杂区与第二重掺杂区， 因此可简化工艺并节省成本。 工业应用性
本发明的太阳能电池为具有选择性射极结构的交指背电极太阳能电池， 其 中电极与基底的重掺杂区接触， 因此具有较低的接触电阻， 而未与电极接触的 轻掺杂区具有较低的饱和电流， 因此可减少电子-空穴对的复合， 同时并可增加 对于红外线的吸收， 而可增加光电转换效率。 本发明的较佳实施例的太阳能电 池的光电转换效率跟传统的太阳能电池的光电转换效率比较后， 大体上可再多 提升 0.5% ~ 0.6%。
当然， 本发明还可有其它多种实施例， 在不背离本发明精神及其实质的情 况下， 熟悉本领域的技术人员可根据本发明作出各种相应的改变和变形， 但这 些相应的改变和变形都应属于本发明权利要求的保护范围。

Claims

权利要求书
1. 一种制作太阳能电池的方法， 其特征在于， 包括：
提供一基底， 其中该基底具有一第一表面与一第二表面， 且该第一表面相 对于该第二表面；
形成一第一图案化掺杂堆栈结构于该基底的该第二表面上并暴露出该基 板的部份该第二表面， 以形成至少一第一遮蔽区与至少一第一暴露区， 其中该 第一暴露区具有一第一尺寸，该第一图案化掺杂堆栈结构包括相互堆栈的一第 一介电层、一第一掺杂层与一第二介电层， 该第一掺杂层包括多个具有一第一 掺杂类型的第一掺质，该第一掺杂层系设置于该第一介电层与该第二介电层之 间， 该第一介电层具有一缺口， 且该第一掺杂层经由该缺口与该基底的该第二 表面接触；
形成且覆盖一第二掺杂层于该第一图案化掺杂堆栈结构与该基底的该第 二表面上， 其中该第二掺杂层接触该第一暴露区所暴露出的该第二表面， 该第 二掺杂层包括多个具有一第二掺杂类型的第二掺质，且该第一掺杂类型相反于 该第二掺杂类型；
进行一扩散工艺，将该第一掺杂层的该等第一掺质驱入该基底的该第二表 面内以于该第一遮蔽区中形成一第一轻掺杂区与一第一重掺杂区，以及将该第 二掺杂层的该等第二掺质驱入该基底的该第二表面内以于至少一部份该第一 暴露区中形成一第二重掺杂区；
移除部分的该第一图案化掺杂堆栈结构以形成暴露出该第一重掺杂区的 一第一接触洞，以及移除部分的该第二掺杂层以形成暴露出该第二重掺杂区的 一第二接触洞； 以及
于该第一接触洞内形成一与该第一重掺杂区电性连接的第一电极，以及于 该第二接触洞内形成一与该第二重掺杂区电性连接的第二电极。
2. 根据权利要求 1 所述的制作太阳能电池的方法， 其特征在于， 该第一 轻掺杂区的一片电阻大体上大于 δΟ Ω /口， 该第一重掺杂区的一片电阻大体上 小于 50 Ω /□， 且该第二重掺杂区大体上小于 50 Ω /口。
3. 根据权利要求 1 所述的制作太阳能电池的方法， 其特征在于， 另包括 进行一粗糙化工艺， 使该基底的该第一表面形成一粗糙化表面。
4. 根据权利要求 1 所述的制作太阳能电池的方法， 其特征在于， 另包括 于该基底的该第一表面形成一抗反射层。
5. 根据权利要求 1 所述的制作太阳能电池的方法， 其特征在于， 该基底 具有该第二掺杂类型或第一掺杂类型。
6. 根据权利要求 1 所述的制作太阳能电池的方法， 其特征在于， 该第一 介电层的厚度介于 1纳米至 20纳米之间， 且该第二介电层的厚度大于 100纳 米。
7. 根据权利要求 1 所述的制作太阳能电池的方法， 其特征在于， 另包括 于进行该扩散工艺之前， 先于该第二掺杂层上形成一第三介电层。
8. 根据权利要求 7所述的制作太阳能电池的方法， 其特征在于， 该第三 介电层的厚度大于 100纳米。
9. 根据权利要求 1 所述的制作太阳能电池的方法， 其特征在于， 另包括 于形成该第二掺杂层之前，先形成一第四介电层于该第一图案化掺杂堆栈结构 以及该基底的该第二表面上，其中该第四介电层包覆该第一图案化掺杂堆栈结 构并遮蔽部份该第一暴露区以形成至少一第二遮蔽区及具有一第二尺寸的至 少一第二暴露区，该第二掺杂层系接触该第二暴露区所暴露出的该基板的该第 二表面， 且该第二尺寸小于该第一尺寸。
10. 根据权利要求 9所述的制作太阳能电池的方法， 其特征在于， 更包括 进行该扩散工艺将该第二掺杂层的该等第二掺质驱入该基底的该第二表面内 以于该第二遮蔽区内形成一第二轻掺杂区，以及于该第二暴露区内形成该第一 重掺杂区。
11. 根据权利要求 9所述的制作太阳能电池的方法， 其特征在于， 该第四 介电层的厚度介于 1纳米至 20纳米之间。
12. 根据权利要求 9所述的制作太阳能电池的方法， 其特征在于， 该第二 轻掺杂区的一片电阻大于 80 Ω /口。
13. 一种太阳能电池， 其特征在于， 包括：
一基底， 其中该基底具有一第一表面与一第二表面， 该第一表面相对于该 第二表面， 且该第一表面系为一入光面；
一第一轻掺杂区， 位于该基底内并邻近该第二表面；
一第一重掺杂区， 位于该基底内并邻近该第二表面， 其中该第一轻掺杂区 与该第一重掺杂区具有一第一掺杂类型； 一第二重掺杂区， 位于该基底内并邻近该第二表面， 其中该第二重掺杂区 具有一第二掺杂类型， 且该第一掺杂类型相反于该第二掺杂类型；
一第一图案化掺杂堆栈结构，设置于该基底的该第二表面且对应于该第一 轻掺杂区并暴露出该第一重掺杂区与该第二重掺杂区，其中该第一图案化掺杂 堆栈结构包括相互堆栈的一第一介电层、 一第一掺杂层与一第二介电层； 一第二掺杂层， 位于该第一图案化掺杂堆栈结构与该基底的该第二表面 上， 其中该第二掺杂层暴露出部份该第一重掺杂区以及部分的该第二重掺杂 区；
一第一电极，与该第一图案化掺杂堆栈结构与该第二掺杂层所暴露出的该 第一重掺杂区电性连接； 以及
一第二电极，与该第一图案化掺杂堆栈结构与该第二掺杂层所暴露出的该 第二重掺杂区电性连接。
14. 根据权利要求 13所述的太阳能电池， 其特征在于， 该第一轻掺杂区 的一片电阻大于 δΟ Ω /口， 该第一重掺杂区的一片电阻小于 50 Ω /Ο，且该第二 重掺杂区小于 50 Ω /口。
15. 根据权利要求 13所述的太阳能电池， 其特征在于， 该基底具有该第 二掺杂类型或该第一掺杂类型。
16. 根据权利要求 13所述的太阳能电池， 其特征在于， 该基底的该第一 表面具有一粗糙化表面。
17. 根据权利要求 13所述的太阳能电池， 其特征在于， 另包括一抗反射 层， 设置于该基底的该第一表面。
18. 根据权利要求 13所述的太阳能电池， 其特征在于， 该第一介电层的 厚度介于 1纳米至 20纳米之间， 且该第二介电层的厚度大于 100纳米。
19. 根据权利要求 13所述的太阳能电池， 其特征在于， 另包括一第三介 电层， 设置于该第二掺杂层上。
20. 根据权利要求 19所述的太阳能电池， 其特征在于， 该第三介电层的 厚度大于 100纳米。
21. 根据权利要求 13所述的太阳能电池， 其特征在于， 另包括： 一第二轻掺杂区， 位于该基底内并邻近该第二表面， 其中该第二轻掺杂区 具有该第二掺杂类型； 以及 一第四介电层， 包覆该第一图案化掺杂堆栈结构并覆盖该第二轻掺杂区。
22. 根据权利要求 21 所述的太阳能电池， 其特征在于， 该第四介电层的 厚度介于 1纳米至 20纳米之间。
23. 根据权利要求 21 所述的太阳能电池， 其特征在于， 该第二轻掺杂区 的一片电阻大于 80 Ω /口。
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