WO2014005365A1 - 3d液晶显示器及其像素结构 - Google Patents

3d液晶显示器及其像素结构 Download PDF

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Publication number
WO2014005365A1
WO2014005365A1 PCT/CN2012/079807 CN2012079807W WO2014005365A1 WO 2014005365 A1 WO2014005365 A1 WO 2014005365A1 CN 2012079807 W CN2012079807 W CN 2012079807W WO 2014005365 A1 WO2014005365 A1 WO 2014005365A1
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Prior art keywords
pixel
photoresist
sub
electrode portion
regions
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English (en)
French (fr)
Inventor
李佳育
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/639,069 priority Critical patent/US8958043B2/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/30—Image reproducers
    • H04N13/332—Displays for viewing with the aid of special glasses or head-mounted displays [HMD]
    • H04N13/337—Displays for viewing with the aid of special glasses or head-mounted displays [HMD] using polarisation multiplexing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/52—RGB geometrical arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N2213/00—Details of stereoscopic systems
    • H04N2213/001—Constructional or mechanical details

Definitions

  • the present invention relates to a pixel structure of a liquid crystal display, and more particularly to a 3D liquid crystal display and a pixel structure thereof.
  • a conventional 3D development system is such that an image is first converted into a linearly polarized image by the polarizer 90.
  • the linearly polarized image is then passed through a 1/4 array wave plate 91 ( ⁇ /4 Pattern retarder Plate).
  • the 1/4 array wave plate 91 having the first phase delay column 910 and the second phase delay column 911 can convert the linearly polarized image into a left circularly polarized image and a right circularly polarized image for respectively as a left eye input image and a right eye input. image.
  • Both lenses of the polarized glasses 8 worn by the viewer are composed of a quarter wave plate 80 and a polarizer 81.
  • the image including the left circularly polarized image and the right circularly polarized image is first converted into a linearly polarized image by the quarter wave plate 80 of the two lenses, and then passed through the polarizer 81 of the lens to reach the viewer respectively. Eyes. Since the polarizer 81 of the two lenses has different polarization directions, the left eye of the user can only see the input image of the left eye, and the right eye can only see the input image of the right eye, thereby achieving the effect of the three-dimensional image.
  • FIG. 2 is a schematic diagram of a pixel arrangement of a conventional liquid crystal display device having a single-gate structure
  • FIG. 3 is a pixel of a conventional liquid crystal display device having a three-gate pixel structure. Schematic diagram of arrangement
  • FIG. 6 is a schematic diagram of a conventional three-gate pixel structure. As shown in FIG. 2, the sub-pixel regions 600, 601, and 602 of the pixel unit 60 of the single-gate pixel structure 6 are arranged along the length direction of the gate line; and as shown in FIGS.
  • the sub-pixel regions 500, 501, and 502 of the pixel unit 50 of 5 are arranged along the length direction of the data line, and the pixel electrodes 52R, 52G, and 52B are respectively disposed in the sub-pixel regions 500, 501, and 502, respectively corresponding to the photoresists of different colors. .
  • the number of gate lines 710 of the liquid crystal display device having the three-gate pixel structure 5 is increased by a factor of three compared to the liquid crystal display device having the single gate type pixel structure 6, and the number of the data lines 700 is The reduction is one-third, so the gate driver 71 of the liquid crystal display device having a three-gate pixel structure uses more gate drive wafers, and the source driver 70 uses less source drive wafers. Since the manufacturing cost and power consumption of the gate driving wafer are low, the use of the three-gate pixel structure 5 can reduce the manufacturing cost and energy consumption of the liquid crystal display device.
  • the 3D liquid crystal display will have a color shift problem in the upper and lower viewing angles.
  • the user wearing the polarized glasses 8 transmits the first phase delay column 910 and the second phase delay column 911 of the 1/4 array wave plate 91 at a horizontal direct viewing angle, an upper viewing angle or a lower viewing angle.
  • the color mixing effect of the pixels received by the user's eyes will be different.
  • 4A in the horizontal direct view angle, the order of the sub-pixel colors of the pixel structure seen by the user through the second phase delay column 911 is R, G, B; and in FIG.
  • the arrangement of the sub-pixel colors of the pixel structure seen by the user through the second phase delay column 911 becomes G, B, and R. Since the first phase delay column 910 and the second phase delay column 911 are used to form the left-eye and right-eye input images, once the first phase delay column 910 and the second phase delay column 911 correspond to the wrong pixel structure, Causes color cast problems.
  • the main object of the present invention is to provide a 3D liquid crystal display and a pixel structure thereof, which can improve the color shift problem of the upper and lower viewing angles of the 3D liquid crystal display.
  • the invention provides a pixel structure of a 3D liquid crystal display, which comprises:
  • a data line interleaved with the gate line, and defining three sub-pixel regions with the gate line, the sub-pixel regions being aligned along the first direction;
  • the three-pixel electrodes each include a main electrode portion and an extended electrode portion connected to the main electrode portion, wherein the main electrode portions of the pixel electrodes are respectively disposed in corresponding sub-pixel regions, and the extended electrode portions of the pixel electrodes are disposed together In one of the sub-pixel regions.
  • the pixel structure further includes three thin film transistors respectively disposed in the sub-pixel region, and the gate of each of the thin film transistors is electrically connected to a corresponding gate line; The source of the thin film transistor is electrically connected to the data line; the drain of each of the thin film transistors is electrically connected to the corresponding pixel electrode.
  • the sub-pixel regions are first, second, and third sub-pixel regions, respectively; the pixel electrodes are first, second, and third pixel electrodes, respectively; The main electrode portions of the second and third pixel electrodes are respectively disposed in the first, second, and third sub-pixel regions; and the extended electrode portions of the first, second, and third pixel electrodes are disposed together The first sub-pixel area;
  • the pixel structure corresponds to a photoresist structure of a color filter, wherein the photoresist structure includes first, second, and third photoresist regions, wherein the first, second, and third photoresist regions Positions respectively correspond to the first, second, and third sub-pixel regions; the first photoresist region includes a first photoresist, a second photoresist, and a third photoresist; and the second photoresist region A second photoresist is included therein; and a third photoresist is included in the third photoresist region.
  • the first photoresist shape and the position in the first photoresist region correspond to the main electrode portion of the first pixel electrode and the extended electrode portion thereof; and the first photoresist region
  • the second photoresist shape and position correspond to the extended electrode portion of the second pixel electrode;
  • the third photoresist shape and position in the first photoresist region correspond to the extended electrode portion of the third pixel electrode;
  • the second photoresist shape and position in the second photoresist region correspond to the main electrode portion of the second pixel electrode
  • the third photoresist shape and position in the third photoresist region correspond to the main electrode portion of the third pixel electrode.
  • the extended electrode portion of the second pixel electrode is insulated to connect the main electrode portion of the second pixel electrode across at least one of the gate lines; the third pixel electrode The extension electrode portion is connected to the main electrode portion of the third pixel electrode in an insulating manner across at least one of the gate lines.
  • the invention further provides a 3D liquid crystal display, comprising:
  • a first substrate includes a plurality of pixel regions, each of the pixel regions including a pixel structure, and the pixel structure includes:
  • a data line interleaved with the gate line, and defining three sub-pixel regions with the gate line, the sub-pixel regions being aligned along the first direction;
  • the three-pixel electrodes each include a main electrode portion and an extended electrode portion connected to the main electrode portion, wherein the main electrode portions of the pixel electrodes are respectively disposed in corresponding sub-pixel regions, and the extended electrode portions of the pixel electrodes are disposed together In one of the sub-pixel regions;
  • liquid crystal layer disposed between the first substrate and the second substrate
  • a phase retarder is disposed to overlap the second substrate.
  • the pixel structure further includes three thin film transistors respectively disposed in the sub-pixel region, and the gate of each of the thin film transistors is electrically connected to a corresponding gate line; The source of the thin film transistor is electrically connected to the data line; the drain of each of the thin film transistors is electrically connected to the corresponding pixel electrode.
  • the 3D liquid crystal display includes a polarizer disposed on the second substrate; the phase retarder is disposed on an outer surface of the polarizer, and includes:
  • a plurality of second phase delay unit columns are staggered with the first phase delay unit columns.
  • an optical axis of the first phase delay unit column and an angle of penetration of the polarizer are 135 degrees; an optical axis of the second phase delay unit column and the polarized light The angle of penetration of the piece is 45 degrees.
  • the sub-pixel regions are first, second, and third sub-pixel regions, respectively; the pixel electrodes are first, second, and third pixel electrodes, respectively; The main electrode portions of the second and third pixel electrodes are respectively disposed in the first, second, and third sub-pixel regions; and the extended electrode portions of the first, second, and third pixel electrodes are disposed together The first sub-pixel area;
  • the second substrate is provided with a color filter, the color filter has a photoresist structure corresponding to the pixel structure of the first substrate; and the photoresist structure includes first, second and third photoresist regions.
  • the first, second, and third photoresist regions respectively correspond to the first, second, and third sub-pixel regions;
  • the first photoresist region includes a first photoresist, a first a second photoresist and a third photoresist;
  • the second photoresist region includes a second photoresist;
  • the third photoresist region includes a third photoresist region.
  • the invention further provides a pixel structure of a 3D liquid crystal display, comprising:
  • a data line interlaced with the gate line, and defining three sub-pixel regions with the gate line, respectively being first, second, and third sub-pixel regions, wherein the three sub-pixel regions are along the Arranged in one direction;
  • a three-pixel electrode which is a first, a second, and a third pixel electrode, each of which includes a main electrode portion and an extended electrode portion connected to the main electrode portion, wherein the main electrodes of the first, second, and third pixel electrodes
  • the portions are respectively disposed in the first, second, and third sub-pixel regions; the extended electrode portions of the first, second, and third pixel electrodes are disposed together in the first sub-pixel region;
  • the three thin film transistors are first, second, and third thin film transistors respectively disposed in the first, second, and third sub-pixel regions, wherein a gate of each of the thin film transistors and a corresponding gate a wire is electrically connected; a source of each of the thin film transistors is electrically connected to the data line; a drain of each of the thin film transistors and a corresponding pixel electrode thereof.
  • the first thin film transistor is an extended electrode portion that connects the first pixel electrode; the second thin film transistor is a main electrode portion that connects the second pixel electrode; and the third thin film transistor is connected to the third pixel electrode.
  • Main electrode portion In an embodiment of the invention, the first thin film transistor is an extended electrode portion that connects the first pixel electrode; the second thin film transistor is a main electrode portion that connects the second pixel electrode; and the third thin film transistor is connected to the third pixel electrode. Main electrode portion.
  • the extended electrode portion of the second pixel electrode is insulated to connect the main electrode portion of the second pixel electrode across at least one of the gate lines; the third pixel electrode The extension electrode portion is connected to the main electrode portion of the third pixel electrode in an insulating manner across at least one of the gate lines.
  • the present invention mainly divides each pixel electrode constituting a sub-pixel into a main electrode portion and an extension electrode portion in a three-gate pixel arrangement structure, so that an extension electrode portion of each pixel electrode in the unit pixel is disposed in the same sub-pixel region. In this way, when viewing from the above viewing angle, three colors of RGB can be seen at the same time, the effect of color compensation is achieved, and the color shift problem caused by the change of the viewing angle is improved.
  • FIG. 1 is a schematic diagram of an apparatus of a conventional 3D development system.
  • FIG. 2 is a schematic view showing a pixel arrangement of a conventional liquid crystal display device having a single-gate structure.
  • FIG. 3 is a schematic view showing a pixel arrangement of a conventional liquid crystal display device having a three-gate pixel structure.
  • FIG. 4 is a schematic view of a 3D liquid crystal display device having a three-gate pixel structure viewed from different viewing angles.
  • 5A is a schematic view showing a pixel arrangement seen when a 3D liquid crystal display device having a three-gate pixel structure is viewed from a horizontal angle of view.
  • FIG. 5B is a schematic diagram of a pixel arrangement seen when viewing a 3D liquid crystal display device having a three-gate pixel structure from a viewing angle.
  • FIG. 6 is a schematic diagram of a conventional three-gate pixel structure.
  • FIG. 7 is a schematic diagram of a pixel structure of a 3D liquid crystal display according to a preferred embodiment of the present invention.
  • FIG. 8 is a schematic diagram showing a photoresist structure of a color filter of a 3D liquid crystal display according to a preferred embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a pixel structure of a 3D liquid crystal display according to a preferred embodiment of the present invention.
  • the pixel structure in each pixel region includes three gate lines G1, G2, G3, a data line D1, a three-pixel electrode, and three thin film transistors T1, T2, T3.
  • the gate lines G1, G2, and G3 are arranged along a first direction.
  • the data line D1 is interleaved with the gate lines G1, G2, and G3, and further defines three sub-pixel regions 10R, 10G, and 10B with the gate lines G1, G2, and G3.
  • the sub-pixel regions 10R, 10G, 10B are also arranged in the first direction.
  • the sub-pixel regions 10R, 10G, and 10B are defined as a first sub-pixel region 10R, a second sub-pixel region 10G, and a third sub-pixel region 10B, respectively.
  • the pixel electrodes each include a main electrode portion 20a, 21a, 22a and an extended electrode portion 20b, 21b, 22b connecting the main electrode portions 10a, 21a, 22a, wherein the main electrode portions 20a, 21a, 22a of the pixel electrode.
  • Each of the extending electrode portions 20b, 21b, and 22b of the pixel electrode is disposed in one of the sub-pixel regions.
  • the pixel electrodes are respectively defined as a first pixel electrode, a second pixel electrode, and a third pixel electrode, wherein the main electrode portion 20a of the first pixel electrode is disposed in the first sub-pixel region 10R
  • the main electrode portion 21a of the second pixel electrode is disposed in the second sub-pixel region 10G
  • the main electrode portion 22a of the third pixel electrode is disposed in the third sub-pixel region 10B
  • the extended electrode portions 20b, 21b, and 22b of the first, second, and third pixel electrodes are disposed together in the first sub-pixel region 10R, wherein the extended electrode portion 21b of the second pixel electrode is insulated across at least One of the gate lines (G2) is connected to the main electrode portion 21a of the second pixel electrode; and the extended electrode portion 22b of the third pixel electrode is insulated across at least one of the gate lines (G2, G3)
  • the main electrode portion 22a of the third pixel electrode is connected.
  • the pixel electrode may be further partially overlapped with
  • the thin film transistors T1, T2, and T3 are respectively disposed in the first, second, and third sub-pixel regions 10R, 10G, and 10B, and the gates and corresponding gates of each of the thin film transistors T1, T2, and T3.
  • the pole lines G1, G2, and G3 are electrically connected; the sources of each of the thin film transistors T1, T2, and T3 are electrically connected to the data line D1; and the drains of each of the thin film transistors T1, T2, and T3 are It is electrically connected to its corresponding pixel electrode.
  • the thin film transistors T1, T2, and T3 can be divided into a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3, wherein the first thin film transistor T1 is an extension connecting the first pixel electrodes.
  • the electrode portion 20b; the second thin film transistor T2 is a main electrode portion 21a that connects the second pixel electrode; and the third thin film transistor T3 is a main electrode portion 22a that connects the third pixel electrode.
  • the pixel structure of the present invention is applied to a 3D liquid crystal display.
  • the basic structure of the 3D liquid crystal display is similar to that of a general liquid crystal display, and may include a first substrate, a second substrate, and a liquid crystal layer, wherein the second substrate and the substrate are The first substrate is oppositely disposed, and the liquid crystal layer is disposed between the first substrate and the second substrate.
  • the first substrate is provided with a plurality of gate lines and a plurality of data lines, the gate lines are arranged along the first direction, and the data lines are arranged in a second direction to be interlaced with the gate lines
  • a plurality of sub-pixel regions are defined, wherein a plurality of sub-pixel regions can be further defined by a pixel region.
  • the pixel structure of the present invention as shown in FIG. 7 is disposed in each pixel region.
  • the second substrate is provided with a color filter.
  • the color filter has a photoresist structure 3 corresponding to the pixel structure. As shown in FIG. 8
  • the photoresist structure 3 includes: a first photoresist region 300, a second photoresist region 301, and a third photoresist region 302, wherein the first photoresist region 300 and the second photoresist region
  • the positions of the 301 and the third photoresist regions 302 correspond to the first sub-pixel region 10R, the second sub-pixel region 10G, and the third sub-pixel region 10B, respectively;
  • the first photoresist region 300 includes a first photoresist at the same time.
  • the second photoresist region 301 includes a second photoresist 31a.
  • the third photoresist region 302 includes a third photoresist 32a.
  • the first photoresist 30 is a red photoresist; the second photoresists 31a and 31b are green photoresists; and the third photoresists 32a and 32b are blue photoresists
  • the shape and position of the first photoresist 30 in the first photoresist region 300 correspond to the main electrode portion 20a of the first pixel electrode and the extended electrode portion 20b thereof; and the first photoresist region 300
  • the shape and position of the second photoresist 31b correspond to the extended electrode portion 21b of the second pixel electrode;
  • the shape and position of the third photoresist 32b in the first photoresist region 300 correspond to the extended electrode of the third pixel electrode a portion 22b;
  • the main electrode portion 22a of the third pixel electrode corresponds to the position.
  • the 3D liquid crystal display having the pixel structure of the present invention may include at least one polarizer and a phase retarder (not shown).
  • the polarizer is disposed on the second substrate.
  • the phase retarder is configured to be disposed on an outer surface of the polarizer and overlapped with the second substrate to implement a 3D development function.
  • the phase retarder may include a plurality of first phase delay unit columns and a plurality of second phase delay unit columns, the second phase delay unit columns and the first phase delay unit columns being staggered to
  • the linearly polarized image of the polarizer is converted into a left circularly polarized image and a right circularly polarized image to be used as a left eye input image and a right eye input image, respectively.
  • An angle between an optical axis of the first phase delay unit column and a transmission axis of the polarizer is 135 degrees; an angle between an optical axis of the second phase delay unit column and a transmission axis of the polarizer is 45 degree.
  • the present invention mainly divides the pixel electrode into a main electrode portion and an extension electrode portion in a three-gate pixel arrangement structure, and the main electrode portions of the pixel electrodes are respectively disposed in corresponding sub-pixel regions.
  • the extended electrode portions of the pixel electrodes are disposed together in one of the sub-pixel regions.

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Description

3D液晶显示器及其像素结构 技术领域
本发明是有关于液晶显示器的像素结构，特别是有关于一种3D液晶显示器及其像素结构。
 背景技术
参考图1所示，现有一种3D显像系统是使影像会先通过偏光片90转为线性偏振影像。所述线性偏振影像接着经过1/4阵列波片91(λ/4 pattern retarder plate)。具有第一相位延迟列910及第二相位延迟列911的1/4阵列波片91可将线性偏振影像转为左圆偏振影像及右圆偏振影像，以分别作为左眼输入影像与右眼输入影像。观看者配戴的偏振眼镜8的两镜片皆由四分之一波片80及偏光片81构成。所述包括左圆偏振影像及右圆偏振影像的影像会先通过两镜片的四分之一波片80而转成线性偏振影像，接着再经过所述镜片的偏光片81后，分别到达观看者的双眼。由于两镜片的偏光片81具有不同偏振方向，使得使用者的左眼只能看到左眼输入影像，而右眼只能看到右眼输入影像，因而可达到三维影像的效果。
再者，液晶显示装置的像素结构可根据驱动模式区分为单栅式(single-gate)像素结构与三栅式(tri-gate)像素结构。请参考图2、图3及图6所示，图2是现有具有单栅式素结构的液晶显示装置的像素排列示意图；图3是现有具有三栅式像素结构的液晶显示装置的像素排列示意图；图6是现有三栅式像素结构的示意图。如图2所示，单栅式像素结构6的像素单元60的子像素区600、601、602是沿栅极线的长度方向排列；而如图3、图6所示，三栅式像素结构5的像素单元50的子像素区500、501、502是沿资料线的长度方向排列，子像素区500、501、502内分别设有像素电极52R、52G、52B，分别对应不同颜色的光阻。在相同的解析度下，相较于具有单栅型像素结构6的液晶显示装置，具有三栅式像素结构5的液晶显示装置的栅极线710数目增加为三倍，而资料线700数目则缩减为三分之一，因此具有三栅式像素结构的液晶显示装置的栅极驱动器71会使用较多的栅极驱动晶片，而源极驱动器70使用较少的源极驱动晶片。由于栅极驱动晶片的制造成本与能耗较低，因此采用三栅式像素结构5可降低液晶显示装置的制造成本及能耗。
然而，当图3的三栅式像素结构5欲应用于3D液晶显示器时，3D液晶显示器将会在上、下视角产生色偏问题。请参考图4所示，配戴偏振眼镜8的使用者以水平直视角度、上视角或下视角透过1/4阵列波片91的第一相位延迟列910及第二相位延迟列911来观看画面时，使用者两眼所接收的像素的混色效果会有所不同。以图4A为例，在水平直视角度下，使用者通过第二相位延迟列911看到的像素结构的子像素颜色的排列顺序为R、G、B；而以图4B而言，在上视角下(由上往下)，使用者通过第二相位延迟列911看到的像素结构的子像素颜色的排列变成G、B、R。由于第一相位延迟列910及第二相位延迟列911是用以形成左眼与右眼输入影像，一但第一相位延迟列910及第二相位延迟列911对应到错误的像素结构，将会导致色偏问题。
故，有必要提供一种3D液晶显示器及其像素结构，以解决现有技术所存在的问题。
 技术问题
有鉴于现有技术的缺点，本发明的主要目的在于提供一种3D液晶显示器及其像素结构，此像素结构可改善3D液晶显示器上、下视角的色偏问题。
 技术解决方案
本发明提供一种3D液晶显示器的像素结构，其包含：
三栅极线，沿一第一方向排列；
一资料线，与所述栅极线交错，而与所述栅极线定义出三子像素区，所述子像素区沿所述第一方向排列；以及
三像素电极，各包含一主电极部及一连接主电极部的延伸电极部，其中所述像素电极的主电极部各设置于对应的子像素区内，所述像素电极的延伸电极部一同设置于其中一子像素区内。
在本发明的一实施例中，所述像素结构进一步包括三薄膜晶体管，分别设置于所述子像素区内，每一所述薄膜晶体管的栅极与对应的栅极线电性连接；每一所述薄膜晶体管的源极均与所述资料线电性连接；每一所述薄膜晶体管的漏极与其对应的像素电极电性连接。
在本发明的一实施例中，所述子像素区分别为第一、第二及第三子像素区；所述像素电极分别为第一、第二及第三像素电极；所述第一、第二及第三像素电极的主电极部分别设置于所述第一、第二及第三子像素区内；所述第一、第二及第三像素电极的延伸电极部一同设置于所述第一子像素区内；以及
所述像素结构与一彩色滤光片的光阻结构相对应，其中所述光阻结构包括第一、第二及第三光阻区，其中所述第一、第二及第三光阻区位置分别对应所述第一、第二及第三子像素区；所述第一光阻区内同时包含一第一光阻、一第二光阻及一第三光阻；第二光阻区内包含一第二光阻；第三光阻区内包含一第三光阻。
在本发明的一实施例中，所述第一光阻区内的第一光阻形状跟位置对应所述第一像素电极的主电极部及其延伸电极部；所述第一光阻区内的第二光阻形状跟位置对应所述第二像素电极的延伸电极部；所述第一光阻区内的第三光阻形状跟位置对应所述第三像素电极的延伸电极部；
所述第二光阻区内的第二光阻形状跟位置对应所述第二像素电极的主电极部；以及
所述第三光阻区内的第三光阻形状跟位置对应所述第三像素电极的主电极部。
在本发明的一实施例中，所述第二像素电极的延伸电极部绝缘地横跨至少一所述栅极线而连接所述第二像素电极的主电极部；所述第三像素电极的延伸电极部绝缘地横跨至少一所述栅极线而连接所述第三像素电极的主电极部。
本发明另提供一种3D液晶显示器，其包括：
一第一基板，包括多个像素区，每一像素区包含一像素结构，所述像素结构包括：
三栅极线，沿第一方向排列；
一资料线，与所述栅极线交错，而与所述栅极线定义出三子像素区，所述子像素区沿所述第一方向排列；以及
三像素电极，各包含一主电极部及一连接主电极部的延伸电极部，其中所述像素电极的主电极部各设置于对应的子像素区内，所述像素电极的延伸电极部一同设置于其中一子像素区内；
一第二基板，与所述第一基板相对设置；
一液晶层，设于所述第一基板与第二基板之间；以及
一相位延迟片，与所述第二基板重叠设置。
在本发明的一实施例中，所述像素结构进一步包括三薄膜晶体管，分别设置于所述子像素区内，每一所述薄膜晶体管的栅极与对应的栅极线电性连接；每一所述薄膜晶体管的源极均与所述资料线电性连接；每一所述薄膜晶体管的漏极与其对应的像素电极电性连接。
在本发明的一实施例中，所述3D液晶显示器包括一设于所述第二基板上的偏光片；所述相位延迟片是设于所述偏光片外表面上，并包括：
多个第一相位延迟单元列；以及
多个第二相位延迟单元列，与所述第一相位延迟单元列呈交错排列。
在本发明的一实施例中，所述第一相位延迟单元列的光轴与所述偏光片的穿透轴夹角为135度；所述第二相位延迟单元列的光轴与所述偏光片的穿透轴夹角为45度。
在本发明的一实施例中，所述子像素区分别为第一、第二及第三子像素区；所述像素电极分别为第一、第二及第三像素电极；所述第一、第二及第三像素电极的主电极部分别设置于所述第一、第二及第三子像素区内；所述第一、第二及第三像素电极的延伸电极部一同设置于所述第一子像素区内；以及
所述第二基板设有一彩色滤光片，所述彩色滤光片具有光阻结构，对应所述第一基板的像素结构；所述光阻结构包括第一、第二及第三光阻区，其中所述第一、第二及第三光阻区位置分别对应所述第一、第二及第三子像素区；所述第一光阻区内同时包含一第一光阻、一第二光阻及一第三光阻；第二光阻区内包含一第二光阻；第三光阻区内包含一第三光阻。
本发明另提供一种3D液晶显示器的像素结构，其包括：
三栅极线，沿一第一方向排列；
一资料线，与所述栅极线交错，而与所述栅极线定义出三子像素区，分别为第一、第二及第三子像素区，所述三子像素区沿所述第一方向排列；
三像素电极，分别为第一、第二及第三像素电极，各包含一主电极部及一连接主电极部的延伸电极部，其中所述第一、第二及第三像素电极的主电极部分别设置于所述第一、第二及第三子像素区内；所述第一、第二及第三像素电极的延伸电极部一同设置于所述第一子像素区内；以及
三薄膜晶体管，分别为第一、第二及第三薄膜晶体管且分别设置于所述第一、第二及第三子像素区内，其中每一所述薄膜晶体管的栅极与对应的栅极线电性连接；每一所述薄膜晶体管的源极均与所述资料线电性连接；每一所述薄膜晶体管的漏极与其对应的像素电极。
在本发明的一实施例中，第一薄膜晶体管是连接第一像素电极的延伸电极部；第二薄膜晶体管是连接第二像素电极的主电极部；第三薄膜晶体管是连接第三像素电极的主电极部。
在本发明的一实施例中，所述第二像素电极的延伸电极部绝缘地横跨至少一所述栅极线而连接所述第二像素电极的主电极部；所述第三像素电极的延伸电极部绝缘地横跨至少一所述栅极线而连接所述第三像素电极的主电极部。
 有益效果
本发明主要是在三栅式像素排列架构下,将构成子像素的每一像素电极分成主电极部与延伸电极部，令单位像素内的每一像素电极的延伸电极部设置在同一子像素区内，如此一来，以上视角观看的时候，可同时看到RGB三种颜色，达到颜色补偿的效果，改善因视角改变产生的色偏问题。
 附图说明
图1是现有3D显像系统的装置示意图。
图2是现有具有单栅式素结构的液晶显示装置的像素排列示意图。
图3是现有具有三栅式像素结构的液晶显示装置的像素排列示意图。
图4是以不同视角观看具有三栅式像素结构的3D液晶显示装置的示意图。
图5A是以水平视角观看具有三栅式像素结构的3D液晶显示装置时所看到的像素排列的示意图。
图5B是以上视角观看具有三栅式像素结构的3D液晶显示装置时所看到的像素排列的示意图。
图6是现有三栅式像素结构的示意图。
图7是本发明一较佳实施例的3D液晶显示器的像素结构的示意图。
图8是本发明一较佳实施例的3D液晶显示器的彩色滤光片的光阻结构的示意图。
 本发明的最佳实施方式
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下。再者，本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参考图7所示，图7是本发明一较佳实施例的3D液晶显示器的像素结构的示意图。如图7所示，每一像素区内的像素结构包括三栅极线G1、G2、G3、一资料线D1、三像素电极以及三薄膜晶体管T1、T2、T3。
所述栅极线G1、G2、G3沿一第一方向排列。
所述资料线D1与所述栅极线G1、G2、G3交错，进而与所述栅极线G1、G2、G3定义出三子像素区10R、10G、10B。所述子像素区10R、10G、10B同样沿所述第一方向排列。本实施例中，所述子像素区10R、10G、10B分别定义为第一子像素区10R、第二子像素区10G及第三子像素区10B。
所述像素电极各包含一主电极部20a、21a、22a及一连接主电极部10a、21a、22a的延伸电极部20b、21b、22b，其中所述像素电极的主电极部20a、21a、22a各设置于对应的子像素区10R、10G、10B内，所述像素电极的延伸电极部20b、21b、22b则一同设置于其中一子像素区内。在本实施例中，所述像素电极分别定义为第一像素电极、第二像素电极及第三像素电极，其中所述第一像素电极的主电极部20a设置于所述第一子像素区10R内；所述第二像素电极的主电极部21a设置于所述第二子像素区10G内；所述第三像素电极的主电极部22a设置于所述第三子像素区10B内；所述第一、第二及第三像素电极的延伸电极部20b、21b、22b则一同设置于所述第一子像素区10R内，其中所述第二像素电极的延伸电极部21b绝缘地横跨至少一所述栅极线(G2)而连接所述第二像素电极的主电极部21a；所述第三像素电极的延伸电极部22b绝缘地横跨至少一所述栅极线(G2、G3)而连接所述第三像素电极的主电极部22a。所述像素电极可进一步与一共通电极线(图中未示)部分重叠，以构成储存电容。
所述薄膜晶体管T1、T2、T3分别设置于所述第一、第二及第三子像素区10R、10G、10B内，每一所述薄膜晶体管T1、T2、T3的栅极与对应的栅极线G1、G2、G3电性连接；每一所述薄膜晶体管T1、T2、T3的源极均与所述资料线D1电性连接；每一所述薄膜晶体管T1、T2、T3的漏极与其对应的像素电极电性连接。在本实施例中，所述薄膜晶体管T1、T2、T3可区分为第一薄膜晶体管T1、第二薄膜晶体管T2及第三薄膜晶体管T3，其中第一薄膜晶体管T1是连接第一像素电极的延伸电极部20b；第二薄膜晶体管T2是连接第二像素电极的主电极部21a；第三薄膜晶体管T3是连接第三像素电极的主电极部22a。
本发明的像素结构应用于一3D液晶显示器中，该3D液晶显示器的基本结构与一般液晶显示器相似，可包括一第一基板、一第二基板及一液晶层，其中所述第二基板与所述第一基板相对设置，而所述液晶层设于所述第一基板与第二基板之间。所述第一基板上设有多条栅极线及多条资料线，所述栅极线沿所述第一方向排列，所述资料线沿第二方向排列而与所述栅极线交错并定义多个子像素区，其中相邻数个子像素区可再定义一像素区。本发明如图7的像素结构即是配置于每一像素区内。所述第二基板设有一彩色滤光片，请进一步参考图8所示，所述彩色滤光片具有对应所述像素结构的光阻结构3。如图8所示，所述光阻结构3包括：第一光阻区300、第二光阻区301及第三光阻区302，其中所述第一光阻区300、第二光阻区301及第三光阻区302位置分别对应所述第一子像素区10R、第二子像素区10G及第三子像素区10B；所述第一光阻区300内同时包含一第一光阻30、一第二光阻31b及一第三光阻32b；第二光阻区301内包含一第二光阻31a；第三光阻区302内包含一第三光阻32a。本实施例中，所述第一光阻30为红色光阻；所述第二光阻31a、31b为绿色光阻；所述第三光阻32a、32b为蓝色光阻。
更详细地，所述第一光阻区300内的第一光阻30形状跟位置对应所述第一像素电极的主电极部20a及其延伸电极部20b；所述第一光阻区300内的第二光阻31b形状跟位置对应所述第二像素电极的延伸电极部21b；所述第一光阻区300内的第三光阻32b形状跟位置对应所述第三像素电极的延伸电极部22b；所述第二光阻区301内的第二光阻31a形状跟位置对应所述第二像素电极的主电极部21a；所述第三光阻区302内的第三光阻32a形状跟位置对应所述第三像素电极的主电极部22a。
由上述说明可知，在所述第一子像素区10R内的延伸电极部20a、21a、22a对应不同光阻而能显示不同颜色，使得每一像素区内的像素结构在上视角或下视角下可获得颜色补偿的效果，进而改善视角改变所产生的色偏问题。
相似其他现有的3D液晶显示器，所述具有本发明的像素结构的3D液晶显示器可包含至少一偏光片及一相位延迟片(图未示)。所述偏光片用以设于所述第二基板上。所述相位延迟片则用以设于所述偏光片的外表面上而与所述第二基板重叠设置，以实现3D显像的功能。所述相位延迟片可包括多个第一相位延迟单元列及多个第二相位延迟单元列，所述第二相位延迟单元列与所述第一相位延迟单元列呈交错排列，以将来自所述偏光片的线性偏振影像转为左圆偏振影像及右圆偏振影像，以分别作为左眼输入影像与右眼输入影像。所述第一相位延迟单元列的光轴与所述偏光片的穿透轴夹角为135度；所述第二相位延迟单元列的光轴与所述偏光片的穿透轴夹角为45度。
由上述说明可知，本发明主要是在三栅式像素排列架构下，将像素电极分成主电极部及延伸电极部，令所述像素电极的主电极部各设置于对应的子像素区内，而所述像素电极的延伸电极部则一同设置于其中一子像素区内。如此一来，相较于现有三栅式像素结构所应用的3D液晶显示器在上、下视角具有色偏问题，本发明的像素结构可通过延伸电极部于同一子像素区内显示的不同颜色来达到颜色补偿的效果，进而改善因视角改变产生的色偏问题。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。
 本发明的实施方式
工业实用性
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Claims (13)

  1. 一种3D液晶显示器的像素结构，其包括：
    三栅极线，沿一第一方向排列；
    一资料线，与所述栅极线交错，而与所述栅极线定义出三子像素区，分别为第一、第二及第三子像素区，所述三子像素区沿所述第一方向排列；
    三像素电极，分别为第一、第二及第三像素电极，各包含一主电极部及一连接主电极部的延伸电极部，其中所述第一、第二及第三像素电极的主电极部分别设置于所述第一、第二及第三子像素区内；所述第一、第二及第三像素电极的延伸电极部一同设置于所述第一子像素区内；以及
    三薄膜晶体管，分别为第一、第二及第三薄膜晶体管且分别设置于所述第一、第二及第三子像素区内，其中每一所述薄膜晶体管的栅极与对应的栅极线电性连接；每一所述薄膜晶体管的源极均与所述资料线电性连接；每一所述薄膜晶体管的漏极与其对应的像素电极。
  2. 如权利要求1所述的3D液晶显示器的像素结构，其中：第一薄膜晶体管是连接第一像素电极的延伸电极部；第二薄膜晶体管是连接第二像素电极的主电极部；第三薄膜晶体管是连接第三像素电极的主电极部。
  3. 如权利要求1所述的3D液晶显示器的像素结构，其中：所述第二像素电极的延伸电极部绝缘地横跨至少一所述栅极线而连接所述第二像素电极的主电极部；所述第三像素电极的延伸电极部绝缘地横跨至少一所述栅极线而连接所述第三像素电极的主电极部。
  4. 一种3D液晶显示器的像素结构，其包括：
    三栅极线，沿一第一方向排列；
    一资料线，与所述栅极线交错，而与所述栅极线定义出三子像素区，所述子像素区沿所述第一方向排列；以及
    三像素电极，各包含一主电极部及一连接主电极部的延伸电极部，其中所述像素电极的主电极部各设置于对应的子像素区内，所述像素电极的延伸电极部一同设置于其中一子像素区内。
  5. 如权利要求4所述的3D液晶显示器的像素结构，其中：所述像素结构进一步包括三薄膜晶体管，分别设置于所述子像素区内，每一所述薄膜晶体管的栅极与对应的栅极线电性连接；每一所述薄膜晶体管的源极均与所述资料线电性连接；每一所述薄膜晶体管的漏极与其对应的像素电极电性连接。
  6. 如权利要求4所述的3D液晶显示器的像素结构，其中：
    所述子像素区分别为第一、第二及第三子像素区；所述像素电极分别为第一、第二及第三像素电极；所述第一、第二及第三像素电极的主电极部分别设置于所述第一、第二及第三子像素区内；所述第一、第二及第三像素电极的延伸电极部一同设置于所述第一子像素区内；以及
    所述像素结构与一彩色滤光片的光阻结构相对应，其中所述光阻结构包括第一、第二及第三光阻区，其中所述第一、第二及第三光阻区位置分别对应所述第一、第二及第三子像素区；所述第一光阻区内同时包含一第一光阻、一第二光阻及一第三光阻；第二光阻区内包含一第二光阻；第三光阻区内包含一第三光阻。
  7. 如权利要求6所述的3D液晶显示器的像素结构，其中：
    所述第一光阻区内的第一光阻形状跟位置对应所述第一像素电极的主电极部及其延伸电极部；所述第一光阻区内的第二光阻形状跟位置对应所述第二像素电极的延伸电极部；所述第一光阻区内的第三光阻形状跟位置对应所述第三像素电极的延伸电极部；
    所述第二光阻区内的第二光阻形状跟位置对应所述第二像素电极的主电极部；以及
    所述第三光阻区内的第三光阻形状跟位置对应所述第三像素电极的主电极部。
  8. 如权利要求6所述的3D液晶显示器的像素结构，其中：所述第二像素电极的延伸电极部绝缘地横跨至少一所述栅极线而连接所述第二像素电极的主电极部；所述第三像素电极的延伸电极部绝缘地横跨至少一所述栅极线而连接所述第三像素电极的主电极部。
  9. 一种3D液晶显示器，其包括：
    一第一基板，包括多个像素区，每一像素区包含一像素结构，所述像素结构包括：
    三栅极线，沿第一方向排列；
    一资料线，与所述栅极线交错，而与所述栅极线定义出三子像素区，所述子像素区沿所述第一方向排列；以及
    三像素电极，各包含一主电极部及一连接主电极部的延伸电极部，其中所述像素电极的主电极部各设置于对应的子像素区内，所述像素电极的延伸电极部一同设置于其中一子像素区内；
    一第二基板，与所述第一基板相对设置；
    一液晶层，设于所述第一基板与第二基板之间；以及
    一相位延迟片，与所述第二基板重叠设置。
  10. 如权利要求9所述的3D液晶显示器，其中：所述像素结构进一步包括三薄膜晶体管，分别设置于所述子像素区内，每一所述薄膜晶体管的栅极与对应的栅极线电性连接；每一所述薄膜晶体管的源极均与所述资料线电性连接；每一所述薄膜晶体管的漏极与其对应的像素电极电性连接。
  11. 如权利要求9所述的3D液晶显示器，其中：所述3D液晶显示器包括一设于所述第二基板上的偏光片；所述相位延迟片是设于所述偏光片外表面上，并包括：
    多个第一相位延迟单元列；以及
    多个第二相位延迟单元列，与所述第一相位延迟单元列呈交错排列。
  12. 如权利要求11所述的3D液晶显示器，其中：所述第一相位延迟单元列的光轴与所述偏光片的穿透轴夹角为135度；所述第二相位延迟单元列的光轴与所述偏光片的穿透轴夹角为45度。
  13. 如权利要求9所述的3D液晶显示器，其中：
    所述子像素区分别为第一、第二及第三子像素区；所述像素电极分别为第一、第二及第三像素电极；所述第一、第二及第三像素电极的主电极部分别设置于所述第一、第二及第三子像素区内；所述第一、第二及第三像素电极的延伸电极部一同设置于所述第一子像素区内；以及
    所述第二基板设有一彩色滤光片，所述彩色滤光片具有光阻结构，对应所述第一基板的像素结构；所述光阻结构包括第一、第二及第三光阻区，其中所述第一、第二及第三光阻区位置分别对应所述第一、第二及第三子像素区；所述第一光阻区内同时包含一第一光阻、一第二光阻及一第三光阻；第二光阻区内包含一第二光阻；第三光阻区内包含一第三光阻。
PCT/CN2012/079807 2012-07-05 2012-08-08 3d液晶显示器及其像素结构 Ceased WO2014005365A1 (zh)

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