Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
  • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
  • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/40—Bus structure
  • G06F13/4004—Coupling between buses
  • G06F13/4027—Coupling between buses using bus bridges
  • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
  • H04L27/2601—Multicarrier modulation systems
  • H04L27/2647—Arrangements specific to the receiver only
  • H04L27/2655—Synchronisation arrangements
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/69—Spread spectrum techniques
  • H04B1/707—Spread spectrum techniques using direct sequence modulation
  • H04B1/7073—Synchronisation aspects
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/69—Spread spectrum techniques
  • H04B1/713—Spread spectrum techniques using frequency hopping
  • H04B1/7156—Arrangements for sequence synchronisation

Definitions

• the invention also provides a method of transferring a data signal from a first clock domain to a second clock domain in a digital system, wherein the first clock domain comprises a first clock having a frequency less than a frequency of a second clock in the second clock domain, the method comprising:
• the data signal is simply transferred from the first clock domain to the second clock domain but a check is carried out as to whether or not a clock transition occurred in the first clock within the predetermined period. If a transition is detected, the data signal from the first clock domain is transferred again to the second clock domain, otherwise the initial transfer of the signal is deemed to have been "safe", i.e. there is no risk of meta-stability.
• the first clock domain comprises a first bus
• the second clock domain comprises a second bus
• data is transferred from the first bus to the second bus, both initially and if a subsequent transfer is deemed necessary. It also means that embodiments of the invention do not need to introduce the latency associated with serial flip flops or other arrangements typically used to match clock domains in the prior art.
• the edge detector is, as mentioned above, conveniently clocked by the second clock.
• the detecting means is clocked by the second clock
• the frequency of the first clock is 32 kHz and the frequency of the second clock is 16 MHz.
• the arrangement simply generates a "safe" synchronisation signal in order to determine whether or not it needs to transfer the data again from the first clock domain to the second clock domain again. It therefore does not matter as to the state of the data signal, which can change during the predetermined period, i.e. it is the value of the data signal in the first clock domain at the end of, or at another time during, the predetermined period which is transferred to the second clock domain if there has been a transition in the first clock cycle, which will generally mean that the value of the data signal will have changed. If there is no transition in the first clock cycle during the predetermined period, the data signal remains that which was transferred initially as generally this will mean that the data signal has not changed value.
• the system is in a steady state until at 565 ns the initialisation signal, start_sync, changes from zero to one, thus triggering the start of the synchronisation process.
• the initialisation signal will be generated by the second clock domain (generally controlling a higher power peripheral device) when it exits a sleep mode in order to request transfer of the data from the first clock domain (generally a lower power timing circuit).
• the down counter 4 is clocked by the next rising edge of the second clock, ck fast, causing it to start counting down from three, i.e. at 625 ns the output, sync_cnt, from the down counter 4 changes to three. It is necessary for the down counter 4 to count down from three because the positive edge detector 2 takes two cycles of the second clock, ck fast, for a positive transition to be detected, i.e. for the necessary logic signals to be passed through its flip-flops.
• a load_bus_fast value of one which is fed to the selector input of the multiplexer 18 causes the data signal, which is now hC, in the first bus, bus_slow, to be fed to the D input of the flip-flop 20, such that on the next rising edge of the second clock, ck fast, the data signal hC is transferred to the second bus, busjast.
• the frequency of the first clock, ck slow is sufficiently low to ensure that the transfer of the data signal is completed before a further positive transition in the first clock will occur.
• sync_cnt from the down counter 4 has reached zero, which causes the value of the first output 8 from the decision node 6 to be one, indicating that the system is ready to receive a new initialisation signal, i.e. the signal, ready, is equal to one.
• the data signal stored in the flip-flop 20 is a valid and stable value which can then be used in the system as data synchronised to the second clock, ck fast, e.g. output to the second bus, busjast, at this rising edge of the second clock, ck fast, as described above.
• the second and third outputs 10, 12 from the decision node 6 are zero when the output, sync_cnt, from the down counter 4 is zero, so no new data signal can be transferred from the first bus, bus_slow, to the flip-flop 20 at this time.

Landscapes

• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• General Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Computer Hardware Design (AREA)
• Information Transfer Systems (AREA)
• Synchronisation In Digital Transmission Systems (AREA)
• Manipulation Of Pulses (AREA)

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Applications Claiming Priority (2)

Publications (1)

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Citations (5)

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• 2012
  • 2012-06-27 GB GB1211425.2A patent/GB2503473A/en not_active Withdrawn
• 2013
  • 2013-06-18 TW TW102121535A patent/TWI604689B/zh not_active IP Right Cessation
  • 2013-06-20 US US14/411,208 patent/US9515812B2/en active Active
  • 2013-06-20 EP EP13731452.2A patent/EP2847664B1/en not_active Not-in-force
  • 2013-06-20 WO PCT/GB2013/051608 patent/WO2014001765A1/en not_active Ceased
  • 2013-06-20 KR KR1020157002135A patent/KR20150037900A/ko not_active Withdrawn
  • 2013-06-20 JP JP2015519327A patent/JP6192065B2/ja not_active Expired - Fee Related
  • 2013-06-20 CN CN201380034642.7A patent/CN104412222B/zh not_active Expired - Fee Related

Patent Citations (5)

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