WO2014000361A1

WO2014000361A1 - Manufacturing method of array substrate via holes and manufacturing method of array substrate

Info

Publication number: WO2014000361A1
Application number: PCT/CN2012/084244
Authority: WO
Inventors: 封宾; 白金超
Original assignee: 京东方科技集团股份有限公司; 北京京东方显示技术有限公司
Priority date: 2012-06-29
Filing date: 2012-11-07
Publication date: 2014-01-03
Also published as: CN102751241A; CN102751241B

Abstract

The invention discloses a manufacturing method of array substrate via holes, the manufacturing method comprising the following steps: step of pre-etching: respectively carrying out partial etching on a hierarchical structure above a metal layer corresponding to at least one of the regions in need of generating via holes, so that the corresponding metal layers in the regions in need of generating via holes have the same etching depth allowance; and step of etching: synchronously etching the regions in need of generating via holes until all the via holes reached the corresponding metal layers. In the manufacturing method of array substrate via holes disclosed by the invention, the regions with different etching depths are etched in different steps; after the pre-etching step, the via holes have the same etching depth allowance; and after the etching step, all the via holes are synchronously etched, so that all the via holes simultaneously reached the corresponding metal layers, thereby lowering the over-etching defectiveness generated at the via holes with shallower etching depth, and enhancing the product yield.

Description

Method for fabricating array substrate via and manufacturing method of array substrate

The present disclosure relates to the field of array substrate processing technology, and in particular, to a method for fabricating via holes of an array substrate and a process for fabricating the array substrate. Background technique

The via process is an important process in the fabrication of array substrates for liquid crystal display panels. In the preparation process of the array substrate, the metal strips at different levels or the different metal portions at the same level are usually exposed by a via process, and then the exposed portions of the metals at different levels are connected by a subsequent process, or Connected to different metal parts located at the same level, such as the connection between the gate line and the data line of the array substrate, the connection between the data line and the pixel electrode, and the formation of a matrix structure of the common electrode line. The quality of the via process directly affects the yield of the product and the associated performance of the final panel.

In the array substrate, the metals at different levels are different in depth from the upper surface of the product to be etched, that is, the etching depth is different. In some cases, even the different metal portions of the same layer have different depths relative to the upper surface of the product to be etched, i.e., the etch depth is different. For ease of description, in this paper, the etching depth in the array substrate is two: a metal layer far away from the etching surface of the array substrate is called a deep-region metal layer, and a via hole corresponding to the deep-region metal layer is called a deep The hole, the area where the deep hole is opened is called the deep hole area; the metal layer which is closer to the etching surface of the array substrate is called the shallow area metal layer, and the corresponding hole of the shallow area metal layer is called the shallow hole, and the shallow hole is opened. The area is called the shallow hole area. In the current via process of the array substrate preparation process, both the deep hole in the deep hole region and the shallow hole in the shallow hole region are uniformly formed by one mask etching, which is easy to cause the shallow layer metal layer to be engraved. Excessive eclipse.

Taking the via process between the gate line and the data line as an example, as shown in FIG. 1 and FIG. 2, FIG. 1 shows that the shallow hole in the shallow hole region of the data line metal layer in the conventional via process has been etched to Schematic diagram of the structure of the data line metal layer; FIG. 2 is a structural schematic view of the deep hole of the deep hole region where the gate line metal layer is etched to the gate line metal layer in the conventional via process.

As shown in FIG. 1, the array substrate shown in FIG. 1 includes a substrate 01, a gate line metal layer 06 deposited on the substrate 01 and etched, and a gate deposited on the gate line metal layer 06 and the substrate 01. a pole insulating layer 02, which is sequentially deposited on the gate insulating layer 02 and the active layer 03 and the data line metal layer 04, And an insulating layer 05 covering the above layers.

According to the structure shown in FIG. 1, the gate insulating layer 02 and the insulating layer 05 are provided on the gate line metal layer 06, and the etching depth is deep when forming the via hole from the upper surface of the array substrate, and belongs to the deep hole region; The data line metal layer 04 has only the insulating layer 05. When the via holes are formed from the upper surface of the array substrate, the etching depth is shallow and belongs to the shallow hole region. The deep hole 061 connected to the gate line metal layer 06 needs to etch the gate insulating layer 02 and the data insulating layer 05, and the shallow hole 041 connected to the data line metal layer 04 only needs to etch the insulating layer 05, so when the shallow hole After the 041 etching is completed, the surface metal of the data line metal layer 04 is exposed, and the deep hole 061 is etched only to the gate insulating layer 02, and the gate insulating layer 02 of the etching depth dl is also required to be etched.

As shown in Figure 2, when the deep hole 061 continues to etch, the data line metal layer 04 passes through the shallow hole.

041 The exposed metal will continue to etch. When the deep hole 061 is etched to the gate line metal layer 06, the etchant will have a depth d2 through the shallow hole 041 to the already exposed metal in the data line metal layer 04. The over-etching causes a poor alignment of the data line metal layer 04.

Poor etching can lead to oxidation of the metal surface, which can lead to undesirable electrical resistance or open circuit, which directly affects the yield of the product. Summary of the invention

The present disclosure provides a method for fabricating via holes of an array substrate and a process for fabricating the array substrate, so as to improve the over-cut defects generated in the via holes having a shallow via hole depth in the prior art via-hole process, thereby improving the yield of the product.

In order to achieve the above object, the present disclosure provides the following technical solutions.

According to an aspect, an embodiment of the present disclosure provides a method for fabricating a via of an array substrate, including: a pre-etching step corresponding to at least one of a plurality of regions in which a via is required to be generated, respectively The hierarchical structure above the metal layer is partially etched such that the etch depth margin to the corresponding metal layer is the same in the plurality of regions where the via holes are to be formed; and the etching step is performed on the plurality of regions where the via holes are required to be formed Simultaneous etching until each via reaches its metal layer.

In one example, the etch depth of the via holes generated in the plurality of regions where the via holes are required to be formed is two, wherein the deep etch holes are called deep holes, and the etch depth is shallow. The hole is called a shallow hole; in the pre-etching step, the deep hole region where the deep hole is located is partially etched, so that the etching depth margin of the deep hole region and the shallow hole region where the shallow hole is located are etched. The depth is the same.

In one example, the method further includes the following steps prior to the pre-etching step: coating Photoresist; exposure and development, full exposure of the photoresist in the deep hole region, half exposure of the photoresist in the shallow hole region, thereby retaining a portion of the photoresist in the shallow hole region; the etching step and The pre-etching step further includes the steps of: ashing, ashing to remove a portion of the photoresist remaining in the shallow hole region; the etching step further comprising the steps of: stripping, the remaining portion of the photoresist Remove.

In one example, in the exposing step, exposure is performed using a half mask having an all-transmissive region and a semi-transmissive region, wherein the semi-transmissive region of the semi-transmissive mask corresponds to the deep-hole region, The semi-transmissive region corresponds to the shallow hole region.

According to another aspect, an embodiment of the present disclosure provides an array substrate fabrication process including the steps of: forming a gate line metal layer on a substrate; forming a gate insulating layer on the gate line metal layer; An active layer and a data line metal layer are sequentially formed on the gate insulating layer; an insulating layer is formed on the data line metal layer and the gate insulating layer; and pre-etching is performed on a plurality of regions that need to generate via holes respectively The layer structure above the metal layer corresponding to at least one of the regions is partially etched such that the etch depth margin to the corresponding metal layer is the same in the plurality of regions where the via holes are to be formed; etching, A plurality of regions where via holes are to be formed are simultaneously etched until each via reaches the corresponding metal layer; an electrode layer is deposited to fill the via holes to achieve connection between the metal layers.

In one example, the metal layer in the deep hole region is a gate line metal layer, the metal layer in the shallow hole region is a data line metal layer, and the electrode layer connects the gate line metal layer and the data line metal Floor.

In one example, in the step of coating a photoresist, a photoresist is coated on the insulating layer; in the exposing and developing steps, photolithography of a deep hole region where a gate line metal layer is located The glue is completely exposed, and the photoresist in the shallow hole region where the data line metal layer is located is half-exposed, and a part of the photoresist in the shallow hole region is retained after development; in the pre-etching step, the depth of the full exposure is deep The hole region is partially etched, and a predetermined etch depth margin is left over the gate line metal layer, the predetermined etch depth margin and the etch depth of the shallow hole region where the data line metal layer is located In the ashing step, ashing removes a portion of the photoresist remaining in the shallow hole region; in the etching step, etching the shallow hole region and the deep hole region until the deep hole of the deep hole region reaches The gate line metal layer, at the same time, the shallow hole of the shallow hole region reaches the data line metal layer; in the stripping step, the excess photoresist is stripped and removed.

In the method for fabricating the via hole of the array substrate provided by the present disclosure, stepwise etching is performed on each of the regions where the via holes are required to be formed according to the etching depth of the etching to the corresponding metal layer. First, a region having a deep etching depth etched into a corresponding metal layer in a region where a via hole is to be formed by a pre-etching step The region is partially etched such that the etch depth margins etched into the corresponding metal layers in the plurality of regions where the vias are to be formed are the same. Of course, the same meaning here is only the same theoretical meaning. In the actual operation process, due to human factors, etchant and other factors and operational uncertainties, the etch depth margin of each region may have The difference is that the difference between the etching depths of the respective metal layers when the regions in which the plurality of via holes are required to be formed in the etching step can be reduced. Then, through the etching step, all the regions that need to generate via holes are synchronously etched, so that each via hole reaches the metal layer at the same time; by this method, the etching depth in the via region is required to be different in the etching depth. The deep via region is etched away to ensure that the etching margin between the vias is nearly the same during the etching step, so that each via reaches its corresponding metal layer at the same time, and the etching depth is reduced. Over-engraving phenomenon at the via.

Therefore, the method for fabricating the via hole of the array substrate provided by the present disclosure can improve the over-cutting phenomenon at the via hole with a shallow etching depth in the via process, and improve the product yield. DRAWINGS

In order to more clearly illustrate the technical solutions of the present disclosure or the prior art, the following description of the technical solutions provided in the present disclosure or the drawings used in the prior art description will be briefly introduced. Obviously, the drawings in the following description Only some of the specific embodiments of the technical solutions of the present disclosure are illustrated, and those skilled in the art can obtain other drawings according to the drawings without any creative work.

1 is a schematic view showing the structure of a shallow hole in a shallow hole region where a data line metal layer is etched to a data line metal layer in a via process in the prior art;

2 is a schematic structural view of a deep hole etched to a gate line metal layer of the deep hole region of a gate line metal layer in a via process in the prior art;

3 is a flowchart of a method for fabricating a via hole of an array substrate according to Embodiment 1 of the present disclosure; FIG. 4 is a flowchart of a method for fabricating a via hole of an array substrate according to Embodiment 2 of the present disclosure; A flow chart of the provided array substrate fabrication process;

6 is a flow chart of a process for fabricating an array substrate according to Embodiment 4 of the present disclosure;

7 is a schematic structural view of an array substrate after a step of coating a photoresist in an array substrate manufacturing process according to Embodiment 4 of the present disclosure; 8 is a schematic structural view of an array substrate after exposure of a step in an array substrate manufacturing process according to Embodiment 4 of the present disclosure;

9 is a schematic structural view of an array substrate after pre-etching in a process of fabricating an array substrate according to Embodiment 4 of the present disclosure;

10 is a schematic structural view of an array substrate after ashing in an array substrate manufacturing process according to Embodiment 4 of the present disclosure;

11 is a schematic structural view of an array substrate after step etching in an array substrate fabrication process according to Embodiment 4 of the present disclosure;

12 is a schematic structural view of an array substrate after stripping steps in an array substrate fabrication process according to Embodiment 4 of the present disclosure;

13 is a schematic structural view of an array substrate after a step of depositing an etched electrode layer in a process of fabricating an array substrate according to Embodiment 4 of the present disclosure. detailed description

The technical solutions in the embodiments of the present disclosure are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present disclosure. It is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without departing from the inventive scope are the scope of the disclosure.

Embodiment 1:

As shown in FIG. 3, the embodiment provides a method for fabricating a via hole of an array substrate, and the method includes:

Step 101: pre-etching, partially etching a hierarchical structure above the metal layer corresponding to at least one of the plurality of regions in which the via holes are to be formed, so as to etch in a plurality of regions where the via holes are required to be formed The etching depth of the corresponding metal layer is the same;

Step 102: Etching, synchronously etching a plurality of regions where via holes are to be formed until each via reaches a corresponding metal layer.

In the method for fabricating the via hole of the array substrate provided by the present disclosure, stepwise etching is performed on each of the regions where the via holes are required to be formed according to the etching depth of the etching to the corresponding metal layer. First, the etching depth to the corresponding metal layer in the region where the via hole is to be formed is deep by the step 101 pre-etching. The area is partially etched such that the etch depth margins etched into the corresponding metal layers in the plurality of regions where the vias are to be formed are the same. Of course, the same meaning here is only the same meaning in theory. In the actual operation process, due to human factors, etchant and other factors and operational uncertainties, the etch depth margin of each region may have The difference is that the difference between the etching depths of the metal layers in the etching of the regions in which the plurality of via holes are required to be formed in the etching in step 102 can be reduced. Then, after etching in step 102, all the regions that need to generate via holes are synchronously etched, so that each via hole reaches the metal layer at the same time; by this method, the etching depth in the via region is required to be different in etching depth first. A deeper via region is etched away to ensure that the etching margin between the vias is nearly the same in the etching in step 102, so that each via reaches its corresponding metal layer at the same time, and the etching depth is lowered. Overcutting at shallow vias.

Therefore, the method for fabricating the via hole of the array substrate provided by the present disclosure can improve the over-cutting phenomenon at the via hole with a shallow etching depth in the via process, and improve the product yield.

Embodiment 2:

As described above, the etch depth of the via holes in the region of the array substrate where a plurality of via holes are required to be formed is two, wherein the deep etching depth is called deep hole, and the shallow etching depth is called shallow hole. Correspondingly, the area where the deep hole is located is called the deep hole area, and the area where the shallow hole is located is called the shallow hole area. As shown in FIG. 4, the method for fabricating the via hole of the array substrate provided in this embodiment includes:

Step 201: coating a photoresist;

Step 202: exposing and developing, completely exposing the photoresist in the deep hole region, and semi-exposing the photoresist in the shallow hole region, thereby retaining a portion of the photoresist in the shallow hole region after development;

Step 203: pre-etching, partially etching the deep hole region, and leaving a predetermined etching depth margin above the metal layer in the deep hole region, the predetermined etching depth margin and the shallow hole region engraving The etch depth is the same:

Step 204, ashing and ashing to remove a portion of the photoresist in the shallow hole region;

Step 205, etching, synchronously etching the shallow hole region and the deep hole region until the deep hole of the deep hole region reaches the corresponding metal layer, and at the same time, the shallow hole of the shallow hole region reaches the corresponding metal layer; The excess photoresist is peeled off.

In this embodiment, after the photoresist is applied in step 201, the etching portion of the deep hole region is exposed by exposure in step 202, and the etching portion of the shallow hole region is protected by the photoresist remaining after the half exposure. Therefore, the effect of etching only the deep hole region during etching is achieved; after the pre-etching is completed in step 203, the photoresist is removed by the step 204, and the remaining photoresist in the shallow hole region is removed by ashing to remove the shallow hole region. The etched portion of the region is exposed, and then etching is performed in step 205 to simultaneously etch the deep hole region and the shallow hole region. After the etching in step 205 is completed, the remaining photoresist is removed by stripping in step 206, so that Affect the subsequent process.

Preferably, in the exposing step 202, the semi-transmissive mask having the full transparent region and the semi-transmissive region is used for exposure, wherein the semi-transmissive region of the semi-transmissive mask corresponds to the deep-hole region, and the semi-transparent The area corresponds to the shallow hole area.

In this embodiment, the stepwise etching of the deep hole region and the shallow hole region can be realized by applying a primary photoresist by a half exposure technique using a semi-transparent mask, which simplifies the process.

Embodiment 3:

As shown in FIG. 5, the present disclosure also provides an array substrate fabrication process using the method described in Embodiment 1. The process includes:

Step 301, forming a gate line metal layer on the substrate;

Step 302, forming a gate insulating layer on the gate line metal layer;

Step 303, sequentially forming an active layer and a data line metal layer on the gate insulating layer;

Step 304, forming an insulating layer over the data line metal layer and the gate insulating layer.

As described above, the etch depth of the via holes in the region of the array substrate where a plurality of via holes are required to be formed is two, wherein the deep etching depth is called deep hole, and the shallow etching depth is called shallow hole. Correspondingly, the area where the deep hole is located is called the deep hole area, and the area where the shallow hole is located is called the shallow hole area.

Step 305: Pre-etching, respectively, partially etching a hierarchical structure above the metal layer corresponding to at least one of the plurality of regions in which the via holes are to be generated, so that a plurality of regions of the via holes need to be generated to the corresponding metal The etching depth of the layer is the same, that is, the gate insulating layer and the insulating layer above the gate line metal layer are partially etched, so that the etching depth of the deep hole region of the gate line metal layer that needs to generate the via hole is The amount of etching depth of the shallow hole region of the metal layer of the data line where the via hole is to be formed is the same;

Step 306, etching, performing synchronous etching on the plurality of regions that need to generate via holes, until each via hole reaches a corresponding metal layer;

Step 307, depositing an electrode layer in the via hole to realize a connection between the corresponding metal layers, that is, a connection between the gate line metal layer and the data line metal layer.

The array substrate fabricated by using the above array substrate fabrication process has greatly improved the overetching phenomenon at the shallow via hole, and reduces the resistance in the region where the via hole having a shallow etching depth is excessive or Bad disconnection and other factors have improved the yield of the product. In the pre-etching of step 305, the deep hole region where the deep hole is located is partially etched so that the etching depth of the deep hole region is the same as the etching depth of the shallow hole region where the shallow hole is located.

Embodiment 4:

As shown in FIG. 6 and FIG. 7, the array substrate manufacturing process provided by this embodiment uses the method described in the second embodiment. The process includes:

Step 401, forming a gate line metal layer 6 on the substrate 1;

Step 402, forming a gate insulating layer 2 on the gate line metal layer 6;

Step 403, sequentially forming an active layer 3 and a data line metal layer 4 on the gate insulating layer 2; Step 404, forming an insulating layer 5 over the data line metal layer 4 and the gate insulating layer 2; Step 405, as shown in 7 is coated with a photoresist 7 on the insulating layer 5;

Step 406, exposing and developing, as shown in FIG. 8, completely exposing the photoresist of the deep hole region A of the gate line metal layer 6 to the photoresist of the shallow hole region B of the data line metal layer 4. After performing half exposure, a portion of the photoresist 8 remains in the shallow hole region after development; after the photoresist in the deep hole region A is completely exposed, the etched surface in the deep hole region A is completely exposed; and the shallow hole region B is engraved The etched surface is also protected by the photoresist portion 8;

Step 407, as shown in FIG. 9, partially etching the fully exposed deep hole region A, the etching depth D1 is as shown in FIG. 9, and leaving a predetermined etching depth above the gate line metal layer 6. The amount D2, the etch depth margin D2 is as shown in FIG. 9; the predetermined etch depth margin D2 remaining above the gate line metal layer 6 is the same as the etch depth D3 of the shallow hole region;

Step 408, as shown in FIG. 10, ashing to remove the exposure margin of the photoresist in the shallow hole region; by ashing, the exposure margin of the half-exposure photoresist in the shallow hole region is removed by ashing, The etched surface in the shallow hole region is exposed;

Step 409, as shown in FIG. 11, etching the shallow hole region and the deep hole region until the deep hole of the deep hole region is connected to the gate line metal layer 6, and the shallow hole of the shallow hole region is connected to the data line metal Layer 5;

Step 410, as shown in FIG. 12, removes excess photoresist.

Specifically, the etching depth of the insulating layer 5 is the same as the etching depth of the gate insulating layer 2. Therefore, in the step pre-etching, the deep hole is pre-etched to the gate insulating layer 2.

Step 411 deposits an electrode layer to achieve a connection between the respective metal layers, that is, a connection between the gate line metal layer and the data line metal layer.

In the above third embodiment and the fourth embodiment, only the manufacturing process of the array substrate is listed. In the process, the via holes of the array substrate described in the first embodiment and the second embodiment are used to fabricate via holes. Of course, the specific structure of the array substrate is various, and the metal layers in the array substrate that require via connections are various. The number of deep holes and shallow holes may also have various options according to actual needs. In the above array, for example, in an array substrate having other hierarchical structures, the deep metal layer may be a data line metal layer, and the shallow metal layer is a pixel. Electrode layer, the electrode layer realizes the connection between the data line metal layer and the pixel electrode layer.

Of course, there are other options for the deep-zone metal layer and the shallow-zone metal layer, which are no longer mentioned here. The above embodiments are merely illustrative of the present invention and are not to be construed as limiting the scope of the invention, and various modifications and changes can be made without departing from the spirit and scope of the invention. Equivalent technical solutions are also within the scope of the invention, and the scope of the invention is defined by the claims.

Claims

claims

1. A method for making via holes in an array substrate, which is characterized by including:

The pre-etching step is to partially etch the hierarchical structure above the metal layer corresponding to at least one of the multiple areas where via holes need to be generated, so that the etching from the multiple areas where via holes need to be generated to the corresponding metal layer is The corrosion depth allowance is the same;

In the etching step, the multiple areas where via holes need to be generated are simultaneously etched until each via hole reaches its metal layer.

2. The method for manufacturing array substrate via holes according to claim 1, characterized in that the etching depths of the via holes generated in the plurality of areas where via holes need to be generated are two types, wherein the etching depth is greater than Deep vias are called deep holes, and vias with shallow etching depth are called shallow holes;

In the pre-etching step, the deep hole area where the deep hole is located is partially etched so that the etching depth margin of the deep hole area is the same as the etching depth of the shallow hole area where the shallow hole is located.

3. The method for manufacturing array substrate via holes according to claim 2, characterized in that, before the pre-etching step, the method further includes the following steps:

Apply photoresist;

Exposure and development, fully exposing the photoresist in the deep hole area, and semi-exposing the photoresist in the shallow hole area, thereby retaining part of the photoresist in the shallow hole area;

The step further includes the following steps between the etching step and the pre-etching step:

Ashing removes part of the photoresist remaining in the shallow hole area;

After the etching step, the following steps are also included:

Peel off and remove the remaining part of the photoresist.

4. The method for manufacturing array substrate via holes according to claim 3, characterized in that, in the exposure step, a half mask with a fully transparent area and a semi-transmissive area is used for exposure, wherein: The fully transparent area of the semi-transparent mask corresponds to the deep hole area, and the semi-transparent area corresponds to the shallow hole area.

5. An array substrate manufacturing process, characterized by including the following steps:

Form a gate line metal layer on the substrate;

forming a gate insulating layer on the gate line metal layer;

Form an active layer and a data line metal layer on the gate insulating layer in sequence;

Form an insulating layer on the data line metal layer and the gate insulating layer;

Pre-etching, respectively etching the gold corresponding to at least one area among the multiple areas where via holes need to be generated. The hierarchical structure above the metal layer is partially etched so that the etching depth margin to the corresponding metal layer in multiple areas where via holes need to be generated is the same;

Etching, simultaneously etching the multiple areas where via holes need to be generated until each via hole reaches the corresponding metal layer;

An electrode layer is deposited to fill the via holes and realize the connection between the metal layers.

6. The array substrate manufacturing process according to claim 5, characterized in that, the via holes generated in the plurality of areas where via holes need to be generated need to be etched to two etching depths, wherein the etching depth is greater than Deep vias are called deep holes, and vias with shallow etching depth are called shallow holes;

7. The array substrate manufacturing process according to claim 6, wherein the metal layer located in the deep hole area is a gate line metal layer, and the metal layer located in the shallow hole area is a data line metal layer, and the electrode A layer connects the gate line metal layer and the data line metal layer.

8. The array substrate manufacturing process according to claim 7, wherein before the pre-etching step, the method further includes the following steps:

Apply photoresist;

Ashing removes part of the photoresist remaining in the shallow hole area;

After the etching step, the following steps are also included:

Peel off and remove the remaining part of the photoresist

9. The array substrate manufacturing process according to claim 8, characterized in that:

In the step of applying photoresist, apply photoresist on the insulating layer;

In the exposure and development steps, the photoresist in the deep hole area where the gate line metal layer is located is fully exposed, and the photoresist in the shallow hole area where the data line metal layer is located is half exposed, and is retained after development. Part of the photoresist in the shallow hole area;

In the pre-etching step, the fully exposed deep hole area is partially etched, and a predetermined etching depth margin is left above the gate line metal layer. The predetermined etching depth margin is consistent with the above data. The etching depth of the shallow hole area where the line metal layer is located is the same;

In the ashing step, part of the photoresist remaining in the shallow hole area is removed by ashing; In the etching step, the shallow hole area and the deep hole area are etched until the deep hole in the deep hole area reaches the gate line metal layer, and at the same time, the shallow hole in the shallow hole area reaches the data line metal layer ; During the peeling step, excess photoresist is peeled off and removed.

10. The array substrate manufacturing process according to claim 9, characterized in that, in the exposure and development steps, a half-mask template having a fully exposed area and a semi-exposed area is used, and the fully exposed area corresponds to the Deep hole area, the half-exposed area corresponds to the shallow hole area.