WO2013189073A1

WO2013189073A1 - Decision feedback equalizer and receiver

Info

Publication number: WO2013189073A1
Application number: PCT/CN2012/077339
Authority: WO
Inventors: 付生猛; 王海莉
Original assignee: 华为技术有限公司
Priority date: 2012-06-21
Filing date: 2012-06-21
Publication date: 2013-12-27
Also published as: CN102870386A; CN102870386B

Abstract

The embodiments of the present invention relate to a decision feedback equalizer and a receiver. The equalizer comprises: a receiving end for receiving a first data signal; a first adjusting unit for performing phase adjustment on a square wave signal outputted by a decider, superposing the square wave signal after phase adjustment and the first data signal to obtain a second data signal, and inputting the second data signal to a first input end of the decider; a second adjusting unit for performing phase adjustment on the data border of the square wave signal outputted by the decider, and then inputting the square wave signal after phase adjustment to a second input end of the decider as a third data signal; a decider for comparing the amplitude of the second data signal inputted to the first input end with the amplitude of the third data signal inputted to the second input end, outputting a square wave signal, and respectively outputting the square wave signal into the first adjusting unit and the second adjusting unit. Adjusting for both voltage amplitude jitter and data border jitter of the adjusted data signal is realized.

Description

Decision feedback equalizer and receiver

The present invention relates to the field of communications technologies, and in particular, to a decision feedback equalizer and a receiver. BACKGROUND OF THE INVENTION With the development of digital signal technology toward high speed and large capacity, the demand for high rate signal processing technology is becoming more and more urgent. The Inter Symbol Interference (ISI) generated during signal transmission is a key factor that restricts the signal rate. ISI will cause pulse broadening, causing the voltage amplitude of the data signal to be unstable, causing jitter on the data edges of the data signal. The bit error ratio (BER) of the channel increases.

In the prior art, the received data signal is subjected to delay processing and then fed back to the receiving end to be superimposed with the data signal received by the receiving end. However, this method cannot balance the voltage amplitude of the data signal and the adjustment of the data edge jitter. SUMMARY OF THE INVENTION Embodiments of the present invention provide a decision feedback equalizer and a receiver, which achieve both voltage amplitude and data edge jitter of adjusting a data signal.

In one aspect, an embodiment of the present invention provides a decision feedback equalizer, including: a receiving end, a first adjusting unit, a second adjusting unit, and a decider;

The receiving end is configured to receive a first data signal, and synchronize a local clock with a frequency of the first data signal, so that a period of the local clock is consistent with a period of the first data signal; a unit, configured to perform phase adjustment on the square wave signal output by the determiner, and superimpose the phase-adjusted square wave signal and the first data signal to obtain a second data signal, and the second data Transmitting a signal to a first input of the decider;

The second adjusting unit is configured to adjust a data edge of the square wave signal output by the decider, and input the adjusted square wave signal as a third data signal to a second input of the determiner end; The determiner is configured to compare the amplitudes of the second data signal input by the first input terminal and the third data signal input by the second input terminal, and output the square wave signal, And inputting the square wave signal to the first adjustment unit and the second adjustment unit, respectively.

In another aspect, an embodiment of the present invention provides a receiver, including: a photoelectric converter, a decision feedback equalizer, and a clock data recovery module;

The photoelectric conversion module is configured to convert the received optical signal into an electrical signal, and input the electrical signal as the first data signal to the decision feedback equalizer;

The decision feedback equalizer includes: a receiving end, a first adjusting unit, a second adjusting unit, and a determiner; the receiving end is configured to receive the first data signal, and synchronize the local clock with the frequency of the first data signal And causing the period of the local clock to coincide with a period of the first data signal; the first adjusting unit, configured to perform phase adjustment on a square wave signal output by the determiner, and adjust a square wave after phase adjustment And superimposing the signal on the first data signal to obtain a second data signal, and inputting the second data signal to a first input end of the determiner; the second adjusting unit, configured to determine the Adjusting the data edge of the square wave signal output by the device, and inputting the adjusted square wave signal as a third data signal to the second input end of the determiner; the determiner is configured to Comparing the amplitude of the second data signal input by an input terminal and the third data signal input by the second input terminal, outputting the square wave signal, and converting the square wave Number are input to the first adjusting means and the second adjustment means;

The clock recovery module is configured to receive a square wave signal output by the decider of the decision equalizer, and synchronize the local clock with the square wave signal.

The decision feedback equalizer and the receiver provided by the embodiment of the present invention use two adjustment units to respectively adjust the square wave signal output by the decider, and the data signal obtained by adjusting one adjustment unit is superimposed on the data signal received by the feedback equalizer as An input terminal of the determiner realizes voltage amplitude adjustment of the data signal; and another data signal obtained by adjusting the adjustment unit serves as another input end of the determiner, thereby realizing adjustment of the data edge of the data signal, thereby enabling adjustment The voltage amplitude and data edge jitter of the data signal. DRAWINGS

The drawings used in the examples or in the description of the prior art are briefly introduced, obviously, below The drawings in the description are only some of the embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative work.

1 is a schematic structural diagram of a first embodiment of a decision feedback equalizer according to the present invention; FIG. 2 is a unit impulse response in the case where an ISI exists in a transmission channel in the embodiment shown in FIG. 1. FIG. 3 is a decision feedback equalization provided by the present invention. FIG. 4 is a schematic structural diagram of a third embodiment of a decision feedback equalizer according to the present invention; FIG. 5 is a schematic structural diagram of a fourth embodiment of a decision feedback equalizer according to the present invention; A schematic diagram of a structure of a fifth embodiment of a decision feedback equalizer provided by the present invention; FIG. 7 is a schematic structural diagram of a first embodiment of a receiver provided by the present invention. The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. example. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

FIG. 1 is a schematic structural diagram of a first embodiment of a decision feedback equalizer according to the present invention. As shown in FIG. 1, the decision feedback equalizer includes: a receiving end 11, a first adjusting unit 12, a second adjusting unit 13, and a decider. 14;

The receiving end 11 is configured to receive a first data signal, and synchronize a local clock with a frequency of the first data signal, so that a period of the local clock is consistent with a period of the first data signal;

The first adjusting unit 12 is configured to perform phase adjustment on the square wave signal output by the decider 14, and superimpose the phase-adjusted square wave signal and the first data signal to obtain a second data signal, and the second data signal Input to the first input 141 of the decider 14;

The second adjusting unit 13 is configured to adjust the data edge of the square wave signal output by the determiner 14, and input the adjusted square wave signal as the third data signal to the second input end 142 of the determiner 14;

a determiner 14 configured to compare a voltage amplitude of the second data signal input by the first input terminal 141 and the third data signal input by the second input terminal 142, output the square wave signal, and the square wave The signals are input to the first adjustment unit 12 and the second adjustment unit 13, respectively.

The decision feedback equalizer provided by the embodiment of the present invention may be set on multiple optical network devices. For example, it can be set in an Optical Line Terminal (OLT), or in an Optical Network Unit (ONU), or in an Optical Network Terminal (ONT). The decision feedback equalizer can adjust the voltage amplitude and data edge of the data signal sent by the transmitting end.

The decision feedback equalizer provided by the embodiment of the present invention includes two feedback loops, wherein the output of the decider 14 and the first adjusting unit 12 form a feedback loop for outputting a square wave to the output of the decider 14. The voltage amplitude of the signal is adjusted; the output of the decider 14, the second adjusting unit 13 and the second input 142 of the decider 14 form another feedback loop for the square wave signal outputted to the output of the decider 14. The data is adjusted along the edge.

Since the data signals sent by the transmitting end are usually square wave signals, and the data signals are transmitted through the transmission link, the first data signal received by the receiving end is interspersed with the interference signal, so that the data signal is distorted, for example: data signal The period of the data is relatively large, and the tailing time of the unit impulse response of the data signal is long. After the adjustment by the first adjusting unit 12, the square wave signal outputted by the output end of the determiner 14 and the interference of the channel on the voltage amplitude of the square wave signal have been reduced; after the adjustment by the second adjusting unit 13, the decision is made. The square wave signal outputted from the output of the device 14 has a reduced jitter of the data edge of the square wave signal.

The arbiter 14 can be implemented by using various existing comparators, or can be implemented by logic circuits composed of logic devices. The determiner 14 compares the voltage amplitudes of the second data signal and the third data signal. In an implementation scenario, the voltage amplitude of the second data signal at the same time is greater than the voltage amplitude of the third data signal, and then the decision is made. The device 14 can output a high level, and if the voltage amplitude of the second data signal is less than the voltage amplitude of the third data signal, the decider 14 can output a low level. Alternatively, if the voltage amplitude of the second data signal at the same time is greater than the voltage amplitude of the third data signal, the determiner 14 may output a low level if the voltage amplitude of the second data signal is less than the voltage amplitude of the third data signal. The value, then the decider 14 can output a high level. The high and low levels outputted by the decider 14 form a square wave signal, which is input to the first adjusting unit 12 and the second adjusting unit 13, respectively.

Optionally, the first adjusting unit 12 may be specifically configured to: perform at least one phase delay on the square wave signal, delay each phase by an integer multiple of the local clock, and obtain a first delay signal each time the phase delay, therefore, A plurality of first delay signals are obtained by performing a plurality of phase delays, and the plurality of delay signals are superimposed with the first data signals to obtain a second data signal. If the first adjustment unit 12 performs a phase delay on the square wave signal, only one first delay signal is obtained, then the second data signal The number is the first delayed signal itself.

Optionally, the second adjusting unit 3 is specifically configured to: perform at least one phase delay on the square wave signal, delay each phase by an odd multiple of a half cycle of the local clock, and obtain a first delay signal each time phase delay, And performing a plurality of phase delays to obtain a plurality of second delay signals, and superimposing the plurality of second delay signals to obtain a third data signal. If the second adjustment unit 3 performs a phase delay for the square wave signal, only one second delay signal is obtained, and then the third data signal is the second delay signal itself.

When the transmission channel between the transmitting end and the receiving end is idle, the square wave test signal is input to obtain a unit impulse response diagram as shown in FIG. 2, and FIG. 2 is the case where the transmission channel between the transmitting end and the receiving end has ISI. The unit impulse response, the solid curve represents the time domain waveform generated by the current time data signal through the transmission channel at the receiving end, and the dashed curve represents the time domain waveform generated by the data signal at the previous moment. It can be seen from Fig. 2 that, for the voltage amplitude of the data signal, in addition to the voltage amplitude generated by the current data signal, the voltage generated at the current time by the data signal at the previous moment or even earlier is superimposed. Moreover, the influence on the voltage amplitude of the current data signal is mainly the time of an integer multiple of the period of the data signal, that is, 0, T, 2 Τ η Τ. Therefore, the voltage amplitude of the data signal at the current time can be expressed as: α1*Τ+α2*2Τ+ ... +αη*ηΤ. Where α1 and α2 αη are coefficients, and the values of a1 and a2 an can be calculated according to Fig. 2, for example: The ratio of the value of the unit impulse response at the current sampling time to the peak value of the unit impulse response can be selected, wherein the current sampling time is An integer multiple of the data signal. According to this, the first adjusting unit 12 can perform multiple phase delays on the square wave signal, and each phase is delayed by an integer multiple of the local clock to obtain a plurality of first delay signals, and the plurality of first delay signals and the first A data signal is superimposed to obtain a second data signal. The second data signal is superimposed with the data signal of the previous cycle, or even earlier, so that the voltage amplitude interference in the square wave signal output by the decider 14 is eliminated.

Similarly, for the data edge of the data signal, that is, the trailing portion of the data signal, in addition to the voltage generated by the current data signal, the data signal of the previous moment is superimposed, and even the tail of the previous data signal is at the current moment. The voltage produced. The influence on the data edge of the current data signal is mainly the time of an odd multiple half cycle of the data signal, that is, T/2, 3Τ/2 (2η+1)Τ/2. Therefore, the data edge of the data signal at the current time can be expressed as: 0.5-(β1 -0.5)*Τ/2-(β2-0.5)*3Τ/2- ...-(βη-0.5)*(2η+1 ) Τ/2). Where β1, β2 βη are coefficients, and the values of β1 and β2 βη can be calculated according to Fig. 2, for example: The ratio of the value of the unit impulse response at the current sampling time to the peak value of the unit impulse response is taken, wherein the current sampling moment may be an odd multiple of a half period of the data signal. According to this, the second adjusting unit 13 can perform multiple phase delays on the square wave signal, and each phase is delayed by an odd multiple of a half cycle of the local clock to obtain a plurality of second delayed signals, and the plurality of second delayed signals are obtained. Superimposed to obtain a third data signal. The data signal of the first half cycle, or even the earlier half cycle, is superimposed on the third data signal, thereby eliminating data edge misinterference in the square wave signal output by the decider 14.

In the decision feedback equalizer provided by the embodiment, two adjustment units respectively perform phase adjustment on the square wave signal output by the determiner, and the data signal obtained by adjusting one adjustment unit is superimposed on the data signal received by the feedback equalizer as a decider. One input terminal realizes voltage amplitude adjustment of the data signal; the other adjusted data unit is used as the other input end of the determiner, thereby realizing adjustment of the data edge of the data signal, thereby being able to adjust the voltage of the data signal Amplitude and data edge jitter.

FIG. 3 is a schematic structural diagram of a second embodiment of a decision feedback equalizer according to the present invention. As shown in FIG. 3, the first adjustment unit 12 may include: a first delay module 21 and a first coefficient. Module 22 and adder 23;

The first delay module 21 is configured to perform a phase delay for the square wave signal, delay the integer multiple of the local clock to obtain a third delay signal, and input the third delay signal to the first coefficient module 22;

The first coefficient module 22 is configured to adjust a voltage amplitude of the third delay signal input by the first delay module 21 to obtain a first delay signal, and input the first delay signal to the adder 23; the adder 23, The first delay signal input by the first coefficient module 22 is superimposed with the first data signal, and the obtained second data signal is input to the first input terminal 141 of the decider 14.

The voltage amplitude based on the current time of the data signal described above can be expressed as:

11 *Τ+α2*2Τ+...... +αη*ηΤ.

A plurality of first delay modules 21 may be disposed in the first adjusting unit 12, and the first delay modules 21 may respectively perform a phase delay for the square wave signal to obtain a square wave signal delay respectively.

多个, 2Τ ηΤ obtained a plurality of third delayed signals. That is, the phase of the delay of each first delay module 21 may be different, and the plurality of first delay modules 21 may be used to delay the square wave signal by D, 2 Τ η, respectively.

Correspondingly, a plurality of first coefficient modules 22 may be disposed in the first adjusting unit 12, each The first coefficient module 22 may correspond to a first delay module 21, for example: a first coefficient module 22 may correspond to the first delay module 21 for delaying the square wave signal T, and may be used to pass The first delay module 21 delays the voltage amplitude adjustment of the third delayed signal obtained after the adjustment, for example, by multiplying α1 to obtain a first delayed signal; and the other first coefficient module 22 can be used to delay the square wave signal by 2Τ. Corresponding to the first delay module 21, which can be used to adjust the amplitude of the third delay signal obtained after the delay adjustment of the first delay module 21, for example, by multiplying α2, to obtain a first delay signal; A first coefficient module 22 may be associated with the first delay module 21 for delaying the square wave signal by η , and may be used for delaying the third delay signal obtained after the first delay module 21 is delayed. The amplitude adjustment, for example multiplied by an, yields the first delayed signal.

The adder 23 may be connected to the first coefficient module 22 by using a device such as an adder, superimposing the first delayed signal input by the first coefficient module 22 with the first data signal, and inputting the obtained second data signal to the decision. The first input 141 of the device 14.

In order to simplify the structure of the first adjusting unit 12, as a possible implementation manner, as shown in FIG. 3, the multiple first delay modules 21 in the first adjusting unit 12 may be arranged in series, each of the first coefficient modules 22 The input can be coupled to the output of a first delay module 21, and the output of each first coefficient module 22 is coupled to the input of the adder 23. In this implementation scenario, the delay time of the first wave delay signal of each first delay module 21 may be equal, for example, one cycle T may be delayed.

Optionally, the number of the first delay modules 21 between the adjacent first coefficient modules 22 is equal. As shown in FIG. 3, a first delay module 21 may be disposed between the adjacent first coefficient modules 22. So that the first adjusting unit 12 can superimpose the data signals of the respective previous integer multiples of the current time data signal on the current time data signal, thereby realizing the data signals of the previous integer multiple times of the current data signal. The effect of the voltage amplitude on the current data signal voltage amplitude.

4 is a schematic structural diagram of a third embodiment of a decision feedback equalizer according to the present invention. As shown in FIG. 4, as a feasible structure, the second adjusting unit 13 may include: a second delay module 31 and a second coefficient. Module 32;

The second delay module 31 is configured to perform a phase delay for the square wave signal, delay the odd multiple times of the local clock to obtain a fourth delay signal, and input the fourth delay signal to the second coefficient module 32;

The second coefficient module 32 is configured to adjust a voltage amplitude of the fourth delay signal input by the second delay module 31 to obtain a second delay signal, and input the second delay signal to the determiner 14 Two inputs 142.

The second delay module 31 can be used for phase delay of the square wave signal, and can obtain a fourth delay signal obtained after the square wave signal delay 172, or 3T/2 or (2n+1)T/2.

Correspondingly, the second coefficient module 32 can be configured to adjust a voltage amplitude of the fourth delay signal obtained by delay adjustment of the second delay module 31 to obtain a second delay signal. The magnitude of the voltage amplitude adjustment of the second coefficient module 32 may be different according to the delay time of the second delay module 31.

Optionally, if the second delay module 31 delays the square wave signal by Τ/2, the second coefficient module 32 may adjust the voltage amplitude of the fourth delay signal obtained by delay adjustment of the second delay module 31. For example, multiplying (β1-0.5) to obtain a second delay signal; or, if the second delay module 31 delays the square wave signal by 3Τ/2, the second coefficient module 32 may pass the second delay module. 31 The voltage amplitude adjustment of the fourth delayed signal obtained after the delay adjustment, for example, multiplied by (β2-0.5), to obtain a second delayed signal; ... or, the second delay module 31 delays the square wave signal (2η+ 1) Τ/2, the second coefficient module 32 may adjust the voltage amplitude of the fourth delayed signal obtained by delay adjustment of the second delay module 31, for example, multiplying (βη-0.5) to obtain a second Delay signal.

In this embodiment, due to a second delay signal obtained by the second adjusting unit 13, the second delayed signal itself is the third data signal, and the second coefficient module 32 obtains the obtained second delay signal (ie, the first The three data signals are input to the second input 142 of the decider 14.

FIG. 5 is a schematic structural diagram of a fourth embodiment of a decision feedback equalizer according to the present invention. As shown in FIG. 5, as a feasible structure, the second adjusting unit 13 may include: a second delay module 31 and a second coefficient. Module 32 and subtractor 33;

The second coefficient module 32 is configured to adjust a voltage amplitude of the fourth delay signal input by the second delay module 31 to obtain a second delay signal, and input the second delay signal to the subtractor 33; the subtractor 33, The second delay signal input by the second coefficient module 32 is superimposed, and the obtained third data signal is input to the second input terminal 142 of the decider 14.

Optionally, the plurality of second delay modules 31 may be disposed in series, and the input end of each second coefficient module 32 is connected to the output end of a second delay module 31, and the output of each second coefficient module 32 is The terminal is connected to the input of the subtractor 33.

The data edge based on the current time of the data signal described above can be expressed as:

0.5-(β1 -0.5)*Τ/2-(β2-0.5)*3Τ/2- ... -(βη-0.5)*(2η+1)Τ/2).

The plurality of second delay modules 31 can be respectively used for phase delay of the square wave signal, and respectively obtain a plurality of fourth delayed signals obtained by delaying the square wave signal by Τ/2, 3Τ/2 (2η+1)Τ/2. . That is, the phase delayed by each second delay module 31 may be different, and the plurality of first delay modules 21 may be respectively used to delay the square wave signal by Τ/2, 3Τ/2 (2η+1) Τ/2.

Correspondingly, each second coefficient module 32 can correspond to a second delay module 31, for example: a second coefficient module 32 can be associated with the second delay module 31 for delaying the square wave signal by Τ/2. Correspondingly, the voltage amplitude of the fourth delay signal obtained by delay adjustment of the second delay module 31 can be adjusted, for example, multiplied by (β1-0.5) to obtain a second delay signal; another second coefficient The module 32 can be associated with the second delay module 31 for delaying the square wave signal by 3 Τ/2, and can be used to adjust the voltage amplitude of the fourth delay signal obtained by delay adjustment of the second delay module 31. For example, multiplying by (β2-0.5), a second delay signal is obtained; ... a second coefficient module 32 can be associated with the second delay module 31 for delaying the square wave signal by (2η+1) Τ/2 Correspondingly, the voltage amplitude of the fourth delay signal obtained by delay adjustment of the second delay module 31 can be adjusted, for example, multiplied by (βη-0.5) to obtain a second delayed signal.

The subtracter 33 is configured to be connected to the plurality of second coefficient modules 32, superimposing the plurality of second delay signals input by the plurality of second coefficient modules 32, and inputting the third data signal to the second input of the decider 14. End 142.

In order to simplify the structure of the first adjusting unit 13, as a possible implementation manner, as shown in FIG. 5, a plurality of second delay modules 31 in the first adjusting unit 13 may be arranged in series, and each second coefficient module 32 The input terminal can be connected to the output of a second delay module 31, and the output of each second coefficient module 32 is coupled to the input of the subtractor 33. In this implementation scenario, the delay time of the second wave delay signal of each second delay module 31 may be equal, for example: a half cycle 12 may be delayed.

Optionally, the number of the second delay modules 31 between the adjacent second coefficient modules 32 is equal. As shown in FIG. 5, a second delay module 31 may be disposed between the adjacent second coefficient modules 32. So that the second adjusting unit 13 can superimpose the data signals of the previous odd-numbered half-cycles of the current time data signal on the current time data signal, thereby realizing the elimination of the current time data signals. The influence of the data edge of the data signal of the previous odd-numbered half-cycle on the data edge of the current data signal.

On the basis of the embodiment of the decision feedback equalizer shown in FIG. 3 and FIG. 5, in order to further simplify the structure of the decision feedback equalizer, as shown in FIG. 6, optionally, each of the second adjustment units 13 The second delay adjustment 31 module in series may be used as a first delay adjustment module 21 in the first adjustment unit 12.

In the embodiment shown in FIG. 6, the delay time of each second delay adjustment 31 module may be a half cycle, and the plurality of second delay adjustments 31 connected in series belong to the first adjustment unit 12 and the second adjustment unit, respectively. The two feedback loops formed by the first feedback unit 12 have a delay of an integer multiple of the period, and the feedback delay of the feedback loop belonging to the second adjustment unit 13 is an odd multiple of a half period. The signal input by the first input terminal 141 of the decider 14 is: the current data signal and the data signal after an integer multiple period delay, which can be expressed by the expression α1 *Τ+α2*2Τ+... +αη* ηΤ is expressed; the signal input by the second input terminal 142 of the arbiter 14 is: an odd-numbered half-cycle delay data signal, which can be expressed by the expression: 0.5-(β1 -0.5)*Τ/2-(β2- 0.5) *3Τ/2- ...-(βη-0.5)*(2η+1)172) to express.

The decision feedback equalizer provided by this embodiment is provided by the output end of the decider 14 and the first adjusting unit

12 constitutes a feedback loop capable of adjusting the voltage amplitude of the square wave signal output by the decider 14, and the feedback loop formed by the output of the determiner 14, the second adjusting unit 13 and the second input 142 of the decider 14 can The data edge of the output square wave signal is adjusted by the decider 14, so that the voltage amplitude and the data edge of the adjustment data signal can be achieved.

FIG. 7 is a schematic structural diagram of a receiver according to a first embodiment of the present invention. As shown in FIG. 7, the receiver includes: a photoelectric converter 41, a decision feedback equalizer 42 and a clock data recovery module 43; and a photoelectric conversion module 41. For converting the received optical signal into an electrical signal, and inputting the electrical signal as a first data signal to the decision feedback equalizer;

The decision feedback equalizer 42 may be the decision feedback equalizer disclosed in the above embodiment; and may include: a receiving end, a first adjusting unit, a second adjusting unit, and a decider; and a receiving end, configured to receive the first data signal; The adjusting unit is configured to perform phase adjustment on the square wave signal output by the determiner, and superimpose the phase-adjusted square wave signal and the first data signal to obtain a second data signal, and input the second data signal to the determiner a first input end; a second adjusting unit, configured to perform phase adjustment on a data edge of the square wave signal output by the decider, and input the adjusted square wave signal as a third data signal to the second input end of the determiner a decider for inputting the first input Comparing the amplitudes of the two data signals and the third data signal input by the second input terminal, outputting a square wave signal, and inputting the square wave signals to the first adjusting unit and the second adjusting unit respectively;

The clock recovery module 43 is configured to receive a square wave signal output by the decider of the decision equalizer, and synchronize the local clock with the square wave signal. Specifically, the clock recovery module 43 synchronizes the local clock so that the local clock and the received square wave signal have the same phase and frequency, so that the sampling is accurate.

The receiver provided by the embodiment of the present invention may be an optical network device such as an OLT, an ONU, or an ONT. The structure of the decision feedback equalizer and its function may refer to the decision feedback equalizer embodiment provided in FIG. 1 to FIG. 6 of the present invention. I will not repeat them here.

One of ordinary skill in the art will appreciate that all or a portion of the steps to implement the various method embodiments described above can be accomplished by hardware associated with the program instructions. The aforementioned program can be stored in a computer readable storage medium. The program, when executed, performs the steps including the above-described method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

It should be noted that the above embodiments are only for explaining the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: The technical solutions described in the foregoing embodiments are modified, or some of the technical features are equivalently replaced. The modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

Rights request

1. A decision feedback equalizer, characterized in that it includes: a receiving end, a first adjustment unit, a second adjustment unit and a decider;

The receiving end is used to receive the first data signal and synchronize the local clock with the frequency of the first data signal so that the period of the local clock is consistent with the period of the first data signal; the first adjustment Unit, configured to perform phase adjustment on the square wave signal output by the determiner, superimpose the phase-adjusted square wave signal with the first data signal, obtain a second data signal, and combine the second data The signal is input to the first input terminal of the decision device;

The second adjustment unit is used to adjust the data edge of the square wave signal output by the determiner, and input the adjusted square wave signal as a third data signal to the second input of the determiner. end;

The determiner is used to compare the voltage amplitude of the second data signal input to the first input terminal and the voltage amplitude of the third data signal input to the second input terminal, and output the square wave signal , and input the square wave signal to the first adjustment unit and the second adjustment unit respectively.

2. The decision feedback equalizer according to claim 1, characterized in that, the first adjustment unit is specifically configured to: perform at least one phase delay on the square wave signal, and each phase delay is an integer of the local clock. times the period, to obtain at least one first delay signal, and superpose the at least one delay signal and the first data signal to obtain the second data signal;

The second adjustment unit is specifically configured to: perform at least one phase delay on the square wave signal, delay each phase by an odd multiple of half cycles of the local clock, and obtain at least one second delayed signal. If the second delayed signal There are multiple second delay signals, and the third data signal is obtained by superimposing the plurality of second delay signals. If there is only one second delay signal, the second delay signal itself is the third data signal.

3. The decision feedback equalizer according to claim 2, characterized in that the first adjustment unit includes: a first delay module, a first coefficient module and an adder;

The first delay module is used to phase-delay the square wave signal, delay an integer multiple of the local clock cycles to obtain a third delay signal, and input the third delay signal to the first delay module. coefficient module;

The first coefficient module is used to adjust the voltage amplitude of the third delay signal input by the first delay module, obtain the first delay signal, and input the first delay signal to the stacker;

The superpositioner is used to superimpose the first delay signal input by the first coefficient module and the first data signal, and input the obtained second data signal to the first input of the decision device. end.

4. The decision feedback equalizer according to claim 3, characterized in that, the first coefficient module is used to multiply the voltage amplitude of the third delayed signal by an, and the value of an is the unit impulse response. The ratio of the value at the current sampling time to the unit impulse response peak value, where n is a value that is an integer multiple of cycles of the local clock, n is an integer, and the current sampling time is n times a cycle of the local clock.

5. The decision feedback equalizer according to claim 3 or 4, characterized in that a plurality of first delay modules are connected in series, and the input end of each first coefficient module is connected to an input end of one of the first delay modules. The output terminal is connected, and the output terminal of each first coefficient module is connected with the input terminal of the adder.

6. The decision feedback equalizer according to any one of claims 3 to 5, characterized in that the delay time of each first delay module to the first output signal is equal, and the delay time of the adjacent first delay modules is equal to that of the first output signal. The number of first delay modules between the first coefficient modules is equal.

7. The decision feedback equalizer according to any one of claims 2 to 6, characterized in that the second adjustment unit includes: a second delay module and a second coefficient module;

The second delay module is used to delay the square wave signal once, delay an odd multiple of the local clock by half cycles to obtain a fourth delay signal, and input the fourth delay signal to the third delay signal. Two-coefficient module;

The second coefficient module is used to adjust the voltage amplitude of the fourth delay signal input by the second delay module to obtain the second delay signal, and input the second delay signal to The second input terminal of the decision device.

8. The decision feedback equalizer according to claim 7, characterized in that the second coefficient module is used to multiply the voltage amplitude of the fourth delayed signal by (βΓΠ-0.5), βΓΊ The value is the ratio of the value of the unit impulse response at the current sampling time to the peak value of the unit impulse response, where m is the value of an odd multiple of half cycles of the local clock, m is an odd number, and the current sampling time is m of the local clock. times half cycle.

9. The decision feedback equalizer according to any one of claims 2 to 6, characterized in that the second adjustment unit includes a second delay module, a second coefficient module and a subtractor,

The second delay module is used to delay the square wave signal once, delaying the local Obtain a fourth delay signal at odd multiples of half cycles of the clock, and input the fourth delay signal to the second coefficient module;

The second coefficient module is used to adjust the voltage amplitude of the fourth delay signal input by the second delay module to obtain the second delay signal, and input the second delay signal to the subtractor;

The subtractor is used to superpose the second delay signal input by the second coefficient module, and input the obtained third data signal to the second input terminal of the decision device.

10. The decision feedback equalizer according to claim 9, characterized in that the second coefficient module is used to multiply the voltage amplitude of the fourth delayed signal by (βΓΠ-0.5), and the value of βΓΊ is The value is the ratio of the value of the unit impulse response at the current sampling time to the peak value of the unit impulse response, where m is the value of an odd multiple of half cycles of the local clock, m is an odd number, and the current sampling time is m of the local clock. times half cycle.

11. The decision feedback equalizer according to any one of claims 7-10, characterized in that a plurality of second delay modules are connected in series, and the input end of each second coefficient module is connected to one of the second delay modules. The output end of the delay module is connected, and the output end of each second coefficient module is connected to the input end of the subtractor.

12. The decision feedback equalizer according to any one of claims 7-10, characterized in that the delay time of each second delay module to the first output signal is equal, and the delay time of the adjacent second delay modules is equal to that of the first output signal. The number of second delay modules between the second coefficient modules is equal.

13. The decision feedback equalizer according to claim 11 or 12, characterized in that, every two second delay adjustment modules in the second adjustment unit connected in series, as one of the first adjustment units one of the first delay adjustment modules.

14. A receiver, characterized in that it includes: a photoelectric converter, a decision feedback equalizer as claimed in any one of claims 1 to 13, and a clock data recovery module;

The photoelectric conversion module is used to convert the received optical signal into an electrical signal, and input the electrical signal as a first data signal to the decision feedback equalizer;

The clock recovery module is used to receive the square wave signal output by the decision unit in the decision equalizer, and synchronize the local clock with the square wave signal.

15. The receiver according to claim 14, characterized in that the receiver is an optical network terminal OLT, an optical network unit ONU or an optical fiber network equipment ONT.