Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G01R19/14—Indicating direction of current; Indicating polarity of voltage
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
  • G05F3/02—Regulating voltage or current
  • G05F3/08—Regulating voltage or current wherein the variable is dc
  • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
  • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
  • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
  • G05F3/26—Current mirrors
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
  • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
  • H02H3/18—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to reversal of direct current
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy
  • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

Definitions

• This relates generally to electronic devices and, more particularly, to power protection circuitry for electronic devices.
• an accessory device may have a display, speakers, or other components that can be used by a host electronic device in playing media files or other content for a user.
• the host device may supply power to the accessory. If the accessory is defective or poorly designed, the accessory may supply power to the host device rather than drawing power from the host device. This behavior, which may sometimes be referred to as back-powering, may cause damage to the host device .
• An accessory may potentially back-power a host electronic device. To prevent damage to the host
• the electronic device may be provided with a protection circuit.
• the protection circuit may be used to block current flow between the accessory and the host device whenever a back-powering condition is
• the host electronic device may be coupled to the accessory electronic device by a power supply path.
• the host device may supply the accessory device with power over a power supply line.
• the accessory may attempt to deliver power to the host device. This type of back-powering operation is undesirable and may be prevented by
• a current mirror may be formed using the protection transistor and an additional transistor.
• a biasing circuit may be used to maintain the drain of the
• the biasing circuit may include mirror transistors formed in a cascode arrangement.
• the biasing circuit may be used to bias the current through the additional transistor to match a predetermined bias current. By biasing the current through the additional transistor to the predetermined bias current and using the cascode arrangement, variations associated with temperature may be mitigated.
• the current mirror may produce a sense current that is proportional to the amount of current currently flowing through the protection transistor and the power supply line.
• a current-to-voltage amplifier may produce a sense voltage that is proportional to the sense current.
• the bias circuit may be configured so that the current-to-voltage amplifier produces a sense voltage that is proportional to the sense current minus the
• a control circuit may use a comparator to compare the sense voltage to a reference voltage .
• the control circuit may turn on the protection transistor to allow the host device to power the accessory whenever the sense voltage is at a level indicating that power is flowing from the host to the accessory.
• the protection transistor may also be turned on so long as no more than an acceptably small amount of reverse current is presented on the power supply line.
• the control circuit may turn off the transistor to prevent current flow from the accessory into the host device over the power supply line.
• the control circuit may detect severe back- powering conditions using a first comparator.
• the control circuit may detect moderate back-powering conditions of excessive duration using a second comparator and a detection circuit.
• the control circuit may turn off the protection transistor in response to either detection of a severe back-powering condition or a moderate back-powering condition of excessive duration.
• a sink transistor may be coupled to the power supply line to divert back-power current away from power supply circuitry of the device.
• the sink transistor may be controlled by the control circuitry based on the sense voltage to sink an appropriate amount of back-current.
• FIG. 1 is a diagram of a system in which a host electronic device is coupled to an accessory electronic device in accordance with an embodiment of the present invention .
• FIG. 2 is graph showing signals that may be measured in an electronic device to detect back-powering conditions in accordance with an embodiment of the present invention .
• FIG. 3 is a circuit diagram of illustrative protection circuitry in accordance with an embodiment of the present invention.
• FIG. 4 is a circuit diagram of illustrative protection circuitry having a cascode mirror arrangement in accordance with an embodiment of the present invention.
• FIG. 5 is a diagram showing how sensed voltage may depend on output current for the circuitry of FIG. 4.
• FIG. 6 is a diagram showing how the circuitry of FIG. 4 may help mitigate variations in sensed voltage associated with temperature in accordance with an
• FIG. 7 is a diagram showing how the circuitry of FIG. 4 may be adjusted to different bias settings in accordance with an embodiment of the present invention.
• FIG. 8 is a diagram of illustrative control circuitry that may detect severe and moderate back- powering conditions in accordance with an embodiment of the present invention.
• FIG. 9 is a timing diagram showing how the control circuitry of FIG. 8 may response to a severe back- powering condition in accordance with an embodiment of the present invention.
• FIG. 10 is a timing diagram showing how the control circuitry of FIG. 8 may response to a moderate back-powering condition in accordance with an embodiment of the present invention.
• FIG. 11 is a diagram of illustrative protection circuitry having a sink transistor in accordance with an embodiment of the present invention.
• system 8 may include a host device such as electronic device 10 and an accessory device such as electronic device 14 or other external equipment.
• Path 12 may be used to couple devices 10 and 14.
• Path 12 may include power lines such as positive power line 16 through which a positive power supply current flows and ground power line 17 through which a ground power supply current flows.
• Path 12 may also include analog and/or digital signals lines (e.g., a pair of data lines, etc.) . When power is being delivered from host 10 to accessory 14, current I that flows through line 16 will be positive.
• Device 10 may have an input-output port with input-output power supply terminals Tl and T2.
• Device 14 may have an input-output port with input-output power supply terminals T3 and T4.
• Terminals Tl and T3 may be positive power supply terminals.
• Terminals T2 and T4 may be ground power supply terminals. When device 10 and device 14 are coupled together, terminal Tl may be
• Terminals Tl and T2 may be associated with contacts in a connector in device 10 (e.g., an input-output connector in an input-output port on device 10) .
• Terminals T3 and T4 may be associated with contacts in a connector in device 14 (e.g., an input- output connector in an input-output port on device 10) .
• Electronic devices such as devices 10 and 14 of FIG. 1 may be cellular telephones, media players, other handheld portable devices, somewhat smaller portable devices such as wrist-watch devices, pendant devices, or other wearable or miniature devices, gaming equipment, tablet computers, notebook computers, desktop computers, televisions, computer monitors, computers integrated into computer displays, embedded equipment such as equipment in an automobile, equipment including speakers and/or a monitor for presenting sound and/or video to a user, or other electronic equipment.
• host computers notebook computers, desktop computers, televisions, computer monitors, computers integrated into computer displays, embedded equipment such as equipment in an automobile, equipment including speakers and/or a monitor for presenting sound and/or video to a user, or other electronic equipment.
• host computers notebook computers
• desktop computers televisions
• computer monitors computers integrated into computer displays
• embedded equipment such as equipment in an automobile
• host such as equipment in an automobile, equipment including speakers and/or a monitor for presenting sound and/
• electronic device 10 may be cellular telephone, media player, or computer and accessory electronic device 14 may be equipment that includes speakers for presenting audio to a user and/or a display for presenting video to a user.
• the audio and/or video content to be displayed may be provided to device 14 from device 10 over a data path associated with path 12.
• Host 10 may include storage and processing circuitry 30 and input-output circuitry 28.
• Electronic device 14 may include storage and processing circuitry 48 and input-output circuitry 50.
• Storage and processing circuitry 30 and 48 may include one or more integrated circuits such as memory circuits, processors, and
• Input-output circuitry 28 and input-output circuitry 50 may include user interface components such as buttons, speakers, microphones, displays, touch sensors, and other devices for gathering input or presenting output to a user.
• Input-output circuitry 28 may also include wired
• Power may be supplied to devices 10 and 14 using alternating current (AC) line power from wall outlets or other sources of AC power (e.g., AC sources 20 and 52) . Power may also be obtained using batteries such as
• Power regulator circuitry 18 and 44 may be used in converting AC power from an AC source or battery power into a regulated source of direct current (DC) power for use by the electrical components of devices 10 and 14 (e.g., a positive voltage on a + terminal and a zero or ground voltage on a - terminal) .
• DC direct current
• circuitry 18 of device 10 may provide a positive power supply voltage to node 38.
• Protection transistor SW (which serves as a protection switch) may normally be on (i.e., the switch formed by the transistor may be closed), so that the voltage on node 38 is conveyed to node 36.
• Positive signal line 16 may connect positive power supply voltage node 36 in device 10 to positive power supply voltage node 54 in device 14.
• Power supply ground line 17 may be used to couple ground 56 in device 14 to ground 58 in device 10.
• transistor SW may be turned off (i.e., switch SW may be opened) as soon as device 10 detects a back-powering condition.
• transistor SW may be turned off to create an open circuit between drain Dl and source SI at values of I below -5 mA or other suitable threshold value (i.e., when the magnitude of current I is above a given threshold and when the polarity of current I is negative) .
• Control circuitry 24 may be used to control the state of transistor SW by applying a control signal such as control voltage Vent to gate Gl of transistor SW via control line 42.
• a control signal such as control voltage Vent
• control circuitry 24 asserts control signal Vent transistor SW may be turned on to allow power to flow from power regulator circuitry 18 to path 12.
• control circuitry 24 deasserts control Vent transistor SW may be turned off to block current flow from device 14 into device 10 and thereby protect device 10 from damage during a back-powering event.
• Control circuitry 24 may use current sensing circuitry such as a current mirror circuit with bias circuitry and current-to-voltage amplifier circuitry
• Circuitry 26 may be coupled to terminal 36 using path 32 and may be coupled to terminal 38 via path 34. Circuitry 26 may be coupled to the gate of transistor SW via path 66. During operation, the components of circuitry 26 may form a current mirror with transistor SW. The current mirror and associated circuitry of circuit 26 may facilitate monitoring of current I .
• device 10 preferably includes a current mirror that is formed using transistor SW and circuitry 26.
• the current mirror circuitry of device 10 and associated current-to-voltage amplifier circuitry may be used to convert sensed a current Isense, which is a small current that is proportional to current I, to a voltage Vsense that is proportional to current I.
• Control circuit 24 may receive signal voltage Vsense from
• circuitry 26 via path 40.
• the magnitude of Vdrop over a range of possible operating currents may be relatively small and may not vary significantly as a function of current I.
• the magnitude of Vsense may be significantly larger (e.g., 10 to 100 times larger, as an example) .
• Voltage Vsense may also change significantly as a function of current I.
• Vsense is larger than Vdrop and, more
• Vsense for a given change in current I (i.e., the slope of line 62) is significantly greater than the change in Vdrop for the same given change in current I (i.e., the slope of line 62)
• the use of Vsense by control circuitry 24 in making decisions regarding the state of transistor SW may improve accuracy .
• FIG. 3 is a circuit diagram showing illustrative components that may be used in implementing circuitry 26 and circuitry 24.
• circuitry 26 may include a transistor such as transistor M2 that is configured to form a current mirror with transistor SW.
• Circuitry 26 may also include bias circuitry and current- to-voltage amplifier circuitry 68.
• Bias and current-to- voltage amplifier circuitry 68 may include transistors such as transistors Ml and M6 that are configured to drive sense current Isense across resistor R to produce voltage Vsense on line 40.
• Transistor SW may have source terminal SI, drain terminal Dl, and gate terminal Gl .
• Transistor M2 may have source terminal S2, drain terminal D2, and gate terminal G2.
• source SI of transistor SW it is desirable for source SI of transistor SW to have the same voltage as source S2 of transistor M2 and for gate Gl of transistor SW to have the same voltage as gate G2 of transistor M2. This may be accomplished by using line 32 to electrically connect source SI and source S2 and by using line 66 to
• Drains Dl and D2 should also be maintained at the same voltage to ensure accurate operation of the current mirror. Drains Dl and D2 of transistors SW and M2 are not shorted together. Nevertheless, the bias
• circuitry of circuitry 68 may be used to match the voltage at node 72 (and therefore drain D2) to the voltage at drain Dl .
• the current mirror formed from transistors SW and M2 may produce a sense current Isense on line 32 that accurately tracks the value of current I on line 14.
• transistors M2 and SW may be configured so that Isense is a small fraction of I (e.g., so that Isense will be equal to 10 ⁇ 6 *I or other suitable fraction of I) .
• the magnitude of the current Isense that is drawn through path 32 is therefore negligible and can be ignored, so that the current (I) passing through line 14 will be substantially equal to the magnitude of the current passing through transistor SW.
• Transistors Ml and M6 may form a common gate amplifier that is used in converting current Isense into a voltage Vsense on line 40.
• transistor M6 is diode connected (i.e., drain D6 and gate G6 are connected by path 76) .
• Current source 78 produces a biasing current Ibias that sets the DC voltage on drain D6 (node 74) .
• Node 74 is one Vgs (i.e., one gate-to-source voltage of transistor M6 at current Ibias) below the voltage at node 38.
• the voltage on node 74 is provided to the gate G of transistor Ml and sets the operating point of transistor Ml.
• the voltage of source terminal S of transistor Ml (i.e., node 72 and drain D2 of transistor M2) roughly tracks the voltage at node 38 (i.e., drain Dl of transistor SW) , because the voltage at node 72 is one Vgs (of Ml) above the voltage of node 74 and because the voltage on node 74 is one Vgs (of M6) below the voltage on node 38.
• the voltage on drain D2 substantially matches the voltage on drain Dl, helping to ensure accurate current mirror operation .
• the current Isense in transistor M2 is proportional to the current of transistor SW because M2 and SW form a current mirror.
• the current Isense flows through sense resistor R and produces voltage drop Vsense on line 40.
• Control circuitry 24 may have a comparator such as comparator 80. Comparator 80 may compare the voltage Vsense on input 82 to a reference voltage Vref on input 84 and may produce a corresponding binary output signal on line 86 that is reflective of whether Vsense is above or below Vref. Using the state of the signal on line 86, control circuitry 24 can assert or deassert control signal Vent on line 42.
• Vref may be set to a value that corresponds to a desired reverse current threshold for path 14.
• Vref may be set to a level corresponding to a -5 mA value for current I. At values of I above -5 mA and below 0, the amount of current flowing into device 10 is minimal, so that device 10 can satisfactorily sink the reverse current I without
• control circuitry 24 can assert the Vent signal on line 42 to ensure that transistor SW is on. With transistor SW on, nodes 38 and 36 will be shorted together and device 10 and device 14 can be operated in a mode in which device 10 powers device 14 over path 12. To help ensure accurate performance, the
• Vref may be calibrated.
• the value of Vref may be set to a value that removes internal offset from the comparator and ensures that the control circuit will be triggered at a desired value of current I (e.g., -5 mA or other suitable level) .
• Control circuitry 24 will respond accordingly by deasserting control signal Vent to turn off transistor SW. With transistor SW turned off, back- powering current flowing from device 14 to device 12 will be blocked, thereby preventing damage to the circuitry of device 10.
• Transistors M2 and SW may have strengths (W/L values) with a ratio (K value) of about 10 ⁇ 2 to 10 ⁇ 4 or other suitable ratio.
• transistor M2 may have a strength of about one thousandth the strength of transistor SW.
• FIG. 4 is an illustrative circuit diagram showing how bias circuitry and current-to- voltage circuitry 68 may form a cascode arrangement.
• bias current Ibias may be mirrored to circuit branches 102 and 104 by transistors M8, M9, and M12 (e.g., transistors M8 and M9 may form a current mirror for circuit branch 102, whereas transistors M8 and M12 may form a current mirror for circuit branch 104) .
• Transistors Mil and M13 may serve as cascode transistors that help to isolate current mirror transistors M9 and M12 from variations associated with differing drain voltages.
• transistor Mil may help match the drain-source voltage of transistor M9 to transistor M8, which tends to isolate the operation of transistor M9 from variations in current Isense (e.g., because the drain-source and gate-source voltages of transistor M9 are matched to the drain-source and gate- source voltages of transistor M8) .
• Transistors M3, M5, M4, and M7 may serve as a cascode arrangement that helps to match the voltage at drain D2 of transistor M2 with the voltage at drain Dl of transistor SW.
• Current Isense that is mirrored from transistor SW by transistor M2 may be provided to transistors Ml and M3.
• Current Isense may be partitioned into currents Is2 and Isl.
• Current Is2 may be determined by the amount of current sourced by current mirror transistor M12 (e.g., current Is2 may be equivalent to Ibias and current II) .
• Current Isl may reflect any remaining current from Isense. For example, for Isense currents that are greater than current Is2 (e.g., greater than Ibias), current Isl may reflect the difference in current between Isense and Is2. As another example, for currents Isense that are greater than current Is2 (e.g., greater than Ibias), current Isl may reflect the difference in current between Isense and Is2. As another example, for currents Isense that are
• FIG. 5 is an illustrative diagram showing how voltage Vsense produced by the circuit of FIG. 4 varies with output current I (e.g., output current provided to an accessory device) .
• Vsense may be zero volts.
• the value of la may reflect the difference between bias currents II and Is2 of circuit branches 102 and 104. For example, if transistors M9 and M12 are matched so that II is equal to Is2, then la may be minimal (e.g., Ia may be a value between -2 mA and 0 mA such as -1.5 mA) .
• Vsense may be zero volts when current Isense is equal to current Is2 and no current passes through resistor R. At device output currents that are greater than Ia voltage Vsense may remain at zero volts.
• Control circuitry 24 may be configured to disable transistor SW in response to determining that voltage Vsense exceeds threshold voltage Vb (e.g., when the magnitude of back-power current exceeds the magnitude of current lb) .
• Threshold voltage Vb may be selected based on the capability of power regulator circuitry 18 to withstand back-power currents with magnitudes up to the magnitude of lb.
• Biasing circuitry 68 of FIG. 4 helps to ensure that the voltage at drain Dl of transistor SW and drain D2 at transistor M2 are matched during back-powering
• current Isense is substantially the same as current IS2 and the cascode mirror structure formed from transistors Ml, M3, M4, M5, M6, M7, Mil, M9, M13, and M12 helps to ensure that the voltage at drain Dl of transistor SW is approximately equal to the voltage at drain D2 of transistor M2.
• biasing circuitry 68 may help to protect against temperature variations.
• FIG. 6 is an illustrative diagram showing how variations in Vsense that are associated with changes in temperature may be mitigated by biasing circuitry 68. As shown in FIG. 6, line 112 may correspond to Vsense
• line 114 may
• lines 112, 114, and 116 may have minimal differences (e.g., Vsense may be insensitive to temperature variations within window 118) .
• threshold current la at which voltage Vsense is produced may be adjusted.
• Threshold current la may be adjusted by adjusting the difference between current II of circuit branch 102 and current Is2 of circuit branch 104.
• the width to length ratio (W/L) of transistor M9 relative to W/L of transistor may be adjusted to control the difference between current II and current Is2.
• W/L of transistor M12 may be increased relative to transistor M9 (e.g., by increasing W of transistor M12 or decreasing W of transistor M9) .
• FIG. 7 is an illustrative diagram showing how threshold current la may be controlled by adjusting the sizing of current mirror transistors M9 and M12.
• line 122 may correspond to threshold current la.
• the threshold current of bias circuitry and current-to-voltage amplifier circuitry 26 may be increased to threshold current la' by decreasing the ratio of W/L between transistors M12 and M9.
• the ratio of W/L of transistor M12 may be
• current Is2 through transistor M12 may be decreased relative to current II through transistor M9, which increases the amount of current provided to sense resistor R for any given output current I (e.g., the sensed voltage of line 126 may be greater than the sensed voltage of line 122 for any given output current I) .
• the threshold current may be decreased to la' ' by increasing the ratio of W/L of M12 to W/L of M9.
• FIG. 8 is an illustrative diagram of control circuitry 24 that may be provided to generate control signal Vent in response to a sensed voltage Vsense
• control circuitry 24 may include comparators 132 and 134 that receive voltage Vsense and compare Vsense to respective reference voltages Vrefl and Vref2.
• Vrefl may be a voltage suitable for detecting large voltages associated with severe back-power conditions (e.g., CI may be
• Vref2 may be a voltage suitable for detecting smaller voltages
• Vrefl may be the voltage sensed by circuitry 26 when Isense is approximately 200mA
• Vref2 may be the voltage sensed by circuitry 26 when Isense is
• Vrefl and Vref2 may be any desired voltages for detecting back-power conditions.
• Detection circuitry 136 may receive signal C2 from comparator 134 and detect when C2 has been
• Detection circuitry 136 may assert detection signal Dl provided to control circuit 138.
• Detection circuitry 136 may be configured with any desired threshold value of time. For example, the threshold value of time may be determined based on the capabilities of regulator circuitry 18 of device 10 to withstand a moderate amount of back-power current from electronic device 14.
• Detection circuitry 136 may include digital and/or analog-based detection circuits.
• detection circuitry 136 may include a clock-based counter that detects how many clock cycles the output of
• comparator 134 has been continuously asserted for.
• detection circuitry 136 may assert
• detection signal Dl in response to determining that the counter has reached a predetermined value (e.g., a counter threshold) .
• a predetermined value e.g., a counter threshold
• FIG. 9 is an illustrative diagram showing the operation of control circuitry 24 during back-powering conditions. As shown in FIG. 9, device output current I may initially oscillate (e.g., power supply path
• inductance associated with paths 16 and 17 may cause ringing when power is supplied by host 10 to accessory
• the initial ringing may have sufficient magnitude to trigger comparator 134 to assert signal C2 during times Tl and T2 (e.g., a corresponding Vsense voltage having a magnitude greater than Vref2 may be produced during times Tl and T2) .
• detection circuitry 136 may
• detection signal Dl may remain deasserted.
• control circuit 138 may disable transistor SW to protect device 10 from the back-powering condition (e.g., by deasserting Vent) .
• FIG. 10 is an illustrative diagram showing the operation of control circuitry 24 during moderate back- powering conditions. As shown in FIG. 10, device output current I may stabilize after initial ringing to a
• negative current of moderate magnitude e.g., the amount of back-power current after initial ringing may be
• detection circuitry 136 may assert detection signal Dl at the end of time period T5 (e.g., because signal C2 has been
• Control circuit 138 may de-assert Vent in response to assertion of signal Dl .
• FIG. 11 is an illustrative diagram showing how control circuitry 24 may be used to control a sink
• Control signal Vs may be determined based on voltage Vsense provided by current-to- voltage amplifier circuitry 26.
• control circuitry 24 may control sink current Is through transistor 202 using control signal Vs to divert back-power current away from power regulator circuitry 18.
• an electronic device configured to provide power to an accessory over a path that includes a power supply line
• the electronic device includes power regulator circuitry that provides a power supply voltage to the power supply line, a first transistor interposed in the power supply line, a second transistor, the first and second transistors form a current mirror that produces a signal indicative of how much current is flowing through the first transistor, and circuitry that provides a control signal to the first transistor to turn the first
• the circuitry includes a control circuit that monitors a sense voltage that is proportional to the signal, a voltage drop across the first transistor changes by a first amount in response to a given change in the current flowing through the first transistor, the sense voltage changes by a second amount in response to the given change in the current flowing through the first transistor, and the second amount is greater than the first amount.
• the circuitry includes a current-to-voltage amplifier that converts the signal into the sense voltage.
• the current-to-voltage amplifier includes a pair of
• transistors coupled to form a common gate amplifier.
• control circuit includes a comparator that receives the sense voltage and a reference voltage.
• the first transistor has a first source, a first drain, and a first gate and the second transistor has a second source, a second drain, and a second gate
• the electronic device further includes a bias circuit that biases the second drain to match a voltage on the first drain.
• the current mirror includes a first line coupling the first source to the second source and includes a second line coupling the first gate to the second gate.
• the circuitry is configured to assert the control signal to turn the first transistor on in response to determining that the current flowing through the first transistor is above a given threshold value and the circuitry is configured to deassert the control signal to turn off the first transistor in response to determining that the current flowing through the second transistor is below the given threshold.
• the given threshold has a negative value
• the control circuitry has a comparator with first and second inputs, and the second input is configured to receive a reference voltage
• the electronic device includes a device selected from the group consisting of a cellular telephone, a tablet
• the electronic device further includes storage and processing circuitry .
• a protection circuit in an electronic device that prevents power delivery to the electronic device from external equipment during a back-powering condition
• the protection circuit includes a first transistor coupled to a power supply input-output terminal, a power supply current flows through the first transistor during at least some operations of the protection circuit, a second transistor that is coupled to the first transistor to form a current mirror, the current mirror produces a sense current that is proportional to the power supply current flowing through the first transistor, and circuitry responsive to the sense current that provides a control signal to turn off the first transistor during the back-powering
• the circuitry includes a current-to-voltage amplifier that converts the sense current to a sense voltage.
• the circuitry includes a control circuit that monitors the sense voltage and provides the control signal based on the sense voltage.
• control circuit includes a comparator having a first input that receives the sense voltage and a second voltage that receives a reference voltage.
• the circuitry includes biasing circuitry that biases a drain voltage in the second transistor to match a drain voltage of the first transistor.
• the biasing circuitry includes a current source.
• an electronic device in accordance with an embodiment, includes a first input-output terminal, a second input-output terminal, a ground power supply line coupled to the second input-output terminal, a positive power supply line coupled to the first input- output terminal, a first transistor coupled to the
• a second transistor that is coupled to the first transistor to form a current mirror, the current mirror produces a sense current proportional to a current flowing through the first transistor and the positive power supply line, and a current-to-voltage amplifier circuit that converts the sense current to a sense voltage.
• the current-to-voltage amplifier includes a resistor through which the sense current flows.
• the electronic device includes a control circuit that receives the sense voltage and produces a corresponding control signal to control the first transistor.
• control circuit includes a comparator having a first input that receives the sense voltage and a second input that receive a reference voltage
• the electronic device further includes a signal line
• the control signal is provided to a gate of the first transistor by the signal line.
• an electronic device in accordance with an embodiment, includes a power supply terminal, power regulator circuitry operable to supply power to external equipment through the power supply terminal, protection circuitry coupled to the power supply terminal, the protection circuitry is configured to detect a back- powering condition in which current is received by the electronic device at the power supply terminal and the protection circuitry is further configured to electrically disconnect the power regulator circuitry from the power supply terminal in response to detecting the back-powering condition .
• an electronic device configured to provide power to an accessory over a path that includes a power supply line
• the electronic device includes power regulator circuitry that provides a power supply voltage to the power supply line, a first transistor interposed in the power supply line, a second transistor, the first and second
• transistors form a current mirror that produces a signal indicative of how much current is flowing through the first transistor
• bias circuitry coupled to the first and second transistors that provides a current bias for the second transistor, the bias circuitry includes an
• additional current mirror formed from at least one cascode transistor; and control circuitry operable to control the first transistor based on the signal produced by the current mirror.
• the bias circuitry includes a first branch and a second branch, a first portion of the current bias for the second
• transistor flows through the first branch and a second portion of the current bias flows through the second branch .
• the first branch includes a resistor and the signal is produced by a voltage drop across the resistor associated with the first portion of the current bias.
• additional current mirror includes a third transistor and a fourth transistor that mirrors the third transistor and wherein the cascode transistor is coupled to the fourth transistor.
• the current mirror includes a first current mirror
• the additional current mirror includes a second current mirror
• the first branch includes a fifth transistor through which the second portion of the current bias flows
• the fifth transistor forms a third current mirror with the third transistor
• the fifth transistor of the third current mirror has a width-to-length ratio that is different from a width-to-length ratio of the fourth transistor of the second current mirror.
• an electronic device in accordance with an embodiment, includes a power supply terminal, power regulator circuitry operable to supply power to external equipment through the power supply terminal, and protection circuitry coupled to the power supply terminal, the protection circuitry is configured to detect a back- powering condition in which current is received by the electronic device at the power supply terminal for a continuous duration exceeding a threshold and the
• protection circuitry is further configured to electrically disconnect the power regulator circuitry from the power supply terminal in response to detecting the back-powering condition.
• the protection circuitry includes a current mirror that produces a signal indicating how much current is received by the electronic device at the power supply terminal, a first comparator that compares the signal to a first reference voltage to produce a first control signal, and a second comparator that compares the signal to a second reference voltage to produce a second control signal, the first reference voltage is greater than the second
• the protection circuitry further includes detection circuitry that receives the second control signal and produces a detection signal that identifies when the second control signal has been continuously asserted for a duration that exceeds the threshold.
• the electronic device includes control circuitry that receives the first control signal and the detection signal, the control circuitry is configured to electrically disconnect the power regulator circuitry from the power supply terminal in response to assertion of the first control signal .
• the detection circuitry is configured to assert the detection signal in response to identifying that the second control signal has been continuously asserted for the duration that exceeds the threshold and the control circuitry is further configured to electrically disconnect the power regulator circuitry from the power supply terminal in response to assertion of the detection signal.

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• Automation & Control Theory (AREA)
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• 2013
  • 2013-06-03 KR KR1020177008619A patent/KR20170038126A/ko not_active Application Discontinuation
  • 2013-06-03 CN CN201710687212.5A patent/CN107390768B/zh active Active
  • 2013-06-03 CN CN201380027991.6A patent/CN104335437B/zh active Active
  • 2013-06-03 KR KR20147033068A patent/KR20150004886A/ko active Application Filing
  • 2013-06-03 WO PCT/US2013/043917 patent/WO2013188155A1/en active Application Filing

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