WO2013186694A3 - System and method for data classification and efficient virtual cache coherence without reverse translation - Google Patents
System and method for data classification and efficient virtual cache coherence without reverse translation Download PDFInfo
- Publication number
- WO2013186694A3 WO2013186694A3 PCT/IB2013/054755 IB2013054755W WO2013186694A3 WO 2013186694 A3 WO2013186694 A3 WO 2013186694A3 IB 2013054755 W IB2013054755 W IB 2013054755W WO 2013186694 A3 WO2013186694 A3 WO 2013186694A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- private
- shared
- data
- cache
- classification
- Prior art date
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
- G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
- G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
An on-chip memory hierarchy organization for a multicore processing system is disclosed. The hierarchy supports virtual- addressed private caches and a physical-addressed shared cache. The hierarchy classifies cache line data as private or shared to support a one-directional request response protocol. The classification can be determined from the generational behavior of a cache line in the private caches. Cache lines having a single generation in a private cache are Private, and cache lines having overlapping generations in two or more private caches are Shared. The Private or Shared classification is performed dynamically at run-time in hardware using a single translation lookaside buffer at the interface between the private and shared caches. The coherence protocol uses the data classification in a dynamic write policy for both shared data race free data and private data, differentiating in when data is put back to the shared cache based on the classification.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201261657929P | 2012-06-11 | 2012-06-11 | |
US61/657,929 | 2012-06-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2013186694A2 WO2013186694A2 (en) | 2013-12-19 |
WO2013186694A3 true WO2013186694A3 (en) | 2014-07-31 |
Family
ID=48985792
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2013/054755 WO2013186694A2 (en) | 2012-06-11 | 2013-06-10 | System and method for data classification and efficient virtual cache coherence without reverse translation |
Country Status (1)
Country | Link |
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WO (1) | WO2013186694A2 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9223717B2 (en) * | 2012-10-08 | 2015-12-29 | Wisconsin Alumni Research Foundation | Computer cache system providing multi-line invalidation messages |
US9330433B2 (en) | 2014-06-30 | 2016-05-03 | Intel Corporation | Data distribution fabric in scalable GPUs |
US10127153B1 (en) | 2015-09-28 | 2018-11-13 | Apple Inc. | Cache dependency handling |
US10482016B2 (en) | 2017-08-23 | 2019-11-19 | Qualcomm Incorporated | Providing private cache allocation for power-collapsed processor cores in processor-based systems |
US10769076B2 (en) | 2018-11-21 | 2020-09-08 | Nvidia Corporation | Distributed address translation in a multi-node interconnect fabric |
US11567791B2 (en) * | 2020-06-26 | 2023-01-31 | Intel Corporation | Technology for moving data between virtual machines without copies |
CN115114192B (en) * | 2021-03-23 | 2024-06-14 | 北京灵汐科技有限公司 | Memory interface, functional core, many-core system and memory data access method |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050102473A1 (en) * | 2002-11-21 | 2005-05-12 | Fujitsu Limited | Cache control method and processor system |
US20110231612A1 (en) * | 2010-03-16 | 2011-09-22 | Oracle International Corporation | Pre-fetching for a sibling cache |
-
2013
- 2013-06-10 WO PCT/IB2013/054755 patent/WO2013186694A2/en active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050102473A1 (en) * | 2002-11-21 | 2005-05-12 | Fujitsu Limited | Cache control method and processor system |
US20110231612A1 (en) * | 2010-03-16 | 2011-09-22 | Oracle International Corporation | Pre-fetching for a sibling cache |
Also Published As
Publication number | Publication date |
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WO2013186694A2 (en) | 2013-12-19 |
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