IN2015DN02742A - - Google Patents

Info

Publication number
IN2015DN02742A
IN2015DN02742A IN2742DEN2015A IN2015DN02742A IN 2015DN02742 A IN2015DN02742 A IN 2015DN02742A IN 2742DEN2015 A IN2742DEN2015 A IN 2742DEN2015A IN 2015DN02742 A IN2015DN02742 A IN 2015DN02742A
Authority
IN
India
Prior art keywords
tlb
gpu
gpus
cpu
task
Prior art date
Application number
Inventor
Misel-Myrto; Papadopoulou
Lisa R ; Hsu
Andrew G ; Kegel
Jayasena S ; Nuwan
Bradford M ; Beckmann
Steven K ; Reinhardt
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of IN2015DN02742A publication Critical patent/IN2015DN02742A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
    • G06F9/4856—Task life-cycle, e.g. stopping, restarting, resuming execution resumption being on a different machine, e.g. task migration, virtual machine migration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/654—Look-ahead translation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatuses are provided for avoiding cold translation lookaside buffer (TLB) misses in a computer system. A typical system is configured as a heterogeneous computing system having at least one central processing unit (CPU) and one or more graphic processing units (GPUs) that share a common memory address space. Each processing unit (CPU and GPU) has an independent TLB. When offloading a task from a particular CPU to a particular GPU, translation information is sent along with the task assignment. The translation information allows the GPU to load the address translation data into the TLB associated with the one or more GPUs prior to executing the task. Preloading the TLB of the GPUs reduces or avoids cold TLB misses that could otherwise occur without the benefits offered by the present disclosure.
IN2742DEN2015 2012-10-05 2013-09-20 IN2015DN02742A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/645,685 US20140101405A1 (en) 2012-10-05 2012-10-05 Reducing cold tlb misses in a heterogeneous computing system
PCT/US2013/060826 WO2014055264A1 (en) 2012-10-05 2013-09-20 Reducing cold tlb misses in a heterogeneous computing system

Publications (1)

Publication Number Publication Date
IN2015DN02742A true IN2015DN02742A (en) 2015-09-04

Family

ID=49305166

Family Applications (1)

Application Number Title Priority Date Filing Date
IN2742DEN2015 IN2015DN02742A (en) 2012-10-05 2013-09-20

Country Status (7)

Country Link
US (1) US20140101405A1 (en)
EP (1) EP2904498A1 (en)
JP (1) JP2015530683A (en)
KR (1) KR20150066526A (en)
CN (1) CN104704476A (en)
IN (1) IN2015DN02742A (en)
WO (1) WO2014055264A1 (en)

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Also Published As

Publication number Publication date
US20140101405A1 (en) 2014-04-10
CN104704476A (en) 2015-06-10
EP2904498A1 (en) 2015-08-12
KR20150066526A (en) 2015-06-16
WO2014055264A1 (en) 2014-04-10
JP2015530683A (en) 2015-10-15

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