WO2013186537A1

WO2013186537A1 - Threshold voltage programming of an ion sensitive field effect transistor

Info

Publication number: WO2013186537A1
Application number: PCT/GB2013/051499
Authority: WO
Inventors: Christofer Toumazou; AbdulRahman ALAHDAL
Original assignee: Dna Electronics Ltd
Priority date: 2012-06-12
Filing date: 2013-06-07
Publication date: 2013-12-19
Also published as: GB201210375D0; GB2502991A; GB2502991B

Abstract

A device and method for threshold voltage programming of an Ion Sensitive Field Effect Transistor (ISFET). This is of particular use in matching ISFETs in an array, which may be used in biological reaction monitoring. A circuit comprises an Ion Sensitive Field Effect Transistor (ISFET) having a floating gate (111) and two tunnelling inputs (Vt-, 148,149; Vt+, 145, 146) coupled by capacitors (Ct-, Ct+) to the floating gate for bidirectional electron tunnelling to program a charge on the floating gate.

Description

Threshold Voltage Programming of an Ion Sensitive Field Effect Transistor

FIELD OF THE INVENTION

The present invention relates to a device and method for threshold voltage programming of an Ion Sensitive Field Effect Transistor (ISFET). This is of particular use in matching ISFETs in an array, which may be used in biological reaction monitoring.

BACKGROUND

An Ion Sensitive Field Effect Transistor (ISFET) is a Metal Oxide Semiconductor (MOS) transistor variant where the gate is directly or indirectly exposed to an electrolyte having an ion concentration that affects the conductance of the channel in the transistor. In early ISFETs, the electrolyte had direct contact to the gate oxide or its replacement dielectric. Later, unmodified CMOS processes were used to mass produce cheaper devices and arrays. Building an array of ISFETs facilitates spatio- temporal detection of ionic concentration profile. This has diverse biomedical applications, such as DNA sequencing and protein identification.

ISFETs built in standard CMOS technology are typically floating gate devices, having a poly silicon floating gate that is connected to a metal stack all the way to the topmost metal layer. Oxi-nitride passivation, which normally acts as a protective cover layer for the whole die, becomes the ion sensing membrane that is exposed to electrolyte. They thus suffer from initial threshold voltage (Vt) variations. This is a problem since it is difficult to design circuits without knowing the electrical characteristics of each transistor. It is even more serious a problem for an array having a common reference. It is important to match threshold voltages/trans- conductances of all devices in order to have comparable responses for similar chemical stimuli.

Figure 1 shows the model of an ISFET built in a CMOS process. It is a floating gate transistor with one input: the super position of its reference voltage (Vref) and chemical voltage (Vchem) coupled through the passivation capacitance (Cpass). Vref is externally supplied via a reference electrode while Vchem models the device's dependence on electrolyte concentration by equation 1 . Cgouy, and Chelm are the Gouy/Chapman and Helmholts capacitances originating in the site binding theory and relating to the liquid/solid interface [1 ]. Vtc models the system's trapped charges referred to the floating gate. It can have a positive or negative value that corresponds to floating gate voltage ranging between a few milli-volts to a few volts [2, 4].

I II

Y is a grouping of all pH independent constants. U_T is the thermal voltage, and a is a sensitivity parameter ranging between 0 and 1 . It accounts for the fact that ISFETs in CMOS generally have lower sensitivities than the Nerstian value of 59.2 mV/pH at 25 °C, for which a=1 .

Initially the threshold voltage (Vt) variations of ISFETs in CMOS are attributed to trapped charges in the system composed of passivation layer 103, a metal stack (104, 147) inter-metal insulation layers 120, poly-silicon gate 1 1 1 , gate oxide 122, and their interfaces. Figure 2 shows a cross-section of an ISFET in CMOS with trapped charges (plus and minus symbols).

Trapped charges introduce polarisation to the ISFET's FG-MOS system which has to maintain charge neutrality. The trapped charges within the system are opposed by an equal but opposite bound charges in either metal or semiconductor surfaces or both. Therefore, the net effect can be seen as an initial Vfg variation.

UV light is known to excite trapped charges into the conduction band. It is traditionally used to erase non-volatile memories. Milgrew [2] used UV to remove trapped charges with the aim of matching transconductance of ISFETs after 10 hours of UV light exposure. Apart from being a post-processing step, drawbacks of this method include long exposure to external UV light source while biasing the circuit in a special way. Moreover, care must be taken during layout phase to allow UV light passage to areas where it is needed.

Floating Gate-MOS (FG-MOS) devices can have a number of capacitively coupled inputs where Vfg is determined by their weighted sum. This idea was first exploited for an ISFET by Georgiou [6], where a second electrical input was capacitively coupled to its floating gate. It was used as a control gate to program Vt. However, the coupling capacitance of this control gate was large in order to increase its effective weight for a voltage range that was within rails. This was at the cost of reducing the coupling weight of the chemical signal and hence reducing that ISFET's sensitivity.

A similar idea was used in reference [7] and reference [8] to build an auto-zeroing amplifier with a feedback loop incorporating two capacitively coupled nodes to the ISFET's floating gate, namely evaluation and sense nodes. The evaluation node was used to read and store a reference level. The sensing node was used for reading the signal change after the chemical stimuli. A comparator amplified the difference between the two levels in order to compensate for trapped charges and drift. This method is similar to correlated double sampling. However it requires a large storage capacitor, an amplifier, a number of switches, and their control circuit to run the system.

The use of a switch to set V_fg was reported in reference [14]. This process is simple and CMOS compatible. However, the switch's leakage current is problematic for the already weak chemical signal. Moreover, it needs large storage capacitance, and fast switching, which is not compatible with slow chemical signals like those seen in DNA hybridization [15].

SUMMARY OF THE INVENTION

According to a first aspect of the invention there is provided a method of programming a charge on a floating gate of an Ion Sensitive Field Effect Transistor. The method comprises applying a positive tunnelling voltage to a first tunnelling input capacitively coupled to the floating gate and a negative tunnelling voltage to a second tunnelling input capacitively coupled to the floating gate.

According to a second aspect of the invention there is provided a method of operating an apparatus comprising an Ion Sensitive Field Effect Transistor having a floating gate. The method, in response to a user input, comprises programming a charge on the floating gate according to any preceding claim and measuring an ion concentration of an electrolyte exposed to the Ion Sensitive Field Effect Transistor. According to a third aspect of the invention there is provided a device comprising an Ion Sensitive Field Effect Transistor having a floating gate; two tunnelling inputs coupled by capacitors to the floating gate; and a programming control circuit connected to the tunnelling inputs and arranged to provide a negative voltage and a positive voltage for bidirectional electron tunnelling to program a charge on the floating gate.

Further preferred features are set out in the appended dependent claims.

Brief Description Of The Drawings

Specific embodiments of the invention will now be described by way of example only with reference to the accompanying figures, in which:

Figure 1 is a model of a traditional ISFET manufactured in a CMOS process;

Figure 2 is a cross-sectional representation of a traditional ISFET manufactured in a CMOS process showing trapped charges;

Figure 3 is a model of an ISFET having an indirect electron tunnelling structures;

Figure 4 is a cross-sectional representation of an ISFET with an indirect tunnelling structures using a standard single well CMOS process;

Figure 5 is a cross-sectional representation of an ISFET with an indirect tunnelling structure featuring a standard double well CMOS process;

Figure 6 is a graph of exemplary tunnelling voltages;

Figure 7 is a graph of floating gate voltage change due to bidirectional tunnelling starting from different initial values;

Figure 8 is a graph of tunnelling current change due to bidirectional tunnelling starting from different initial values;

Figure 9 shows l_d-V_ref curves of a pMOS ISFET at three states: initial state, after tunnelling at (+7.6,-7.6)V, and after tunnelling at (+8.7, -6.5)V;

Figure 10 shows l_d-V_ref curves of a nMOS ISFET at three states: initial state, after tunnelling at (+7.6,-7.6)V, and after tunnelling at (+8.7, -6.5)V;

Figure 1 1 is a model of an ISFET inverter arrangement; with indirect bidirectional tunnelling structures; and

Figure 12 is a block diagram of the device with battery supplied positive and negative power supplies for hand held matching and operation. DETAILED DESCRIPTION

An overall system may comprise an array of ISFETs manufactured in a standard CMOS process. The array may be used in a biological reaction device whereby each ISFET is exposed to a microfluidic volume containing a biological sample to be detected or identified. The sample may contain a protein or nucleic acid which is mixed with reagents to create a reaction that absorbs or releases ions. The sample is mixed with an analyte specific reagent to cause a reaction which produces ions detectable by the ISFET exposed to it. The ions detected by the one or more ISFETs changes an electrical output signal which is monitored by a circuit. The array may be used in sequencing a nucleic acid, wherein the reactions are incorporations of known nucleotides into a growing nucleic acid.

Further details of such a system are described in patents applications WO03/073088, US-2010-0255595, WO2008/107014, GB2485068, and GB1205497.9 incorporated herein by reference.

Due to trapped charges in the floating gate of the ISFETs, which would otherwise produce problems with the electrical outputs as described above, it is desirable to remove these charges or set them to a predetermined level. Of particular advantage, this enables signals of different ISFETs in the array to be directly compared to determine a difference in the corresponding reactions. An array of ISFETs with equal electrical properties is advantageous in monitoring and comparing a plurality of reactions.

Embodiments of the invention provide a device and method to program an ISFET's floating gate charge in order to bring the electrical parameters to a desirable point. This can be accomplished using circuit techniques alone, without post-CMOS processing steps.

Electron tunnelling refers to the phenomena whereby electrons may pass a potential barrier which they would not otherwise be able to according to classical mechanics. In semiconductors, this may refer to electrons crossing an oxide layer by the application of a sufficiently high electrical field across the oxide. In Figure 4, a negative voltage applied to inputs (148) and (149) provides electrons to substrate doping regions (132) and (133) to pass the oxide barrier (123) to enter the floating gate via polysilicon (1 10). Similarly, a positive voltage applied to inputs (145) and (146) enables electrons from the poly silicon gate (1 12) to pass the oxide barrier (121 ) to enter substrate doping regions (137) and (138). The oxide barrier is an insulator and does not easily permit the passage of electrons. Ct+ is thus constructed by conductive poly (1 12), insulting oxide (121 ), and conductive regions (137, 138).

Tunnelling is normally avoided in CMOS devices because electrons may get trapped within a silicon oxide insulator which causes degradation. However, this problem decreases with reduced trapping sites and reduced tunnelling current. Thus, it is advantageous to use the high quality thermal gate oxide regions (121 ) and (123), which have far less trapping sites than the inter-poly or inter-metal oxide insulator. Charges trapped in such sites may cause mismatch when released in the stress induced leakage current phenomena, whereby electrons trapped in such oxide cites are slowly released. For these reasons, preferred embodiments do not use poly- poly capacitors or metal-metal capacitors. Instead the tunnelling is across the structures comprised of the poly-silicon gate, gate oxide, and substrate.

The application of an electric field across the insulating gate oxide bends energy levels of the system. If a high enough electric field is applied, the probability of electrons tunnelling through the insulating oxide increases. The relationship between electric field and electron tunnelling is exponential and so low electric fields provide little appreciable tunnelling effect, whilst high electric fields can cause breakdown of the oxide. In preferred embodiments, the electric field is more than 0.6V/nm, more preferably more than 0.75V/nm. The electric field is preferably below 1 .25V/nm, more preferably below 1 V/nm (the distance in nanometers is the thickness of oxide to be crossed, which is typically 4-8nm, depending on the fabrication process).

The tunnelling voltages applied to the tunnelling inputs thus depends on the fabrication process which determines the oxide thickness. These voltages will thus need to be sufficient to enable (significant numbers of) electrons to tunnel across the oxide barrier to program a charge on the floating gate in a short time. For hand-held devices, the time to complete the tunnelling should be minimised, preferably less than 10 minutes, more preferably less than 5 minutes, or less than 2 minutes. The magnitudes of the tunnelling voltages is typically greater than the operating voltage (typically 2-5V) of the device. Tunnelling voltages should be set to enable an electron to surmount the silicon/silicon-dioxide 3.1 eV energy barrier. For metal-insulator-semiconductor (MIS) devices with silicon oxide thickness's greater than 5 nm, Fowler-Nordheim tunnelling dominates other tunnelling mechanisms [22]. It is modelled by equation 2.

Where J_tun is the tunnelling current density, Ao is a pre-exponential constant approximated by 9.63x 1 0^"7 A/V², and E₀ is a constant representing the starting point of analysis, nearly equals to 2.77 x 1 0⁸ V/cm. E_ox is the electric field across the oxide insulator given by the difference between tunnelling voltage V_tun and floating gate voltage V_fg divided by oxide thickness t_ox. Thus tunnelling depends only on E_ox = (V_tun - V_fg)/ t_ox and current flows in the direction to reduce it. Electrons may move in both directions to/from the floating gate depending on the polarity of applied tunnelling voltage.

Figure 3 shows an ISFET of a device according to a preferred embodiment with two inputs coupled to its floating gate: a positive tunnelling voltage (Vt+), coupled via Ct+; and a negative tunnelling voltage (Vt-) coupled through Ct- . They are used to provide bidirectional indirect tunnelling across their oxide isolation to/from the floating gate in a controlled way. The floating gate charge is thus programmed by the voltage applied to the inputs to achieve a desirable Vfg using a balanced combination of these two tunnelling voltages. Floating gate charges can be programmed to be zero or a non-zero value, as needed.

Because, tunnelling is carried out between a substrate diffusion area and a poly- silicon gate that is shorted to the ISFET's floating gate, current must be prevented from flowing to other substrate areas. Diode isolation is used to make sure this diffusion area always has a reverse biased junction with the surroundings. Therefore, the two tunnelling inputs are connected to regions doped and arranged in the substrate such that there is a reverse biased junction (diode junction) between the tunnelling voltage and ground. Because thin gate oxide is used in modern processes, the tunnelling voltage needed to invoke tunnelling is less than the isolation diode breakdown voltage. For example, in the AMS 0.35 μηι process, 6.5 to 8.5 volts are enough to tunnel electrons across the 7.6 nm gate oxide, while less than the isolation diode break down voltage of 9 V. Figure 4 is a cross-section representation for an n-ISFET and Figure 5 is for the p-ISFET, showing how the diode junction is provided by the n-well and source and drain doping depending on the polarity of the tunnelling voltage.

Figure 4 depicts a cross-section of an integrated circuit having n-ISFET (100) and the indirect tunnelling structures connected to Vt+ and Vt-. This figure shows a standard single well CMOS process. However, the embodiments for other CMOS processes, like the double well process, are viable too.

Figure 5 shows a cross-section of an integrated circuit having an ISFET (100). The ISFET may be a p-ISFET in a standard single or double well CMOS process, or an n-ISFET in a double well process. The topmost metal layer (104) is the chemical gate of the ISFET. It is covered by the passivation layer (103), which acts as the ion sensitive membrane that comes into contact with the fluid under test (101 ). Immersed in this fluid is a reference electrode (102) which is externally supplied by reference voltage Vref. The ISFET's source (135) and drain (136) are doped according to the type of device. For n-ISFET, they are n-doped regions within a p- well (151 ) in a double well process or within the substrate in a single well process. In both cases, this is the standard MOS configuration. For a p-ISFET, the source and drain regions are p-doped in an n-well (151 ). The ISFET's intrinsic gate (1 1 1 ) is connected via the metal stack (147) to the chemical gate of topmost metal layer (104). The substrate (160) is p-doped and its contacts (130), and (139) are also p- doped with a higher concentration. These contacts set the substrate ground voltage. The n-doped N-Well (150) contains the p-MOS drain (132) and source (133). Its floating gate (1 10) is shorted to the ISFET's floating gate (1 1 1 ) via the metal connection (147). The n-doped regions (137) and (138) form the source and drain of an nMOS transistor. Its floating gate (1 12) is shorted to the ISFET's floating gate (1 1 1 ). The three floating gates are connected through a low resistive means which may be metal or poly-silicon. The thin gate oxide regions (121 ), (122), and (123) isolate the floating gates from the substrate underneath them, wherein (121 ) and (123) are used to tunnel electrons from/to the floating gate in a controlled and balanced way in order to set its trapped charge to a desired level.

By charge conservation, Vfg is given by: C ,_W . ... .. . _{T V} , . ½ ^. . .. VMOS^MO-S

Here, C_tot is the total capacitance seen by the floating gate and (V_mosC_mos=V_dC_gd +V_sC_gs + V_bC_gb) is the MOS transistor contribution to V_fg given by its drain, source and body voltages multiplied by their respective gate capacitances. V_tc represents the instantaneous trapped charges.

For normal ISFET sensing operation, all voltages are used as normal apart from Vt+ and Vt- which are rounded. Therefore, equation 3 may be rewritten as:

This is the same as the case for a single ISFET without tunnelling structures. During floating gate tunnel programming, only Vt+ and Vt- are non-zero while all other voltages are set to ground, including Vdd. Thus, equation 3 becomes:

(5)

Therefore, during tunnelling, Vfg is dictated by the tunnelling voltages and present floating gate trapped charges, which changes in time. From equation 2, after the onset of tunnelling, Jtun depends only on Eox which, in turn, is a function of the voltage difference between the instantaneous Vfg and Vt+ or Vt-. Their coupling weight depends on their coupling capacitances. Tunnelling current depends on the actual area exhibiting tunnelling, assumed to be the full area of the capacitor, and current densities, wherein the magnitudes are given by:

, where Li,_{; Y}.+ —

The positive tunnelling voltage Vt+ is used to remove electrons from the floating gate, whereas, the negative voltage Vt- is used to add electrons. In some embodiments these are of equal magnitude (i.e. Vt+ = -Vt-), and the coupling capacitances are equal. This has two advantages. Firstly, equal current magnitudes will result from equal difference from Vfg. This makes the equilibrium point at Vfg = OV per equation 4. Secondly, after Vfg is brought to zero, they will have equal and opposite coupling weights. Therefore, their contributions towards Vfg cancel each other out per equation 3. Therefore, this method can be used even during normal ISFET's operation simply because the net coupling weight of the tunnelling voltages is zero and they are applied in an indirect way.

Vt+ and Vt- are chosen in such a way as to result in the flow of tiny and opposite currents from/to the ISFET's floating gate. These currents will be constant and equal at the desired point of operation. Any deviation from this causes imbalance that will bring Vfg back to its equilibrium operating point within a limited time frame. Thus, one way to bring Vfg to zero regardless of its initial charge is by choosing Vt+ = - Vt-. Though this arrangement is advantageous, different magnitudes may have other advantages. For example, according to equations 4, it is possible to select tunnelling voltages in order to choose an appropriate equilibrium value of Vfg that is non-zero. Vfg reaches steady state when both tunnelling currents are equal and in opposite directions.

The time needed to match an ISFET array is collectively determined by the amount of trapped charges, (manifested by Vfg variations); the magnitudes of tunnelling currents, and each floating node total capacitance (Ctot). Higher tunnelling currents provide faster programming but need higher voltages. In a preferred method, both tunnelling voltages (Vt+) and (Vt-) are ramped together in opposite directions to values that are suitable for the manufacturing process. These voltages are preferably maintained for one minute or longer. Then the tunnelling voltages are disconnected or ramped down to zero volts. For the AMS 0.35μηι process it is preferable to set Vt+ to |Vt-|+2 V to produce threshold voltages comparable to intrinsic transistors. Preferably the ramping rates for Vt- and Vt+ are of substantially equal magnitudes and the starting time is the same. Ramping down the voltages insures that Eox does not reach undesirable values that can cause oxide breakdown. Moreover, this results in nearly zero net coupling weight on Vfg throughout the matching process. This insures there is no effect on mobile ionic charges that may cause drift.

The bidirectional tunnelling preferably takes place simultaneously whereby the two tunnelling voltages are ramped up together from zero volts to a maximum level, maintained at a maximum, then ramped down to zero volts. The maximum level will be a positive voltage at one tunnelling input and negative at the other. The ramping rates and/or ramping period need not be the same. Ramping of the applied tunnelling voltage may be accomplished by charging a capacitor in a similar way to saw tooth signal generating circuits. This is enough to generate a small ramping signal that is amplified later on. Simple inverting and non-inverting amplifiers may be used to generate the desired signals from a charging capacitor.

In a preferred embodiment the total tunnelling time for the first calibration session is more than 20 seconds, more preferably more than 2 minutes, and successive tunnelling sessions (if needed) are preferably less than 1 minute, less than 30 seconds or less than 10 seconds. The total tunnelling time is the period measured from the onset of non-zero voltages Vt+/Vt- until they return to zero. Preferably the tunnelling voltages are ramped (from 0V to a maximum value or vice versa) over a period of more than 1 ms, more preferably more than 10ms.

The magnitude of the tunnelling voltages may be less than 10V, preferably less than 9V, more preferably less than 8V. To ensure tunnelling is effective in a reasonable time, the tunnelling voltage is preferably more than 4V, more than 5V or more than 6V. In some embodiments, the tunnelling voltages are in the range ±6.5V to ±8.5V. This is achievable with two 9V batteries where ground is their middle point as shown in Figure 12. The tunnelling voltages may be either generated within the Integrated Circuit (IC) using charge pumps or generated within the system (outside the IC) and externally applied to it by a battery. The circuit need only provide low power as the tunnelling currents are in the range of few nano amperes (10^"9A). Sensing circuits measure the tunnelling currents and may operate transistors in the weak inversion mode.

This method can be applied without feedback as it relies on homing Vfg to a value dictated by both Vt+ and Vt-. Though a grounded electrolyte provides a reference level, dry ISFETs may be used as these trapped charges are inherent in the devices before they come into contact with an electrolyte.

Whilst known methods for programming a charge are typically used in the factory as part of a post-processing step, embodiments may be field programmable. Thus the floating gate charge may be set by the user (as opposed to a manufacturing technician) immediately prior to using the ISFET device for measurement. Programming can be repeated as many times as needed. The method may thus be considered as part of a calibration step in a measurement process. The method may be automated such that upon initiation by a user input, the device connects the tunnelling inputs to a programming control circuit providing tunnelling voltages, derived from a portable power supply. After a suitable period, the tunnelling voltages are brought to zero or disconnected and the device enters a measurement mode to measure an ion concentration of an electrolyte exposed to the ISFET.

The electrical parameters of the ISFET (such as threshold voltage, leakage current, and net floating gate charge) may be measured by a circuit to determine the state of the ISFET after programming. These measurements may be compared to predetermined values stored in a memory element to determine whether a repeat tunnelling step is required (for example, if they are outside of a range of those values). Alternatively or additionally the electrical parameter measurements may be stored in a memory element and used to modify the ion concentration measurements. The electrical model of an ISFET can be used with knowledge of the floating gate charge to correct the output signal to provide the contribution due to the ion concentration alone. The electrical parameters may be measured by exposing the ISFET's sensing surface 103 to an electrolyte 101 of known ion concentration (Vchem) and monitoring the drain current (Id) whilst varying the reference voltage (Vref) of the electrode 102 in the electrolyte. This is demonstrated below in the Simulation Results section.

The Integrated Circuit may comprise a plurality of ISFETs arranged in an array, each ISFET coupled to tunnelling inputs. All of the positive tunnelling inputs may be connected together, as the tunnelling voltages required depend on the manufacturing process which will be common to all ISFETs and so the final floating gate voltages will be equal, regardless of the initial trapped charge on each floating gate. Similarly, all of the negative tunnelling inputs may be connected together. Although theoretical tunnelling mechanism have been provided by the equations provided herein, the results and mechanism may differ in some aspects. A difference may result from different tunnelling mechanisms between the two structures. For the n-diffusion case, tunnelling may be dominated by electrons from the conduction band while hole tunnelling from the valence band dominate the current mechanism for the p-diffusion case.

Poly-silicon gate depletion, as the tunnelling voltage is supplied via the substrate, may also affect the results. For equal magnitudes of tunnelling voltages, poly-1 gate depletion may result in a negative floating gate charge. For n-doped poly-1 gate, Vt- will attract holes and repel electrons. This may cause inversion in the gate across Ct- with a depletion capacitance in series with it. The result may be reduced net coupling capacitance for Vt-. Equation 5 would explain excess negative charge bound to Ct+ and the positive charge bound to Ct- during tunnelling. These charges may be freed when the tunnelling voltages are removed and a net negatively charged floating gate may result. In order to compensate for this, in preferred embodiment Vfg is positively charged during the tunnelling session in such a way to achieve the desired Vtc.

The results of employing methods and devices according to the invention will vary according to the manufacturing process used because each process has its own doping profiles and concentrations which are generally classified. No feedback loop is needed, which simplifies the design. Through knowledge of or experiments with the manufacturing process used, the skilled person will be able to tune the tunnelling voltages required to obtain a desired result. The desired result may be a near zero floating gate voltage or providing electrical characteristics of the ISFET comparable to an equivalent FET.

To aid the skilled person in the understanding of the theoretical mechanisms of tunnelling and provide an exemplary embodiment, simulations and experiments were carried out. The results are provided below. SIMULATION RESULTS

The AMS 0.35um CMOS process that was used in simulations was used to fabricate two ISFFETs in the same die: an nMOS and a pMOS. Both had an aspect ratio (W/L) of 3.0um /0.35um. All tunnelling capacitors were matched to about 0.98fF. Both ISFETs had equal chemical sensitive areas of 200um2 corresponding to about 44±6fF. The reference voltage was applied via a standard Ag/AgCI reference electrode that was immersed in a pH 7 buffer solution.

The passivation capacitance was Cpass=45fF. The circuit of Figure 3 was simulated in Cadence using BSIM3V3.2 MOS model and a verilog-A ISFET model based on equation 1 and a verilog-A tunnelling model according to equations 6.

The nominal gate oxide thickness in this process is 7.6 nm and the minimum diode break down voltage is 9.0 V. Therefore, there is a small range where electron tunnelling can take place before the reverse biased isolation diode breaks down, which is between 6.0V - 9.0V. This is within the supply range of batteries for hand held devices.

Tunnelling voltages of Vt+= -Vt- =7.6V were chosen as seen in the wave form of Figure 6. They were first swept from 0 V to 7.6V in 10 ms in order to avoid breaking down the gate oxide since initial Vfg is not known. Then, they were kept at ±7.6V for a time that is more than enough to bring Vfg to zero (in this case about 1 second). Finally, they were swept back to 0.0 V.

Figure 7 shows the change of Vfg in response to these applied tunnelling voltages. A number of parametric sweeps were done where the initial Vfg was changed amongst values -0.4, -0.2, 0.0, 0.2, and 0.4V. Each time, Vfg was brought to its steady state value of 0V within about 100 ms. Figure 8 depicts both tunnelling currents during this process. The currents drop very fast with the change of Vfg and reach a steady state value of about ±0.1 pA.

For the ISFETs' characterization, as Vfg cannot be directly access, Vref was used in its place keeping in mind the scaling factor of equation 4. Ids- Vref curves of the two ISFETs were measured by sweeping Vref in pH 7 while grounding the tunnelling nodes, to nullify their contribution, as per equation 5. Both devices were biased with Vdsn= Vsdp =0.5V , where the suffix n stands for the n-type device and p for p-type device. The reference Voltages Vref that resulted in 2uA drain current were reported for each case.

During the application of potentials Vt+ and Vt- in tunnelling sessions, all other nodes were grounded. The n-Well, that housed the p-diffusion used for Vt-, was also grounded. This prevented it from playing the base role of the lateral pnp BJT between grounded substrate and tunnelling diffusion. The CMOS process was a single well. Thus, the n-diffusion that was used for Vt+ was surrounded by ground in the p-type substrate (see Figures 4 and 5).

Table 1 lists the simulated Vref for drain currents of 2uA for both devices under different initial floating gate charges. It is used as a reference to indicate the polarity of floating gate charges that resulted from tunnelling experiments. It also gives an idea of how close the charges are from the targeted results.

Table 1 : Simulated Vref required to achieve ld=2uA, for the circuit of Figure 3 for both ISFETs, under different initial Vfg (VfgO) voltages. All values are in Volts.

The curves labelled "initial" in Figures 10 and 9 show the initial Id- Vref traces measured for both ISFETs before any tunnelling experiments. At Idn =2uA the Vref was -1 .62V. Comparing this with table 1 , this indicates that the initial floating gate charge in the nISFET was positive. At ldp= 2uA resulted when Vref =2.38V, which indicated negative initial floating gate charge; as table 1 reveals. This is an indication of how much variation is possible in an ISFET's Vt .

Afterwards, both ISFETs were subjected to a tunnelling session where Vt+ and Vt- were swept from OV to ±7.6V, kept constant for about five minutes, and then swept back to zero volts. The results were the curves labelled accordingly. Here, for ld=2uA Vref was 1 .894 V for the nISFET and 1 .45 V for the pISFET. Thus by comparing these values with Table 1 , it is evident that the ISFETs floating gates are negatively charged. In order to bring the ISFETs' Vt closer to the intrinsic devices' threshold voltages (i.e. the Vt of an equivalent FET), they were subjected to a number of tunnelling sessions with different Vt+ and Vt- combinations. The combination Vt+ = +8.7V and Vt- = - 6.5V resulted in the curves labelled accordingly of Figures 9 and 10 . The Vref that produced ld=2uA for the n-ISFET and p-ISFET were 0.603 V and -0.362 V respectively. These are close the to the intrinsic MOS Vt and their difference is 0.965V which is nearly equal to the intrinsic devices threshold voltages difference. The above measurements for both ISFETs are listed in table 2.

Table 2: Measured Vref for ld=2uA, initially and after two tunnelling sessions with tunnelling voltages (Vt+,Vt-)

The invention may be further understood by reference to the following documents:

[1 ] Bergveld P, ^"Thirty years of ISFETOLOGY: What happened in the past 30 years and what may happen in the next 30 years^", Sensors and Actuators B: Chemical, Volume 88, Issue 1 , 1 January 2003, Pages 1 -20

[2] Milgrew, M.J.; Cumming, D.R.S.; ^"Matching the Transconductance Characteristics of CMOS ISFET Arrays by Removing Trapped Charge^" , IEEE Transactions on Electron Devices, Volume: 55, No. 4, pp. 1074 - 1079, 2008.

[3] Georgiou P, Toumazou C, ^" ISFET characteristics in CMOS and their application to weak inversion operation^", Sensors and Actuators B-CHEM, 2009, Vol:143, Pages:21 1 -217, ISSN:0925-4005

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Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein. The various voltages and periods provided herein may be selected by the skilled person to design embodiments falling within the scope of the invention.

Claims

CLAIMS:

1 . A method of programming a charge on a floating gate of an Ion Sensitive Field Effect Transistor, the method comprising applying a positive tunnelling voltage to a first tunnelling input capacitively coupled to the floating gate and a negative tunnelling voltage to a second tunnelling input capacitively coupled to the floating gate.

2. The method of claim 1 , wherein the tunnelling voltages are applied substantially simultaneously for a predetermined period.

3. The method of claims 1 or 2, wherein the tunnelling voltages are applied in the field instead of a factory.

4. The method of any of claims 1 to 3, wherein the tunnelling voltages are of substantially equal magnitude.

5. The method of any of claims 1 to 3, wherein the tunnelling voltages are set to program a zero net charge on the floating gate.

6. The method of any of claims 1 to 3, wherein the tunnelling voltages are set to program a non-zero net charge on the floating gate to achieve a predetermined threshold voltage of the ISFET, wherein preferably the threshold voltage is substantially equal to the threshold voltage of an equivalent Field Effect Transistor.

7. The method of any of claims 1 to 3, wherein the tunnelling voltages are set to program a non-zero net charge on the floating gate such that the Ion Sensitive Field

Effect Transistor is biased in weak inversion mode.

8. The method of any of claims 1 to 7, wherein the positive tunnelling voltage is ramped from zero to a positive voltage level over a first period and the negative tunnelling voltage is ramped from zero to a negative voltage level over a second period.

9. The method of claim 8, wherein the positive and negative tunnelling voltages are maintained above the positive voltage level and below the negative voltage level, respectively, for a third period.

10. The method of any of claims 2 to 9, wherein said tunnelling voltages and/or said periods are determined from knowledge of or from experimentation with the

CMOS process used to make the Ion Sensitive Field Effect Transistor.

1 1 . The method of any of claims 1 to 10, wherein the tunnelling voltages are disconnected to the inputs when a desired charge on the floating gate is reached.

12. The method of any of claims 1 to 1 1 applied to an array of said Ion Sensitive Field Effect Transistors.

13. A method of operating an apparatus comprising an Ion Sensitive Field Effect Transistor having a floating gate, the method comprising:

in response to a user input,

programming a charge on the floating gate according to any preceding claim; measuring an ion concentration of an electrolyte exposed to the Ion

Sensitive Field Effect Transistor.

14. The method according to claim 13, further comprising measuring one or more electrical parameters of the Ion Sensitive Field Effect Transistor.

15. The method according to claim 14, further comprising re-programming a charge according to any of claims 1 to 13 if the one or more electrical parameter measurements is not within a predetermined range.

16. The method according to claim 14, further comprising using the one or more electrical parameters measurements to calculate a corrected ion concentration of the electrolyte.

17. The method according to any of claims 14 to 16, wherein the one or more electrical parameters is the drain current at a predetermined operating point or threshold voltage.

18. A device comprising :

an Ion Sensitive Field Effect Transistor having a floating gate;

two tunnelling inputs coupled by capacitors to the floating gate; and

a programming control circuit connected to the tunnelling inputs and arranged to provide a negative voltage and a positive voltage for bidirectional electron tunnelling to program a charge on the floating gate.

19. The device of claim 18, wherein each capacitor is formed by an oxide layer between each input and a poly-silicon gate connected to the floating gate.

20. The device of claim 18 or 19, further comprising separate doped regions in a semiconductor substrate connected to the tunnelling inputs, such that electrons tunnel between the substrate and floating gate.

21 . The device of claim 20, wherein the doped regions and a region surrounding each doped region are arranged to form a reverse biased junction, preferably wherein a magnitude of the breakdown voltage of the reverse based junction is higher than a maximum voltage applied to each tunnelling input by the programming control circuit.

22. The device of claim 20 or 21 , wherein one of the doped regions is n-type and the other is p-type.

23. The device of any of claims 18 to 22, wherein said capacitors have substantially equal capacitance.

24. The device of any of claims 18 to 23, wherein the magnitude of voltages applied to each tunnelling input is less than 10V, preferably less than 9V, more preferably less than 8V.

25. The device of any of claims 18 to 24, wherein the programming control circuit is arranged to ramp the voltages from zero volts to a maximum magnitude over a predetermined period.

26. The device of any of claims 18 to 25, wherein the programming control circuit is connected to a portable power supply.

27. The device of any of claims 18 to 26, wherein the programming control circuit comprises a charge pump.

28. The device of any of claims 18 to 27, wherein the Ion Sensitive Field Effect Transistor comprises two Field Effect Transistors whose gates are connected to the floating gate and wherein the two transistors are arranged as an inverter.

29. The device of any of claims 18 to 28, further comprising an array of said Ion Sensitive Field Effect Transistors.