WO2013176247A1

WO2013176247A1 - Method for manufacturing transistor and transistor

Info

Publication number: WO2013176247A1
Application number: PCT/JP2013/064466
Authority: WO
Inventors: 翔平小泉; 敬杉▲崎▼; 宮本　健司; 雄介川上
Original assignee: 株式会社ニコン
Priority date: 2012-05-25
Filing date: 2013-05-24
Publication date: 2013-11-28

Abstract

A method for manufacturing transistors comprises a step for forming a gate electrode, a step for forming a layer including an insulator layer, and a step for forming a source electrode and a drain electrode on the surface of the layer including the insulator layer. At least one of the gate electrode, source electrode or drain electrode is formed by a step for forming a base membrane by coating with a moulding material including a silane coupling agent and a step for electroless plating after a metal which is an electroless plating catalyst has been deposited on the surface of the base membrane. The silane coupling agent comprises a group containing nitrogen atoms and/or sulphur atoms.

Description

Transistor manufacturing method and transistor

The present invention relates to a transistor manufacturing method and a transistor.
This application claims priority based on Japanese Patent Application No. 2012-120154 for which it applied on May 25, 2012, and uses the content here.

Conventionally, as a transistor manufacturing method, application of a solution process that is inexpensive and suitable for an increase in size has been studied. When a solution process is employed, a transistor can be manufactured at a lower temperature than in the past. Further, by forming an organic semiconductor layer using an organic semiconductor material on a flexible substrate using a resin material, a flexible organic transistor can be manufactured.

In such a transistor manufacturing method, chemical plating (electroless plating) can be used. Chemical plating (electroless plating) is, for example, a plating method that uses reduction by contact action on the surface of a material. Electroless plating does not use electrical energy. Therefore, it is possible to apply plating to resin materials and glass that are non-conductors. However, difficult-to-plat materials such as resin materials and glass have weak adhesion to the formed plating film, and the plating is easily peeled off due to the internal stress of the plating film, resulting in peeling such as swelling.

Therefore, the surface of the substrate is etched using a chromic acid solution or the like to chemically roughen the surface. Thereby, the plating film to be formed is formed so as to bite into the unevenness of the roughened resin material. Therefore, adhesion can be obtained (anchor effect).

In addition, a method is disclosed in which a base film made of a filler component such as fine powder silica and a resin composition component is provided on the substrate surface and electroless plating is performed on the base film (see, for example, Patent Document 1). Yes.

Japanese Unexamined Patent Publication No. 2008-208389

However, the electrode formed by the above method is provided with a concavo-convex shape reflecting the concavo-convex shape of the base to which the concavo-convex shape is provided due to the etching treatment or the base film containing the filler component. That is, the electrode formed by the above method has an uneven shape caused by an etching process or a base film containing a filler component. The transistor has a stacked structure, and has an electrode and a semiconductor layer in each layer. Therefore, when the electrode has an uneven shape, the performance of the transistor may be deteriorated.

An object of an aspect of the present invention is to provide a method for manufacturing a transistor capable of manufacturing a high-performance transistor by using an electroless plating method. Another object is to provide a high-performance transistor.

According to one embodiment of the present invention, a step of forming a gate electrode on a substrate, a step of forming a layer including the insulator layer so that the insulator layer is in contact with the gate electrode, and the insulator layer Forming a source electrode and a drain electrode on the surface of the layer including, at least one of the gate electrode, the source electrode or the drain electrode is coated with a forming material containing a silane coupling agent, A step of forming a base film, and a step of performing electroless plating after depositing a metal which is a catalyst for electroless plating on the surface of the base film, and the silane coupling agent contains nitrogen atoms or A method of manufacturing a transistor is provided that includes a group having at least one of sulfur atoms.

According to another aspect of the present invention, a step of forming a gate electrode on a substrate, a step of forming a layer including the insulator layer so that the insulator layer is in contact with the gate electrode, Forming a source electrode and a drain electrode on the surface of the layer including the insulator layer, and at least one of the gate electrode, the source electrode, or the drain electrode is made of a metal that is an electroless plating catalyst. Applying a forming material containing a silane coupling agent having a group capable of trapping to form a base film, and depositing the metal on the surface of the base film and then performing electroless plating; A method of manufacturing the formed transistor is provided.

According to another aspect of the present invention, a source electrode and a drain electrode, a gate electrode provided corresponding to a channel between the source electrode and the drain electrode, and the source electrode and the drain electrode And at least one of the gate electrode, the source electrode, or the drain electrode is stacked on a base film containing a silane coupling agent, and the silane coupling agent includes a nitrogen atom. Alternatively, a transistor including a group having at least one of sulfur atoms is provided.

According to another aspect of the present invention, a source electrode and a drain electrode, a gate electrode provided corresponding to a channel between the source electrode and the drain electrode, and the source electrode and the drain electrode A base layer comprising a silane coupling agent having a group capable of capturing a metal that is a catalyst for electroless plating, wherein at least one of the gate electrode, the source electrode, and the drain electrode is provided in contact with the semiconductor layer Transistors are provided that are stacked on top of each other.

According to the aspect of the present invention, a transistor manufacturing method capable of manufacturing a high-performance transistor using an electroless plating method can be provided. In addition, a high-performance transistor can be provided.

It is a schematic sectional drawing of the transistor of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is process drawing which shows the manufacturing method of 1st Embodiment. It is a figure which shows the mode of the drive of the transistor manufactured with the manufacturing method of this embodiment. It is a figure which shows the mode of the drive of the transistor manufactured with the manufacturing method of this embodiment. It is a schematic sectional drawing of the transistor of 2nd Embodiment. It is process drawing which shows the manufacturing method of 2nd Embodiment. It is process drawing which shows the manufacturing method of 2nd Embodiment. It is process drawing which shows the manufacturing method of 2nd Embodiment. It is process drawing which shows the manufacturing method of 2nd Embodiment. It is process drawing which shows the manufacturing method of 2nd Embodiment. It is process drawing which shows the manufacturing method of 2nd Embodiment. It is process drawing which shows the manufacturing method of 2nd Embodiment. It is a photograph which shows the result of an Example. It is a photograph which shows the result of an Example. It is a photograph which shows the result of an Example. It is a graph which shows the result of an Example.

[First Embodiment]
The transistor manufacturing method according to the first embodiment of the present invention and the transistor according to the present embodiment will be described below with reference to FIGS. 1 to 3B. In all the drawings below, the dimensions and ratios of the constituent elements are appropriately changed in order to make the drawings easy to see.

FIG. 1 is a schematic cross-sectional view showing a transistor manufactured by the transistor manufacturing method of the present embodiment and the transistor of the present embodiment. The transistor 1A is a so-called bottom contact type transistor. In the following description, an organic transistor using an organic semiconductor as a material for forming a semiconductor layer will be described. However, the embodiment of the present invention can also be applied to an inorganic transistor using an inorganic semiconductor as a material for forming a semiconductor layer.

The transistor 1A includes a substrate 2,

base films

3 and 13,

catalysts

5 and 15 for electroless plating, a gate electrode 6, an insulator layer 7, a source electrode 16, a drain electrode 17, and an organic semiconductor layer. (Semiconductor layer) 20. In the transistor 1A, a layer including the insulator layer 7 and the base film 13 is a “layer including an insulator layer”.

The substrate 2 can be either a light transmissive material or a non-light transmissive material. For example, an inorganic substance such as glass, quartz glass, or silicon nitride, or an organic polymer (resin) such as an acrylic resin, a polycarbonate resin, or a polyester resin such as PET (polyethylene terephthalate) or PBT (polybutylene terephthalate) can be used. .

These materials of the substrate 2 do not form a metal bond with a metal plating film formed as a result of electroless plating. Therefore, in the present embodiment, the material of the substrate 2 is handled as a difficult-to-platable material in which it is difficult to directly form a plating film and the formed plating film is easily peeled off. For example, a composite material of the above-described materials can be used as the material for forming the substrate 2 as long as the plating film is easily peeled off for the same reason.

The base film 3 is a gate base film in the present invention. The base film 3 is formed so as to cover the entire main surface of the substrate 2. A catalyst (electroless plating catalyst) 5 is selectively provided on a part of the surface of the base film 3. The catalyst 5 is a catalyst that reduces metal ions contained in a plating solution for electroless plating. Examples of the catalyst 5 include silver and metallic palladium. Of these, metallic palladium is preferably used.

The base film 3 is a film capable of capturing the metal that is the catalyst 5 described above. The base film 3 uses a silane coupling agent having a group capable of capturing the metal as a forming material. The base film 3 is formed by applying a liquid material containing such a silane coupling agent to one main surface of the substrate 2.

The “silane coupling agent” which is a material for forming the base film 3 is a compound in which a group capable of capturing the metal which is the catalyst 5 and a group capable of binding to the substrate 2 are bonded to a silicon atom.

The “group capable of capturing a metal” refers to a group capable of capturing the metal that is the catalyst 5 or an ion of the metal by, for example, an ionic bond or a coordinate bond. Examples of such groups include groups having a nitrogen atom or a sulfur atom. As the “group capable of capturing a metal”, for example, an amino group, a urea group, a thiol group (or mercapto group), a thiocarbonyl group, a thiourea group, a hydrogen atom bonded to a heterocyclic compound containing a nitrogen atom or a sulfur atom is 1 Examples thereof include groups having groups obtained by removing two or more.

The “heterocyclic compound containing a nitrogen atom or sulfur atom” includes a monocyclic heteroaromatic compound, a polycyclic heteroaromatic compound, and two or more aromatic rings in these aromatic compounds. Examples include heterocyclic compounds in which carbon atoms are hydrogenated and do not have an aromatic attribute. Examples of monocyclic heteroaromatic compounds include pyrrole, imidazole, pyridine, pyrimidine, thiophene and the like. Examples of polycyclic heteroaromatic compounds include indole and benzothiophene.

The “group capable of binding to the substrate 2” includes a hydroxy group and an alkoxy group having 1 to 6 carbon atoms.

Specific examples of compounds that can be used as a material for forming such an undercoat film 3 include N-cyclohexylaminopropyltrimethoxysilane, bis (3- (trimethoxysilyl) propyl) ethylenediamine, and 1- (3- (Trimethoxysilylpropyl)) urea, bis (3- (trimethoxysilylpropyl)) urea, 2,2-dimethoxy-1,6-diaza-2-silacyclooctane, N- (3- (trimethoxysilylpropyl) ))-4,5-dihydroimidazole, bis (3- (trimethoxysilyl) propyl) thiourea, 3-trimethoxysilylpropanethiol, polyethyleneimine modified with a trimethoxysilylpropyl group, and the like.

Among them, the silane coupling agent preferably has an amino group as a “group capable of capturing a metal”, and is a primary amine or a secondary amine (the “group capable of capturing a metal” is —NH ₂ , And a group represented by —NH— is more preferable. In the following description, it is assumed that the base film 3 is formed using a silane coupling agent that is a primary amine.

The gate electrode 6 is a metal electrode formed on the surface of the catalyst 5. The gate electrode 6 is formed of a metal deposited on the surface of the catalyst 5 by electroless plating as will be described later. Examples of the material of the gate electrode 6 include nickel-phosphorus (NiP) and copper (Cu).

The insulator layer 7 is formed using any of an inorganic material and an organic material as long as it has insulating properties and can electrically insulate the gate electrode 6 from the source electrode 16 and the drain electrode 17. May be. Among these, it is preferable to use a photocurable resin material as a forming material because it is easy to manufacture and finely process. Examples of the material for forming the insulator layer 7 include an ultraviolet curable acrylic resin, an epoxy resin, an ene / thiol resin, and a silicone resin.

The base film 13 is formed on the entire upper surface of the insulator layer 7. The base film 13 is a source base film and a drain base film in the embodiment of the present invention. The base film 13 is formed as a film in which a source base film and a drain base film are continuous. The base film 13 is formed so as to cover the entire main surface of the substrate 2. A catalyst (electroless plating catalyst) 15 is selectively provided on a part of the surface of the base film 13. As a material for forming the catalyst 15, the same material as the catalyst 5 described above can be used.

As a material for forming the base film 13, the same material as the base film 3 described above can be used. However, the base film 3 and the base film 13 may be formed of different materials. In the following description, it is assumed that the base film 13 is formed using a silane coupling agent that is the same primary amine as the base film 3.

In the figure, it is assumed that the base film 13 is formed on the entire upper surface of the insulator layer 7. However, the base film 13 may be selectively formed only at the position where the catalyst 15 is provided. In that case, the base film 13 is selectively formed on the upper surface of the insulator layer 7 by selectively applying a silane coupling agent, which is a material for forming the base film 13, using a generally known method. Can do. Further, on the upper surface of the insulator layer 7, first, a silane coupling agent is applied to a region wider than a region where the base film 13 is formed, and then a film formed in a portion protruding from the region where the base film 13 is formed. The base film 13 may be selectively formed by decomposing and removing the silane coupling agent by irradiating the substrate with ultraviolet rays.

The source electrode 16 and the drain electrode 17 are metal electrodes formed on the surface of the catalyst 15. The source electrode 16 includes a first electrode 161 and a second electrode 162 that covers the surface of the first electrode 161. Similarly, the drain electrode 17 includes a first electrode 171 and a second electrode 172 that covers the surface of the first electrode 171.

The

first electrodes

161 and 171 are formed by electroless plating similarly to the gate electrode 6 described above. Examples of the material of the

first electrodes

161 and 171 include nickel-phosphorus (NiP) and copper (Cu). In the present embodiment, it is assumed that nickel-phosphorus (work function: 5.5 eV) is used as a material for forming the

first electrodes

161 and 171.

The

second electrodes

162 and 172 are metal plating layers formed so as to cover the entire surface of the

first electrodes

161 and 171 that do not contact the catalyst 15. That is, the

second electrodes

162 and 172 are provided so as to cover the side surfaces 16a and 17a (opposing surfaces) facing each other in the source electrode 16 and the drain electrode 17, respectively.

As a material for forming the

second electrodes

162 and 172, a metal material having a work function that facilitates electron transfer (or hole transfer) is used in relation to the HOMO / LUMO level of the material for forming the semiconductor layer 20 described later. . In the present embodiment, it is assumed that gold (work function: 5.4 eV) is used as a material for forming the

second electrodes

162 and 172.

The semiconductor layer 20 is provided on the surface of the base film 13 between the source electrode 16 and the drain electrode 17, and is formed in contact with the source electrode 16 and the drain electrode 17. Specifically, the semiconductor layer 20 is provided in contact with the side surface 16 a of the source electrode 16 and the side surface 17 a of the drain electrode 17, and is in contact with the

second electrodes

162 and 172.

As a forming material of the semiconductor layer 20, a generally known organic semiconductor material can be used. For example, copper phthalocyanine (CuPc), pentacene, rubrene, tetracene, p-type semiconductor and as P3HT (poly (3-hexylthiophene- 2,5-diyl)), fullerenes such as _{C 60,} PTCDI-C8H (N N-type semiconductors such as perylene derivatives such as N′-dioctyl-3,4,9,10-perylene tetracarboxylic diimide) can be used. Among them, soluble pentacene such as TIPS pentacene (6,13-Bis (triisopropylsilylethynyl) pentacene) and organic semiconductor polymers such as P3HT are soluble in organic solvents such as toluene, and form the semiconductor layer 20 in a wet process. This is preferable because it is possible. In the present embodiment, it is assumed that TIPS pentacene (HOMO level: 5.2 eV) which is a p-type semiconductor is used as a material for forming the semiconductor layer 20.
The material for forming the semiconductor layer 20 is not limited to an organic semiconductor material, and a generally known inorganic semiconductor material can also be used.

In such a transistor 1A, the gate electrode 6, the source electrode 16, and the drain electrode 17 formed by electroless plating are the base films 3 and 13 (gate base film, source base film, A drain base film). For example, when these electrodes are formed in a region having a concavo-convex shape, each electrode is provided with a concavo-convex shape reflecting the unevenness of the base. Then, the distance between the electrodes stacked via the insulator layer is not constant, and there is a possibility that the insulation breaks at a position where the distance between the gate electrode and the source electrode or the gate electrode and the drain electrode is close, and a leakage current is generated. . When the base has an uneven shape, an uneven shape is also given (formed) to the channel region (indicated by symbol AR in the drawing) of the semiconductor layer that overlaps the gate electrode in a planar manner, and the carrier travel distance in the channel region May become longer and performance may be reduced.

However, in the transistor 1A of this embodiment, the

base films

3 and 13 use a silane coupling agent as a forming material. Therefore, since the substrate surface is not roughened and a base film containing a filler component is not used, the

base films

3 and 13 are smooth films. Therefore, by forming the

base films

3 and 13, the uneven shape is not formed, and a problem caused by the uneven shape does not occur. Therefore, a high-performance transistor can be manufactured.

Hereinafter, a manufacturing method of the above-described transistor 1A will be described with reference to FIGS. 2A to 2R.

First, as shown in FIG. 2A, a liquid material obtained by diluting the above-described silane coupling agent with an organic solvent as necessary is applied to the surface of the substrate 2 to form a coating film 3A. Examples of the application method include generally known methods such as spin coating, dip coating, spray coating, roll coating, brush coating, printing methods such as flexographic printing and screen printing.
Here, it is assumed that 3-aminopropyltriethoxysilane which is a primary amine is used as the silane coupling agent.

As the organic solvent, various solvents can be used as long as they can dissolve the silane coupling agent. Especially, as an organic solvent, a polar solvent can be used conveniently. Usable solvents include, for example, alcohols such as methanol, ethanol, 1-propanol and 2-propanol (isopropyl alcohol, IPA), ethers such as propylene glycol monomethyl ether acetate (PGMEA), and aromatics such as toluene. Examples include hydrocarbons, nitriles such as acetonitrile, esters such as acetate, and ketones such as acetone, methyl ethyl ketone, and methyl isobutyl ketone.

Next, as shown in FIG. 2B, the organic solvent is volatilized and removed by heat treatment to form the base film 3. The base film 3 formed in this way becomes a silane coupling agent layer having a very thin film thickness. Therefore, light scattering hardly occurs and a transparent film is obtained. Therefore, for example, when the transistor manufactured by the manufacturing method of the present embodiment is provided on a light-transmitting substrate, the substrate 2 and the base film 3 are combined even if the base film 3 is formed on the entire surface of the substrate 2. In addition, light transmittance can be maintained as a whole, and film formation is easy.

Next, as shown in FIG. 2C, a resist material is applied on the base film 3 and pre-baked to form a resist layer 4A that is not patterned. Here, a positive photoresist is used as the resist material.

Thereafter, the resist layer 4A is exposed to ultraviolet rays L through the mask M1 to expose the resist layer 4A. The mask M1 includes an opening Ma at a position corresponding to a region where the metal electrode is formed, and includes a light shielding portion Mb in a region where the metal electrode is not formed.

Next, as shown in FIG. 2D, the resist layer 4 provided with the openings 4a is formed by developing with a developer that dissolves the resist layer irradiated with ultraviolet rays.

Next, as shown in FIG. 2E, the catalyst 5 used for electroless plating is captured on the surface of the base film 3 exposed from the opening 4 a formed in the resist layer 4. Specifically, the metal which is the catalyst 5 is captured by the base film 3 by contacting a colloidal solution of a divalent palladium salt.

A general resin electroless plating step is represented by washing → etching → catalyst application (catalyst formation) → electroless plating. Here, “catalyst application (catalyst formation)” is a process in which a metal such as palladium (Pd), which is a reaction initiator (catalyst) for electroless plating, is attached to the surface of the region to be plated. The usual “catalyst application (catalyst formation)” is a method in which a colloidal solution of divalent palladium salt and divalent tin (Sn) salt is brought into contact with a substrate to deposit palladium, and then palladium is added to an acid or alkali solution called an accelerator. Soak. The usual “catalyst application (catalyst formation)” includes a step of reducing palladium to zero valence and activating it as described above.

On the other hand, when the silane coupling agent that is the material for forming the base film is a primary amine or a secondary amine as in the present embodiment, the reduction treatment using the accelerator described above is unnecessary. It has been confirmed by the inventors (described later). Therefore, when primary amine or secondary amine is used as the silane coupling agent, the operation of electroless plating is simplified.
In the present embodiment, 3-aminopropyltriethoxysilane which is a primary amine is used as a material for forming the base film 3. Therefore, a reduction process is unnecessary and the operation is simplified.

When the silane coupling agent is a tertiary amine or a silicon compound having another “group capable of capturing a metal”, after applying a colloidal solution of a divalent palladium salt, an ordinary accelerator using the above-described accelerator is used. By performing the treatment (activation step), the base film 3 can capture the catalyst 5 for electroless plating.

Next, as shown in FIG. 2F, by bringing the electroless plating solution into contact with the catalyst 5, metal ions dissolved in the electroless plating solution on the surface of the catalyst 5 are reduced and deposited. As described above, the gate electrode 6 made of nickel-phosphorus is formed selectively in the opening 4a. When the silane coupling agent is a primary amine or a secondary amine, the surface of the catalyst 5 is plated by immersing in an electroless plating solution without activation using an accelerator. From this, it can be indirectly confirmed that metal palladium is captured on the surface of the base film 3.

Next, as shown in FIG. 2G, the entire surface of the remaining resist layer is exposed to ultraviolet rays, and then the resist layer is removed with a generally known developer. In this way, the gate electrode 6 is formed.

Next, as shown in FIG. 2H, a coating solution is applied to the surface of the base film 3 so as to cover the gate electrode 6. This coating solution is obtained by dissolving a precursor of an insulating resin material in an organic solvent. As a coating method, the above-described method can be used.

As the resin material, for example, an ultraviolet curable acrylic resin, an epoxy resin, an ene / thiol resin, or a silicone resin can be used. Moreover, as an organic solvent, the polar solvent similar to the coating liquid concerning the above-mentioned coating film 3A can be used suitably. Moreover, in the coating liquid, the viscosity of the whole coating liquid can be adjusted by changing the concentration and the type of the organic solvent, and the film thickness of the coating film 7A of the coating liquid can be controlled.

In the process shown in the figure, in order to suppress leakage between the gate electrode 6 and the source electrode and drain electrode formed in the upper layer, the coating film 7A is thickly applied to a thickness of about several hundred nm.

Next, as shown in FIG. 2I, the resin material is cured by irradiating the coating film 7 </ b> A with ultraviolet rays L through the mask M <b> 2 to form the insulator layer 7. The mask M2 has an opening corresponding to a region where the insulator layer 7 is formed. At this time, in order to promote the curing reaction of the resin material, it is preferable to perform a heat treatment simultaneously with the ultraviolet irradiation or after the ultraviolet irradiation.

Next, as shown in FIG. 2J, the uncured coating film is removed by developing with a solvent S that dissolves the coating film, and a patterned insulator layer 7 is formed.

In this embodiment, a coating solution in which a precursor of an insulating resin material is dissolved in an organic solvent is applied to the surface of the base film 3 so as to cover the gate electrode 6, and the precursor is cured by irradiation with ultraviolet rays. Thus, the embodiment in which the insulator layer 7 is formed has been described. However, in order to improve the adhesion between the insulator layer 7 and the gate electrode 6, a silane coupling agent may be applied to cover the surface including the gate electrode 6 before applying the coating solution.

Next, as shown in FIG. 2K, a liquid material obtained by diluting the above-described silane coupling agent with an organic solvent as required is applied to the entire upper surface of the insulator layer 7. Subsequently, heat treatment is performed to volatilize and remove the organic solvent, and the base film 13 is formed. As the silane coupling agent and the organic solvent, those similar to those exemplified in the formation of the base film 3 described above can be used.

Next, as shown in FIG. 2L, a resist material is applied so as to cover the insulator layer 7 and the base film 13, and a pre-baked resist layer 14A is formed. Here, a positive photoresist is used as the resist material.

Thereafter, the resist layer 14A is irradiated with ultraviolet rays L through the mask M3 to expose the resist layer 14A. The mask M3 is provided with an opening corresponding to a region where the source electrode and the drain electrode are formed.

Next, as shown in FIG. 2M, the resist layer 14 provided with the openings 14a is formed by developing with a developer that dissolves the resist layer irradiated with ultraviolet rays.

Next, as shown in FIG. 2N, the base film 13 exposed from the opening 14a is brought into contact with a colloidal solution of a divalent palladium salt, whereby the catalyst 15 used for electroless plating is applied to the surface of the base film 13. Capture. Thereafter, by bringing the electroless plating solution into contact with the catalyst 15, metal ions dissolved in the electroless plating solution on the surface of the catalyst 15 are reduced and deposited. As described above, the

first electrodes

161 and 171 are formed selectively using nickel-phosphorus as a forming material in the opening 14a.

Next, as shown in FIG. 2P, after the entire surface of the remaining resist layer is exposed to ultraviolet rays, the resist layer is removed with a generally known developer. In this way, the

first electrodes

161 and 171 are formed.

Next, as shown in FIG. 2Q, gold is substituted and deposited on the surfaces of the

first electrodes

161 and 171 by immersing the whole in a substitution gold plating bath. Furthermore, by immersing in a reduced gold plating bath,

second electrodes

162 and 172 using gold as a forming material are formed on the surfaces of the

first electrodes

161 and 171. In this way, the source electrode 16 and the drain electrode 17 are formed.

Next, as shown in FIG. 2R, the semiconductor layer 20 is formed by applying the solution S1 between the source electrode 16 and the drain electrode 17 and drying it. The solution S1 is obtained by dissolving an organic semiconductor material soluble in an organic solvent, such as TIPS pentacene, in the organic solvent. In the present embodiment, the semiconductor layer 20 is formed by a wet method. However, methods such as a sublimation method and a transfer method can also be used.
As described above, the transistor 1A can be manufactured.

According to the method of manufacturing a transistor having the above-described configuration, the

base films

3 and 13 are made of a silane coupling agent as a forming material, and are smooth films. Therefore, there is no problem due to the uneven shape of the base film, and a high-performance transistor can be easily manufactured.

Further, the resist layer 14 is removed in advance before the formation of the

second electrodes

162 and 172. Therefore, the

second electrodes

162 and 172 can be reliably formed on the side surface 16 a of the source electrode 16 and the side surface 17 a of the drain electrode 17. Thus, in the manufactured transistor 1A, current can easily flow between the semiconductor layer 20 and the source electrode 16 (or the semiconductor layer 20 and the drain electrode 17) during driving, and good driving is possible.

In addition, since the

first electrodes

161 and 171 are covered with the

second electrodes

162 and 172, corrosion over time of the

first electrodes

161 and 171 is suppressed, and the performance of the transistor can be stably maintained. It also has an effect.

FIG. 3A and FIG. 3B are schematic diagrams showing how the transistors are driven. FIG. 3A shows a transistor 1x having a configuration similar to that of the transistor 1A except that the second electrode is not provided. FIG. 3B is a diagram showing the transistor 1A manufactured by the manufacturing method of the present embodiment.

In the present embodiment, “the energy level of molecular orbitals used for electron transfer in the organic semiconductor layer forming material” is the HOMO energy level when the organic semiconductor layer is a p-type semiconductor. In the case of an n-type semiconductor, it is the LUMO energy level.

First, when the second electrode is not provided like the transistor 1x shown in FIG. 3A, the gap (energy level difference) between the HOMO of the semiconductor layer 20 and the work function of the first electrode 161 is large. For this reason, a Schottky resistor is generated, and current does not flow easily. Therefore, for example, a current flow through the high-resistance semiconductor layer 20 as shown by an arrow A in FIG. 3A is easily formed, and it is difficult to ensure good conduction.

On the other hand, as shown in FIG. 3B, when applied to a gate electrode (not shown) in the transistor 1A, a channel region AR having a thickness of several nm is formed in the semiconductor layer 20 near the interface with the base film 13. The conduction between the source electrode 16 and the drain electrode (not shown) is enabled. At this time, the surface of the source electrode 16 has a work function in which electron transfer between the surface of the source electrode 16 and the material for forming the semiconductor layer 20 is easier than that of the first electrode 161 (energy level difference from the HOMO of the semiconductor layer 20 is small). The second electrode 162 is formed using a metal material, and the Schottky resistance is reduced. Therefore, the current flows into the channel region AR favorably through the first electrode 161 and the second electrode 162. In FIG. 3B, an arrow B is used to indicate the current flow. Therefore, a high-performance transistor 1A can be realized.

[Second Embodiment]
FIG. 4 is a schematic cross-sectional view of a transistor 1B manufactured by the method for manufacturing a transistor according to the second embodiment of the present invention.

The transistor 1B of this embodiment is partially in common with the transistor 1A of the first embodiment. The difference is that the transistor of the first embodiment is a bottom contact type transistor, and the transistor 1B of this embodiment is a top contact type transistor. Therefore, in this embodiment, the same code | symbol is attached | subjected about the component which is common in 1st Embodiment, and detailed description is abbreviate | omitted.

The transistor 1B has a semiconductor layer 20. The semiconductor layer 20 is disposed on the insulator layer 7, and the source electrode 16 and the drain electrode 17 are formed on the surface thereof.

That is, the semiconductor layer 20 is formed on the entire upper surface of the insulator layer 7, and the base film 13 is formed on the entire upper surface of the semiconductor layer 20. In the transistor 1B, a layer including the insulator layer 7, the semiconductor layer 20, and the base film 13 is a “layer including an insulator layer”.

A catalyst 15 is selectively provided on the upper surface of the base film 13, and a source electrode 16 and a drain electrode 17 are formed. The source electrode 16 has a first electrode 161 and a second electrode 162. The drain electrode 17 has a first electrode 171 and a second electrode 172. In the semiconductor layer 20, the vicinity of the upper surface sandwiched between the source electrode 16 and the drain electrode 17 becomes the channel region AR.

Hereinafter, a method for manufacturing the transistor 1B will be described with reference to FIGS. 5A to 5G.

In the manufacture of the transistor 1B, first, as in the first embodiment, the base film 3, the catalyst 5, the gate electrode 6, and the insulator layer 7 are laminated on the upper surface of the substrate 2. Next, as illustrated in FIG. 5A, the solution S <b> 1 is applied between the source electrode 16 and the drain electrode 17 and dried to form the semiconductor layer 20. The solution S1 is obtained by dissolving an organic semiconductor soluble in an organic solvent in the organic solvent.

Next, as shown in FIG. 5B, a liquid material is applied to the entire upper surface of the semiconductor layer 20, and heat treatment is performed to volatilize and remove the organic solvent, thereby forming a base film 13. The liquid material is obtained by diluting the above silane coupling agent with an organic solvent as necessary.

Next, as shown in FIG. 5C, a resist material is applied so as to cover the insulator layer 7, the semiconductor layer 20, and the base film 13. This is pre-baked to form an unpatterned resist layer 14A. Thereafter, the resist layer 14A is irradiated with ultraviolet light L through the mask M3 to expose the resist layer 14A. The mask M3 is provided with an opening corresponding to a region where the source electrode and the drain electrode are formed.

Next, as shown in FIG. 5D, the resist layer 14 provided with the openings 14a is formed by developing with a developer that dissolves the resist layer irradiated with ultraviolet rays.

Next, as shown in FIG. 5E, a catalyst 15 used for electroless plating is applied to the surface of the base film 13 by bringing a colloidal solution of a divalent palladium salt into contact with the base film 13 exposed from the opening 14a. Capture. Thereafter, by bringing the electroless plating solution into contact with the catalyst 15, metal ions dissolved in the electroless plating solution on the surface of the catalyst 15 are reduced and deposited. As described above, the

first electrodes

161 and 171 using nickel-phosphorus as a forming material are selectively formed in the opening 14a (first electroless plating).

Next, as shown in FIG. 5F, the entire surface of the remaining resist layer is exposed to ultraviolet rays, and then the resist layer is removed with a generally known developer. In this way, the

first electrodes

161 and 171 are formed.

Next, as shown in FIG. 5G, gold is substituted and deposited on the surfaces of the

first electrodes

161 and 171 by immersing the whole in a substitution gold plating bath. Further, by dipping in a reduced gold plating bath,

second electrodes

162 and 172 using gold as a forming material are formed on the surfaces of the first electrodes 161 and 171 (second electroless plating). In this way, the source electrode 16 and the drain electrode 17 are formed.
As described above, the transistor 1B can be manufactured.

Also in such a transistor 1B, the

base films

3 and 13 use a silane coupling agent as a forming material, and the

base films

3 and 13 are smooth films. Therefore, there is no problem due to the uneven shape of the base film, and a high-performance transistor can be easily manufactured.

Further, in the source electrode 16 and the drain electrode 17 of the transistor 1B, electron transfer is easier between the forming material of the semiconductor layer 20 than the first electrodes 161 and 171 (energy level difference from the HOMO of the semiconductor layer 20). The

second electrodes

162 and 172 are formed using a metal material having a work function. Current flows from the

second electrodes

162 and 172 into the channel region AR at a position surrounded by the symbol α. Therefore, a high-performance transistor 1B can be realized.

Further, since the

first electrodes

161 and 171 are covered with the

second electrodes

162 and 172, corrosion of the

first electrodes

161 and 171 with time is suppressed. Therefore, the transistor performance can be stably maintained.

In the transistor of this embodiment, the semiconductor layer 20 and the source electrode 16 and the drain electrode 17 are in direct contact with each other through the base film 13. However, the base film 13 is formed in a very thin layer of several nm. For this reason, the influence of the base film 13 on the transistor characteristics is small, and a good current flows between the semiconductor layer 20 and the source electrode 16 and the drain electrode 17.

As described above, the preferred embodiments according to the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to such examples. Various shapes and combinations of the constituent members shown in the above-described examples are merely examples, and various modifications can be made based on design requirements and the like without departing from the gist of the present invention.

For example, a non-metallic material can be used as the substrate. Using a PET substrate, which is a non-metallic material, prepare a plurality of plating members on which a base film is formed, and manufacture transistors using the above-described manufacturing method in the transport process while transporting the plurality of plating members. Thus, a high-performance transistor can be formed on the PET substrate.

Furthermore, a transistor can be formed on a PET film in a so-called roll-to-roll process. Specifically, a flexible long PET film is used as a substrate, and a plating member having a base film formed on the film is rolled up. Then, the plating member is conveyed while being unwound, and transistors are continuously formed using the above-described manufacturing method. Thereafter, the transistor can be formed on a PET film so that the manufactured transistor is rolled up.

In this embodiment, after forming a base film using a silane coupling agent as a forming material, a catalyst for electroless plating is captured by the base film, and electroless plating is performed to form a gate electrode, a source electrode, and a drain. An electrode was formed. However, any one or two of these electrodes may be formed by the above method, and the remaining electrodes may be formed by another method. For example, the gate electrode may be formed using a generally known patterning method, and the source electrode and the drain electrode formed in the same layer may be formed using the above-described manufacturing method.

Hereinafter, the present invention will be described by way of examples, but the present invention is not limited to these examples.

[Fabrication of gate electrode]
In this example, 3-aminopropyltriethoxysilane (KBE903, manufactured by Shin-Etsu Silicone Co., Ltd.), which is an amine silane coupling agent, is methyl isobutyl ketone (hereinafter referred to as MIBK) so as to be 0.2% by mass. And a liquid material was prepared and used to form the base film.

After cleaning the surface of a PET substrate (model number: A-4100 (no coating), manufactured by Toyobo Co., Ltd.) with atmospheric pressure oxygen plasma, the liquid material is applied onto the PET substrate by spin coating (4000 rpm × 30 seconds). did. Then, it heated at 120 degreeC for 10 minute (s), and formed the base film.

Next, a resist material (SUMIRESIST PFI-34A6, manufactured by Sumitomo Chemical Co., Ltd.) was spin-coated on the surface of the substrate on which the base film was formed, and heated (prebaked) at 90 ° C. for 5 minutes. A resist layer was formed as described above. The spin coating conditions are 1000 rpm for 30 seconds. A resist layer having a thickness of about 1 μm was formed.

Next, UV light having an intensity of 18 mW / cm ² was exposed for 5 seconds through a photomask and heated (post-baked) at 110 ° C. for 5 minutes. Thereafter, the mask pattern was developed in the resist layer to form an opening by immersing in a 2.38% TMAH solution for 2 minutes.

Next, the substrate on which the resist layer opening was formed was subjected to ultrasonic water washing at room temperature for 30 seconds. After that, it was immersed in a catalyst colloid solution for electroless plating (Melplate ™ activator 7331, manufactured by Meltex) for 60 seconds at room temperature. As described above, the catalyst was adhered to the base film exposed from the opening of the resist layer.

Next, the surface was washed with water and then immersed in an electroless plating solution (Melplate NI-867, manufactured by Meltex) at 73 ° C. for 60 seconds. As described above, nickel-phosphorus was deposited on the catalyst adhering to the opening of the resist layer to perform nickel-phosphorus plating.

Next, the surface was washed with water and dried, and the entire surface including the remaining resist layer was exposed to ultraviolet light having an intensity of 18 mW / cm ² for 1 minute. Then, the resist layer was removed by immersing in ethanol for 1 minute, and the gate electrode was produced.

[Preparation of insulator layer]
In order to improve the adhesion between the gate electrode and the insulator layer to be formed, a silane coupling agent (N-2- (aminoethyl) -3-aminopropyltrimethyl trichloride is formed on the entire surface of the PET substrate on which the gate electrode is formed. Ethoxysilane, KBM603, manufactured by Shin-Etsu Silicone Co., Ltd.) was applied. Specifically, the silane coupling agent was diluted to 1% by mass with a mixed solvent of ethanol and water. Thereafter, the diluted silane coupling agent was further diluted with MIBK to prepare a 0.2 mass% silane coupling agent solution. This 0.2 mass% silane coupling agent solution was applied by spin coating on the entire surface of the PET substrate on which the gate electrode was formed.

Next, after heating at 120 ° C. for 5 minutes, an ultraviolet curable resin solution was applied by spin coating. The ultraviolet curable resin solution is composed of urethane acrylate resin (Art Resin HA3220, manufactured by Negami Kogyo Co., Ltd.), polymerization initiator IRGACURE 1173 (manufactured by Ciba Specialty Chemicals), and propylene glycol monoethyl ether (hereinafter referred to as solvent). , Sometimes referred to as PGME) and butyl acetate. The mixing ratio (mass ratio) was resin: polymerization initiator: PGME: butyl acetate = 15: 0.5: 50: 34.5. The spin coating conditions were 1000 rpm for 30 seconds.

Next, ultraviolet rays were irradiated for 45 seconds through a mask having an opening at the portion where the insulator layer was formed. In order to accelerate curing, heat treatment was performed at 120 ° C. for 5 minutes. Then, it was immersed in an acetone developer and subjected to ultrasonic treatment for 10 seconds. As described above, an ultraviolet curable resin was patterned into a film. After patterning film formation, heat treatment was performed at 120 ° C. for 10 minutes to form an insulator layer.

[Production of source / drain electrodes]
Next, on the entire surface of the PET substrate on which the insulator layer was formed, a base film and a resist layer were prepared and electroless plating was performed in the same manner as in [Preparation of gate electrode] described above. As described above, a patterned NiP electrode was formed on the insulator layer. The NiP electrode corresponds to the first electrode described in the embodiment.

In addition, after the resist was stripped, it was immersed in a displacement gold plating bath for 1 minute and further immersed in a reduction plating bath for 3 minutes. As described above, electroless gold plating was performed, and the surface of the NiP electrode was covered with gold to produce a source electrode and a drain electrode.

6A and 6B are cross-sectional images of the multilayer wiring structure manufactured by the above procedure. 6A is an SEM image, and FIG. 6B is a TEM image.

From the cross-sectional SEM image shown in FIG. 6A, it was observed that the source / drain electrode was composed of two layers, and the surface of the NiP electrode was covered with gold cleanly. Further, from the cross-sectional TEM image shown in FIG. 6B, it was found that smooth gate electrodes and source / drain electrodes were formed.

[Production of organic semiconductor layer]
Under a nitrogen atmosphere, a toluene solution of TIPS pentacene (manufactured by Sigma-Aldrich) was dropped between the source electrode and the drain electrode and allowed to dry naturally. A semiconductor layer was formed as described above to manufacture a transistor. The TIPS pentacene / toluene solution used was also adjusted under a nitrogen atmosphere.

FIG. 7 is an enlarged photograph of a source electrode and a drain electrode having an organic semiconductor layer formed on the surface. It was observed that a TIPS pentacene crystal was formed between the source electrode and the drain electrode.

[Evaluation of transistors]
The transistor characteristics of the manufactured transistor were evaluated using a semiconductor parameter analyzer (model number: 4145B, manufactured by Yokogawa / Hewlett Packard).

FIG. 8 is a graph showing transistor characteristics of a transistor manufactured by a wet process using the above-described method.

A gate voltage of 0 V to −40 V was applied to the gate electrode of the obtained organic thin film transistor, and a voltage of 0 V to −40 V was applied between the source and drain to pass a current. As a result, as shown in FIG. 8, holes were induced in the channel region (between the source and drain) of the semiconductor layer, and the manufactured transistor operated as a p-type transistor.

From the above results, it was found that a transistor (organic thin film transistor) can be produced by a fully wet process. Further, it was confirmed that the use of a silane coupling agent, which is a primary amine, as the undercoat film eliminates the need for an accelerator treatment and simplifies the operation of electroless plating.

The base film formed using the silane coupling agent is a flat film with extremely small irregularities. Therefore, it was found that when the stacked structure was formed, the upper layer structure of the base film was not provided with an uneven shape (not formed), and a high-performance transistor could be obtained.

Furthermore, the entire surface of the source / drain electrodes can be covered with a metal material having a work function with a small energy gap and HOMO as a material for forming the organic semiconductor layer by using an electroless plating method. Therefore, it was found that a transistor having a small electrical contact resistance between the organic semiconductor layer and the source / drain electrodes can be provided.
From the above results, the usefulness of the present invention was confirmed.

DESCRIPTION OF SYMBOLS 1 ... Transistor, 2 ... Substrate, 3 ... Base film (gate base film), 6 ... Gate electrode, 7 ... Insulator layer, 13 ... Base film (source base film, drain base film), 14 ... Resist layer, 14a ... Opening portion, 15 ... catalyst for electroless plating, 16 ... source electrode, 16a, 17a ... side surface (opposing surface), 17 ... drain electrode, 20 ... semiconductor layer

Claims

Forming a gate electrode on the substrate;
Forming a layer including the insulator layer so that the insulator layer is in contact with the gate electrode;
Forming a source electrode and a drain electrode on the surface of the layer including the insulator layer, and
At least one of the gate electrode, the source electrode or the drain electrode is:
Applying a forming material containing a silane coupling agent to form a base film;
A step of performing electroless plating after depositing a metal as a catalyst for electroless plating on the surface of the base film,
The silane coupling agent includes a group having at least one of a nitrogen atom and a sulfur atom.
Forming a gate electrode on the substrate;
Forming a layer including the insulator layer so that the insulator layer is in contact with the gate electrode;
Forming a source electrode and a drain electrode on the surface of the layer including the insulator layer, and
At least one of the gate electrode, the source electrode or the drain electrode is:
Applying a forming material containing a silane coupling agent having a group capable of capturing a metal which is a catalyst for electroless plating, and forming a base film;
And a step of performing electroless plating after depositing the metal on the surface of the base film. A method of manufacturing a transistor.
The source electrode and the drain electrode are formed by forming the source base film and the drain base film, which are the base films, and then depositing the metal on the surfaces of the source base film and the drain base film and performing electroless plating. The method for manufacturing a transistor according to claim 1, wherein the transistor is formed by a process.
The method for manufacturing a transistor according to claim 3, wherein the source base film and the drain base film are formed as a continuous film.
5. The gate electrode is formed by a step of depositing the metal on the surface of the gate underlayer after forming a gate underlayer which is the underlayer, and performing electroless plating. A method for producing the transistor according to 1.
The method for manufacturing a transistor according to claim 1, wherein the silane coupling agent has an amino group.
The method for manufacturing a transistor according to claim 6, wherein the silane coupling agent is a primary amine or a secondary amine.
The layer including the insulator layer includes the insulator layer, and an organic semiconductor layer disposed on the insulator layer and having the source electrode and the drain electrode formed on a surface thereof. The manufacturing method of the transistor of any one of Claims 1.
The transistor according to claim 1, further comprising: forming an organic semiconductor layer in contact with surfaces of the source electrode and the drain electrode facing each other after forming the source electrode and the drain electrode. Manufacturing method.
Prior to forming the source electrode and the drain electrode, a resist layer having an opening corresponding to the source electrode and the drain electrode is formed, and at least the base film formed on the surface exposed from the opening is formed. Depositing the metal on the surface;
Removing the resist layer after performing the first electroless plating;
Performing a second electroless plating on the surface of the electrode formed by the first electroless plating to form the source electrode and the drain electrode, and
The energy level difference between the work function of the metal material used for the second electroless plating and the energy level of the molecular orbital used for electron transfer in the material for forming the organic semiconductor layer is the same as that of the first electroless plating. 10. The method for manufacturing a transistor according to claim 8, wherein an energy level difference between a work function of a metal material to be used and an energy level of the molecular orbital is smaller.
The method for manufacturing a transistor according to claim 1, wherein the substrate is made of a nonmetallic material.
The method for manufacturing a transistor according to claim 11, wherein the substrate is made of a resin material.
The method for manufacturing a transistor according to claim 12, wherein the substrate has flexibility.
A source electrode and a drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode;
With
At least one of the gate electrode, the source electrode or the drain electrode is laminated on a base film containing a silane coupling agent,
The silane coupling agent includes a group having at least one of a nitrogen atom and a sulfur atom.
A source electrode and a drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode,
At least one of the gate electrode, the source electrode, and the drain electrode is laminated on a base film containing a silane coupling agent having a group capable of capturing a metal that is a catalyst for electroless plating.
The transistor according to claim 14, wherein the semiconductor layer is an organic semiconductor layer.
The source electrode and the drain electrode each have a first electrode and a second electrode formed to cover the first electrode,
The energy level difference between the work function of the material forming the second electrode and the energy level of the molecular orbital used for electron transfer in the material forming the organic semiconductor layer is the work function of the material forming the first electrode, The transistor according to claim 16, wherein the transistor has an energy level difference smaller than an energy level of the molecular orbital.
The transistor according to claim 14, formed on a substrate made of a nonmetallic material.
The transistor according to claim 18, wherein the substrate is made of a resin material.
The transistor according to claim 19, wherein the substrate has flexibility.