WO2013153695A1 - Method for producing photoelectric conversion device and photoelectric conversion device - Google Patents
Method for producing photoelectric conversion device and photoelectric conversion device Download PDFInfo
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- WO2013153695A1 WO2013153695A1 PCT/JP2012/079408 JP2012079408W WO2013153695A1 WO 2013153695 A1 WO2013153695 A1 WO 2013153695A1 JP 2012079408 W JP2012079408 W JP 2012079408W WO 2013153695 A1 WO2013153695 A1 WO 2013153695A1
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- semiconductor layer
- photoelectric conversion
- conversion device
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- intrinsic semiconductor
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
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- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
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- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Definitions
- the present invention relates to a method for manufacturing a photoelectric conversion device and a photoelectric conversion device.
- Patent Document 1 proposes a method of forming a solar cell by forming a tetrahedral amorphous carbon layer on a substrate and then depositing a pin or nip type semiconductor. Yes.
- the tetrahedral amorphous carbon layer used for suppressing impurity diffusion is formed by the FCVA (Filtered Cathodic Vacuum Arc) method. Cost is inevitable. Further, since the tetrahedral amorphous carbon layer is not inserted into the interface of the pi-type semiconductor layer, but is inserted into the interface between the substrate and the pin-type semiconductor layer, the pi-type semiconductor layer Impurity diffusion at the interface cannot be suppressed, and the effect of improving cell conversion efficiency is weak.
- FCVA Flutered Cathodic Vacuum Arc
- Patent Document 1 there is a description that impurity diffusion at the interface of the pi-type semiconductor layer is suppressed by forming the film in the order of the nip-type semiconductor layer. According to the experimental results conducted, it was confirmed that even if the i-type semiconductor layer and the p-type semiconductor layer were formed in this order on the silicon substrate, impurity diffusion into the i-type semiconductor layer and the substrate could not be suppressed.
- the present invention has been made in view of the above, and an object of the present invention is to obtain a photoelectric conversion device that is easy to manufacture, can suppress impurity diffusion at the interface, and has high photoelectric conversion efficiency.
- the present invention it is possible to suppress the penetration of the dopant into the lower layer (i-type semiconductor layer, substrate, etc.) of the first conductivity type semiconductor layer and the lower layer deterioration without requiring a special apparatus or process. Therefore, it is possible to improve the open-circuit voltage, the fill factor, and the photoelectric conversion efficiency without causing an increase in cost.
- FIG. 1 is a schematic cross-sectional view of a photoelectric conversion device after formation of a p-type semiconductor layer by the method for manufacturing a photoelectric conversion device according to Embodiment 1 of the present invention.
- FIG. 2-1 is a process cross-sectional view (schematic diagram illustrating the i-type amorphous silicon layer after formation) illustrating the manufacturing process of the photoelectric conversion device according to Embodiment 1 of the present invention.
- 2-2 is a process cross-sectional view (schematic diagram showing a state during an i-type amorphous silicon layer forming process for p-type conversion) showing the manufacturing process of the photoelectric conversion device according to Embodiment 1 of the present invention.
- FIG. 1 is a schematic cross-sectional view of a photoelectric conversion device after formation of a p-type semiconductor layer by the method for manufacturing a photoelectric conversion device according to Embodiment 1 of the present invention.
- FIG. 2-1 is a process cross-sectional view (schematic diagram illustrating the
- FIG. 2-3 is a process cross-sectional view (schematic diagram showing a state during the p-type process of the i-type amorphous silicon layer) showing the manufacturing process of the photoelectric conversion device according to Embodiment 1 of the present invention.
- 2-4 is a process cross-sectional view (schematic diagram showing a state during an i-type amorphous silicon layer forming process for p-type conversion) showing the manufacturing process of the photoelectric conversion device according to Embodiment 1 of the present invention.
- FIG. FIG. 2-5 is a process cross-sectional view (schematic diagram showing a state during the p-type process of the second i-type amorphous silicon layer) showing the manufacturing process of the photoelectric conversion device according to Embodiment 1 of the present invention. .
- FIG. 3 is a flowchart showing the formation process of the i-type semiconductor layer and the p-type semiconductor layer in the manufacturing process of the photoelectric conversion device according to Embodiment 1 of the present invention.
- FIG. 4 is a diagram showing a substrate temperature profile in the manufacturing process of the photoelectric conversion device according to Embodiment 1 of the present invention.
- FIG. 5 is a schematic diagram showing the photoelectric conversion apparatus according to Embodiment 1 of the present invention.
- FIG. 6 is a diagram showing the results of dopant intrusion evaluation by SIMS of a sample manufactured by the photoelectric conversion device manufacturing process according to Embodiment 1 of the present invention and a conventional process.
- FIG. 7 is a diagram showing the relationship between the thickness of each i-type amorphous silicon film that contributes to p-type formation and the electrical characteristics.
- FIG. 1 is a schematic view showing a cross section after formation of a p-type semiconductor layer (amorphous silicon layer) in a photoelectric conversion device formed by the method for manufacturing a photoelectric conversion device according to Embodiment 1 of the present invention.
- FIGS. 2-1 to 2-5 are process cross-sectional views illustrating the manufacturing process of the photoelectric conversion device.
- a plasma CVD method is used.
- a substrate whose surface is a semiconductor layer of a desired conductivity type a p-type or n-type crystalline silicon substrate is used, but since it is usually cut out by slicing, a natural oxide film and a slicing surface are formed on the surface. In many cases, there are structural defects such as damage of metal and contamination by metals. For this reason, the n-type single crystal silicon substrate 1 is first removed from the ingot by etching by immersing the n-type single crystal silicon substrate 1 in an acid or heated alkaline solution, for example, in an aqueous solution of sodium hydroxide. A damage region that occurs when the crystalline silicon substrate 1 is cut out and exists near the surface of the n-type single crystal silicon substrate 1 is removed.
- gettering is performed to remove impurities in the n-type single crystal silicon substrate 1.
- Phosphorus is thermally diffused at a processing temperature of about 1000 ° C., impurities are segregated in the phosphorous glass layer formed by the thermal diffusion, and the phosphorous glass layer is etched with hydrogen fluoride or the like.
- a texture is formed by wet etching using an alkaline solution and an additive (not shown) for the purpose of reducing light reflection loss on the surface of the n-type single crystal silicon substrate 1.
- Potassium hydroxide, sodium hydroxide or the like is used for the alkaline solution, and isopropyl alcohol or the like is used for the additive.
- fine irregularities may be formed as a texture structure on the surface of the n-type single crystal silicon substrate 1 on the light receiving surface side.
- the present embodiment is characterized by the formation of the n-type semiconductor layer, and thus the formation method and shape of the texture structure are not particularly limited.
- an alkaline aqueous solution containing isopropyl alcohol, a method using acid etching mainly composed of a mixed solution of hydrofluoric acid and nitric acid, or a mask material partially provided with an opening is formed on the surface of the n-type single crystal silicon substrate 1.
- Any method such as a method of obtaining a honeycomb structure or an inverted pyramid structure on the surface of the n-type single crystal silicon substrate 1 by etching through the mask material, or a method using reactive gas etching (RIE). May be used.
- RIE reactive gas etching
- the substrate is cleaned to remove particles, organic contamination, and metal contamination on the surface of the n-type single crystal silicon substrate 1 that becomes the heterojunction interface.
- so-called RCA cleaning, SPM, HPM, DHF cleaning, alcohol cleaning, or the like is used.
- a film forming tray on which the n-type single crystal silicon substrate 1 is mounted as a semiconductor substrate is mounted on a CVD apparatus stage in the CVD film forming chamber.
- a process gas is supplied via a mass flow controller and a shower plate electrode.
- a voltage is applied between the shower plate electrode and the CVD apparatus stage by an RF power source, and the catalyst line CVD method is applied.
- the process gas is decomposed by heat caused by the heated catalyst wire in the apparatus, an i-type semiconductor layer and a p-type semiconductor layer are formed on the substrate surface, and an i-type semiconductor layer and n are formed on the back surface of the substrate.
- FIG. 4 shows the temperature profile of the substrate temperature.
- the substrate temperature in the formation step S 1 of the i-type amorphous silicon layer 2 , the formation step S 2 of the i-type amorphous silicon layer 4 i, and the chemical adsorption step S 3 for p-type formation were all set to 165 ° C.
- the formation process S 2 of the i-type amorphous silicon layer 4 i and the chemical adsorption process S 3 for p-type conversion are repeated four times in succession, but only the first one is shown here and the others are omitted. ing.
- the n-type single crystal silicon substrate 1 is transferred to a plasma CVD (PECVD) apparatus (step S101). Then, as shown in FIG. 2A, an i-type amorphous silicon layer 2 is formed on the surface of the n-type single crystal silicon substrate 1.
- PECVD plasma CVD
- silane gas or hydrogen gas flowing out from the shower plate electrode is decomposed by applying a voltage between the electrodes to form an i-type amorphous silicon layer 2 on the n-type single crystal silicon substrate 1. This is done by depositing.
- a p-type amorphous silicon layer 4 is formed as a p-type semiconductor layer.
- an i-type amorphous silicon layer 4ai is formed by plasma CVD (FIG. 2-2: Step S102).
- P is a gas plasma.
- a doping gas DG is supplied to the i-type amorphous silicon layer 4ai to chemisorb the dopant, thereby making the i-type amorphous silicon layer 4ai a p-type amorphous silicon layer 4a (FIG. 2-3: Step S103).
- the supply of the doping gas DG is stopped, and the film forming chamber is evacuated by a vacuum pump (step S104).
- i-type amorphous silicon layers 4ai to 4di having a thickness of 2 nm are sequentially formed one by one in the gas plasma P. Then, each time one layer is formed, the doping gas DG is supplied and the process of chemisorbing the dopant (four times such as FIGS. 2-3 and 2-5) is repeated. In this way, the p-type amorphous silicon layer 4 (4a, 4b, 4c, 4d) is formed, and a pn junction of the photoelectric conversion device is formed.
- silane gas and hydrogen gas flowing out from the shower plate electrode are decomposed by applying a voltage between the electrodes, and after depositing an i-type amorphous silicon layer as an i-type semiconductor film on the n-type single crystal silicon substrate 1, silane gas Then, supply of hydrogen gas and application of RF power are stopped, doping gas DG is supplied into the apparatus, and is chemically adsorbed on the surface of the i-type amorphous silicon layer. These series of steps can be performed by switching the doping gas DG while keeping the substrate temperature constant in the same chamber.
- the film thickness of the i-type semiconductor film is 2 nm or less, 0.1 nm or more, and in consideration of the film thickness deviation during film formation, it is preferably 1 nm or less and 0.5 nm or more.
- each i-type amorphous silicon film that contributes to p-type formation is 2 nm or less and the dark conductivity reaches a level that functions as a p-layer of a photoelectric conversion device, the electrical characteristics decrease as the thickness decreases. Will improve.
- the finished thickness of the p-type amorphous silicon film is 10 nm. Moreover, by setting it to 0.1 nm or more, diffusion of the dopant to the lower layer can be suppressed.
- diborane or trimethylboron as the doping gas. All of these gases can be decomposed at relatively low temperatures.
- diborane having a good thermal decomposition reaction even at about 100 to 200 ° C. is used.
- boron density on the surface of the intrinsic semiconductor film that contributes to p-type conversion by supplying doping gas per time can be reduced to 1 ⁇ 10 14 / cm 2 or less, and an increase in electrical resistance due to a polymerization reaction between boron is suppressed. be able to.
- the substrate heating temperature in the chemical adsorption process is set to 100 to 200 ° C., which is the film forming temperature of the i-type semiconductor film to be made p-type
- the doping gas can be thermally decomposed sufficiently.
- the time required for temperature control can be greatly shortened, and basically, the entire film forming process can be realized only by switching gases at the same temperature.
- the thermal decomposition efficiency of the doping gas is lowered, the boron density of the intrinsic semiconductor film contributing to p-type formation is significantly lowered, and it does not function as the p layer of the photoelectric conversion device.
- the process may be controlled so that the film forming temperature is 50 ° C. or higher and 250 ° C. or lower.
- the intrinsic semiconductor film that contributes to p-type conversion should be a hydrogenated intrinsic semiconductor.
- a hydrogenated intrinsic semiconductor has a hydrogen content of 2 at% or more, generally about 10 to 20 at%, and an unhydrogenated intrinsic semiconductor film has a very low hydrogen content of about 1 at% or less.
- this hydrogen content is proportional to the amount of hydrogen bonds in the film, when the process of this embodiment is applied, boron is substituted at the hydrogen bond portion, or boron forms a bond in an unbonded hand.
- a hydrogenated intrinsic semiconductor has more hydrogen content and dangling bonds than an unhydrogenated intrinsic semiconductor, and boron activity is high when the process of the present invention is applied.
- the hydrogen content is excessively high, the mobility of electric charges involved in electric conduction is reduced and the photoelectric conversion device does not function as a p-layer.
- the hydrogen density in the hydrogenated intrinsic semiconductor film may be 2 at% or more and 30 at% or less.
- BF-STEM and HAADF -STEM evaluation allows observation of structural disorder in the lower layer of the p-type semiconductor layer and denseness of the film, and depth profiling of boron element on one slope of the texture structure by the three-dimensional atom probe method. The presence or absence can be determined.
- a translucent conductive film is formed on the front and back surfaces of the substrate 10 on which the heterojunction photoelectric conversion cell is formed by sputtering or vapor deposition.
- Indium tin oxide and indium oxide are formed.
- a deposition method or a film forming method using a mask is used so that a conductive film is not formed on the side surface of the substrate, and insulation is separated between the p layer and the n layer.
- the current collecting electrode is formed.
- a pattern of aluminum, silver, or the like is formed on the surface 10S of the substrate 10 on the surface transparent conductive film 5 by sputtering, vapor deposition, screen printing, or the like.
- the current collecting electrode 9 on the back surface aluminum, silver, or the like is formed on the back surface transparent conductive film 6 by sputtering, vapor deposition, printing, or the like.
- Reference numeral 7 denotes a back surface reflecting film.
- the back surface reflection film 7 is provided on the back surface 10R of the substrate 10 and reflects the light that has reached the back surface 10R of the n-type single crystal silicon substrate 1.
- a silver paste as an electrode paste is screen printed on the p-type amorphous silicon layer 4 and dried.
- an aluminum paste as an electrode paste is screen-printed and subjected to the printing / drying process of drying at about 200 ° C., for example.
- the light-transmitting conductive film in addition to indium tin oxide (ITO), crystalline metal oxides such as zinc oxide (ZnO), tin oxide (SnO 2 ), and zirconium oxide (ZrO 2 ) are used.
- the light-transmitting conductive oxide film as a main component and a light-transmitting film such as a film obtained by adding aluminum (Al) to these light-transmitting conductive oxide films are used.
- the light-transmitting electrode layer has aluminum (Al), gallium (Ga), indium (In), boron (B), yttrium (Y), silicon (Si), zirconium (Zr), and titanium (Ti) as dopants.
- a ZnO film using at least one element selected from the above, an ITO film, a SnO 2 film, a light-transmitting conductive film formed by stacking these, or a light-transmitting conductive film may be used. That's fine.
- the dopant can enter the lower layer (i-type semiconductor layer, substrate, etc.) and the lower layer deterioration can be suppressed, so that the cost increases.
- the open-circuit voltage, fill factor, and photoelectric conversion efficiency can be improved without incurring.
- the i-type semiconductor film is a silicon-based material
- either an amorphous layer or a crystalline thin film can be selected.
- the passivation characteristics can be enhanced.
- a crystalline thin film when a crystalline thin film is used, light transmittance can be enhanced.
- the film forming temperature of the i-type semiconductor film is about 100 to 200 ° C., as is generally known, in the case of an amorphous silicon film or a microcrystalline silicon film, thereby reducing the amount of hydrogen in the film.
- the crystallinity can be improved, and a high-quality silicon film can be obtained. Therefore, it is desirable to form the film within this range.
- the film forming temperature is a low temperature of 100 ° C. or lower, defects increase and as a result, the amount of hydrogen in the film increases. In other words, when the film forming temperature is low, hydrogen becomes excessive in the bonding network in the amorphous silicon film, and a sparse film, that is, a film containing many defects is formed.
- the plasma CVD method is desirable as the film forming method, but the method is not limited to the plasma CVD method, and can be changed as appropriate, such as a catalytic wire CVD method, a photo CVD method, a sputtering method, a vapor deposition method, and a liquid coating method. is there. ⁇ Example 1>
- FIG. A1 is a curve showing the boron B concentration in the photoelectric conversion device of the first embodiment.
- R1 is a curve showing the boron B concentration in the conventional photoelectric conversion device.
- A2 is a curve showing the secondary ion intensity of hydrogen in the photoelectric conversion device of the first embodiment.
- R2 is a curve showing the secondary ion intensity of hydrogen in the conventional photoelectric conversion device.
- A3 is a curve showing the silicon concentration in the photoelectric conversion device of the first embodiment.
- R3 is a curve showing the silicon concentration in the conventional photoelectric conversion device.
- A4 is a curve showing the indium concentration in the photoelectric conversion device of the first embodiment.
- R4 is a curve showing the indium concentration in the conventional photoelectric conversion device.
- the formation conditions of the i-type amorphous silicon layer were as follows: RF power density was 32 mW / cm 2 , film forming temperature was 165 ° C., film forming pressure was 150 Pa, distance between electrodes was 15 mm, silane gas flow rate was 10 sccm, and hydrogen gas flow rate was 100 sccm. .
- the conditions for forming the p-type amorphous silicon layer will be described separately for the process for forming the i-type amorphous silicon film and the process for p-type formation in which diborane gas is chemically adsorbed.
- the formation conditions of the i-type amorphous silicon film are as follows: RF power density is 32 mW / cm 2 , film forming temperature is 165 ° C., film forming pressure is 300 Pa, distance between electrodes is 15 mm, silane gas flow rate is 10 sccm, hydrogen gas flow rate is 100 sccm. It was.
- p-type conditions for chemical adsorption of diborane gas are as follows: substrate temperature is 165 ° C., process pressure is 150 Pa, distance between electrodes is 15 mm, diborane gas flow rate is 0.3 sccm, and the flow rate of hydrogen gas that plays the role of carrier gas is 50 sccm. It was. ⁇ Example 2>
- a photoelectric conversion device 100 having a heterojunction of crystalline silicon and amorphous silicon using an n-type single crystal silicon substrate 1 having a pn junction of Example 1 is used.
- the layers other than the silicon layer are formed in the same manner as the method described in Embodiment Mode 1.
- an indium tin oxide layer is formed as the front surface light-transmitting conductive film 5 and the back surface light-transmitting conductive film 6, and a silver layer and an aluminum layer are formed as the current collecting electrodes 8 and 9 on the front surface and the back surface.
- a back surface reflection film 7 was formed on the back surface 10R of the substrate 10.
- a sample was prepared in the same manner as in Example 1, and the same evaluation was performed.
- the formation conditions of the p-type amorphous silicon layer are as follows: RF power density is 32 mW / cm 2 , film forming temperature is 165 ° C., pressure is 150 Pa, distance between electrodes is 15 mm, silane gas flow rate is 10 sccm, hydrogen gas flow rate is 100 sccm, diborane gas flow rate is 0.1 sccm.
- a photoelectric conversion device was produced in the same manner as in Example 2 except for the conditions for forming the p-type amorphous silicon layer, and the electrical characteristics were similarly evaluated.
- the p-type amorphous silicon layer was formed under the same conditions as in Comparative Example 1.
- Example 1 the evaluation results of Example 1 and Comparative Example 1 are shown. From the comparison between the curve A1 indicating the boron B concentration in the photoelectric conversion device of the first embodiment in FIG. 6 and the curve R1 of the comparative example, in the comparative example which is a conventional method for forming the p-type amorphous silicon layer, the i-type is shown. It is clear that the diffusion of boron into the amorphous silicon layer is deeper than the embodiment and the amount of diffusion is large. Further, the amount of impurities entering the lower layer of the p-type amorphous silicon layer (semiconductor layer) is 1/10 or less of the amount of impurities in the p-type amorphous silicon layer within the penetration length of 1 nm.
- the curve A2 showing the secondary ion intensity of hydrogen in the photoelectric conversion device of the first embodiment and the curve R2 showing the secondary ion intensity of hydrogen in the photoelectric conversion device of the conventional example are based on the hydrogen ion concentration level. Used to identify the amorphous silicon layer.
- the curve A3 indicating the silicon concentration in the photoelectric conversion device of the first embodiment and the curve R3 indicating the silicon concentration in the photoelectric conversion device of the conventional example are used for specifying the interface with the TCO depending on the silicon concentration level. .
- the curve A4 indicating the In concentration in the photoelectric conversion device of the first embodiment and the curve R4 indicating the In concentration in the photoelectric conversion device of the conventional example are for detecting the In concentration in the TCO based on the In concentration level. Is used to identify the interface with the TCO.
- Example 2 the evaluation results of Example 2 and Comparative Example 2 are shown.
- Table 1 lists values obtained by standardizing the short-circuit current density Jsc, open-circuit voltage Voc, fill factor FF, and conversion efficiency Eff of the photoelectric conversion devices listed in Example 2 and Comparative Example 2 in Comparative Example 2.
- Eff is improved by improving Voc and FF. This is because the implantation of boron ions or the like into the i-type amorphous silicon film or the n-type single crystal silicon substrate, which is the lower layer of the p-type amorphous silicon film, is suppressed and the generation of defects is suppressed. This shows the effect of suppressing carrier recombination.
- the present invention is applied to an n-type single crystal silicon substrate.
- this method and apparatus is not limited to a p-type single crystal silicon substrate, but may be a crystal such as polycrystalline silicon or silicon germanium.
- the present invention can be applied to a photoelectric conversion device using a crystalline semiconductor substrate such as a silicon based substrate.
- the photoelectric conversion device according to the present invention can be formed at a low temperature, is useful for forming a highly efficient photoelectric conversion device, and is particularly suitable for forming a thin photoelectric conversion device.
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Abstract
In this method, which is for producing a photoelectric conversion device by forming a p-n junction and includes a step for forming a semiconductor layer having a second conductivity type on an n-type monocrystalline silicon substrate (1) having a semiconductor region of a first conductivity type, the step for forming a semiconductor layer includes: a step for forming an intrinsic semiconductor layer (4ai) by means of a plasma CVD method; and a doping step for supplying a doping gas (DG) containing a dopant in a manner so that the dopant is chemisorbed by the surface of the intrinsic semiconductor layer (4ai), thus doping the intrinsic semiconductor layer (4ai) and forming a semiconductor layer of the aforementioned conductivity type.
Description
本発明は、光電変換装置の製造方法および光電変換装置に関する。
The present invention relates to a method for manufacturing a photoelectric conversion device and a photoelectric conversion device.
シリコン太陽電池の導電膜形成において、一般的にプラズマＣＶＤ（ＰＥＣＶＤ:Plasma-Enhanced Chemical Vapor Deposition）法によってドーピングガスをプラズマ中で分解するが、プラズマ発生に伴ってドーパントを含むイオンがＲＦ電場によって加速され、導電膜の下層（ｉ型半導体層、基板等）までドーパントが侵入して下層を劣化させてセル変換効率向上を妨げる。そこで、特許文献１では、基板上にテトラヘドラル非晶質カーボン層を形成した後に、ｐ－ｉ－ｎ、または、ｎ－ｉ－ｐ型半導体を堆積させて太陽電池を形成する方法が提案されている。
In the formation of conductive films for silicon solar cells, the doping gas is generally decomposed in the plasma by the plasma CVD (Plasma-Enhanced Chemical Vapor Deposition) method, but ions containing dopants are accelerated by the RF electric field as the plasma is generated. Then, the dopant penetrates to the lower layer (i-type semiconductor layer, substrate, etc.) of the conductive film and degrades the lower layer, thereby hindering cell conversion efficiency improvement. Therefore, Patent Document 1 proposes a method of forming a solar cell by forming a tetrahedral amorphous carbon layer on a substrate and then depositing a pin or nip type semiconductor. Yes.
しかしながら、上記特許文献１の技術によれば、不純物拡散の抑制のために用いるテトラヘドラル非晶質カーボン層は、ＦＣＶＡ（Filtered Cathodic Vacuum Arc)法によって形成されるため、専用の製造装置と専用の工程を要し、コスト上昇が不可避である。さらに、テトラヘドラル非晶質カーボン層をｐ－ｉ型半導体層界面に挿入するのではなく、基板とｐ－ｉ－ｎ型半導体層との界面に挿入する構造であるため、ｐ－ｉ型半導体層界面での不純物拡散を抑制出来ず、セル変換効率の向上効果が薄い。また、上記特許文献１では、ｎ－ｉ－ｐ型半導体層順に膜を形成することでｐ－ｉ型半導体層界面での不純物拡散が抑制される、との記載があるが、本発明者らが行った実験結果によると、シリコン基板上へｉ型半導体層、ｐ型半導体層の順に形成しても、ｉ型半導体層および基板への不純物拡散は抑制し得ないことを確認した。
However, according to the technique of Patent Document 1, the tetrahedral amorphous carbon layer used for suppressing impurity diffusion is formed by the FCVA (Filtered Cathodic Vacuum Arc) method. Cost is inevitable. Further, since the tetrahedral amorphous carbon layer is not inserted into the interface of the pi-type semiconductor layer, but is inserted into the interface between the substrate and the pin-type semiconductor layer, the pi-type semiconductor layer Impurity diffusion at the interface cannot be suppressed, and the effect of improving cell conversion efficiency is weak. Further, in the above-mentioned Patent Document 1, there is a description that impurity diffusion at the interface of the pi-type semiconductor layer is suppressed by forming the film in the order of the nip-type semiconductor layer. According to the experimental results conducted, it was confirmed that even if the i-type semiconductor layer and the p-type semiconductor layer were formed in this order on the silicon substrate, impurity diffusion into the i-type semiconductor layer and the substrate could not be suppressed.
本発明は、上記に鑑みてなされたもので、製造が容易でかつ、界面での不純物拡散を抑制することができ、光電変換効率の高い光電変換装置を得ることを目的とする。
The present invention has been made in view of the above, and an object of the present invention is to obtain a photoelectric conversion device that is easy to manufacture, can suppress impurity diffusion at the interface, and has high photoelectric conversion efficiency.
上述した課題を解決し、目的を達成するために、本発明は、第１導電型の半導体領域を有する基板上に第２導電型の半導体層を形成する工程を含み、ｐｎ接合を形成して、光電変換装置を製造する方法であって、前記半導体層を形成する工程が、真性半導体層を形成する工程と、前記真性半導体層の表面にドーパントが化学吸着するように、前記ドーパントを含むドーピングガスを供給し、前記真性半導体層をドーピングして、前記第２導電型の半導体層を形成するドーピング工程とを含むことを特徴とする。
In order to solve the above-described problems and achieve the object, the present invention includes a step of forming a second conductivity type semiconductor layer on a substrate having a first conductivity type semiconductor region, and forming a pn junction. A method for manufacturing a photoelectric conversion device, wherein the step of forming the semiconductor layer includes a step of forming an intrinsic semiconductor layer, and a doping containing the dopant so that the dopant is chemisorbed on the surface of the intrinsic semiconductor layer. A doping step of supplying a gas and doping the intrinsic semiconductor layer to form the semiconductor layer of the second conductivity type.
本発明によれば、特殊な装置あるいは工程を要することなく、第１導電型の半導体層の下層（ｉ型半導体層、基板等）へのドーパントの侵入、および、下層劣化の抑制が可能となるため、コストの高騰を招くことなく開放端電圧、フィルファクター、および、光電変換効率の向上をはかることができる。
According to the present invention, it is possible to suppress the penetration of the dopant into the lower layer (i-type semiconductor layer, substrate, etc.) of the first conductivity type semiconductor layer and the lower layer deterioration without requiring a special apparatus or process. Therefore, it is possible to improve the open-circuit voltage, the fill factor, and the photoelectric conversion efficiency without causing an increase in cost.
以下に、本発明にかかる光電変換装置の製造方法の実施の形態を図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。また、以下の実施の形態で用いられる光電変換装置の断面図は模式的なものであり、層の厚みと幅との関係や各層の厚みの比率などは現実のものとは異なる。
Hereinafter, an embodiment of a method for manufacturing a photoelectric conversion device according to the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. In addition, cross-sectional views of photoelectric conversion devices used in the following embodiments are schematic, and the relationship between layer thickness and width, the ratio of the thickness of each layer, and the like are different from actual ones.
実施の形態１．
図１は、本発明の実施の形態１による光電変換装置の製造方法によって形成された光電変換装置におけるｐ型半導体層（アモルファスシリコン層）形成後の断面を示す模式図である。図２－１～図２－５は、同光電変換装置の製造工程を示す工程断面図である。本実施の形態１の方法では、表面に第１導電型の半導体領域を有する基板としてのｎ型単結晶シリコン基板１表面に、ｐｎ接合を形成して光電変換装置を形成するに際し、プラズマＣＶＤ法により真性半導体層としてｉ型アモルファスシリコン層４ｉ（４ａｉ～４ｄｉ）を形成する工程と、このｉ型アモルファスシリコン層４ａｉ～４ｄｉの表面にドーパントが化学吸着するように、このドーパントとしてのボロンを含むドーピングガスであるジボランガスを供給し、ｉ型アモルファスシリコン層４ａｉ～４ｄｉをドーピングして、第２導電型の半導体層としてｐ型アモルファスシリコン層４（４ａ～４ｄ）を形成するドーピング工程とを含むことを特徴とする。これらｉ型アモルファスシリコン層４ａｉ～４ｄｉの各形成工程とこれに不純物ガスを化学吸着することによりドーピングしてｐ型化する各ドーピング工程とは、１層毎に実施される。ここで化学吸着とは、加熱されたｉ型アモルファスシリコン層などの真性半導体層の最表面へドーピングガスを接触させると、ドーピングガスが熱分解し、真性半導体層の最表面もしくは真性半導体層の内部の未結合手を持つ原子と結合して活性化ドーパントとして振舞う状態をさすものとする。Embodiment 1 FIG.
FIG. 1 is a schematic view showing a cross section after formation of a p-type semiconductor layer (amorphous silicon layer) in a photoelectric conversion device formed by the method for manufacturing a photoelectric conversion device according toEmbodiment 1 of the present invention. FIGS. 2-1 to 2-5 are process cross-sectional views illustrating the manufacturing process of the photoelectric conversion device. In the method of the first embodiment, when a pn junction is formed on the surface of an n-type single crystal silicon substrate 1 as a substrate having a first conductivity type semiconductor region on the surface, a plasma CVD method is used. Forming an i-type amorphous silicon layer 4i (4ai to 4di) as an intrinsic semiconductor layer, and doping containing boron as a dopant so that the dopant is chemisorbed on the surface of the i-type amorphous silicon layer 4ai to 4di A doping step of supplying a diborane gas as a gas and doping the i-type amorphous silicon layers 4ai to 4di to form a p-type amorphous silicon layer 4 (4a to 4d) as a second conductivity type semiconductor layer. Features. Each of the formation processes of these i-type amorphous silicon layers 4ai to 4di and each doping process of doping the impurity gas by chemical adsorption to form p-type is performed for each layer. Here, chemisorption means that when a doping gas is brought into contact with the outermost surface of an intrinsic semiconductor layer such as a heated i-type amorphous silicon layer, the doping gas is thermally decomposed, and the outermost surface of the intrinsic semiconductor layer or the inside of the intrinsic semiconductor layer. It is assumed that it is bonded to an atom having a dangling bond and behaves as an activating dopant.
図１は、本発明の実施の形態１による光電変換装置の製造方法によって形成された光電変換装置におけるｐ型半導体層（アモルファスシリコン層）形成後の断面を示す模式図である。図２－１～図２－５は、同光電変換装置の製造工程を示す工程断面図である。本実施の形態１の方法では、表面に第１導電型の半導体領域を有する基板としてのｎ型単結晶シリコン基板１表面に、ｐｎ接合を形成して光電変換装置を形成するに際し、プラズマＣＶＤ法により真性半導体層としてｉ型アモルファスシリコン層４ｉ（４ａｉ～４ｄｉ）を形成する工程と、このｉ型アモルファスシリコン層４ａｉ～４ｄｉの表面にドーパントが化学吸着するように、このドーパントとしてのボロンを含むドーピングガスであるジボランガスを供給し、ｉ型アモルファスシリコン層４ａｉ～４ｄｉをドーピングして、第２導電型の半導体層としてｐ型アモルファスシリコン層４（４ａ～４ｄ）を形成するドーピング工程とを含むことを特徴とする。これらｉ型アモルファスシリコン層４ａｉ～４ｄｉの各形成工程とこれに不純物ガスを化学吸着することによりドーピングしてｐ型化する各ドーピング工程とは、１層毎に実施される。ここで化学吸着とは、加熱されたｉ型アモルファスシリコン層などの真性半導体層の最表面へドーピングガスを接触させると、ドーピングガスが熱分解し、真性半導体層の最表面もしくは真性半導体層の内部の未結合手を持つ原子と結合して活性化ドーパントとして振舞う状態をさすものとする。
FIG. 1 is a schematic view showing a cross section after formation of a p-type semiconductor layer (amorphous silicon layer) in a photoelectric conversion device formed by the method for manufacturing a photoelectric conversion device according to
表面が所望の導電型の半導体層である基板としては、ｐ型またはｎ型の結晶系シリコン基板を用いるが、通常、スライスにより切り出されたものであるため、表面に自然酸化膜、およびスライス時のダメージなどの構造的欠陥、金属等による汚染をはらんでいることが多い。このため、まずはこのダメージ層の除去も兼ねて、ｎ型単結晶シリコン基板１を酸または加熱したアルカリ溶液中、例えば水酸化ナトリウム水溶液に浸漬して表面をエッチングすることにより、インゴットからｎ型単結晶シリコン基板１を切り出す時に発生してｎ型単結晶シリコン基板１の表面近くに存在するダメージ領域を取り除く。
As a substrate whose surface is a semiconductor layer of a desired conductivity type, a p-type or n-type crystalline silicon substrate is used, but since it is usually cut out by slicing, a natural oxide film and a slicing surface are formed on the surface. In many cases, there are structural defects such as damage of metal and contamination by metals. For this reason, the n-type single crystal silicon substrate 1 is first removed from the ingot by etching by immersing the n-type single crystal silicon substrate 1 in an acid or heated alkaline solution, for example, in an aqueous solution of sodium hydroxide. A damage region that occurs when the crystalline silicon substrate 1 is cut out and exists near the surface of the n-type single crystal silicon substrate 1 is removed.
以下ではヘテロ接合型単結晶シリコンセルの作製を想定し、ｎ型単結晶シリコン基板１を用いた場合について説明する。
In the following, the case where an n-type single crystal silicon substrate 1 is used will be described assuming the production of a heterojunction single crystal silicon cell.
ｎ型単結晶シリコン基板１の洗浄、ダメージ層エッチング後、ｎ型単結晶シリコン基板１内の不純物を除去するためにゲッタリングを行う。処理温度１０００℃程度のリンの熱拡散を行ない、この熱拡散により形成されたリンガラス層に不純物を偏析させ、リンガラス層をフッ化水素等でエッチングする。
After cleaning the n-type single crystal silicon substrate 1 and etching the damaged layer, gettering is performed to remove impurities in the n-type single crystal silicon substrate 1. Phosphorus is thermally diffused at a processing temperature of about 1000 ° C., impurities are segregated in the phosphorous glass layer formed by the thermal diffusion, and the phosphorous glass layer is etched with hydrogen fluoride or the like.
ゲッタリング後、ｎ型単結晶シリコン基板１表面での光反射損失を低減させる目的で、アルカリ溶液および添加剤を用いたウェットエッチングによりテクスチャーを形成する（図示せず）。アルカリ溶液には水酸化カリウム、水酸化ナトリウム等を、添加剤にはイソプロピルアルコール等を用いる。
After gettering, a texture is formed by wet etching using an alkaline solution and an additive (not shown) for the purpose of reducing light reflection loss on the surface of the n-type single crystal silicon substrate 1. Potassium hydroxide, sodium hydroxide or the like is used for the alkaline solution, and isopropyl alcohol or the like is used for the additive.
また、ダメージ除去と同時に、ｎ型単結晶シリコン基板１の受光面側の表面にテクスチャー構造として微小凹凸を形成してもよい。このようなテクスチャー構造をｎ型単結晶シリコン基板１の受光面側に設けることで、太陽電池セルの表面側で光の多重反射を生じさせ、光電変換装置に入射する光を効率的にｎ型単結晶シリコン基板１の内部に吸収させることができ、実効的に反射率を低減して変換効率を向上させることができる。
In addition, at the same time as the damage removal, fine irregularities may be formed as a texture structure on the surface of the n-type single crystal silicon substrate 1 on the light receiving surface side. By providing such a texture structure on the light-receiving surface side of the n-type single crystal silicon substrate 1, multiple reflection of light is caused on the surface side of the solar battery cell, and light incident on the photoelectric conversion device is efficiently converted into n-type. It can be absorbed inside the single crystal silicon substrate 1, and the reflectance can be effectively reduced and the conversion efficiency can be improved.
なお、本実施の形態はｎ型半導体層の形成に特徴を有するものであるので、テクスチャー構造の形成方法や形状については、特に制限するものではない。例えば、イソプロピルアルコールを含有させたアルカリ水溶液や主にフッ酸、硝酸の混合液からなる酸エッチングを用いる方法、部分的に開口を設けたマスク材をｎ型単結晶シリコン基板１の表面に形成して該マスク材を介したエッチングによりｎ型単結晶シリコン基板１の表面にハニカム構造や逆ピラミッド構造を得る方法、或いは反応性ガスエッチング（ＲＩＥ：Reactive Ｉon Etching）を用いた手法など、何れの手法を用いてもよい。
Note that the present embodiment is characterized by the formation of the n-type semiconductor layer, and thus the formation method and shape of the texture structure are not particularly limited. For example, an alkaline aqueous solution containing isopropyl alcohol, a method using acid etching mainly composed of a mixed solution of hydrofluoric acid and nitric acid, or a mask material partially provided with an opening is formed on the surface of the n-type single crystal silicon substrate 1. Any method such as a method of obtaining a honeycomb structure or an inverted pyramid structure on the surface of the n-type single crystal silicon substrate 1 by etching through the mask material, or a method using reactive gas etching (RIE). May be used.
テクスチャー形成後、ヘテロ接合界面となるｎ型単結晶シリコン基板１表面のパーティクル、有機物汚染、金属汚染を除去するために基板洗浄を実施する。洗浄には、いわゆるＲＣＡ洗浄や、ＳＰＭ、ＨＰＭ、ＤＨＦ洗浄、アルコール洗浄等を用いる。
After the texture is formed, the substrate is cleaned to remove particles, organic contamination, and metal contamination on the surface of the n-type single crystal silicon substrate 1 that becomes the heterojunction interface. For the cleaning, so-called RCA cleaning, SPM, HPM, DHF cleaning, alcohol cleaning, or the like is used.
基板洗浄後、ヘテロ接合、及び、ｐｎ、ｎｎ+接合を形成するために、半導体基板としてｎ型単結晶シリコン基板１を載置した製膜トレーをＣＶＤ製膜室内のＣＶＤ装置ステージに載置して、ＣＶＤ装置内に、マスフローコントローラー、および、シャワープレート電極を介してプロセスガスを供給し、ＰＥＣＶＤ法ではシャワープレート電極とＣＶＤ装置ステージとの間にＲＦ電源によって電圧を印加して触媒線ＣＶＤ法では装置内の加熱された触媒線に起因する熱によって、プロセスガスを分解し、基板表面へｉ型半導体層、および、ｐ型半導体層を形成し、基板裏面へｉ型半導体層、および、ｎ型半導体層を形成する。
After the substrate cleaning, in order to form a heterojunction and a pn, nn + junction, a film forming tray on which the n-type single crystal silicon substrate 1 is mounted as a semiconductor substrate is mounted on a CVD apparatus stage in the CVD film forming chamber. In the CVD apparatus, a process gas is supplied via a mass flow controller and a shower plate electrode. In the PECVD method, a voltage is applied between the shower plate electrode and the CVD apparatus stage by an RF power source, and the catalyst line CVD method is applied. Then, the process gas is decomposed by heat caused by the heated catalyst wire in the apparatus, an i-type semiconductor layer and a p-type semiconductor layer are formed on the substrate surface, and an i-type semiconductor layer and n are formed on the back surface of the substrate. Forming a mold type semiconductor layer;
ｎ型単結晶シリコン基板１表面へのｐｎ接合の形成方法について説明する。ｐｎ接合の形成工程は、図２－１～図２－５に工程断面図を示すとおりである。ｐｎ接合の形成工程のフローチャートは図３に示すとおりである。また、基板温度の温度プロファイルを図４に示す。ｉ型アモルファスシリコン層２の形成工程Ｓ１、ｉ型アモルファスシリコン層４ｉの形成工程Ｓ2、ｐ型化のための化学吸着工程Ｓ３における基板温度はすべて１６５℃に設定した。実際には、ｉ型アモルファスシリコン層４ｉの形成工程Ｓ2、ｐ型化のための化学吸着工程Ｓ3を連続して４回繰り返すが、ここでは最初の１回分のみを示し、他は省略している。
A method of forming a pn junction on the surface of n-type single crystal silicon substrate 1 will be described. The process of forming the pn junction is as shown in the process cross-sectional views in FIGS. 2-1 to 2-5. A flowchart of the process of forming the pn junction is as shown in FIG. FIG. 4 shows the temperature profile of the substrate temperature. The substrate temperature in the formation step S 1 of the i-type amorphous silicon layer 2 , the formation step S 2 of the i-type amorphous silicon layer 4 i, and the chemical adsorption step S 3 for p-type formation were all set to 165 ° C. Actually, the formation process S 2 of the i-type amorphous silicon layer 4 i and the chemical adsorption process S 3 for p-type conversion are repeated four times in succession, but only the first one is shown here and the others are omitted. ing.
まず、ｎ型単結晶シリコン基板１をプラズマＣＶＤ（ＰＥＣＶＤ）装置に搬送する（ステップＳ１０１）。そして、図２－１に示すように、ｎ型単結晶シリコン基板１表面にｉ型アモルファスシリコン層２を形成する。形成に際しては、一般的なプラズマＣＶＤ法と同様、シャワープレート電極から流れ出すシランガスや水素ガスを、電極間に電圧を印加して分解し、ｎ型単結晶シリコン基板１上へｉ型アモルファスシリコン層２を堆積させて行う。
First, the n-type single crystal silicon substrate 1 is transferred to a plasma CVD (PECVD) apparatus (step S101). Then, as shown in FIG. 2A, an i-type amorphous silicon layer 2 is formed on the surface of the n-type single crystal silicon substrate 1. At the time of formation, similarly to a general plasma CVD method, silane gas or hydrogen gas flowing out from the shower plate electrode is decomposed by applying a voltage between the electrodes to form an i-type amorphous silicon layer 2 on the n-type single crystal silicon substrate 1. This is done by depositing.
続いてｐ型半導体層としてｐ型アモルファスシリコン層４を形成するが、まず、プラズマＣＶＤ法により、ｉ型アモルファスシリコン層４ａｉを形成する（図２－２：ステップＳ１０２）。Ｐはガスプラズマである。この後このｉ型アモルファスシリコン層４ａｉにドーピングガスＤＧを供給して、ドーパントを化学吸着させｉ型アモルファスシリコン層４ａｉをｐ型アモルファスシリコン層４ａとする（図２－３：ステップＳ１０３）。そしてドーピングガスＤＧの供給を停止し、製膜室を真空ポンプにより真空排気する（ステップＳ１０４）。この工程は膜厚２ｎｍのｉ型アモルファスシリコン層４ａｉ～４ｄｉをガスプラズマＰ中で順次１層ずつ形成する。そして、１層形成する度にドーピングガスＤＧを供給し、ドーパントを化学吸着させる工程（図２－３、図２－５など４回）を繰り返す。このようにしてｐ型アモルファスシリコン層４（４ａ、４ｂ、４ｃ、４ｄ）が形成され、光電変換装置のｐｎ接合が形成される。ここでは、シャワープレート電極から流れ出すシランガス、水素ガスを電極間に電圧を印加して分解し、ｎ型単結晶シリコン基板１上へｉ型半導体膜としてｉ型アモルファスシリコン層を堆積させた後、シランガス、水素ガスの供給とＲＦパワーの印加を停止し、ドーピングガスＤＧを装置内へ供給し、ｉ型アモルファスシリコン層の表面へ化学吸着させる。これら一連の工程は同一チャンバー内で基板温度を一定にし、ドーピングガスＤＧの切り替えによって実施することができる。
Subsequently, a p-type amorphous silicon layer 4 is formed as a p-type semiconductor layer. First, an i-type amorphous silicon layer 4ai is formed by plasma CVD (FIG. 2-2: Step S102). P is a gas plasma. Thereafter, a doping gas DG is supplied to the i-type amorphous silicon layer 4ai to chemisorb the dopant, thereby making the i-type amorphous silicon layer 4ai a p-type amorphous silicon layer 4a (FIG. 2-3: Step S103). Then, the supply of the doping gas DG is stopped, and the film forming chamber is evacuated by a vacuum pump (step S104). In this step, i-type amorphous silicon layers 4ai to 4di having a thickness of 2 nm are sequentially formed one by one in the gas plasma P. Then, each time one layer is formed, the doping gas DG is supplied and the process of chemisorbing the dopant (four times such as FIGS. 2-3 and 2-5) is repeated. In this way, the p-type amorphous silicon layer 4 (4a, 4b, 4c, 4d) is formed, and a pn junction of the photoelectric conversion device is formed. Here, silane gas and hydrogen gas flowing out from the shower plate electrode are decomposed by applying a voltage between the electrodes, and after depositing an i-type amorphous silicon layer as an i-type semiconductor film on the n-type single crystal silicon substrate 1, silane gas Then, supply of hydrogen gas and application of RF power are stopped, doping gas DG is supplied into the apparatus, and is chemically adsorbed on the surface of the i-type amorphous silicon layer. These series of steps can be performed by switching the doping gas DG while keeping the substrate temperature constant in the same chamber.
ｉ型半導体膜（アモルファスシリコン層）の膜厚は２ｎｍ以下、０．１ｎｍ以上、成膜時の膜厚のずれを考慮すると、好ましくは１ｎｍ以下０．５ｎｍ以上とすることが望ましい。厚みを２ｎｍ以下として図３に示したプロセスフローでｐ型アモルファスシリコン層４を形成することで、ｐ型半導体層の膜厚方向のドーパント濃度ムラが解消され、ヘテロセルのｐ型膜として良好な電気特性が得られる。一例として図７に、ｐ型化に寄与するｉ型アモルファスシリコン膜の一回の製膜あたりの厚みと電気特性との関係を表す。ｐ型化に寄与するｉ型アモルファスシリコン膜の一回の製膜あたりの厚みが２ｎｍ以下で暗導電率が光電変換装置のｐ層として機能するレベルに達し、その厚みを減らすに連れ、電気特性は向上する。なお、ｐ型アモルファスシリコン膜の仕上がり厚みは１０ｎｍである。また、０．１ｎｍ以上とすることで、下層へのドーパントの拡散が抑制できる。
The film thickness of the i-type semiconductor film (amorphous silicon layer) is 2 nm or less, 0.1 nm or more, and in consideration of the film thickness deviation during film formation, it is preferably 1 nm or less and 0.5 nm or more. By forming the p-type amorphous silicon layer 4 by the process flow shown in FIG. 3 with a thickness of 2 nm or less, the dopant concentration unevenness in the film thickness direction of the p-type semiconductor layer is eliminated, and a good electrical property as a p-type film of the heterocell is obtained. Characteristics are obtained. As an example, FIG. 7 shows the relationship between the thickness of each i-type amorphous silicon film contributing to p-type formation and the electrical characteristics. As the thickness of each i-type amorphous silicon film that contributes to p-type formation is 2 nm or less and the dark conductivity reaches a level that functions as a p-layer of a photoelectric conversion device, the electrical characteristics decrease as the thickness decreases. Will improve. The finished thickness of the p-type amorphous silicon film is 10 nm. Moreover, by setting it to 0.1 nm or more, diffusion of the dopant to the lower layer can be suppressed.
ドーピングガスとしては、ジボランまたはトリメチルボロンを用いることが望ましい。これらのガスはいずれも比較的低温下で分解可能である。好ましくは、１００～２００℃程度でも熱分解反応が良好なジボランを用いる方が良い。また、ジボランまたはトリメチルボロンを用いてドーピングガスの化学吸着をさせる場合、ジボランガスまたはトリメチルボロンガス自体のドーパント濃度、供給時間、処理時の基板加熱温度、供給時のチャンバ内圧力を調整することで、一回当りのドーピングガス供給によってなるｐ型化に寄与する真性半導体膜表面のボロン密度を１×１０14／ｃｍ2以下とすることができ、ボロン同士の重合反応による電気抵抗の増加を抑制することができる。
It is desirable to use diborane or trimethylboron as the doping gas. All of these gases can be decomposed at relatively low temperatures. Preferably, diborane having a good thermal decomposition reaction even at about 100 to 200 ° C. is used. Also, when chemisorption of doping gas using diborane or trimethylboron, by adjusting the dopant concentration of diborane gas or trimethylboron gas itself, the supply time, the substrate heating temperature during processing, and the pressure in the chamber during supply, The boron density on the surface of the intrinsic semiconductor film that contributes to p-type conversion by supplying doping gas per time can be reduced to 1 × 10 14 / cm 2 or less, and an increase in electrical resistance due to a polymerization reaction between boron is suppressed. be able to.
上記の製膜パラメータを変化させることでボロン同士の重合反応が起こるが、これは、ｉ型半導体膜の最表面に対するドーピングガス供給量と密接な関係があると考えられる。ドーパント濃度、供給時間、チャンバ内圧力が過度な状態にあるとき、すなわち、ドーパントの供給量が過大であると、ｉ型半導体膜の最表面に存在する未結合手を持つシリコンと結合した後、その表面において更に、ボロン同士の重合反応が始まると考えられるからである。しかし、ｐ型化に寄与する真性半導体膜表面のボロン密度が１×１０9／ｃｍ2以上でなければ、ｐ型化が不十分となり、光電変換装置のｐ層として機能しないため、ボロン密度が上記範囲内となるように、ドーパントガスの供給量を調整するよう、プロセスを制御すればよい。
The polymerization reaction of boron occurs by changing the film forming parameters described above, and this is considered to be closely related to the doping gas supply amount to the outermost surface of the i-type semiconductor film. When the dopant concentration, supply time, and pressure in the chamber are in an excessive state, that is, if the supply amount of the dopant is excessive, after bonding with silicon having dangling bonds existing on the outermost surface of the i-type semiconductor film, This is because it is considered that the polymerization reaction between the boron further starts on the surface. However, if the boron density on the surface of the intrinsic semiconductor film contributing to the p-type conversion is not 1 × 10 9 / cm 2 or more, the p-type conversion becomes insufficient and the boron density does not function as the p layer of the photoelectric conversion device. What is necessary is just to control a process so that the supply amount of dopant gas may be adjusted so that it may become in the said range.
ここで、化学吸着工程における基板加熱温度は、ｐ型化しようとするｉ型半導体膜の製膜温度である１００～２００℃とすると、プロセスフローを通して温度を変更することなく、ガスの切り替えのみで、簡易に実施できる上、ドーピングガスの熱分解も十分可能となる。基板温度を一定にすることで、温度制御に要する時間を大幅に短縮することができ、基本的に、全製膜工程を同一温度でガスの切り替えのみで実現可能となる。また、上記製膜温度を５０℃未満とすると、ドーピングガスの熱分解効率が低下し、ｐ型化に寄与する真性半導体膜のボロン密度が著しく低下し、光電変換装置のｐ層として機能しない。一方、上記製膜温度を２５０℃よりも高温にすると、下地の層または基板最表面での変質、例えば水素結合の乖離、すなわち欠陥が生じ、セル変換効率を著しく低下させる。以上の理由から、上記製膜温度を５０℃以上、２５０℃以下となるようにプロセスを制御すればよい。
Here, when the substrate heating temperature in the chemical adsorption process is set to 100 to 200 ° C., which is the film forming temperature of the i-type semiconductor film to be made p-type, only the gas is switched without changing the temperature throughout the process flow. In addition, the doping gas can be thermally decomposed sufficiently. By making the substrate temperature constant, the time required for temperature control can be greatly shortened, and basically, the entire film forming process can be realized only by switching gases at the same temperature. Further, when the film forming temperature is less than 50 ° C., the thermal decomposition efficiency of the doping gas is lowered, the boron density of the intrinsic semiconductor film contributing to p-type formation is significantly lowered, and it does not function as the p layer of the photoelectric conversion device. On the other hand, when the film forming temperature is higher than 250 ° C., alteration of the underlying layer or the outermost surface of the substrate, for example, dissociation of hydrogen bonds, that is, defects occur, and the cell conversion efficiency is remarkably lowered. For the above reasons, the process may be controlled so that the film forming temperature is 50 ° C. or higher and 250 ° C. or lower.
ｐ型化に寄与する真性半導体膜でボロンを効率的に活性化させるため、ここで言うｐ型化に寄与する真性半導体膜は、水素化真性半導体とすべきである。ここで、水素化真性半導体は、水素含有量が２at％以上、一般的には１０～２０at％程度であり、水素化していない真性半導体膜は、水素含有量が１at％以下程度と非常に少ない。この水素含有量は膜中の水素結合量と比例するが、本実施の形態のプロセスを適用すると、その水素結合部分においてボロンが置換する、もしくは、未結合手にボロンが結合を形成する。そのため、水素化真性半導体は水素化していない真性半導体に比べて水素含有量も未結合手も多く、本発明のプロセスを適用したときにボロンの活性度が大きい。ただし、水素含有量が多くなりすぎると、電気伝導に関与する電荷の易動度が低下して光電変換装置のｐ層として機能しなくなる。上記事由を考慮して、水素化真性半導体の膜中水素密度としては、２at％以上、３０at％以下とすればよい。なお、以上のことから、ｐ型化に寄与する真性半導体膜の形成方法としては、比較的低温下で成膜可能なＰＥＣＶＤ法、触媒線ＣＶＤ法が望ましく、高温工程を必要とする、熱ＣＶＤ法は不適である。
In order to efficiently activate boron with an intrinsic semiconductor film that contributes to p-type conversion, the intrinsic semiconductor film that contributes to p-type conversion should be a hydrogenated intrinsic semiconductor. Here, a hydrogenated intrinsic semiconductor has a hydrogen content of 2 at% or more, generally about 10 to 20 at%, and an unhydrogenated intrinsic semiconductor film has a very low hydrogen content of about 1 at% or less. . Although this hydrogen content is proportional to the amount of hydrogen bonds in the film, when the process of this embodiment is applied, boron is substituted at the hydrogen bond portion, or boron forms a bond in an unbonded hand. Therefore, a hydrogenated intrinsic semiconductor has more hydrogen content and dangling bonds than an unhydrogenated intrinsic semiconductor, and boron activity is high when the process of the present invention is applied. However, when the hydrogen content is excessively high, the mobility of electric charges involved in electric conduction is reduced and the photoelectric conversion device does not function as a p-layer. Considering the above reasons, the hydrogen density in the hydrogenated intrinsic semiconductor film may be 2 at% or more and 30 at% or less. From the above, as a method for forming an intrinsic semiconductor film that contributes to p-type conversion, a PECVD method or a catalytic wire CVD method that can be formed at a relatively low temperature is desirable, and a thermal CVD that requires a high-temperature process. The law is inappropriate.
なお、本実施の形態の方法でｎ型単結晶シリコン基板１上に形成したｐ型アモルファスシリコン層４を用いてヘテロ接合型光電変換セルを形成した基板１０を作製した場合、ＢＦ-ＳＴＥＭおよびＨＡＡＤＦ-ＳＴＥＭ評価により、ｐ型半導体層の下層の構造乱れ、および、膜の緻密性を観察、および、３次元アトムプローブ法によるテクスチャー構造の一斜面上におけるボロン元素のデプスプロファイリングをすることで実施の有無を判別できる。
Note that when the substrate 10 in which the heterojunction photoelectric conversion cell is formed using the p-type amorphous silicon layer 4 formed on the n-type single crystal silicon substrate 1 by the method of the present embodiment, BF-STEM and HAADF -STEM evaluation allows observation of structural disorder in the lower layer of the p-type semiconductor layer and denseness of the film, and depth profiling of boron element on one slope of the texture structure by the three-dimensional atom probe method. The presence or absence can be determined.
このようにしてヘテロ接合、及び、ｐｎ、ｎｎ+接合を形成した後、スパッタ法や蒸着法等により、ヘテロ接合型光電変換セルを形成した基板１０の表裏面に透光性導電膜（ＴＣＯ）として、酸化インジウム錫や酸化インジウムを形成する。ここでは、デポアップ方式や、マスクを用いた製膜方法を用い、基板側面に導電膜が形成されないようにし、ｐ層とｎ層との間の絶縁分離をはかる。
After forming the heterojunction and the pn, nn + junction in this way, a translucent conductive film (TCO) is formed on the front and back surfaces of the substrate 10 on which the heterojunction photoelectric conversion cell is formed by sputtering or vapor deposition. Indium tin oxide and indium oxide are formed. Here, a deposition method or a film forming method using a mask is used so that a conductive film is not formed on the side surface of the substrate, and insulation is separated between the p layer and the n layer.
そして最後に、集電電極を形成する。表面の集電電極８として、基板１０の表面１０Ｓに表面透光性導電膜５上にスパッタ法や蒸着法あるいはスクリーン印刷法等によりアルミニウムや銀等のパターンを形成する。また、裏面の集電電極９として、スパッタ法や蒸着法あるいは印刷法等により、裏面透光性導電膜６上にアルミニウムや銀等を形成する。このようにして図５に示す光電変換装置１００が形成される。７は裏面反射膜である。この裏面反射膜７は基板１０の裏面１０Ｒに設けられ、ｎ型単結晶シリコン基板１の裏面１０Ｒに到達した光を反射する。
Finally, the current collecting electrode is formed. As the current collecting electrode 8 on the surface, a pattern of aluminum, silver, or the like is formed on the surface 10S of the substrate 10 on the surface transparent conductive film 5 by sputtering, vapor deposition, screen printing, or the like. Further, as the current collecting electrode 9 on the back surface, aluminum, silver, or the like is formed on the back surface transparent conductive film 6 by sputtering, vapor deposition, printing, or the like. In this way, the photoelectric conversion device 100 shown in FIG. 5 is formed. Reference numeral 7 denotes a back surface reflecting film. The back surface reflection film 7 is provided on the back surface 10R of the substrate 10 and reflects the light that has reached the back surface 10R of the n-type single crystal silicon substrate 1.
具体的には、ｐ型アモルファスシリコン層４上に電極ペーストである銀ペーストをスクリーン印刷し、乾燥させる。一方裏面側にも、電極ペーストであるアルミニウムペーストをスクリーン印刷し、例えば２００℃程度で乾燥させる当該印刷・乾燥処理を施す。
Specifically, a silver paste as an electrode paste is screen printed on the p-type amorphous silicon layer 4 and dried. On the other hand, on the back side, an aluminum paste as an electrode paste is screen-printed and subjected to the printing / drying process of drying at about 200 ° C., for example.
なお、透光性導電膜としては、酸化インジウム錫（ＩＴＯ：Ｉndium Tin Oxide）の他、酸化亜鉛（ＺｎＯ）、酸化錫（ＳｎＯ２）および酸化ジルコニウム（ＺｒＯ２）等の結晶性金属酸化物を主成分とする透光性の導電性酸化膜や、これらの透光性の導電性酸化膜にアルミニウム（Ａｌ）を添加した膜等の透光性の膜によって構成される。また、透光性電極層は、ドーパントとしてアルミニウム（Ａｌ）、ガリウム（Ｇａ）、インジウム（Ｉｎ）、ホウ素（Ｂ）、イットリウム（Ｙ）、シリコン（Ｓｉ）、ジルコニウム（Ｚｒ）、チタン（Ｔｉ）から選択した少なくとも１種類以上の元素を用いたＺｎＯ膜、ＩＴＯ膜、ＳｎＯ２膜、またはこれらを積層して形成した透光性導電膜であってもよく、透光性を有する導電膜であればよい。
As the light-transmitting conductive film, in addition to indium tin oxide (ITO), crystalline metal oxides such as zinc oxide (ZnO), tin oxide (SnO 2 ), and zirconium oxide (ZrO 2 ) are used. The light-transmitting conductive oxide film as a main component and a light-transmitting film such as a film obtained by adding aluminum (Al) to these light-transmitting conductive oxide films are used. Further, the light-transmitting electrode layer has aluminum (Al), gallium (Ga), indium (In), boron (B), yttrium (Y), silicon (Si), zirconium (Zr), and titanium (Ti) as dopants. A ZnO film using at least one element selected from the above, an ITO film, a SnO 2 film, a light-transmitting conductive film formed by stacking these, or a light-transmitting conductive film may be used. That's fine.
以上説明してきたように、本実施の形態の光電変換装置によれば、下層（ｉ型半導体層、基板等）へのドーパントの侵入、および、下層劣化の抑制が可能となるため、コストの高騰を招くことなく開放端電圧、フィルファクター、および、光電変換効率の向上をはかることができる。
As described above, according to the photoelectric conversion device of this embodiment, the dopant can enter the lower layer (i-type semiconductor layer, substrate, etc.) and the lower layer deterioration can be suppressed, so that the cost increases. The open-circuit voltage, fill factor, and photoelectric conversion efficiency can be improved without incurring.
本実施の形態において、ｉ型半導体膜をシリコンベースの材料とする場合、アモルファス層、あるいは結晶系薄膜のいずれをも選択することができる。アモルファス層を用いた場合にはパッシベーション特性を強化することができる。一方、結晶系薄膜を用いた場合には光透過性を強化することができる。
In this embodiment, when the i-type semiconductor film is a silicon-based material, either an amorphous layer or a crystalline thin film can be selected. When an amorphous layer is used, the passivation characteristics can be enhanced. On the other hand, when a crystalline thin film is used, light transmittance can be enhanced.
また、このｉ型半導体膜の製膜温度は、アモルファスシリコン膜、または、微結晶シリコン膜であれば、一般によく知られるように、１００～２００℃程度とすることで膜中水素量を低減させる、または、結晶性を高めることができ、良質なシリコン膜が得られるため、この範囲で製膜するのが望ましい。製膜温度が１００℃以下の低温となると、欠陥が多くなり、その結果、膜中水素量が増大する。いいかえると、製膜温度が低いとアモルファスシリコン膜中の結合ネットワーク中に水素が過剰となり、疎な膜、即ち、欠陥を多く含む膜が形成される。
In addition, the film forming temperature of the i-type semiconductor film is about 100 to 200 ° C., as is generally known, in the case of an amorphous silicon film or a microcrystalline silicon film, thereby reducing the amount of hydrogen in the film. Alternatively, the crystallinity can be improved, and a high-quality silicon film can be obtained. Therefore, it is desirable to form the film within this range. When the film forming temperature is a low temperature of 100 ° C. or lower, defects increase and as a result, the amount of hydrogen in the film increases. In other words, when the film forming temperature is low, hydrogen becomes excessive in the bonding network in the amorphous silicon film, and a sparse film, that is, a film containing many defects is formed.
さらにまた、製膜方法としては、プラズマＣＶＤ法が望ましいが、プラズマＣＶＤ法に限定されることなく、触媒線ＣＶＤ法、フォトＣＶＤ法、スパッタ法、蒸着法、液体塗布法など、適宜変更可能である。
＜実施例１＞ Further, the plasma CVD method is desirable as the film forming method, but the method is not limited to the plasma CVD method, and can be changed as appropriate, such as a catalytic wire CVD method, a photo CVD method, a sputtering method, a vapor deposition method, and a liquid coating method. is there.
<Example 1>
＜実施例１＞ Further, the plasma CVD method is desirable as the film forming method, but the method is not limited to the plasma CVD method, and can be changed as appropriate, such as a catalytic wire CVD method, a photo CVD method, a sputtering method, a vapor deposition method, and a liquid coating method. is there.
<Example 1>
次に同光電変換装置の実施例について説明する。ミラー研磨を施したｎ型単結晶シリコン基板１を用いて、ミラー面へ下記の条件でｉ型アモルファスシリコン層、ｐ型アモルファスシリコン層の順に堆積させて、非製膜面からＳＩＭＳ評価を行った。その結果を図６に示す。Ａ１は本実施の形態１の光電変換装置におけるボロンＢ濃度を示す曲線である。Ｒ１は従来例の光電変換装置におけるボロンＢ濃度を示す曲線である。Ａ２は本実施の形態１の光電変換装置における水素の二次イオン強度を示す曲線である。Ｒ２は従来例の光電変換装置における水素の二次イオン強度を示す曲線である。Ａ３は本実施の形態１の光電変換装置におけるシリコン濃度を示す曲線である。Ｒ３は従来例の光電変換装置におけるシリコン濃度を示す曲線である。Ａ４は本実施の形態１の光電変換装置におけるインジウム濃度を示す曲線である。Ｒ４は従来例の光電変換装置におけるインジウム濃度を示す曲線である。
Next, an example of the photoelectric conversion device will be described. Using the n-type single crystal silicon substrate 1 subjected to mirror polishing, the i-type amorphous silicon layer and the p-type amorphous silicon layer were sequentially deposited on the mirror surface under the following conditions, and SIMS evaluation was performed from the non-film-formed surface. . The result is shown in FIG. A1 is a curve showing the boron B concentration in the photoelectric conversion device of the first embodiment. R1 is a curve showing the boron B concentration in the conventional photoelectric conversion device. A2 is a curve showing the secondary ion intensity of hydrogen in the photoelectric conversion device of the first embodiment. R2 is a curve showing the secondary ion intensity of hydrogen in the conventional photoelectric conversion device. A3 is a curve showing the silicon concentration in the photoelectric conversion device of the first embodiment. R3 is a curve showing the silicon concentration in the conventional photoelectric conversion device. A4 is a curve showing the indium concentration in the photoelectric conversion device of the first embodiment. R4 is a curve showing the indium concentration in the conventional photoelectric conversion device.
ｉ型アモルファスシリコン層の形成条件は、ＲＦパワー密度を３２ｍＷ/ｃｍ2、製膜温度を１６５℃、製膜圧力を１５０Ｐａ、電極間距離を１５ｍｍ、シランガス流量を１０ｓｃｃｍ、水素ガス流量を１００ｓｃｃｍとした。
The formation conditions of the i-type amorphous silicon layer were as follows: RF power density was 32 mW / cm 2 , film forming temperature was 165 ° C., film forming pressure was 150 Pa, distance between electrodes was 15 mm, silane gas flow rate was 10 sccm, and hydrogen gas flow rate was 100 sccm. .
ｐ型アモルファスシリコン層の形成条件は、ｉ型アモルファスシリコン膜の形成工程と、ジボランガスを化学吸着させるｐ型化工程とに分けて説明する。まず、ｉ型アモルファスシリコン膜の形成条件は、ＲＦパワー密度を３２ｍＷ/ｃｍ2、製膜温度を１６５℃、製膜圧力を３００Ｐａ、電極間距離を１５ｍｍ、シランガス流量を１０ｓｃｃｍ、水素ガス流量を１００ｓｃｃｍとした。次に、ジボランガスを化学吸着させるｐ型化条件は、基板温度を１６５℃、プロセス圧力を１５０Ｐａ、電極間距離を１５ｍｍ、ジボランガス流量を０．３ｓｃｃｍ、キャリアガスの役割を担う水素ガスの流量を５０ｓｃｃｍとした。
＜実施例２＞ The conditions for forming the p-type amorphous silicon layer will be described separately for the process for forming the i-type amorphous silicon film and the process for p-type formation in which diborane gas is chemically adsorbed. First, the formation conditions of the i-type amorphous silicon film are as follows: RF power density is 32 mW / cm 2 , film forming temperature is 165 ° C., film forming pressure is 300 Pa, distance between electrodes is 15 mm, silane gas flow rate is 10 sccm, hydrogen gas flow rate is 100 sccm. It was. Next, p-type conditions for chemical adsorption of diborane gas are as follows: substrate temperature is 165 ° C., process pressure is 150 Pa, distance between electrodes is 15 mm, diborane gas flow rate is 0.3 sccm, and the flow rate of hydrogen gas that plays the role of carrier gas is 50 sccm. It was.
<Example 2>
＜実施例２＞ The conditions for forming the p-type amorphous silicon layer will be described separately for the process for forming the i-type amorphous silicon film and the process for p-type formation in which diborane gas is chemically adsorbed. First, the formation conditions of the i-type amorphous silicon film are as follows: RF power density is 32 mW / cm 2 , film forming temperature is 165 ° C., film forming pressure is 300 Pa, distance between electrodes is 15 mm, silane gas flow rate is 10 sccm, hydrogen gas flow rate is 100 sccm. It was. Next, p-type conditions for chemical adsorption of diborane gas are as follows: substrate temperature is 165 ° C., process pressure is 150 Pa, distance between electrodes is 15 mm, diborane gas flow rate is 0.3 sccm, and the flow rate of hydrogen gas that plays the role of carrier gas is 50 sccm. It was.
<Example 2>
また、上記実施例１のｐｎ接合の形成された、ｎ型単結晶シリコン基板１を用い、結晶シリコンとアモルファスシリコンのヘテロ接合を有する光電変換装置１００を、図５に示すように、ｐ型アモルファスシリコン層以外は実施の形態１に記載の方法と同様に形成する。ここでは、表面透光性導電膜５及び裏面透光性導電膜６として、酸化インジウム錫層を形成し、表面及び裏面の集電電極８、９として、銀層およびアルミニウム層を形成する。そしてさらに基板１０の裏面１０Ｒには裏面反射膜７を形成した。
Further, as shown in FIG. 5, a photoelectric conversion device 100 having a heterojunction of crystalline silicon and amorphous silicon using an n-type single crystal silicon substrate 1 having a pn junction of Example 1 is used. The layers other than the silicon layer are formed in the same manner as the method described in Embodiment Mode 1. Here, an indium tin oxide layer is formed as the front surface light-transmitting conductive film 5 and the back surface light-transmitting conductive film 6, and a silver layer and an aluminum layer are formed as the current collecting electrodes 8 and 9 on the front surface and the back surface. Further, a back surface reflection film 7 was formed on the back surface 10R of the substrate 10.
このようにして形成された光電変換装置に対し、電気特性を評価した。
＜比較例１＞ The electrical characteristics of the photoelectric conversion device thus formed were evaluated.
<Comparative Example 1>
＜比較例１＞ The electrical characteristics of the photoelectric conversion device thus formed were evaluated.
<Comparative Example 1>
ｐ型アモルファスシリコン層の形成条件以外は、実施例１と同様にサンプルを作製し、同様の評価を実施した。ｐ型アモルファスシリコン層の形成条件は、ＲＦパワー密度を３２ｍＷ/ｃｍ2、製膜温度を１６５℃、圧力を１５０Ｐａ、電極間距離を１５ｍｍ、シランガス流量を１０ｓｃｃｍ、水素ガス流量を１００ｓｃｃｍ、ジボランガス流量を０．１ｓｃｃｍとした。
＜比較例２＞ Except for the conditions for forming the p-type amorphous silicon layer, a sample was prepared in the same manner as in Example 1, and the same evaluation was performed. The formation conditions of the p-type amorphous silicon layer are as follows: RF power density is 32 mW / cm 2 , film forming temperature is 165 ° C., pressure is 150 Pa, distance between electrodes is 15 mm, silane gas flow rate is 10 sccm, hydrogen gas flow rate is 100 sccm, diborane gas flow rate is 0.1 sccm.
<Comparative example 2>
＜比較例２＞ Except for the conditions for forming the p-type amorphous silicon layer, a sample was prepared in the same manner as in Example 1, and the same evaluation was performed. The formation conditions of the p-type amorphous silicon layer are as follows: RF power density is 32 mW / cm 2 , film forming temperature is 165 ° C., pressure is 150 Pa, distance between electrodes is 15 mm, silane gas flow rate is 10 sccm, hydrogen gas flow rate is 100 sccm, diborane gas flow rate is 0.1 sccm.
<Comparative example 2>
ｐ型アモルファスシリコン層の形成条件以外は、実施例２と同様にして光電変換装置を作製し、同様に電気特性を評価した。なお、ｐ型アモルファスシリコン層の形成条件は、比較例１と同様とした。
A photoelectric conversion device was produced in the same manner as in Example 2 except for the conditions for forming the p-type amorphous silicon layer, and the electrical characteristics were similarly evaluated. The p-type amorphous silicon layer was formed under the same conditions as in Comparative Example 1.
まずは、実施例１と比較例１の評価結果を示す。図６における本実施の形態１の光電変換装置におけるボロンＢ濃度を示す曲線Ａ１と同比較例の曲線Ｒ１との比較から、従来のｐ型アモルファスシリコン層の形成方法である比較例では、ｉ型アモルファスシリコン層へのボロンの拡散が実施例に比べて深く、拡散量も多いことが明確である。また、ｐ型アモルファスシリコン層（半導体層）の下層に侵入する不純物量が侵入長１ｎｍ以内でｐ型アモルファスシリコン層中の不純物量の１／１０以下となっている。ここで本実施の形態１の光電変換装置における水素の二次イオン強度を示す曲線Ａ２および、同従来例の光電変換装置における水素の二次イオン強度を示す曲線Ｒ２とは、水素イオン濃度レベルにより、アモルファスシリコン層の特定に用いられる。また本実施の形態１の光電変換装置におけるシリコン濃度を示す曲線Ａ３および、同従来例の光電変換装置におけるシリコン濃度を示す曲線Ｒ３とは、シリコン濃度レベルにより、ＴＣＯとの界面の特定に用いられる。また本実施の形態１の光電変換装置におけるＩｎ濃度を示す曲線Ａ４および、同従来例の光電変換装置におけるＩｎ濃度を示す曲線Ｒ４とは、Ｉｎ濃度レベルにより、ＴＣＯ中のＩｎ濃度を検出することによりＴＣＯとの界面の特定に用いられる。
First, the evaluation results of Example 1 and Comparative Example 1 are shown. From the comparison between the curve A1 indicating the boron B concentration in the photoelectric conversion device of the first embodiment in FIG. 6 and the curve R1 of the comparative example, in the comparative example which is a conventional method for forming the p-type amorphous silicon layer, the i-type is shown. It is clear that the diffusion of boron into the amorphous silicon layer is deeper than the embodiment and the amount of diffusion is large. Further, the amount of impurities entering the lower layer of the p-type amorphous silicon layer (semiconductor layer) is 1/10 or less of the amount of impurities in the p-type amorphous silicon layer within the penetration length of 1 nm. Here, the curve A2 showing the secondary ion intensity of hydrogen in the photoelectric conversion device of the first embodiment and the curve R2 showing the secondary ion intensity of hydrogen in the photoelectric conversion device of the conventional example are based on the hydrogen ion concentration level. Used to identify the amorphous silicon layer. The curve A3 indicating the silicon concentration in the photoelectric conversion device of the first embodiment and the curve R3 indicating the silicon concentration in the photoelectric conversion device of the conventional example are used for specifying the interface with the TCO depending on the silicon concentration level. . The curve A4 indicating the In concentration in the photoelectric conversion device of the first embodiment and the curve R4 indicating the In concentration in the photoelectric conversion device of the conventional example are for detecting the In concentration in the TCO based on the In concentration level. Is used to identify the interface with the TCO.
次に、実施例２と比較例２の評価結果を示す。表１には実施例２と比較例２で挙げた光電変換装置の短絡電流密度Ｊｓｃ、開放端電圧Ｖｏｃ、フィルファクターＦＦ、変換効率Ｅｆｆを、比較例２で規格化した値を記載している。ここで、実施例２では、Ｖｏｃ、および、ＦＦが向上していることによってＥｆｆが向上している。これは、ｐ型アモルファスシリコン膜の下層にあたる、ｉ型アモルファスシリコン膜、ｎ型単結晶シリコン基板へのボロンイオンなどの注入が抑制され、欠陥の生成が抑制されたことにより、その部分での少数キャリア再結合が抑制された効果を示すものである。
Next, the evaluation results of Example 2 and Comparative Example 2 are shown. Table 1 lists values obtained by standardizing the short-circuit current density Jsc, open-circuit voltage Voc, fill factor FF, and conversion efficiency Eff of the photoelectric conversion devices listed in Example 2 and Comparative Example 2 in Comparative Example 2. . Here, in Example 2, Eff is improved by improving Voc and FF. This is because the implantation of boron ions or the like into the i-type amorphous silicon film or the n-type single crystal silicon substrate, which is the lower layer of the p-type amorphous silicon film, is suppressed and the generation of defects is suppressed. This shows the effect of suppressing carrier recombination.
なお、前記実施の形態では、ｎ型単結晶シリコン基板に適用した場合について説明したが、この方法及び装置は、ｐ型単結晶シリコン基板はいうまでもなく、多結晶シリコン、シリコンゲルマニウムなど、結晶系シリコン基板をはじめとする結晶系半導体基板を用いた光電変換装置に適用可能である。
In the above-described embodiment, the case where the present invention is applied to an n-type single crystal silicon substrate has been described. However, this method and apparatus is not limited to a p-type single crystal silicon substrate, but may be a crystal such as polycrystalline silicon or silicon germanium. The present invention can be applied to a photoelectric conversion device using a crystalline semiconductor substrate such as a silicon based substrate.
また、前記実施の形態では、第２導電型の半導体層としてアモルファスシリコン層に適用した場合について説明したが、アモルファスシリコン、微結晶シリコンあるいはアモルファスシリコン合金、微結晶シリコン合金などのアモルファスあるいは微結晶半導体薄膜への適用が可能である。さらにまた、アモルファス薄膜、微結晶薄膜に混じってわずかに結晶性薄膜が形成されている場合もある。
In the above-described embodiment, the case where the second conductive type semiconductor layer is applied to an amorphous silicon layer has been described. However, an amorphous or microcrystalline semiconductor such as amorphous silicon, microcrystalline silicon, an amorphous silicon alloy, or a microcrystalline silicon alloy. Application to thin films is possible. Furthermore, a slightly crystalline thin film may be formed by mixing with an amorphous thin film or a microcrystalline thin film.
以上のように、本発明にかかる光電変換装置は、低温形成が可能で、高効率の光電変換装置の形成に有用であり、特に、薄型の光電変換装置の形成に適している。
As described above, the photoelectric conversion device according to the present invention can be formed at a low temperature, is useful for forming a highly efficient photoelectric conversion device, and is particularly suitable for forming a thin photoelectric conversion device.
１ ｎ型単結晶シリコン基板、２ ｉ型アモルファスシリコン層、４ｉ（４ａｉ，４ｂｉ） ｉ型アモルファスシリコン層、４（４ａ，４ｂ，４ｃ，４ｄ） ｐ型アモルファスシリコン層、５ 表面透光性導電膜、６ 裏面透光性導電膜、７ 裏面反射膜、８ 表面の集電電極、９ 裏面の集電電極、１０ 基板、１０Ｓ 表面、１０Ｒ 裏面、１００ 光電変換装置、Ｐ ガスプラズマ、ＤＧ ドーピングガス。
1 n-type single crystal silicon substrate, 2 i-type amorphous silicon layer, 4i (4ai, 4bi) i-type amorphous silicon layer, 4 (4a, 4b, 4c, 4d) p-type amorphous silicon layer, 5 surface translucent conductive film , 6 Back translucent conductive film, 7 Back reflective film, 8 Current collecting electrode, 9 Back current collecting electrode, 10 Substrate, 10S surface, 10R back surface, 100 Photoelectric conversion device, P gas plasma, DG doping gas.
Claims (15)
- 第１導電型の半導体領域を有する基板上に第２導電型の半導体層を形成する工程を含み、ｐｎ接合を形成して、光電変換装置を製造する方法であって、
前記第２導電型の半導体層を形成する工程が、
真性半導体層を形成する工程と、
前記真性半導体層の表面にドーパントが化学吸着するように、前記ドーパントを含むドーピングガスを供給し、前記真性半導体層をドーピングして、前記第２導電型の半導体層を形成するドーピング工程とを含むことを、
特徴とする光電変換装置の製造方法。 A method of manufacturing a photoelectric conversion device by forming a pn junction by forming a second conductivity type semiconductor layer on a substrate having a first conductivity type semiconductor region,
Forming the second conductivity type semiconductor layer;
Forming an intrinsic semiconductor layer;
A doping step of supplying a doping gas containing the dopant and doping the intrinsic semiconductor layer so that the dopant is chemisorbed on the surface of the intrinsic semiconductor layer to form the second conductivity type semiconductor layer. That
A method for manufacturing a photoelectric conversion device. - 前記真性半導体層を形成する工程は、
アモルファスまたは微結晶の真性半導体層を形成する工程であることを、
特徴とする請求項１に記載の光電変換装置の製造方法。 The step of forming the intrinsic semiconductor layer includes
It is a process of forming an amorphous or microcrystalline intrinsic semiconductor layer,
The method for manufacturing a photoelectric conversion device according to claim 1, wherein: - 前記真性半導体層を形成する工程は、
水素化されたアモルファスまたは微結晶の真性半導体層を形成する工程であることを、
特徴とする請求項１に記載の光電変換装置の製造方法。 The step of forming the intrinsic semiconductor layer includes
The step of forming a hydrogenated amorphous or microcrystalline intrinsic semiconductor layer,
The method for manufacturing a photoelectric conversion device according to claim 1, wherein: - 前記第２導電型の半導体層を形成する工程は、
前記真性半導体層を形成する工程と、
前記ドーピング工程とを交互に複数回繰り返し実行するように構成されたことを、
特徴とする請求項１から３のいずれか１項に記載の光電変換装置の製造方法。 The step of forming the second conductivity type semiconductor layer includes:
Forming the intrinsic semiconductor layer;
The doping process is configured to be repeatedly performed a plurality of times alternately.
The manufacturing method of the photoelectric conversion apparatus of any one of Claim 1 to 3 characterized by the above-mentioned. - 前記真性半導体層を形成する工程は、プラズマＣＶＤ法による製膜工程であり、
一回当りに製膜される真性半導体膜の膜厚が２ｎｍ以下であることを、
特徴とする請求項１～４のいずれか１項に記載の光電変換装置の製造方法。 The step of forming the intrinsic semiconductor layer is a film formation step by a plasma CVD method,
The thickness of the intrinsic semiconductor film formed per time is 2 nm or less,
The method for producing a photoelectric conversion device according to any one of claims 1 to 4, characterized in that: - 前記ドーピング工程は、ドーピングガスとしてジボランまたは、トリメチルボロンを用いる工程であることを、
特徴とする請求項１～５のいずれか１項に記載の光電変換装置の製造方法。 The doping process is a process using diborane or trimethylboron as a doping gas.
The method for producing a photoelectric conversion device according to any one of claims 1 to 5, characterized in that: - 前記ドーピング工程は、
前記真性半導体膜表面のボロン密度が１×１０14／ｃｍ2以下となるように、ドーピングガスを化学吸着させる工程であることを、
特徴とする請求項６に記載の光電変換装置の製造方法。 The doping step includes
The step of chemically adsorbing a doping gas so that the boron density on the surface of the intrinsic semiconductor film is 1 × 10 14 / cm 2 or less,
The method for manufacturing a photoelectric conversion device according to claim 6. - 前記真性半導体層を形成する工程と、前記ドーピング工程とは、同一の基板温度で実行されることを、
特徴とする請求項１～７のいずれか１項に記載の光電変換装置の製造方法。 The step of forming the intrinsic semiconductor layer and the doping step are performed at the same substrate temperature.
The method for producing a photoelectric conversion device according to any one of claims 1 to 7, characterized in that: - 前記真性半導体層を形成する工程および、前記ドーピング工程は、基板温度が５０℃以上、２５０℃以下で実行されることを、
特徴とする請求項１～８のいずれか１項に記載の光電変換装置の製造方法。 The step of forming the intrinsic semiconductor layer and the doping step are performed at a substrate temperature of 50 ° C. or higher and 250 ° C. or lower.
The method for producing a photoelectric conversion device according to any one of claims 1 to 8, characterized in that: - 前記真性半導体層を形成する工程および、前記ドーピング工程は、基板温度が１００℃以上、２００℃以下で実行されることを、
特徴とする請求項９に記載の光電変換装置の製造方法。 The step of forming the intrinsic semiconductor layer and the doping step are performed at a substrate temperature of 100 ° C. or higher and 200 ° C. or lower.
The method for manufacturing a photoelectric conversion device according to claim 9, wherein - 前記水素化真性半導体層は、２at％以上、３０at％以下の水素を含有する真性半導体層であることを、
特徴とする請求項１～１０のいずれか１項に記載の光電変換装置の製造方法。 The hydrogenated intrinsic semiconductor layer is an intrinsic semiconductor layer containing hydrogen of 2 at% or more and 30 at% or less,
The method for manufacturing a photoelectric conversion device according to any one of claims 1 to 10, characterized in that: - 前記基板が第１導電型の結晶系シリコン基板であり、
前記第２導電型の半導体層を形成する工程に先立ち、
前記結晶系シリコン基板上に第１の真性半導体層を形成する工程を含み、
前記第２導電型の半導体層を形成する工程が、
前記第１の真性半導体層上に第２の真性半導体層を形成する工程と、
前記第２の真性半導体層に対し、第２導電型のドーパントをドーピングする工程とを含み、
第１導電型－真性－第２導電型半導体層の積層構造体からなる光電変換部を形成することを、
特徴とする請求項１に記載の光電変換装置の製造方法。 The substrate is a crystalline silicon substrate of a first conductivity type;
Prior to the step of forming the second conductivity type semiconductor layer,
Forming a first intrinsic semiconductor layer on the crystalline silicon substrate;
Forming the second conductivity type semiconductor layer;
Forming a second intrinsic semiconductor layer on the first intrinsic semiconductor layer;
Doping the second intrinsic semiconductor layer with a dopant of a second conductivity type,
Forming a photoelectric conversion portion comprising a laminated structure of a first conductivity type-intrinsic-second conductivity type semiconductor layer;
The method for manufacturing a photoelectric conversion device according to claim 1, wherein: - 請求項１～１２のいずれか１項に記載の光電変換装置の製造方法で形成された光電変換装置であって、
前記第２導電型の半導体層の下層に侵入する不純物量が侵入長１ｎｍ以内で前記半導体層中の不純物量の１／１０以下であることを、
特徴とする光電変換装置。
A photoelectric conversion device formed by the method for manufacturing a photoelectric conversion device according to any one of claims 1 to 12,
The amount of impurities entering the lower layer of the semiconductor layer of the second conductivity type is 1/10 or less of the amount of impurities in the semiconductor layer within a penetration length of 1 nm,
A featured photoelectric conversion device.
- 請求項１３に記載の光電変換装置であって、
前記結晶系シリコン基板が単結晶または多結晶シリコン基板であり、
前記第２導電型半導体層が、アモルファスシリコン半導体層またはアモルファスシリコン合金半導体層であることを、
特徴とする光電変換装置。 The photoelectric conversion device according to claim 13,
The crystalline silicon substrate is a single crystal or polycrystalline silicon substrate;
The second conductivity type semiconductor layer is an amorphous silicon semiconductor layer or an amorphous silicon alloy semiconductor layer,
A featured photoelectric conversion device. - 請求項１３または１４に記載の光電変換装置であって、
前記第２導電型半導体層の膜中水素濃度が２at％以上、３０at％以下であることを、
特徴とする光電変換装置。 The photoelectric conversion device according to claim 13 or 14,
The hydrogen concentration in the film of the second conductivity type semiconductor layer is 2 at% or more and 30 at% or less,
A featured photoelectric conversion device.
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| JPH03173423A (en) * | 1989-12-01 | 1991-07-26 | Seiko Instr Inc | Manufacture of p-n junction element |
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| JPH03173423A (en) * | 1989-12-01 | 1991-07-26 | Seiko Instr Inc | Manufacture of p-n junction element |
| JP2010520638A (en) * | 2007-03-06 | 2010-06-10 | ヴァリアン セミコンダクター イクイップメント アソシエイツ インコーポレイテッド | Atomic layer deposition technology |
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