WO2013149238A1

WO2013149238A1 - Source-follower based voltage mode transmitter

Info

Publication number: WO2013149238A1
Application number: PCT/US2013/034800
Authority: WO
Inventors: Matthew D. ROWLEY; Rajarshi Mukhopadhyay
Original assignee: Texas Instruments Inc
Current assignee: Texas Instruments Inc
Priority date: 2012-03-30
Filing date: 2013-04-01
Publication date: 2013-10-03
Anticipated expiration: 2014-09-30
Also published as: JP2015518313A; CN104170257A; US20130257514A1; WO2013149238A8

Description

SOURCE-FOLLOWER BASED VOLTAGE MODE TRANSMITTER

[0001] This relates generally to transmitter and, more particularly, to voltage mode transmitter having an H-bridge that uses source-followers.

BACKGROUND

[0002] FIG. 1 shows an example conventional driver 100. In operation, controller 102 provides complementary drive or control signals to H-bridge 104 (which generally comprises transistors Ql to Q4 and capacitors CI and C2). Specifically, these complementary signals are provided to transistor pair Ql and Q2 (which, as shown, are PMOS transistors) and transistor pair Q3 and Q4 (which, as shown, are NMOS transistors) in order to generate output signals for resistors Rl and R2 (which are typically impedance matching resistors) and the transmission channel (not shown). This means that controller 102 provides a logic high or "1" signal to transistors Ql and Q4 (while providing a logic low or "0" signal to transistors Q2 and Q3) to create one current path and visa versa for another current path. With either current path, there is a loss that occurs as result of using transistors Q5 and Q6; namely, there is high output impedance and a slow response due to transistors Q5 and Q6 operating as current sources. Therefore, there is a need for a driver having improved performance.

[0003] Some examples of conventional circuits are described in U.S. Patent No.

6,917,169; U.S. Patent No. 5,689,144; U.S. Patent Pre-Grant Publ. No. 2008/0252372; and Krenzket et al, "A 36-V H-BRIDGE DRIVER INTERFACE IN A STANDARD 0.35-μιη CMOS PROCESS," IEEE Intl. Symposium on Circuits and Systems 2005, Vol. 4, May 23-26 2005, pp. 3651-3554.

SUMMARY

[0004] In one aspect, the invention provides an apparatus.

[0005] A described embodiment of the apparatus comprises a first supply rail; a second supply rail; an H-bridge having: a first node; a second node; a third node; a fourth node; a first switch that is coupled between the first and third nodes; a second switch that is coupled between the first and fourth nodes; a third switch that is coupled between the second and third nodes; and a fourth switch that is coupled between the second and fourth nodes; a first source-follower that is coupled to the first node of the H-bridge, that is coupled to the first supply rail, and that is configured to receive a first reference signal; and a second source-follower that is coupled to the second node of the H-bridge, that is coupled to the second supply rail, and that is configured to receive a second reference signal.

[0006] In specific implementations, the first and second switches may further comprise first and second PMOS transistors, wherein each of the first and second PMOS transistors are coupled to the first node at its source. The third and fourth switches may further comprise first and second NMOS transistors, wherein each of the first and second NMOS transistors are coupled to the second node at its source. The first source-follower may further comprise a third NMOS transistor that is coupled to the first node at its source and body, that is coupled to the first supply rail at its drain, and that is configured to receive the first reference signal at its gate. The second source-follower may further comprise a third PMOS transistor that is coupled to the second node at its source and body, that is coupled to the second supply rail at its drain, and that is configured to receive the second reference signal at its gate. The third NMOS and third PMOS transistors are depletion mode transistors.

[0007] In another aspect an apparatus is provided that comprises a first supply rail; a second supply rail; a transmitter having: a transmit circuit; an H-bridge having: a first node; a second node; a third node; a fourth node; a first switch that is coupled between the first and third nodes and that is controlled by the transmit circuit; a second switch that is coupled between the first and fourth nodes and that is controlled by the transmit circuit; a third switch that is coupled between the second and third nodes and that is controlled by the transmit circuit; and a fourth switch that is coupled between the second and fourth nodes and that is controlled by the transmit circuit; a first source-follower that is coupled to the first node of the H-bridge, that is coupled to the first supply rail, and that is configured to receive a first reference signal; and a second source- follower that is coupled to the second node of the H-bridge, that is coupled to the second supply rail, and that is configured to receive a second reference signal; an transmission channel that is coupled to the third and fourth nodes; and a receiver that is coupled to the interconnect. [0008] In specific implementations, the transmit circuit may further comprise an input circuit; and a write circuit that is coupled to the input circuit and the gates of the first and second PMOS transistors and the gates of the first and second NMOS transistors. The transmission channel may further comprise an interconnect. The receiver may further comprise a magnetic head. The write circuit may further comprise a driver that is coupled to the gates of the first and second PMOS transistors and the gates of the first and second NMOS transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 is a diagram of an example of a conventional H-bridge transmitter.

[0010] FIG. 2 is a diagram of system in accordance with the invention.

[0011] FIG. 3 is diagram of an example implementation of the system of FIG. 2.

[0012] FIG. 4 is a diagram of an example of a driver of the systems of FIGS. 2 and 3.

[0013] FIG. 5 is a diagram comparing the performance of the drivers of FIGS. 1 and 4. DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0014] FIG. 2 illustrates an example of a system 200 in accordance with the invention.

In operation, transmitter 202 (and transmit circuit 204, in particular) receives an input signal IN. The transmit circuit 204 (which, can, for example, perform wave-shaping operations) provides control signals to driver 206 that permit a signal to be driven over the transmission channel 208. The receiver 210 can then generate an output signal OUT based on the signal received from the transmission channel 208.

[0015] One example implementation of the system 200 can be seen in FIG. 3. In this example, the system 200 is implemented as a write channel for a hard disk drive or HDD (which is labeled 300). For the system 300, a write signal is received from the HDD channel by the preamplifier 301 (namely the input circuit 302). Collectively, the input circuit 302 and write circuit 304 can perform wave-shaping so as to allow driver 206 to transmit a write signal over interconnect 308 to the magnetic head 310. Based on this write signal, the magnetic head 310 can write to an HDD platter.

[0016] The driver 206 (which can be seen in greater detail in FIG. 4) is used in systems

200 and 300. Driver 206 has a similar construction driver 100, except that current sources (i.e., transistors Q5 and Q6) have been replaced with source-followers (i.e., transistors Q7 and Q8), which are coupled to nodes Nl and N2 of H-bridge 104. Source-followers respond very quickly (compared to current sources) to changes in the source voltage (which occur during switching of H-bridge 104). Since the gates of transistors Q7 and Q8 are generally held at fixed reference voltages REF1 and REF2, any source voltage changes results in an increase of the gate-source voltage of transistors Q7 and Q8, which prompts a rapid increase in drain-to-source current. Thus, driver 206 more rapidly charges and discharges the output nodes N3 and N4 compared to driver 100, improving efficiency.

[0017] Moreover, by using source-followers (i.e., transistors Q7 and Q8), the common source impedance Ζουτ looking back into the H-bridge 104 is also decreased. Looking back to driver 100, impedance Zou_Tjoo is:

V A _Λ

7 = 7 + 7 = 7

(1) ^ουτ,ιοο SWITCH CS SWITCH

I D

where ZSWITCH is the switch impedance (i.e., on-resistance of one of transistors Ql to Q4), Zcs is current source impedance, VA is the Early voltage of transistor Q5 or Q6, and ID is the drain current of transistor Q5 or Q6. This means that for an Early voltage of about 10V and a drain current I_D of about 50mA, impedance Ζ₀υτ,ιοο is about 200Ω (which is very high). With driver 206, the impedance ZQUT,206 is

1

z, OUT 200 = z SWITCH "I" Z SWITCH +

where ZSF is source-follower impedance, W/L is the aspect ratio of transistor Q7 or Q8, Cox is the oxide unit capacitance of transistor Q7 or Q8, μ is the carrier mobility, and ID is the drain current of transistor Q7 or Q8. The impedance Ζ_Ουτ,206 is comparative much smaller, being about 1-5Ω with a drain current ID of about 10mA. This lower impedance can, therefore, move the resulting parasitic pole out to a higher frequency so as to permit higher frequency operation.

[0018] To further improve performance, transistors Q7 and Q8 can be depletion mode transistors. Depletion mode devices (i.e., depletion mode NMOS or PMOS transistors) have a negative threshold voltage VT. This allows the source-followers (i.e., transistors Q7 and Q8) to achieve a maximum output swing (which, theoretically, is a dynamic range from the voltage on rail VSS plus a drain-source voltage drop across transistor Q8 to the voltage on rail VDD minus a drain-source voltage drop across transistor Q7) without having to provide reference voltage REF1 and REF2 that exceed the voltages on rails VDD and VSS (which is usually accomplished with charge pumps).

[0019] Turning to FIG. 5, a comparison of the drivers 100 and 206 can be seen. As shown, driver 206 settles much more quickly than driver 100. As a result the efficiency of driver 206 is greatly improved over that of driver 100.

[0020] Those skilled in the art will appreciate that modifications may be made to the described example implementations, and also that many other embodiments are possible, within the scope of the claimed invention.

Claims

CLAIMS What is claimed is:

1. An apparatus comprising:

a first supply rail;

a second supply rail;

an H-bridge having a first node; a second node; a third node; a fourth node; a first switch that is coupled between the first and third nodes; a second switch that is coupled between the first and fourth nodes; a third switch that is coupled between the second and third nodes; and a fourth switch that is coupled between the second and fourth nodes;

a first source-follower that is coupled to the first node of the H-bridge, that is coupled to the first supply rail, and that is configured to receive a first reference signal; and

a second source-follower that is coupled to the second node of the H-bridge, that is coupled to the second supply rail, and that is configured to receive a second reference signal.

2. The apparatus of Claim 1, wherein the first and second switches further comprise first and second PMOS transistors, wherein each of the first and second PMOS transistors are coupled to the first node at its source.

3. The apparatus of Claim 2, wherein the third and fourth switches further comprise first and second NMOS transistors, wherein each of the first and second NMOS transistors are coupled to the second node at its source.

4. The apparatus of Claim 3, wherein the first source-follower further comprises a third NMOS transistor that is coupled to the first node at its source and body, that is coupled to the first supply rail at its drain, and that is configured to receive the first reference signal at its gate.

5. The apparatus of Claim 4, wherein the second source-follower further comprises a third PMOS transistor that is coupled to the second node at its source and body, that is coupled to the second supply rail at its drain, and that is configured to receive the second reference signal at its gate.

6. The apparatus of Claim 5, wherein the third NMOS and third PMOS transistors are depletion mode transistors.

7. The apparatus of Claim 6, further comprising:

a transmitter having a transmit circuit including the H-bridge;

an transmission channel that is coupled to the third and fourth nodes; and

a receiver that is coupled to the interconnect.

8. The apparatus of Claim 7, wherein the transmit circuit further comprises:

an input circuit; and

a write circuit that is coupled to the input circuit and the gates of the first and second PMOS transistors and the gates of the first and second NMOS transistors.

9. The apparatus of Claim 8, wherein the transmission channel further comprises an interconnect.

10. The apparatus of Claim 8, wherein the receiver further comprises a magnetic head.

11. The apparatus of Claim 8, wherein the write circuit further comprises a driver that is coupled to the gates of the first and second PMOS transistors and the gates of the first and second NMOS transistors.

12. The apparatus of Claim 1, wherein the transmit circuit further comprises:

an input circuit; and