WO2013145792A1 - Electric power conversion device - Google Patents

Electric power conversion device Download PDF

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Publication number
WO2013145792A1
WO2013145792A1 PCT/JP2013/050160 JP2013050160W WO2013145792A1 WO 2013145792 A1 WO2013145792 A1 WO 2013145792A1 JP 2013050160 W JP2013050160 W JP 2013050160W WO 2013145792 A1 WO2013145792 A1 WO 2013145792A1
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Prior art keywords
power
circuit
gate
gate drive
power semiconductor
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PCT/JP2013/050160
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French (fr)
Japanese (ja)
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裕章 市川
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富士電機株式会社
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Publication of WO2013145792A1 publication Critical patent/WO2013145792A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/12—Modifications for increasing the maximum permissible switched current
    • H03K17/127—Modifications for increasing the maximum permissible switched current in composite switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/168—Modifications for eliminating interference voltages or currents in composite switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/689—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
    • H03K17/691—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit

Definitions

  • the present invention relates to a power conversion device that controls power semiconductor elements connected in parallel by individual gate drive circuits.
  • FIG. 3 shows an example of a main circuit of a conventional power converter (for example, a three-phase inverter).
  • the main circuit includes a DC power supply 100 and an intelligent power module (hereinafter abbreviated as IPM) 200.
  • the IPM 200 includes three arm pairs connected in parallel between the positive electrode and the negative electrode of the power supply 100, and a gate driving circuit 203 (only one in the figure) connected to each of the power semiconductor elements 201 constituting the arm pairs. Is shown).
  • an insulated gate bipolar transistor (IGBT) is used as the power semiconductor element 201.
  • a diode 202 is connected in antiparallel to each power semiconductor element 201, and a power supply 300 is connected to the gate drive circuit 203.
  • Each gate drive circuit 203 generates a gate drive signal in response to a command signal Sc from an external device (not shown) and controls the corresponding power semiconductor element 201 on and off.
  • IPM intelligent power module
  • FIG. 4 shows a configuration example of the gate drive circuit 203.
  • the gate drive circuit 203 includes output stage switch elements S1 and S2 connected in series between the positive and negative electrodes of the power supply 300.
  • the switch element S1 When the switch element S1 is turned on, the power semiconductor element 201 is turned on, and the switch element S2 is turned on.
  • the power semiconductor element 201 When turned on, the power semiconductor element 201 is turned off.
  • MOSFET metal oxide field effect transistor
  • the delay circuit D1 inputs the command signal Sc through the buffer B1, and delays the rise of the command signal Sc.
  • the delay circuit D2 inputs the command signal Sc via the buffer B1 and the inverter I2, and delays the fall of the control signal Sc.
  • the output signal of the delay circuit D1 is inverted by the inverter I1 and then applied to the switch element S1, while the output signal of the delay circuit D2 is directly applied to the switch element S2.
  • the delay circuits D1 and D2 are provided to prevent the switch elements S1 and S2 from being turned on simultaneously and to prevent malfunction due to noise.
  • FIG. 5 shows a configuration in which IPM 200A and IPM 200B are connected in parallel in order to increase the capacity.
  • FIG. 3 reference numerals corresponding to elements common to the elements shown in FIG. 4 are given.
  • a NAND circuit N1A is provided between the delay circuit D1A and the switch element S1A
  • an AND circuit A2A is provided between the delay circuit D2A and the switch element S2A.
  • the gate drive circuit 203B of the IPM 200B has a NAND circuit N1B and an AND circuit A2B corresponding to the NAND circuit N1A and the AND circuit A2A.
  • the output signal of the delay circuit D1A is input to one input terminal of the NAND circuit N1A and one input terminal of the NAND circuit N1B, and the output signal of the delay circuit D2A is input to one input terminal of the AND circuit A1A and the AND circuit A1B. Input to one input terminal.
  • the output signal of the delay circuit D1B is input to the other input terminal of the NAND circuit N1B and the other input terminal of the NAND circuit N1A, and the output signal of the delay circuit D2B is input to the other input terminal of the AND circuit A1B and the AND circuit. It is input to the other input terminal of A1A.
  • the switch elements S1A, S1B or S2A, S2B of the gate drive circuits 203A, 203B are turned on and off almost simultaneously, so that the power semiconductor elements 201A of the IPM 200A and the power semiconductor elements 201B of the IPM 200B connected in parallel are connected. Variations in switching time are suppressed.
  • the NAND circuit N1A and the AND circuit A1A of the IPM 200A are supplied with power from the power source 300A, and the NAND circuit N1B and the AND circuit A1B of the IPM 200B are supplied with power from the power source 300B. Further, since signals are transmitted between the gate drive circuits 203A and 203B, the ground lines of the circuits 203A and 203B are shared as shown by dotted lines.
  • the currents flowing through the power semiconductor elements 201A and 201B of the IPMs 200A and 200B are not balanced due to the influence of variations in delay times of circuit elements constituting the IPMs 200A and 200B.
  • the electromotive voltage in the wiring WA leading to the load L There is a difference between the electromotive voltage in the wiring WA leading to the load L and the electromotive voltage in the wiring WB leading from the emitter of the power semiconductor element 201B to the load L.
  • a loop current Ic as indicated by an arrow flows in the loop circuit including the ground lines of the gate drive circuits 203A and 203B.
  • the loop current Ic is about 20A.
  • the difference between the electromotive voltage in the wiring WA and the electromotive voltage in the wiring WB induced based on the loop current Ic results in the difference between the gate voltage of the power semiconductor element 201A and the gate voltage of the power semiconductor element 201B. There is a possibility that the switching loss may be extremely increased by causing a malfunction of the turn-on timing.
  • an object of the present invention is to provide a power conversion device capable of improving the operation reliability by suppressing variations in gate voltage of power semiconductor elements connected in parallel.
  • the present invention relates to an improvement of a power conversion apparatus that controls power semiconductor elements connected in parallel by using individual gate drive circuits.
  • Each of the gate driving devices is configured such that the return paths of the gate currents of the power semiconductor elements are separated from each other.
  • Each of the gate drive circuits according to the embodiment includes a transmission circuit element that transmits an instruction signal and an output circuit that operates according to a signal output from the transmission circuit element.
  • the synchronization of the operation of each power semiconductor element can be improved by sharing the transmission circuit element of each gate drive circuit.
  • the output circuit can be configured to selectively output a predetermined forward bias voltage and reverse bias voltage to the gate of the corresponding power semiconductor element.
  • the return paths of the gate currents of the power semiconductor elements are separated from each other, a loop circuit including these return paths is not formed. Therefore, variation in gate voltage of each power semiconductor element is suppressed, and operation reliability is improved.
  • FIG. 1 is a circuit diagram showing a configuration of a power conversion device according to an embodiment of the present invention.
  • This power conversion device includes a DC power source 1, power modules 2A and 2B, and gate drive modules 3A and 3B.
  • the output power of the DC power source 1 is changed to a desired power by switching operation of power semiconductor elements in the power modules 2A and 2B. Convert.
  • the electric power converted by this power conversion device is supplied to the load 4.
  • the power module 2A includes power semiconductor elements 21 and 22 connected in series, and free wheel diodes 23 and 24 connected in reverse parallel to the power semiconductor elements 21 and 22, respectively.
  • a series connection point of the power semiconductor elements 21 and 22 is connected to one end of the load 4 via a terminal 27.
  • the power module 2B has the same configuration.
  • the power modules 2 ⁇ / b> A and 2 ⁇ / b> B are connected in parallel between the positive electrode and the negative electrode of the DC power supply 1. The reason why the two power modules 2A and 2B are connected in parallel is to increase the capacity.
  • IGBTs insulated gate bipolar transistors
  • the gate drive module 3A includes a gate drive circuit 30AU and a gate drive circuit 30AL.
  • the gate drive circuit 30AU includes a power supply unit 31 that outputs positive and negative voltages (for example, ⁇ 15 V), and receives an upper arm command signal SU from a control circuit (not shown) via the inverter 4AU.
  • the output signal of the inverter 4AU is input to the output circuit 34 that functions as a buffer via the photocoupler 32 and the amplifier 33.
  • the output circuit 34 includes a complementary pair of transistors connected between the positive electrode and the negative electrode of the power supply unit 31.
  • the output circuit 34 has a gate-on signal (about + 15V) and a gate-off signal (about -15V) are output between the terminals 35 and 36.
  • the terminal 36 is connected to the intermediate pole (0 V) of the power supply unit 31.
  • the terminal 35 is connected to the terminal 25 of the power module 2A via the gate resistor 41 and the diode 42, and the terminal 36 is connected to the terminal 26 of the power module 2A.
  • the gates and emitters of the power semiconductor element 21 are connected to the terminals 25 and 26 of the power module 2A, respectively. Therefore, the gate drive signal (gate on signal or gate off signal) output from the gate drive circuit 30 is the power It is input between the gate and emitter of the semiconductor element 21.
  • the other gate drive circuit 30AL of the gate drive module 3A has the same configuration. Since the gate drive circuit 30AL receives the lower arm command signal SL from the control circuit via the inverter 4AL, the gate drive signal corresponding to the command of the command signal SL is supplied to the power on the lower arm side of the power module 2A. Output between the gate and emitter of the semiconductor element 22.
  • the gate drive module 3B includes gate drive circuits 30BU and 30BL having the same configuration as the gate drive circuits 30AU and 30AL of the gate drive module 3A.
  • the gate drive circuits 30BU and 30BL receive the command signals SU and SL via the inverters 4BU and 4BL, respectively. Therefore, the gate drive circuit 30BU outputs a gate drive signal corresponding to the command of the command signal SU to the upper arm side power semiconductor element 21 of the power module 2B, and the gate drive circuit 30BL corresponds to the command of the command signal SL.
  • the gate drive signal to be output is output to the lower arm side power semiconductor element 22 of the power module 2B.
  • the line constitutes a loop circuit together with a line from the terminal 27 of the power module 2A to the load 4 and a line from the terminal 27 of the power module 2B to the load 4.
  • a voltage induced based on the wiring inductance of the line from the terminal 27 of the power module 2A to the load 4 and a voltage induced based on the wiring inductance of the line from the terminal 27 of the power module 2B to the load 4 A loop current based on the difference flows in the loop circuit.
  • This loop current results in a difference between the gate voltage of the power semiconductor element 21 of the power module 2A and the gate voltage of the power semiconductor element 21 of the power module 2B, which causes a malfunction in turn-on timing.
  • a line from the terminal 36 of the gate drive circuit 30AU to the terminal 26 of the power module 2A, and a line from the terminal 36 of the gate drive circuit 30BU to the terminal 26 of the power module 2B. are separated from each other, that is, the return paths of the gate currents of the power semiconductor elements 21 in the power modules 2A and 2B are separated from each other. Reliability is improved.
  • FIG. 2 shows another embodiment of the present invention.
  • the power converter according to this embodiment is different from the power converter shown in FIG. 1 in the following points. That is, in the power conversion device according to the present embodiment, the inverters 4BU and 4BL shown in FIG. 1 are omitted, the output terminal of the amplifier 33 of the gate drive circuit 30AU, and the input terminal of the buffer 34 of the gate drive circuit 30BU. Are connected by a wiring 51, the negative electrode of the power supply 31 of the gate drive circuit 30AU and the negative electrode of the power supply 31 of the gate drive circuit 30BU are connected by a wiring 52, and the gate drive circuit 30AL and the gate drive circuit. It differs from the power converter shown in FIG. 1 in that connection according to the above is made between 30BL.
  • the transmission circuit elements (the photocoupler 32 and the amplifier 33) that transmit the instruction signal SU are shared by the gate drive circuits 30AU and 30BU, and the transmission circuit element that transmits the instruction signal SL is provided. It is shared by the gate drive circuits 30AL and 30BL. Therefore, the synchronism between the gate drive signals output from the gate drive modules 3A and 3B is improved, and as a result, the synchronism of the operations of the power modules 2A and 2B is improved.
  • the number of parallel connections of the power modules is 2, but the present invention can also be applied when the number of parallel connections is 3 or more.

Abstract

In order to suppress fluctuations in gate voltage and enhance reliability of operation of parallel-connected power semiconductor elements, the present invention is an electric power conversion device for controlling parallel-connected power semiconductor elements (21), using individual gate drive circuits (30AU, 30BU). The gate drive devices (30AU, 30BU) are configured so that gate current return paths of the parallel-connected power semiconductor elements (21) are separated from each other.

Description

電力変換装置Power converter
　本発明は、並列接続されたパワー半導体素子を個別のゲート駆動回路によって制御する電力変換装置に関する。 The present invention relates to a power conversion device that controls power semiconductor elements connected in parallel by individual gate drive circuits.
　図３に、従来の電力変換装置（例えば、三相インバータ）の主回路の一例を示す。この主回路は、直流電源１００とインテリジェントパワーモジュール（以下、ＩＰＭと略称する）２００とを有する。ＩＰＭ２００は、電源１００の正極と負極間に並列接続した３つのアーム対と、それらのアーム対を構成するパワー半導体素子２０１のそれぞれに対して接続されたゲート駆動回路２０３（図では、１個のみが示されている）とを備えている。パワー半導体素子２０１としては、例えば絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ）が使用される。各パワー半導体素子２０１にはダイオード２０２が逆並列接続され、また、ゲート駆動回路２０３には電源３００が接続されている。
　各ゲート駆動回路２０３は、図示しない外部装置からの指令信号Ｓｃに応じてゲート駆動信号を発生し、対応するパワー半導体素子２０１をオンオフ制御する。 FIG. 3 shows an example of a main circuit of a conventional power converter (for example, a three-phase inverter). The main circuit includes a DC power supply 100 and an intelligent power module (hereinafter abbreviated as IPM) 200. The IPM 200 includes three arm pairs connected in parallel between the positive electrode and the negative electrode of the power supply 100, and a gate driving circuit 203 (only one in the figure) connected to each of the power semiconductor elements 201 constituting the arm pairs. Is shown). For example, an insulated gate bipolar transistor (IGBT) is used as the power semiconductor element 201. A diode 202 is connected in antiparallel to each power semiconductor element 201, and a power supply 300 is connected to the gate drive circuit 203.
Each gate drive circuit 203 generates a gate drive signal in response to a command signal Sc from an external device (not shown) and controls the corresponding power semiconductor element 201 on and off.
　図４にゲート駆動回路２０３の構成例を示す。このゲート駆動回路２０３は、電源３００の正極と負極間に直列接続された出力段スイッチ素子Ｓ１，Ｓ２を備え、スイッチ素子Ｓ１がオンした場合にパワー半導体素子２０１がオンするとともに、スイッチ素子Ｓ２がオンした場合にパワー半導体素子２０１がオフする。スイッチ素子Ｓ１，Ｓ２には、例えばＭＯＳＦＥＴ（金属酸化膜型電界効果トランジスタ）が使用される。
　遅延回路Ｄ１は、指令信号ＳｃをバッファＢ１を介して入力して、この指令信号Ｓｃの立ち上がりを遅延させる。また、遅延回路Ｄ２は、指令信号ＳｃをバッファＢ１及びインバータＩ２を介して入力して、この制御信号Ｓｃの立ち下がりを遅延させる。遅延回路Ｄ１の出力信号はインバータＩ１によって反転されたのちスイッチ素子Ｓ１に与えられ、一方、遅延回路Ｄ２の出力信号はスイッチ素子Ｓ２に直接与えられる。この遅延回路Ｄ１，Ｄ２は、スイッチ素子Ｓ１，Ｓ２を同時オンさせないためと、ノイズによる誤動作を防止するために設けられている。 FIG. 4 shows a configuration example of the gate drive circuit 203. The gate drive circuit 203 includes output stage switch elements S1 and S2 connected in series between the positive and negative electrodes of the power supply 300. When the switch element S1 is turned on, the power semiconductor element 201 is turned on, and the switch element S2 is turned on. When turned on, the power semiconductor element 201 is turned off. For example, MOSFET (metal oxide field effect transistor) is used for the switch elements S1 and S2.
The delay circuit D1 inputs the command signal Sc through the buffer B1, and delays the rise of the command signal Sc. The delay circuit D2 inputs the command signal Sc via the buffer B1 and the inverter I2, and delays the fall of the control signal Sc. The output signal of the delay circuit D1 is inverted by the inverter I1 and then applied to the switch element S1, while the output signal of the delay circuit D2 is directly applied to the switch element S2. The delay circuits D1 and D2 are provided to prevent the switch elements S1 and S2 from being turned on simultaneously and to prevent malfunction due to noise.
　図５は、大容量化を図るためにＩＰＭ２００Ａ，ＩＰＭ２００Ｂを並列接続した構成を示す。この図３においては、図４に示す要素と共通する要素に対応する符号を付してある。ＩＰＭ２００Ａのゲート駆動回路２０３Ａは、遅延回路Ｄ１Ａとスイッチ素子Ｓ１Ａとの間にナンド回路Ｎ１Ａを設けるとともに、遅延回路Ｄ２Ａとスイッチ素子Ｓ２Ａとの間にアンド回路Ａ２Ａを設けてある。ＩＰＭ２００Ｂのゲート駆動回路２０３Ｂは、上記ナンド回路Ｎ１Ａ及びアンド回路Ａ２Ａに対応するナンド回路Ｎ１Ｂ及びアンド回路Ａ２Ｂを有する。 FIG. 5 shows a configuration in which IPM 200A and IPM 200B are connected in parallel in order to increase the capacity. In FIG. 3, reference numerals corresponding to elements common to the elements shown in FIG. 4 are given. In the gate drive circuit 203A of the IPM 200A, a NAND circuit N1A is provided between the delay circuit D1A and the switch element S1A, and an AND circuit A2A is provided between the delay circuit D2A and the switch element S2A. The gate drive circuit 203B of the IPM 200B has a NAND circuit N1B and an AND circuit A2B corresponding to the NAND circuit N1A and the AND circuit A2A.
　遅延回路Ｄ１Ａの出力信号は、ナンド回路Ｎ１Ａの一方の入力端子とナンド回路Ｎ１Ｂの一方の入力端子に入力され、遅延回路Ｄ２Ａの出力信号は、アンド回路Ａ１Ａの一方の入力端子とアンド回路Ａ１Ｂの一方の入力端子に入力される。また、遅延回路Ｄ１Ｂの出力信号は、ナンド回路Ｎ１Ｂの他方の入力端子とナンド回路Ｎ１Ａの他方の入力端子に入力され、遅延回路Ｄ２Ｂの出力信号は、アンド回路Ａ１Ｂの他方の入力端子とアンド回路Ａ１Ａの他方の入力端子に入力される。
　この結果、ゲート駆動回路２０３Ａ，２０３Ｂのスイッチ素子Ｓ１Ａ，Ｓ１ＢまたはＳ２Ａ，Ｓ２Ｂがほぼ同時にオン，オフされることになるので、並列接続されたＩＰＭ２００Ａのパワー半導体素子２０１ＡとＩＰＭ２００Ｂのパワー半導体素子２０１Ｂのスイッチング時間のばらつきが抑制される。 The output signal of the delay circuit D1A is input to one input terminal of the NAND circuit N1A and one input terminal of the NAND circuit N1B, and the output signal of the delay circuit D2A is input to one input terminal of the AND circuit A1A and the AND circuit A1B. Input to one input terminal. The output signal of the delay circuit D1B is input to the other input terminal of the NAND circuit N1B and the other input terminal of the NAND circuit N1A, and the output signal of the delay circuit D2B is input to the other input terminal of the AND circuit A1B and the AND circuit. It is input to the other input terminal of A1A.
As a result, the switch elements S1A, S1B or S2A, S2B of the gate drive circuits 203A, 203B are turned on and off almost simultaneously, so that the power semiconductor elements 201A of the IPM 200A and the power semiconductor elements 201B of the IPM 200B connected in parallel are connected. Variations in switching time are suppressed.
特開２００２－３６９４９６号公報Japanese Patent Laid-Open No. 2002-369496
　図５に点線で示すように、ＩＰＭ２００Ａのナンド回路Ｎ１Ａ及びアンド回路Ａ１Ａは電源３００Ａから給電され、ＩＰＭ２００Ｂのナンド回路Ｎ１Ｂ及びアンド回路Ａ１Ｂは電源３００Ｂから給電される。また、ゲート駆動回路２０３Ａ，２０３Ｂ間で信号の伝送が行なわれることから、該回路２０３Ａ，２０３Ｂのグランドライン相互は点線で示すように共通化されている。 5, the NAND circuit N1A and the AND circuit A1A of the IPM 200A are supplied with power from the power source 300A, and the NAND circuit N1B and the AND circuit A1B of the IPM 200B are supplied with power from the power source 300B. Further, since signals are transmitted between the gate drive circuits 203A and 203B, the ground lines of the circuits 203A and 203B are shared as shown by dotted lines.
　ＩＰＭ２００Ａ，２００Ｂのパワー半導体素子２０１Ａ，２０１Ｂを流れる電流は、該ＩＰＭ２００Ａ，２００Ｂを構成する回路要素の遅延時間のばらつきの影響でバランスしないのが通常であり、この場合、パワー半導体素子２０１Ａのエミッタから負荷Ｌに至る配線ＷＡでの起電圧と、パワー半導体素子２０１Ｂのエミッタから負荷Ｌに至る配線ＷＢでの起電圧とに差を生じる。そして、例えば、配線ＷＡでの起電圧が配線ＷＢでの起電圧よりも高い場合、ゲート駆動回路２０３Ａ，２０３Ｂのグランドラインを含むループ回路に矢印で示すようなループ電流Ｉｃが流れることになる。パワー半導体素子２０１Ａ，２０１Ｂの定格電流が１０００Ａである場合、このループ電流Ｉｃは２０Ａ程度になることが確認されている。
　このループ電流Ｉｃに基づいて誘起される配線ＷＡでの起電圧と配線ＷＢでの起電圧の差は、パワー半導体素子２０１Ａのゲート電圧とパワー半導体素子２０１Ｂのゲート電圧の差をもたらし、これは、ターンオンタイミングについての誤動作を招いて、スイッチング損失を極端に増加させるおそれがある。 Normally, the currents flowing through the power semiconductor elements 201A and 201B of the IPMs 200A and 200B are not balanced due to the influence of variations in delay times of circuit elements constituting the IPMs 200A and 200B. In this case, from the emitter of the power semiconductor element 201A There is a difference between the electromotive voltage in the wiring WA leading to the load L and the electromotive voltage in the wiring WB leading from the emitter of the power semiconductor element 201B to the load L. For example, when the electromotive voltage in the wiring WA is higher than the electromotive voltage in the wiring WB, a loop current Ic as indicated by an arrow flows in the loop circuit including the ground lines of the gate drive circuits 203A and 203B. When the rated current of the power semiconductor elements 201A and 201B is 1000A, it is confirmed that the loop current Ic is about 20A.
The difference between the electromotive voltage in the wiring WA and the electromotive voltage in the wiring WB induced based on the loop current Ic results in the difference between the gate voltage of the power semiconductor element 201A and the gate voltage of the power semiconductor element 201B. There is a possibility that the switching loss may be extremely increased by causing a malfunction of the turn-on timing.
　そこで、本発明の課題は、並列接続されたパワー半導体素子のゲート電圧のばらつきを抑制して動作の信頼性を向上することができる電力変換装置を提供することにある。 Therefore, an object of the present invention is to provide a power conversion device capable of improving the operation reliability by suppressing variations in gate voltage of power semiconductor elements connected in parallel.
　本発明は、並列接続されたパワー半導体素子を個別のゲート駆動回路を用いて制御する電力変換装置の改良に係るものである。前記各ゲート駆動装置は、前記各パワー半導体素子のゲート電流の帰路が互いに分離されるように構成される。 The present invention relates to an improvement of a power conversion apparatus that controls power semiconductor elements connected in parallel by using individual gate drive circuits. Each of the gate driving devices is configured such that the return paths of the gate currents of the power semiconductor elements are separated from each other.
　実施形態に係る前記各ゲート駆動回路は、指示信号を伝達する伝達回路要素と、この伝達回路要素から出力される信号に応じて作動する出力回路とを備える。この場合、前記各ゲート駆動回路の前記伝達回路要素を共通化することによって、前記各パワー半導体素子の動作の同期性を向上することができる。 Each of the gate drive circuits according to the embodiment includes a transmission circuit element that transmits an instruction signal and an output circuit that operates according to a signal output from the transmission circuit element. In this case, the synchronization of the operation of each power semiconductor element can be improved by sharing the transmission circuit element of each gate drive circuit.
　前記出力回路は、対応する前記パワー半導体素子のゲートに対して所定の順バイアス電圧と逆バイアス電圧を選択的に出力するように構成することができる。 The output circuit can be configured to selectively output a predetermined forward bias voltage and reverse bias voltage to the gate of the corresponding power semiconductor element.
　本発明によれば、各パワー半導体素子のゲート電流の帰路が互いに分離されているので、それらの帰路を含むループ回路か形成されない。従って、各パワー半導体素子のゲート電圧のばらつきが抑制されて動作の信頼性が向上する。 According to the present invention, since the return paths of the gate currents of the power semiconductor elements are separated from each other, a loop circuit including these return paths is not formed. Therefore, variation in gate voltage of each power semiconductor element is suppressed, and operation reliability is improved.
本発明に係る電力変換装置の実施形態を示す回路図である。It is a circuit diagram showing an embodiment of a power converter concerning the present invention. 本発明に係る電力変換装置の他の実施形態を示す回路図である。It is a circuit diagram which shows other embodiment of the power converter device which concerns on this invention. インテリジェントパワーモジュールを用いた従来の電力変換装置の一例を示す回路図である。It is a circuit diagram which shows an example of the conventional power converter device using an intelligent power module. 図３の電力変換装置におけるゲート駆動回路の構成を示す回路図である。It is a circuit diagram which shows the structure of the gate drive circuit in the power converter device of FIG. インテリジェントパワーモジュールを並列接続した電力変換装置の構成を示す回路図である。It is a circuit diagram which shows the structure of the power converter device which connected the intelligent power module in parallel.
　以下、図面を参照しながら本発明の一実施形態を説明する。
　図１は、本発明の一実施形態に係る電力変換装置の構成を示す回路図である。この電力変換装置は、直流電源１、パワーモジュール２Ａ，２Ｂ及びゲート駆動モジュール３Ａ，３Ｂを備え、パワーモジュール２Ａ，２Ｂ内のパワー半導体素子のスイッチング動作によって直流電源１の出力電力を所望の電力に変換する。この電力変換装置によって変換された電力は、負荷４に供給される。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing a configuration of a power conversion device according to an embodiment of the present invention. This power conversion device includes a DC power source 1, power modules 2A and 2B, and gate drive modules 3A and 3B. The output power of the DC power source 1 is changed to a desired power by switching operation of power semiconductor elements in the power modules 2A and 2B. Convert. The electric power converted by this power conversion device is supplied to the load 4.
　パワーモジュール２Ａは、直列接続されたパワー半導体素子２１，２２と、これらのパワー半導体素子２１，２２にそれぞれ逆並列接続されたフリーホイール・ダイオード２３，２４とを備えている。パワー半導体素子２１，２２の直列接続点は、端子２７を介して負荷４の一端に接続されている。パワーモジュール２Ｂも同様の構成を有する。
　パワーモジュール２Ａ，２Ｂは、直流電源１の正極と負極間に互いに並列に接続されている。このように２つのパワーモジュール２Ａ，２Ｂを並列接続するのは、大容量化を図るためである。本実施形態においては、パワー半導体素子２１，２２としてＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）が使用されている。 The power module 2A includes power semiconductor elements 21 and 22 connected in series, and free wheel diodes 23 and 24 connected in reverse parallel to the power semiconductor elements 21 and 22, respectively. A series connection point of the power semiconductor elements 21 and 22 is connected to one end of the load 4 via a terminal 27. The power module 2B has the same configuration.
The power modules 2 </ b> A and 2 </ b> B are connected in parallel between the positive electrode and the negative electrode of the DC power supply 1. The reason why the two power modules 2A and 2B are connected in parallel is to increase the capacity. In the present embodiment, IGBTs (insulated gate bipolar transistors) are used as the power semiconductor elements 21 and 22.
　ゲート駆動モジュール３Ａは、ゲート駆動回路３０ＡＵ及びゲート駆動回路３０ＡＬを有する。ゲート駆動回路３０ＡＵは、正負の電圧（例えば±１５Ｖ）を出力する電源部３１を備え、図示していない制御回路からの上アーム用指令信号ＳＵをインバータ４ＡＵを介して入力する。インバータ４ＡＵの出力信号は、フォトカプラ３２及び増幅器３３を介してバッファとして機能する出力回路３４に入力される。
　出力回路３４は、電源部３１の正極と負極間に接続されたトランジスタの相補対を備え、指令信号ＳＵがゲートオンを指令している場合及びゲートオフを指令している場合に、それぞれゲートオン信号（約+１５Ｖ）及びゲートオフ信号（約－１５Ｖ）を端子３５，３６間に出力する。なお、端子３６は電源部３１の中間極（０Ｖ）に接続されている。
　端子３５はゲート抵抗４１及びダイオード４２を介してパワーモジュール２Ａの端子２５に接続され、端子３６は該パワーモジュール２Ａの端子２６に接続されている。パワーモジュール２Ａの端子２５，２６には、パワー半導体素子２１のゲート、エミッタがそれぞれ接続されており、従って、ゲート駆動回路３０から出力されるゲート駆動信号（ゲートオン信号またはゲートオフ信号）は、該パワー半導体素子２１のゲート・エミッタ間に入力される。 The gate drive module 3A includes a gate drive circuit 30AU and a gate drive circuit 30AL. The gate drive circuit 30AU includes a power supply unit 31 that outputs positive and negative voltages (for example, ± 15 V), and receives an upper arm command signal SU from a control circuit (not shown) via the inverter 4AU. The output signal of the inverter 4AU is input to the output circuit 34 that functions as a buffer via the photocoupler 32 and the amplifier 33.
The output circuit 34 includes a complementary pair of transistors connected between the positive electrode and the negative electrode of the power supply unit 31. When the command signal SU commands the gate-on and when the gate-off command, the output circuit 34 has a gate-on signal (about + 15V) and a gate-off signal (about -15V) are output between the terminals 35 and 36. The terminal 36 is connected to the intermediate pole (0 V) of the power supply unit 31.
The terminal 35 is connected to the terminal 25 of the power module 2A via the gate resistor 41 and the diode 42, and the terminal 36 is connected to the terminal 26 of the power module 2A. The gates and emitters of the power semiconductor element 21 are connected to the terminals 25 and 26 of the power module 2A, respectively. Therefore, the gate drive signal (gate on signal or gate off signal) output from the gate drive circuit 30 is the power It is input between the gate and emitter of the semiconductor element 21.
　ゲート駆動モジュール３Ａの他方のゲート駆動回路３０ＡＬも同様の構成を有する。このゲート駆動回路３０ＡＬは、上記制御回路からの下アーム用指令信号ＳＬをインバータ４ＡＬを介して入力するので、この指令信号ＳＬの指令に対応するゲート駆動信号をパワーモジュール２Ａの下アーム側のパワー半導体素子２２のゲート・エミッタ間に出力する。 The other gate drive circuit 30AL of the gate drive module 3A has the same configuration. Since the gate drive circuit 30AL receives the lower arm command signal SL from the control circuit via the inverter 4AL, the gate drive signal corresponding to the command of the command signal SL is supplied to the power on the lower arm side of the power module 2A. Output between the gate and emitter of the semiconductor element 22.
　ゲート駆動モジュール３Ｂは、ゲート駆動モジュール３Ａのゲート駆動回路３０ＡＵ，３０ＡＬと同一の構成を有するゲート駆動回路３０ＢＵ，３０ＢＬを備えている。
　ゲート駆動回路３０ＢＵ，３０ＢＬは、それぞれ指令信号ＳＵ，ＳＬをインバータ４ＢＵ，４ＢＬを介して入力する。従って、ゲート駆動回路３０ＢＵは、指令信号ＳＵの指令に対応するゲート駆動信号をパワーモジュール２Ｂの上アーム側パワー半導体素子２１に出力し、また、ゲート駆動回路３０ＢＬは、指令信号ＳＬの指令に対応するゲート駆動信号をパワーモジュール２Ｂの下アーム側パワー半導体素子２２に出力する。 The gate drive module 3B includes gate drive circuits 30BU and 30BL having the same configuration as the gate drive circuits 30AU and 30AL of the gate drive module 3A.
The gate drive circuits 30BU and 30BL receive the command signals SU and SL via the inverters 4BU and 4BL, respectively. Therefore, the gate drive circuit 30BU outputs a gate drive signal corresponding to the command of the command signal SU to the upper arm side power semiconductor element 21 of the power module 2B, and the gate drive circuit 30BL corresponds to the command of the command signal SL. The gate drive signal to be output is output to the lower arm side power semiconductor element 22 of the power module 2B.
　ここで、ゲート駆動回路３０ＡＵの端子３６からパワーモジュール２Ａの端子２６に至るラインと、ゲート駆動回路３０ＢＵの端子３６からパワーモジュール２Ｂの端子２６に至るラインとが分離していないとすると、これらのラインは、パワーモジュール２Ａの端子２７から負荷４に至るラインと、パワーモジュール２Ｂの端子２７から負荷４に至るラインと共にループ回路を構成することになる。
　この場合、パワーモジュール２Ａの端子２７から負荷４に至るラインの配線インダクタンスに基づいて誘起される電圧と、パワーモジュール２Ｂの端子２７から負荷４に至るラインの配線インダクタンスに基づいて誘起される電圧との差に基づくループ電流が上記ループ回路に流れることになる。そして、このループ電流は、結果的にパワーモジュール２Ａのパワー半導体素子２１のゲート電圧とパワーモジュール２Ｂのパワー半導体素子２１のゲート電圧の差をもたらすので、ターンオンタイミングについての誤動作を招く要因になる。 Here, if the line from the terminal 36 of the gate drive circuit 30AU to the terminal 26 of the power module 2A and the line from the terminal 36 of the gate drive circuit 30BU to the terminal 26 of the power module 2B are not separated, The line constitutes a loop circuit together with a line from the terminal 27 of the power module 2A to the load 4 and a line from the terminal 27 of the power module 2B to the load 4.
In this case, a voltage induced based on the wiring inductance of the line from the terminal 27 of the power module 2A to the load 4 and a voltage induced based on the wiring inductance of the line from the terminal 27 of the power module 2B to the load 4 A loop current based on the difference flows in the loop circuit. This loop current results in a difference between the gate voltage of the power semiconductor element 21 of the power module 2A and the gate voltage of the power semiconductor element 21 of the power module 2B, which causes a malfunction in turn-on timing.
　しかし、本実施形態に係る電力変換装置によれば、ゲート駆動回路３０ＡＵの端子３６からパワーモジュール２Ａの端子２６に至るラインと、ゲート駆動回路３０ＢＵの端子３６からパワーモジュール２Ｂの端子２６に至るラインとが分離されているので、つまり、パワーモジュール２Ａ、２Ｂにおける各パワー半導体素子２１のゲート電流の帰路が互いに分離されているので、上記のようなループ回路が構成されることがなく、従って動作の信頼性が向上する。 However, according to the power converter according to the present embodiment, a line from the terminal 36 of the gate drive circuit 30AU to the terminal 26 of the power module 2A, and a line from the terminal 36 of the gate drive circuit 30BU to the terminal 26 of the power module 2B. Are separated from each other, that is, the return paths of the gate currents of the power semiconductor elements 21 in the power modules 2A and 2B are separated from each other. Reliability is improved.
　図２に本発明の他の実施形態を示す。本実施形態に係る電力変換装置は、図１に示した電力変換装置と次の点で相違する。
　すなわち、本実施形態に係る電力変換装置は、図１に示すインバータ４ＢＵ，４ＢＬが省略されている点と、ゲート駆動回路３０ＡＵの増幅器３３の出力端子とゲート駆動回路３０ＢＵのバッファ３４の入力端子とが配線５１によって接続されている点と、ゲート駆動回路３０ＡＵの電源３１の負極とゲート駆動回路３０ＢＵの電源３１の負極とが配線５２によって接続されている点と、ゲート駆動回路３０ＡＬとゲート駆動回路３０ＢＬ相互間において上記に準じた接続がなされている点と、において図１に示した電力変換装置と相違している。 FIG. 2 shows another embodiment of the present invention. The power converter according to this embodiment is different from the power converter shown in FIG. 1 in the following points.
That is, in the power conversion device according to the present embodiment, the inverters 4BU and 4BL shown in FIG. 1 are omitted, the output terminal of the amplifier 33 of the gate drive circuit 30AU, and the input terminal of the buffer 34 of the gate drive circuit 30BU. Are connected by a wiring 51, the negative electrode of the power supply 31 of the gate drive circuit 30AU and the negative electrode of the power supply 31 of the gate drive circuit 30BU are connected by a wiring 52, and the gate drive circuit 30AL and the gate drive circuit. It differs from the power converter shown in FIG. 1 in that connection according to the above is made between 30BL.
　本実施形態に係る電力変換装置によれば、指示信号ＳＵを伝達する伝達回路要素（フォトカプラ３２及び増幅器３３）がゲート駆動回路３０ＡＵ，３０ＢＵによって共用され、指示信号ＳＬを伝達する伝達回路要素がゲート駆動回路３０ＡＬ，３０ＢＬによって共用される。従って、ゲート駆動モジュール３Ａ，３Ｂから出力されるゲート駆動信号相互の同期性が向上し、結果的に、パワーモジュール２Ａ，２Ｂの動作の同期性が向上する。
　なお、上記各実施形態では、パワーモジュールの並列接続数が２であるが、本発明はこの並列接続数が３以上の場合においても適用することができる。 According to the power conversion device according to the present embodiment, the transmission circuit elements (the photocoupler 32 and the amplifier 33) that transmit the instruction signal SU are shared by the gate drive circuits 30AU and 30BU, and the transmission circuit element that transmits the instruction signal SL is provided. It is shared by the gate drive circuits 30AL and 30BL. Therefore, the synchronism between the gate drive signals output from the gate drive modules 3A and 3B is improved, and as a result, the synchronism of the operations of the power modules 2A and 2B is improved.
In each of the above embodiments, the number of parallel connections of the power modules is 2, but the present invention can also be applied when the number of parallel connections is 3 or more.
　１　直流電源
　２Ａ，２Ｂ　パワーモジュール
　２１，２２　パワー半導体素子
　２３，２４　フリーホイール・ダイオード
　３Ａ，３Ｂ　ゲート駆動モジュール
　３０ＡＵ，３０ＡＬ　ゲート駆動回路
　３１　電源部
　３２　フォトカプラ
　３３　増幅器
　３４　出力回路
　４　負荷
　４１　ゲート抵抗
　４２　ダイオード
　５１，５２　ライン DESCRIPTION OF SYMBOLS 1 DC power supply 2A, 2B Power module 21, 22 Power semiconductor element 23, 24 Freewheel diode 3A, 3B Gate drive module 30AU, 30AL Gate drive circuit 31 Power supply part 32 Photocoupler 33 Amplifier 34 Output circuit 4 Load 41 Gate resistance 42 Diode 51,52 lines

Claims (3)

  1. 　並列接続されたパワー半導体素子を個別のゲート駆動回路を用いて制御する電力変換装置であって、
    　前記各ゲート駆動装置は、前記各パワー半導体素子のゲート電流の帰路が互いに分離されるように構成されていることを特徴とする電力変換装置。     A power conversion device for controlling power semiconductor elements connected in parallel using individual gate drive circuits,
    Each of the gate driving devices is configured such that the return paths of the gate currents of the power semiconductor elements are separated from each other.
  2. 　前記各ゲート駆動回路は、指示信号を伝達する伝達回路要素と、この伝達回路要素から出力される信号に応じて作動する出力回路とを備え、前記各ゲート駆動回路の前記伝達回路要素を共通化したことを特徴とする請求項１に記載の電力変換装置。 Each of the gate driving circuits includes a transmission circuit element that transmits an instruction signal and an output circuit that operates according to a signal output from the transmission circuit element, and the transmission circuit elements of the gate driving circuits are shared. The power conversion device according to claim 1, wherein:
  3. 　前記出力回路は、対応する前記パワー半導体素子のゲートに対して所定の順バイアス電圧と逆バイアス電圧を選択的に出力するように構成されていることを特徴とする請求項２に記載の電力変換装置。 3. The power conversion according to claim 2, wherein the output circuit is configured to selectively output a predetermined forward bias voltage and a reverse bias voltage to a gate of the corresponding power semiconductor element. apparatus.
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DE102022201640A1 (en) 2022-02-17 2023-08-17 Zf Friedrichshafen Ag Low-impedance clamp circuit for a semiconductor switching element in a power converter

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CN108258885A (en) * 2016-12-28 2018-07-06 上海沪工焊接集团股份有限公司 Inversion welding source drive dynamic control device
WO2020219857A1 (en) 2019-04-25 2020-10-29 Magna International Inc. Motor drive topologies for traction and charging in electrified vehicles
EP3915188A4 (en) * 2019-04-25 2022-05-18 Magna International Inc. Motor drive topologies for traction and charging in electrified vehicles

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