WO2013143284A1

WO2013143284A1 - Transistor and manufacturing method thereof, array substrate and display

Info

Publication number: WO2013143284A1
Application number: PCT/CN2012/083987
Authority: WO
Inventors: 谢春燕; 张卓
Original assignee: 京东方科技集团股份有限公司
Priority date: 2012-03-30
Filing date: 2012-11-02
Publication date: 2013-10-03
Also published as: CN102629665B; CN102629665A

Abstract

Embodiments of the present invention provide a transistor and a manufacturing method thereof, an array substrate and a display. The transistor comprises: a substrate; an active layer and a source/drain layer stacked on the substrate, the source/drain layer comprising a source and a drain that are spaced from each other, and the active layer forming a channel area at the part corresponding to the space between the source and the drain electrode; an insulating layer, formed on the stacked active layer and source/drain layer and comprising a micropore area corresponding to the channel area, the micropore area comprising a micropore running through the insulating layer; and at least one gate layer being formed on the micropore area, the gate layer not covering the micropore in the micropore area.

Description

Transistor and manufacturing method thereof, array substrate and display

Embodiments of the present invention relate to a transistor and a method of fabricating the same, an array substrate, and a display. Background technique

Organic Thin Film Transistors (OTFTs) are favored by users because of their small size, light weight, low manufacturing cost, strong resilience and easy preparation in large areas.

The OTFTs are mainly composed of a semiconductor active layer, an insulating layer, a gate electrode layer, a source electrode layer, and a drain electrode layer. Due to the different arrangement of the above layers, the OTFTs have different structures, including the following two structures:

The first type, the top gate bottom contact structure shown in FIG. 1A; the order of the layers in the structure on the substrate is from bottom to top: Substrate (Sub) 11, organic semiconductor (OSC) layer 12, source (Source, S) 13, drain (Drain, D) 14, insulating layer 15 and gate (G, G) 16;

Secondly, the top gate top contact structure as shown in FIG. 1B; the order of the layers on the substrate in the structure is from bottom to top: Substrate (Sub) 11, Source (S) 13, A drain (Drain, D) 14, an organic semiconductor (OSC) layer 12, an insulating layer 15, and a gate (G, G) 16.

The working principle of the above OTFTs is as follows:

First, a digital signal is added to the source, that is, a Data signal. Second, a voltage is applied to the gate. When the voltage is greater than a certain value, the organic semiconductor layer starts to conduct, and carriers can be formed in the organic semiconductor layer. At this time, the digital signal added to the source metal layer is transferred to the drain metal layer by carriers.

The present inventors have found that, regardless of which of the above-described OTFTs are used, the carrier mobility of the organic thin film transistor is low due to limitations of the characteristics of the organic semiconductor material, and thus the application range of the OTFTs is limited. Summary of the invention

An embodiment of the present invention provides a transistor, including: a substrate; an active layer and a source/drain layer stacked on the substrate, the source/drain layer including a source and a drain spaced apart from each other, and The active layer forms a channel region at a portion corresponding to a space between the source and the drain; an insulating layer formed on the active layer and the source/drain layer of the stack, and includes a corresponding In the micropore region of the channel region, the micropore region includes micropores penetrating the insulating layer; and at least one gate layer formed on the micropore region, the gate layer is not covered Micropores in the microporous region.

Another embodiment of the present invention provides a method of fabricating a transistor, including: forming a stacked active layer and a source/drain layer on a substrate, the source/drain layer including a source and a drain spaced apart from each other, And the active layer forms a channel region at a portion corresponding to a space between the source and the drain; forming a micropore region on the stacked active layer and the source/drain layer The insulating layer; the micropore region is located at a portion of the insulating layer corresponding to the channel region, the micropore region includes micropores penetrating the insulating layer; and forming on the microporous region At least one gate layer, the gate layer not covering the microvias in the microporous region.

Yet another embodiment of the present invention provides an array substrate comprising a transistor in accordance with any of the embodiments of the present invention.

Yet another embodiment of the present invention provides a display comprising the array substrate as described above. DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .

1A is a schematic diagram of a top gate bottom contact structure of a transistor in the prior art;

1B is a schematic diagram of a top gate top contact structure of a transistor in the prior art;

2A is a schematic view showing a first structure of a transistor according to Embodiment 1 of the present invention;

2B is a schematic diagram of a second structure of a transistor according to Embodiment 1 of the present invention;

2C is a schematic view showing a third structure of a transistor according to Embodiment 1 of the present invention;

2D is a schematic view showing a fourth structure of a transistor according to Embodiment 1 of the present invention;

2E is a schematic view showing a fifth structure of a transistor according to Embodiment 1 of the present invention;

3A is a schematic structural diagram of a first reticle according to an embodiment of the present invention; 3B is a schematic structural view of a first reticle according to an embodiment of the present invention; FIG. 3C is a schematic structural diagram of a first reticle according to an embodiment of the present invention;

4A is a schematic diagram of a first structure of a transistor according to Embodiment 1 of the present invention;

4B is a schematic diagram showing a second structure of a transistor according to Embodiment 1 of the present invention;

4C is a schematic diagram showing a third structure of a transistor according to Embodiment 1 of the present invention;

4D is a fourth schematic structural diagram of a transistor according to Embodiment 1 of the present invention; and FIG. 4E is a schematic diagram of a fifth structure of a transistor according to Embodiment 1 of the present invention. detailed description

The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

The transistor provided by the embodiment of the present invention is formed by forming an insulating layer including a micropore region on a functional board (active layer and source/drain layer). The micropore region is located at a position corresponding to the channel region of the active layer. Since the micropore region includes a plurality of micropores, and at least one gate layer not covering the micropores is formed over the microporous region, the effect is equivalent to the superposition of a plurality of double gate structures, so that inside each of the micropores Both form a strong electric field. Therefore, the electric field effect of the microporous region is enhanced, so that the mobility of carriers is greatly improved. In one embodiment, the specific process for making a transistor is as follows:

Step 21, forming a functional board (including an active layer and a source/drain layer), the active layer including a channel region;

Step 22, forming an insulating layer including a micropore region on the function board, the micropore region being located at a position corresponding to the channel region, that is, an orthographic projection of the micropore region is located in the trench Road area i or inside;

Step 23, forming at least one gate layer on the micropore region, the gate layer not covering the microvia in the micropore region.

In one embodiment, the forming the functional board includes: forming a semiconductor layer on the substrate; forming a source/drain layer including a source and a drain on the semiconductor layer; the source is located in the semiconductor layer One side; the drain is located on the other side of the semiconductor layer. In this embodiment, at the source / An insulating layer including the micropore region is formed on the drain layer.

In one embodiment, the forming a function plate includes: forming a source/drain layer including a source and a drain on a substrate; the source is located at one side of the substrate; and the drain is located at the substrate The other side; a semiconductor layer is formed on the source/drain layer. In this embodiment, an insulating layer including the microporous regions is formed on the semiconductor layer.

That is, in the above two examples of forming the active layer and the source/drain layer, the source/drain layer may be formed either after the active layer to form the bottom contact structure or before the active layer. A top contact structure is formed. In either case, the source and drain in the source/drain layer are spaced apart from each other, and the portion of the active layer corresponding to the interval between the source and the drain becomes the channel region.

In one embodiment, in order to further strengthen the strength of the electric field in the micropore to better improve the mobility of the carrier, after the gate layer is formed, the method further includes: the exposed portion after forming the micropore region A thin layer of high conductivity is formed on the semiconductor layer (active layer).

In one embodiment, forming the semiconductor layer (active layer) comprises: forming the semiconductor layer by an inkjet printing process.

In one embodiment, forming the source/drain layer including the source region and the drain region includes: forming the source/drain layer including the source region and the drain region by an inkjet printing process.

In one embodiment, forming the insulating layer including the microvia region includes: forming an insulating layer material by an inkjet printing process, and forming a microvia region including the microvia in a portion of the insulating layer material corresponding to the channel region by a plasma processing process To form the insulating layer.

In one embodiment, forming a thin layer of high conductivity on the exposed semiconductor layer after forming the microvia region comprises: passing the plasma treatment process on the semiconductor layer exposed by the microvias in the microporous region A thin layer of high conductivity is formed.

The specific embodiments are described in more detail below with reference to the accompanying drawings:

Embodiment 1:

In the first embodiment, a first transistor is provided, which is an organic thin film transistor having a top gate bottom contact, and the specific process is as follows:

In the first step, the active layer 32 and the source/drain layers 33 and 34 are formed.

First, as shown in FIG. 2A, a semiconductor layer 32 is formed on a substrate;

For example, the material of the substrate in this step may be selected from a plastic material, but is not limited thereto; for example, a semiconductor layer may be formed by various processes in this step, for example, by an inkjet printer Any process that can form a semiconductor layer on a substrate, art, printing process, and the like. For example, in this step, an inkjet printing process is selected to print a layer of organic semiconductor material on the substrate to form a semiconductor layer. The semiconductor layer material which can be used is, for example, a polymer of 3-hexylthiophene (P3HT), a single-walled carbon nanotube or the like, and preferably P3HT. The thickness of the semiconductor layer is, for example, about 30 nm to 200 nm, for example, 50 nm is selected in the present embodiment.

Then, as shown in Fig. 2B, source/drain layers 33 and 34 (e.g., including source 33 and drain 34) are formed on the semiconductor layer 32. The source 33 is located on one side of the semiconductor layer 32; the drain 34 is located on the other side of the semiconductor layer 32. The source 33 and the drain 34 are spaced apart from each other, and a portion of the active layer 32 corresponding to the interval between the source 33 and the drain 34 becomes a channel region.

For example, in this step, a layer of electrode material may be printed on the semiconductor layer by an inkjet printing process to form a source/drain layer including a source 33 and a drain 34.

The electrode material may be selected from materials having a conductive function, such as a polythiophene derivative, polyethylene dioxythiophene (PEDOT) and sodium polystyrene sulfonate (Pss), which can be adjusted by adjusting the ratio of the two materials. Adjust the resistance value to form the source and drain.

Step 2, as shown in FIG. 2C, forming an insulating layer including a microporous region on the source/drain layer

35. The micropore region is located in a region between the source 33 and the drain 34, i.e., a position corresponding to the channel region. The material used for the insulating layer may be any material having an insulating function and which can be used in an organic transistor. Preferably, polyvinylpyrrolidone (pvp) can be used. The micropores in the microporous region penetrate the insulating layer 35 to expose the underlying active layer 32.

For example, there may be various processes for forming an insulating layer on the source/drain layer in this step. Preferably, the insulating layer material may be printed on the source/drain layer by an inkjet printing process; The nanopore mask is formed using a plasma processing process to form the insulating layer including the microporous regions.

For example, the pore size of the nanopores on the reticle can be from 300 nm to 1000 nm, and can be set according to actual conditions. The size and shape of the nanopores formed on the insulating layer may be equal or unequal; and the number and arrangement of the nanopores may also be set according to actual conditions; specifically, the masks shown in FIG. 3A to FIG. 3C may be selected according to actual conditions. template. For example, the mask shown in Fig. 3A can be selected in order to realize the micropore region by a relatively simple process.

Step 3, as shown in FIG. 2D, at least one gate layer is formed on the microvia region, and the gate layer does not cover the microvia in the microvia region, that is, on the microvia region, the gate layer Only formed on the insulating layer between the holes. For example, in this step, one or more gate layers may be formed at specified positions on the microvia region; when there are multiple gate layers, all gate layers may be connected or disconnected or partially connected to each other. . For example, the gate layers may be integrally connected, and the transistor only needs to apply a driving signal to the gate during operation; or the gate layers may be disconnected from each other, not integrally connected, and respectively, separate gates are required. Applying a drive signal, this can have an effect similar to multiple gates.

For example, the shape of the gate layer can be selected to be the shape of the mask shown in Fig. 3A.

For example, in order to obtain a better mobility, the embodiment may further include step five, and step five is performed after step four;

Step 5, as shown in FIG. 2E, a thin layer of high conductivity is formed on the semiconductor layer exposed by the micropores of the insulating layer; at this time, the high conductivity thin layer has strong activity;

For example, in this step, the semiconductor layer exposed by the micropores may be processed by using a plasma processing process, thereby forming a thin layer of high conductivity inside the exposed portion of the semiconductor layer; the thin layer forming the high conductivity may be Reduce the resistance and increase the current effect in the channel.

Embodiment 2:

In the second embodiment, a second transistor is provided, which is an organic thin film transistor having a top gate top contact, and the specific process is as follows:

Step one, forming source/drain layers 52 and 53 and active layer 54:

First, as shown in Fig. 4A, a source/drain layer including a source 52 and a drain 53 is formed on a substrate. The source 52 is located on one side of the substrate; the drain 53 is located on the other side of the substrate. Source 52 and drain 53 are spaced apart from one another.

For example, in this step, a layer of electrode material may be printed on the substrate by an inkjet printing process to form a source/drain layer including the source 52 and the drain 53; the source/drain layer may select a material having a conductive function. Specifically, polythiophene derivatives (PEDOT) and sodium polystyrene sulfonate (Pss), which can be adjusted by adjusting the ratio of the two materials, form a source and a drain.

Then, as shown in Fig. 4B, a semiconductor layer 54 is formed on the source/drain layers 52 and 53, and a region of the semiconductor layer 54 corresponding to the interval between the source 52 and the drain 53 becomes a channel region.

For example, in this step, a semiconductor layer can be formed by various processes, specifically, any process that can form a semiconductor layer on a substrate by an inkjet printing process, a printing process, or the like. For example, in this step, an inkjet printing process is selected to print a layer of organic semiconductor material on the substrate on which the active/drain layer is formed to form a semiconductor layer. The semiconductor material that can be used is a polymer of 3-hexylthiophene (P3HT), single wall An organic semiconductor material such as carbon nanotubes is preferably P3HT. The thickness of the semiconductor layer is, for example, approximately 30 nm to 200 nm, and 50 nm is selected in the present embodiment.

Step 2, as shown in FIG. 4C, forming an insulating layer including a microporous region on the semiconductor layer; the micropore region is located in a region between the source 52 and the drain 53; that is, the microvia region Corresponding to the channel region of the active layer 54; that is, the orthographic projection of the microvia region is located in the channel region of the active layer 54. The material used for the insulating layer may be any material having an insulating function and which can be used in an organic transistor. Preferably, polyvinylpyrrolidone (pvp) can be used.

For example, there may be various processes for forming an insulating layer material on the source/drain layer in this step. Preferably, the insulating layer material may be printed on the semiconductor layer by an inkjet printing process; The mask of the hole is formed using an plasma treatment process to form an insulating layer including a microporous region.

For example, the pore size of the nanopores on the reticle is from 300 nm to 1000 nm, which may be specifically set according to actual conditions. Therefore, the size and shape of the nanopores formed on the insulating layer may be equal or unequal; The number and arrangement of the holes can also be set according to actual conditions; specifically, the mask plates shown in FIG. 3A to FIG. 3C can be selected according to actual conditions. For example, the mask shown in Fig. 3A can be selected in order to realize the micropore region by a relatively simple process.

Step 3, as shown in FIG. 4D, at least one gate layer 56 is formed on the microvia region; the gate layer does not cover the microvias in the microvia region, that is, in the microvia region, the gate layer 56 is only Formed on the insulating layer between the micropores.

Specifically, in this step, a plurality of gate layers may be formed at a specified position on the microvia region; when there are multiple gate layers, all gate layers may be connected or disconnected or partially gate layers Connected. For example, the gate layers may be integrally connected, and the transistor only needs to apply a driving signal to the gate during operation; or the gate layers may be disconnected from each other, not integrally connected, and respectively, separate gates are required. Applying a drive signal, this can have an effect similar to multiple gates.

Step 5, as shown in FIG. 4E, a thin layer of high conductivity is formed in the semiconductor layer exposed by the nanopores of the insulating layer; the high conductivity thin layer has strong activity at this time;

For example, in this step, the semiconductor layer exposed by the micropores may be processed by using a plasma processing process, thereby forming a high conductivity thin layer inside the exposed portion of the semiconductor layer; Forming a thin layer of high conductivity reduces resistance and increases current effects in the channel.

Preferably, any of the above embodiments may have an insulating layer with a microporous region by any method, and only the micropore region is located in the channel region, and may include, but is not limited to, the following methods:

First forming a source/drain metal layer; laying an insulating material on the source/drain metal layer, etching a location where a channel region needs to be formed, etching away the source/drain metal layer at the channel location, and Insulating material, the channel region is formed at this time; the insulating material is laid again in the channel region, and the thickness of the laying is equal to the thickness of the first laying insulating material, and the second laying of the insulating material is processed to form a micro The hole region, at this time, forms an insulating layer including the microporous region. An orthographic projection of the micropore region is located within the channel region.

The positional relationship of the noun "on" for indicating the orientation in the above embodiment may include, but is not limited to, the following:

First, the second layer is on the first layer, and the second layer is adjacent to the first layer;

Second, the second layer is on the first layer, but the second layer is separated from the first layer by another layer; third, the second layer is on the first layer, and the second layer partially or entirely covers the first layer.

As shown in FIG. 2E and FIG. 4E, an embodiment of the present invention provides a transistor, the transistor including: a function board including an active layer and a source/drain layer on a substrate, and an active layer at the source/drain Above or below the layer, the source and the drain in the source/drain layer are spaced apart from each other, and a region of the active layer corresponding to the interval between the source and the drain is a channel region;

An insulating layer, the insulating layer includes a micropore region; the insulating layer is located on the function board, and the micropore region is located at a position corresponding to the channel region, that is, an orthographic projection of the micropore region Located in the channel region;

At least one gate layer is included on the microvia region, the gate layer not covering the pupil in the microwell region.

In one embodiment, the transistor may further include: a high conductivity thin layer formed on the semiconductor layer exposed by the microvia region of the insulating layer.

In one embodiment, the microporous region comprises one or more microwells of the same or different shape.

An array substrate is further provided according to an embodiment of the present invention, and the array substrate includes the above crystal Body tube.

There is further provided, in accordance with an embodiment of the invention, a display comprising the transistor described above or comprising an array substrate as described above.

The transistor provided in the embodiment of the present invention is formed by forming an insulating layer including a micropore region on a functional board (including an active layer and a source/drain layer); the micropore region is located corresponding to a channel region of the active layer. In part, that is, the orthographic projection of the micropore region is located within the channel region. Since the micropore region includes a plurality of micropores, and at least one uncovered microporous gate layer is formed on the microporous region, the effect is equivalent to the superposition of a plurality of double gate structures, so that inside each micropore A strong electric field is formed. Therefore, the electric field effect of the microporous region is strengthened, so that the mobility of carriers is greatly improved.

In order to further strengthen the strength of the electric field in the micropore to better improve the mobility of the carrier, after forming the gate layer, further comprising: forming a thin layer of high conductivity on the exposed semiconductor layer after forming the microporous region .

The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

Claim

1. A transistor comprising:

Substrate

An active layer and a source/drain layer stacked on the substrate, the source/drain layer including a source and a drain spaced apart from each other, and the active layer is corresponding to the source and the drain The portion between the spaces forms a channel region i or;

An insulating layer formed on the active layer and the source/drain layer of the stack, and including a micropore region corresponding to the channel region, the micropore region including micro through the insulating layer a hole; and at least one gate layer formed on the micropore region, the gate layer not covering the microvia in the micropore region.

The transistor of claim 1, wherein the active layer is formed of a semiconductor layer, and the source/drain layer is over the semiconductor layer.

The transistor of claim 1, wherein the active layer is formed of a semiconductor layer, and the semiconductor layer is over the source/drain layer.

4. The transistor of any of claims 1-3, further comprising:

A high conductivity thin layer is disposed on the semiconductor layer exposed by the micropores in the microporous region of the insulating layer.

The transistor according to any one of claims 1 to 4, wherein the microporous region comprises one or more micropores of the same or different shape.

The transistor according to any one of claims 1 to 5, wherein the pores in the microporous region have a pore size of from 300 nm to 1000 nm.

7. A method of fabricating a transistor, comprising:

Forming a stacked active layer and a source/drain layer on the substrate, the source/drain layer including source and drain spaced apart from each other, and the active layer corresponding to the source and the drain The portion between the poles forms a channel region i or;

Forming an insulating layer including a microporous region on the stacked active layer and the source/drain layer; the micropore region is located at a portion of the insulating layer corresponding to the channel region, the micro a microvia extending through the insulating layer in the hole region;

Forming at least one gate layer on the microvia region, the gate layer not covering the microvia region Micropores in the domain.

8. The method of claim 7, wherein forming the stacked active layer and source/drain layers comprises:

Forming a semiconductor layer on the substrate to form the active layer;

The source/drain layer is formed on the semiconductor layer.

9. The method of claim 7, wherein forming the stacked active layer and source/drain layers comprises:

Forming the source/drain layer on the substrate;

The method according to any one of claims 7 to 9, wherein after forming the gate layer, further comprising:

A high conductivity thin layer is formed on the semiconductor layer exposed by the microvias in the microporous region.

11. The method of claim 8 or 9, wherein forming the semiconductor layer comprises: forming the semiconductor layer by an inkjet printing process.

12. The method of claim 8 or 9, wherein forming the source/drain layer comprises: forming the source/drain layer by an inkjet printing process.

13. The method of any of claims 7-12, wherein forming the insulating layer comprising a microvia region comprises:

Forming an insulating layer material by an inkjet printing process;

A microporous region including micropores is formed in a portion of the insulating layer material corresponding to the channel region by a plasma treatment process to form the insulating layer.

14. The method of claim 10, wherein forming the high conductivity thin layer comprises: forming the high by a plasma processing process on the semiconductor layer exposed by the microvias in the microporous region A thin layer of conductivity.

An array substrate comprising the transistor of any one of claims 1-6.

16. A display comprising the array substrate of claim 15.