WO2013143273A1 - 一种降低读延时的方法及装置 - Google Patents

一种降低读延时的方法及装置 Download PDF

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Publication number
WO2013143273A1
WO2013143273A1 PCT/CN2012/082964 CN2012082964W WO2013143273A1 WO 2013143273 A1 WO2013143273 A1 WO 2013143273A1 CN 2012082964 W CN2012082964 W CN 2012082964W WO 2013143273 A1 WO2013143273 A1 WO 2013143273A1
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Prior art keywords
data
read
error
flash
flash chip
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PCT/CN2012/082964
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English (en)
French (fr)
Inventor
李延松
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华为技术有限公司
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Priority to EP12872554.6A priority Critical patent/EP2811392B1/en
Publication of WO2013143273A1 publication Critical patent/WO2013143273A1/zh
Priority to US14/474,502 priority patent/US9542271B2/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G06F11/1088—Reconstruction on already foreseen single or plurality of spare disks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G06F11/108—Parity data distribution in semiconductor storages, e.g. in SSD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G06F11/1092—Rebuilding, e.g. when physically replacing a failing disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G06F11/167—Error detection by comparing the memory output
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/26—Using a specific storage system architecture
    • G06F2212/261—Storage comprising a plurality of storage devices
    • G06F2212/262—Storage comprising a plurality of storage devices configured as RAID
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7208—Multiple device management, e.g. distributing data over multiple flash devices

Definitions

  • the invention belongs to the technical field of data storage, and relates to a method and device for reducing read delay.
  • the data carriers commonly used in the storage field are mechanical hard disks and solid-state hard disks (SSDs). Due to the high performance, low latency, low power consumption, and strong environmental adaptability of SSDs, the cost is also decreasing. universal.
  • a NAND flash internally includes one or more wafers, each wafer including a plurality of planes, each plane including a plurality of blocks, each block including a plurality of pages.
  • the page is the basic unit for reading and writing data, including multiple bytes (for example, 2048+64 bytes), where +16 bytes per 512 bytes is an error detection/correction unit, and 512 bytes is used to save data. , 16 bytes are used to save the error detection/error correction code.
  • each 512+16-byte unit will be verified. If the number of errors is small, it can be corrected. If there are too many incorrect bits, you cannot use the upper-level error correction mechanism such as RAID. Algorithm to solve.
  • a block of NAND flash is a basic erase unit, and each block includes a plurality of pages (for example, 64).
  • the block in which the data is located must be erased before the new data can be written. This is the basic feature of flash.
  • the SSD needs to continuously perform an erase or write operation during the work process, and the flash chip is busy when performing these two operations (represented by the hardware pin R/B# of the chip, the high level indicates that it is ready, low power Flat means busy), can no longer respond to read operations, and can only continue to perform read operations after waiting for the erase or write operation to complete. Since the block erase of the NAND flash chip generally takes 3ms, the write operation generally requires 900us, and the read operation generally only needs 50us, so the erase and write operations will block the read operation, resulting in a large read delay, affecting the performance of the storage system. This phenomenon is more pronounced in scenes where erasing or writing operations are particularly frequent.
  • the invention solves the problem that the existing flash chip-based storage device is blocked by the erasing and writing operations when the read, write, and erase are simultaneously existed, thereby causing a problem of large read delay, and providing a reduction.
  • Method and device for reading delay is provided.
  • Embodiments of the present invention provide a method of reducing read latency, including:
  • the data read by the one or more flashes in the busy state is set as erroneous data
  • the reconstructed correct data is obtained based on the erroneous data and data read from other flash chips, and the correct data is reported.
  • Embodiments of the present invention also provide an apparatus for reducing read latency, including:
  • the error-reading unit is configured to: when the one or more flash chips corresponding to the read command are in a busy state, set the data read by the one or more flashes in the busy state to the wrong data; And a reconstruction reporting unit, configured to obtain the reconstructed correct data according to the erroneous data and data read from other flash chips, and report the correct data.
  • the data read from the flash chip is set as erroneous data, and the reconstructed data is obtained according to the erroneous data and the data read from other flash chips.
  • the correct data when the flash chip is busy, can prevent the read operation from being erased and the write operation is blocked, thereby effectively reducing the delay and improving the performance of the storage system.
  • FIG. 1 is a schematic structural diagram of an SSD device combined with a specific hardware according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of an SSD controller according to an embodiment of the present invention.
  • FIG. 3 is a block diagram showing an overall process of a method for reducing read latency according to an embodiment of the present invention
  • FIG. 4 is a schematic flowchart of a method for reducing a read delay according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of a SSD device based on a RAID controller according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of a SSD controller based on a RAID controller according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of an apparatus for reducing read delay according to an embodiment of the present invention.
  • the embodiment provides a method for reducing the read latency, including: when the one or more flash chips corresponding to the read command are in a busy state, the data read on one or more flashes in a busy state is set to Wrong data; obtaining reconstructed correct data based on the erroneous data and data read from other flash chips, and reporting the correct data.
  • the technical solution provided in this embodiment is mainly applied to an SSD device composed of a host, an SSD controller, and a plurality of channels of flash, and the corresponding host reads and writes data in the flash through the SSD controller.
  • the hardware structure of the SSD device includes a server chassis, and a bottom plate is arranged in the server frame.
  • the CPU, the memory, the south bridge and the like are mounted on the bottom plate, and are used for controlling other expansion cards to implement the functions of the host;
  • the SSD controller (controls the internal flash of the SSD) can also use chips, such as FPGAs, ASICs, etc., to program the chip to complete the read and write requests of the receiving host, and to perform various accesses to the flash chip in the SSD device.
  • the corresponding chip of the SSD controller can be set on a PCB board with each flash, connected by PCB traces, and finally presented in the form of a hard disk box, connected to the backplane through a SATA or SAS interface, or can also be flashed
  • the chip and the SSD controller are formed as an expansion card and connected to the backplane through the PCIe interface.
  • the structure of a SSD device combined with specific hardware is shown in Figure 1.
  • the structure of the SSD controller is shown in Figure 2, including the host interface, error detection/correction module, and transceiver module.
  • the corresponding host interface is used to receive various commands and corresponding responses from the host.
  • the address, data such as reading the data of an address or writing the data to an address, etc., the current common interface is SATA, SAS, PCIe;
  • the transceiver module is used to complete the transmission and reception of data or commands; error detection / error correction module It is used to ensure the correctness of the data from the flash, and then report the data to the host. It mainly performs two functions: 1. Error detection and correction of the data of each flash channel and its check code. If the error correction capability is exceeded.
  • FIG. 3 is a block diagram showing the overall flow of the method for reducing the read delay provided by this embodiment.
  • the method includes:
  • Step 41 When one or more flash chips corresponding to the read command are in a busy state, the data read on one or more flashes in a busy state is set as erroneous data.
  • the flash chip corresponding to the address information is determined according to the address information included in the read command, that is, the strips corresponding to the flash chips.
  • the current state of the flash chip corresponding to the address information is also queried, that is, whether it is in a busy state. If the current state of a flash chip is idle, the data of the flash chip read is directly reported to the error detection/correction module of the SSD device; if one of the flash chips is in a busy state, the flash chip will be from the flash chip.
  • the data is subjected to error processing so that the data forwarded to the error detection/correction module does not conform to the verification rule inside the flash chip.
  • the transceiver module constructs a data that does not satisfy the even parity requirement, and allows the error detection/correction module to detect the error, thereby triggering the module to execute a RAID algorithm to correct the channel flash. Wrong data for the chip.
  • the free/busy state of the flash chip of each channel can be implemented by software mode, hardware mode or a combination of software and hardware, specifically:
  • a status register is provided inside the NAND flash.
  • the value of the register can be obtained by the chip status read command (read status).
  • the free/busy status of the flash chip can be known according to the 0 and 1 status of the specified bit. .
  • the NAND flash chip also provides an R/B# signal, which can be connected to the SSD controller.
  • the busy/busy state of the flash chip can be known by querying the level state of the corresponding signal.
  • R / B # signal is a drain open output, can support the connection mode of the line, you can connect the signal of all the flash chips of the same channel, and then access the controller, so the total number of signal lines will A lot less.
  • the SSD controller can know whether a flash chip is busy in a certain channel, and then use the read status command to distinguish which flash chip is busy under the channel. If the flash chip where the data is to be read is in an idle state, the data can be directly read; if the flash chip in which it is located is busy, the read data is set to the wrong data.
  • the initiation of the status query command (read status) of the flash chip is not affected by the busy/busy state of the chip. If the status query command is sent by the host, after the transceiver module obtains the status of the flash chip on the corresponding channel, Without error detection/correction The processing of the module is reported directly to the host because the status information is not processed by the RAID algorithm.
  • the internal verification rules of the flash chip can also use Hamming codes with error detection and error correction capabilities, and the generated error data can have many options, which can be determined in advance when designing the controller. This is because the flash chip is in a busy state and cannot respond to commands that read data. The command is ignored, so that the data read by the SSD controller is indeterminate, possibly through the error detection/correction module check, or through However, if the former case occurs, invalid data is reported as correct data, so in order to ensure reliability, it is necessary to construct incorrect data.
  • Step 42 Obtain the reconstructed correct data according to the erroneous data and data read from other flash chips, and report the correct data.
  • the error detection/correction module of the SSD device checks the data of each channel separately. If the error data is detected, it is corrected by the RAID algorithm, otherwise it is directly reported to the host. When the error detection/correction module detects that there is an error in the data read from the flash in the busy state, it will be corrected by the corresponding RAID algorithm, and then reported to the host together with the reconstruction data obtained from the other channels to complete the corresponding reading. operating.
  • the error detection/correction module After the error detection/correction module finds that the data of a certain channel is in error and corrects it, it usually performs error statistics. When a certain threshold is exceeded, it will report to the host, requesting to replace the entire SSD (for the case where the flash chip cannot be replaced separately) For example, soldering on the backplane) or replacing the flash chip on a channel (for flash chips that can be replaced separately, for example, the flash chip on each channel forms a replaceable module). Since the channel data of the flash chip in the busy state is treated as erroneous data, and the flash chip of the channel does not malfunction, it is necessary to distinguish this situation from misjudgment. An identification bit can be defined in the transceiver module. The default is 0. Each time the module intentionally constructs error data and reports it to the error detection/correction module, the flag is set to 1, otherwise it is 0, so error detection/correction is performed. The module can decide whether to add value to the error counter based on this flag.
  • the data reconstruction capability of the MID algorithm is limited.
  • RAID5 can only correct errors on one channel, so it must be based on
  • the specific AID algorithm limits the number of flash chips that are busy on each strip at any time, which is done by the transceiver module. It can control the number of erase and write commands issued to the flash chip on each channel, and query the free/busy state of the flash chip on each channel in real time to ensure the number of flash chips in each strip. Does not exceed the ability of the RAID algorithm to reconstruct data.
  • the error data corrected in step 42 is artificially created, the purpose is to reconstruct the data, and the problems of different sources can be uniformly processed.
  • the corresponding problem may be data error of the flash chip, or the flash chip is busy. Conducive to the reuse of modules.
  • This embodiment also provides a method for reducing read latency by using a RAID controller.
  • an SSD controller generally supports multiple channels, and multiple flash chips are connected to each channel, and RAID is Mode work.
  • multiple flash chips store data and check codes in a stripe manner according to the RAID algorithm. When a flash chip is unavailable, data that is read by other flash chips on the strip can be recovered, thereby improving reliability.
  • RAID MSD4 and RAID5 are commonly used in SSDs.
  • RAID4 is to store the check code in all flash chips of a certain channel
  • RAID5 is to save the check code one by one in all flashes of multiple channels. On the chip.
  • the RAID controller is also a commonly used device to improve the performance and reliability of the storage system. It is usually connected to the host through a PCI or PCIe interface, and then through multiple channels (for example, 8) and the hard disk. Connected (can be mechanically hard Disk or SSD), each channel uses SAS or FC interface and can only connect one hard disk, as shown in Figure 5. An example of a specific application scenario is shown in Figure 6.
  • One of the expansion cards in the rack server is a RAID card, the RAID card has a RAID controller, and the SSD hard disk box (including the SSD controller and multiple Flash) The SSD controller is connected; multiple expansion cards are still connected to the backplane through the PCIe interface.
  • the RAID controller saves data in stripes on multiple SSDs according to the RAID algorithm.
  • the SSD control must be performed between the RAID controller and the SSD according to the above embodiment.
  • the NAND flash chip to reconstruct the data that is: the RAID controller queries the free/busy state of each channel SSD through commands, and the SSD of the busy state, the data transceiver module inside the RAID controller, the data of the channel When it is set to error, it is reported to the error detection/correction module inside the RAID controller together with the valid data obtained by other channels.
  • the error detection/correction module inside the RAID controller detects the data of each channel first, and finds the above busy state. If the channel data is incorrect, the error data is reconstructed through the data of the other channel according to the RAID algorithm, and then reported to the host through the PCI/PCIe interface.
  • the data read from the ash chip is set as erroneous data, and the reconstructed correct data is obtained according to the erroneous data and the data read from other flash chips, so that the flash chip is enabled.
  • the busy state it can avoid the read operation being blocked by the erase and write operations, thereby effectively reducing the delay and improving the performance of the storage system.
  • An embodiment of the present invention further provides a device for reducing read latency, as shown in FIG. 7, comprising:
  • the error-reading unit 71 is configured to: when the one or more flash chips corresponding to the read command are in a busy state, set data read on one or more flashes in a busy state as erroneous data;
  • the reconstruction reporting unit 72 is configured to obtain the reconstructed correct data according to the erroneous data and the data read from other flash chips, and report the correct data.
  • an SSD controller (such as an FPGA or a similar hardware chip) or a RAID controller can be correspondingly programmed to obtain a unit module capable of performing the corresponding function.
  • the unit modules of the device for reducing the read delay may be disposed in the SSD controller as shown in FIG. 2, or may be disposed in the RAID controller as shown in FIG. 5.
  • the error-distributing unit 71 may include: a determining sub-unit, configured to detect a busy/idle signal level of each flash chip, issue a read status command, or simultaneously detect a busy/flash of each flash chip. The idle signal level and the issued read status command determine whether the flash chip is busy.
  • the read command for reading the flash chip data is received through the SATA, SAS or PCIe interface.
  • the error-reading unit 71 further includes: a read sub-unit, configured to determine, according to a correspondence between an address field carried in the read command message and a flash chip address in the SSD, the read command and the flash chip relationship.
  • the data that is set to be incorrect includes: setting the read data to any data combination that does not meet the flash data check rule.
  • the reestablishing and reporting unit 72 may include: a rebuilding subunit, where the SSD controller receives the sent error. After the data is detected and the data error is detected, the error correction function is started, and the reconstructed correct data is obtained by using the data constraint relationship existing between the plurality of sets of flash storage units.
  • the apparatus may further include: an error counting unit, configured to: when the read data error is detected and the flag is 0, the error counter is incremented by 1; when the read data error is detected and the flag is 1, the error counter is not change.
  • an error counting unit configured to: when the read data error is detected and the flag is 0, the error counter is incremented by 1; when the read data error is detected and the flag is 1, the error counter is not change.
  • the data read from the flash chip is set to the wrong data, and the reconstructed correct data is obtained according to the erroneous data and the data read from other flash chips, so that the flash chip is busy.
  • the state can prevent the read operation from being erased and the write operation is blocked, thereby effectively reducing the delay and improving the performance of the storage system.
  • inventive arrangements may be described in the general context of computer-executable instructions executed by a computer, such as a program element.
  • program units include routines, programs, objects, components, data structures, and the like that perform particular tasks or implement particular abstract data types.
  • inventive arrangements can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are connected through a communication network.
  • program units can be located in both local and remote computer storage media including storage devices.
  • the various embodiments in the specification are described in a progressive manner, and the same or similar parts between the various embodiments are referred to each other, and each embodiment focuses on differences from other embodiments.
  • the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.
  • the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, ie may be located One place, or it can be distributed to multiple network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment. Those of ordinary skill in the art can understand and implement without any creative effort.
  • the disclosed systems, devices, and methods may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not executed.
  • the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Can be based on Actually, some or all of the units need to be selected to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium.
  • the technical solution of the present invention which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a removable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and the like, which can store program codes. .
  • the present invention can be implemented by means of software plus necessary general hardware including general-purpose integrated circuits, general-purpose CPUs, general-purpose memories, general-purpose components, and the like.
  • dedicated hardware including an application specific integrated circuit, a dedicated CPU, a dedicated memory, a dedicated component, etc., but in many cases, the former is a better implementation.
  • the technical solution of the present invention which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a readable storage medium, such as a floppy disk of a computer.
  • a hard disk or optical disk, etc. includes instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the methods of various embodiments of the present invention.

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Abstract

一种降低读延时的方法及装置，相应的方法包括：当读命令对应的一个或多个flash芯片处于忙状态时，将处于忙状态的一个或多个flash上读取到的数据置为错误的数据；根据所述错误的数据以及从其它flash芯片上读取的数据获得重建后的正确数据，并将所述正确数据上报。本发明通过从flash芯片上读取到的数据置为错误的数据，并根据错误的数据以及从其它flash芯片上读取的数据获得重建后的正确数据，使flash芯片处于忙状态时能够避免读操作被擦除和写操作阻塞，从而有效减少延时，提高了存储系统的性能。

Description

一种降低读延时的方法及装置
本申请要求了 2012年 03月 30日提交的、 申请号为 201210095907· 1、 发明名称为 "一种降低 读延时的方法及装置" 的中国申请的优先权， 其全部内容通过引用结合在本申请中。
技术领域
本发明属于数据存储技术领域， 涉及一种降低读延时的方法及装置。
发明背景
存储领域常用的数据载体是机械硬盘和固态硬盘 (SSD)， 由于 SSD具有高性能、低延迟、低功耗、 环境适应性强等优点， 同时成本也在不断降低， 因此目前应用的越来越普遍。
SSD—般由 NAND flash芯片组成， 它存在固有的比特跳变、 读干扰等问题， 会导致读出的数据 出错， 同时还有擦写次数的限制， 因此在 NAND flash芯片的结构和 SSD设计上都采取了保证可靠性 的措施。 例如： NAND flash内部包括一个或多个晶片， 每个晶片包括多个平面， 每个平面包括多个 块， 每个块包括多个页。
其中页是读、 写数据的基本单元， 包括多个字节 (例如 2048+64字节）， 其中每 512字节 +16字 节为一个检错 /纠错单元， 512字节用来保存数据， 16字节用来保存检错 /纠错码。 当读取数据时， 每个 512+16字节的单元会进行校验， 如果出错的位数较少可以被纠正， 如果出错的位数太多无法纠 正就需要利用上层的纠错机制例如 RAID算法来解决。
NAND flash的块是基本的擦除单元， 每个块包括多个页 (例如 64个）。 为了修改 flash中已经 写入的数据， 必须先将该数据所在的块擦除， 然后才能写入新数据， 这是 flash的基本特征。
SSD在工作过程中需要不断执行擦除或写操作， 而 flash芯片在执行这两种操作的时候处于忙 状态 (通过芯片的硬件管脚 R/B#来表示， 高电平表示准备好， 低电平表示忙）， 不能再响应读操作， 只有等待擦除或写操作完成后才能继续执行读操作。 由于 NAND flash芯片的块擦除一般需要 3ms, 写操作一般需要 900us， 而读操作一般只需要 50us, 这样擦除和写操作会阻塞读操作， 造成较大的 读延时， 影响存储系统的性能， 在擦除或写操作特别频繁的场景下这种现象更为明显。
发明内容
本发明为解决现有的基于 flash芯片的存储设备在读、 写、 擦除同时存在的情况下， 读操作被 擦除和写操作阻塞， 从而造成较大读延时的问题， 提供了一种降低读延时的方法及装置。
本发明的实施例提供了一种降低读延时的方法， 包括：
当读命令对应的一个或多个 flash芯片处于忙状态时， 将处于忙状态的一个或多个 flash上读 取到的数据置为错误的数据；
根据所述错误的数据以及从其它 flash芯片上读取的数据获得重建后的正确数据， 并将所述正 确数据上报。
本发明的实施例还提供了一种降低读延时的装置， 包括：
置错单元， 用于当读命令对应的一个或多个 flash芯片处于忙状态时， 将处于忙状态的一个或 多个 flash上读取到的数据置为错误的数据； 重建上报单元， 用于根据所述错误的数据以及从其它 flash芯片上读取的数据获得重建后的正 确数据， 并将所述正确数据上报。
由上述本发明的实施例提供的技术方案可以看出， 通过从 flash芯片上读取到的数据置为错误 的数据， 并根据错误的数据以及从其它 flash芯片上读取的数据获得重建后的正确数据， 使 flash 芯片处于忙状态时能够避免读操作被擦除和写操作阻塞， 从而有效减少延时， 提高了存储系统的性 能。
附图简要说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例描述中所需要使用的附图作简单 地介绍， 显而易见地， 下面描述中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员来 讲， 在不付出创造性劳动性的前提下， 还可以根据这些附图获得其他的附图。
图 1为本发明的实施例提供的结合具体硬件的 SSD设备的结构示意图；
图 2为本发明的实施例提供的 SSD控制器的结构示意图；
图 3为本发明的实施例提供的降低读延时的方法的整体流程框图；
图 4为本发明的实施例提供的降低读延时的方法的流程示意图；
图 5为本发明的实施例提供的基于 RAID控制器的结合具体硬件的 SSD设备的结构示意图； 图 6为本发明的实施例提供的基于 RAID控制器的 SSD控制器的结构示意图；
图 7为本发明的实施例提供的降低读延时的装置的结构示意图。
实施本发明的方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行清楚、 完整地描述， 显 然， 所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的 范围。
本实施例提供了一种降低读延时的方法， 包括： 当读命令对应的一个或多个 flash芯片处于忙 状态时， 将处于忙状态的一个或多个 flash上读取到的数据置为错误的数据； 根据所述错误的数据 以及从其它 flash芯片上读取的数据获得重建后的正确数据， 并将所述正确数据上报。 本实施例提 供的技术方案主要应用在由主机、 SSD控制器以及多个通道的 flash组成的 SSD设备中， 相应的主 机通过 SSD控制器读写 flash中的数据。 其中， SSD设备的硬件结构包括一个服务器机框， 在服务 器机框中设有一块底板， 底板上安装有 CPU、 内存、 南桥等芯片， 用于对其它扩展卡进行控制， 实 现主机的功能； SSD控制器 （对 SSD内部的 flash进行控制） 也可采用芯片， 如 FPGA、 ASIC等， 通 过对这个芯片进行编程来完成接收主机的读写请求， 并对 SSD设备中的 flash芯片进行各种访问及 控制； SSD控制器对应的芯片可以与各个 flash都设置在一个 PCB板上， 通过 PCB走线相连， 最后 呈现的形式是一个硬盘盒， 通过 SATA或 SAS接口与底板相连， 或者也可以将 flash芯片和 SSD控制 器做成一个扩展卡， 通过 PCIe接口与底板相连。
一个结合具体硬件的 SSD设备的结构如图 1所示。 其中的 SSD控制器的结构如图 2所示， 包括 主机接口、检错 /纠错模块、 收发模块几个部分。相应的主机接口用来从主机接收各种命令及其对应 的地址、 数据， 例如读某个地址的数据或将数据写入某个地址等， 目前常见的接口是 SATA、 SAS、 PCIe; 收发模块用来完成数据或命令的收发； 检错 /纠错模块用于保证来自 flash数据的正确性， 然 后将数据上报给主机，主要完成两个功能： 1、将每个 flash通道的数据及其校验码进行检错和纠错， 如果超出纠错能力则调用 RAID算法恢复数据， 2、执行 RAID算法， 当某个通道的数据有错且无法纠 正时， 利用其他通道的正确数据恢复该通道数据； 收发模块用于接收来自多个通道的 flash数据或 状态， 其中数据再转发给检错 /纠错模块而状态一般不会返回主机（如果主机需要的话也会返回给主 机， 例如 SATA接口也可以査询 SSD的忙状态） ， 而是由收发模块自己使用， 或者将来自主机的命令 转换为 flash可以识别的命令， 或者将来自主机的数据写入多个通道的 flash, 同时还要满足 RAID 算法对数据排列方式的要求 (即条带方式）。
图 3所示的是本实施例提供的降低读延时的方法的整体流程框图， 下面结合说明书附图对本实 施例作详细说明， 如图 4所示， 该方法包括：
步骤 41， 当读命令对应的一个或多个 flash芯片处于忙状态时， 将处于忙状态的一个或多个 flash上读取到的数据置为错误的数据。
当主机下发读取 flash芯片数据的读命令时， 根据读命令中包含的地址信息， 确定该地址信息 对应的 flash芯片， 即对应于哪些 flash芯片组成的条带。另外，还査询上述地址信息对应的 flash 芯片的当前状态， 即是否处于忙状态。如果某个 flash芯片的当前状态为空闲，则将读取的该 flash 芯片的数据直接上报给 SSD设备的检错 /纠错模块； 如果其中某个 flash芯片处于忙状态， 则将来自 该 flash芯片的数据进行置错处理，使转发给检错 /纠错模块的数据不符合 flash芯片内部的校验规 则。 例如， 假设校验规则为偶校验， 那么收发模块构造一个不满足偶校验要求的数据， 并且让检错 / 纠错模块能够发现这个错误，从而触发该模块执行 RAID算法来纠正这个通道 flash芯片的错误数据。
其中， 各通道 flash芯片的忙 /闲状态可以通过软件方式、硬件方式或者软硬件结合的方式来实 现， 具体为：
①、软件方式： NAND flash的内部提供了一个状态寄存器，通过芯片状态读取命令 (read status) 可以得到该寄存器的值， 根据指定位的 0、 1状态就能知道 flash芯片的忙 /闲状态。 当主机下发读 数据的命令时， 需要将该命令对应的所有 flash芯片状态都读取一遍。
②、 硬件方式： NAND flash芯片还提供了一个 R/B#信号， 可以将它们都接入 SSD控制器， 通过 査询对应信号的电平状态就能知道 flash芯片的忙 /闲状态。
③、 软硬件结合方式： R/B#信号是漏级开路输出， 可以支持线与的连接方式， 可以将同一个通 道所有 flash芯片的该信号连接起来， 然后接入控制器， 这样信号线总数会减少很多。 SSD控制器 通过检测这个线与信号的电平可以知道是否某个通道有 flash 芯片处于忙状态， 然后再通过 read status命令来区分该通道下是哪一个 flash芯片处于忙状态。 如果要读取数据所在的 flash芯片处 于空闲状态， 可以直接读取数据； 如果所在的 flash芯片处于忙状态， 则读取到的数据置为错误的 数据。
并且， flash 芯片的状态査询命令 (read status)的发起不受芯片忙 /闲状态影响， 如果这个状 态査询命令是主机下发的， 则当收发模块取得对应通道上的 flash芯片状态之后， 不经过检错 /纠错 模块的处理而是直接上报给主机， 因为状态信息没有经过 RAID算法处理。
另外， flash 芯片内部的校验规则还可以采用具有检错和纠错能力的汉明码， 而且产生的错误 数据可以有很多选择， 可以在设计控制器的时候事先确定下来。 这是因为 flash芯片处于忙状态时 不能响应读数据的命令， 该命令会被忽略， 这样 SSD控制器读到的数据是不确定的， 可能通过检错 / 纠错模块的校验， 也可能通不过， 如果前一种情况发生就会把无效数据当成正确数据上报了， 所以 为了确保可靠性必须人为构造错误数据。
步骤 42， 根据所述错误的数据以及从其它 flash芯片上读取的数据获得重建后的正确数据， 并 将所述正确数据上报。
具体的， SSD设备的检错 /纠错模块会将每个通道的数据分别做校验，如果检测到有错误的数据， 则通过 RAID算法纠正， 否则直接上报给主机。 当检错 /纠错模块检测到从处于忙状态的 flash读取 的数据存在错误时， 会通过相应的 RAID算法纠正， 然后结合从其它通道得到的重建数据一起上报给 主机， 以完成相应的读操作。
检错 /纠错模块在发现某个通道的数据出错并将其纠正之后，一般会做错误统计， 当超出某个门 限时会上报给主机， 要求更换整个 SSD (对于 flash芯片无法单独更换的场合， 例如焊接在底板上） 或者更换某个通道上的 flash芯片 (对于 flash芯片可以单独更换的场合， 例如每个通道上的 flash 芯片组成一个可更换的模块）。由于本实施例是将处于忙状态的 flash芯片的通道数据当作错误数据 处理的， 而该通道的 flash芯片并未发生故障， 因此需要区分这种情况避免误判。 可以在收发模块 中定义一个标识位， 缺省为 0， 每次当该模块有意构造错误数据上报给检错 /纠错模块时， 标识位设 置为 1， 否则为 0， 于是检错 /纠错模块可以根据这个标识位来决定是否给错误计数器增值。
在重建数据的过程中，由于各通道 flash芯片的擦除、写命令都是由收发模块发出来的，而 MID 算法的数据重建能力有限， 例如 RAID5只能纠正一个通道上的错误， 因此必须根据具体的 AID算法 来限制任意时刻每个条带上处于忙状态的 flash芯片的数量， 这是由收发模块完成的。 它可以通过 控制每次向各通道上 flash芯片发出的擦除、 写命令数量， 并实时査询各通道上 flash芯片的忙 / 闲状态， 来保证每个条带上处于忙状态的 flash芯片数量不会超出 RAID算法重建数据的能力。
由于步骤 42中纠正的是人为制造的错误数据， 目的都是为了重建数据， 可以将来源不同的问题 统一处理， 相应的问题可以是 flash芯片的数据错误， 也可以是 flash芯片处于忙状态， 有利于模 块的重用。
本实施例还提供了一种通过 RAID控制器降低读延时的方法，为了进一步提高容错能力同时提高 性能， SSD控制器通常支持多个通道， 每个通道上连接多个 flash芯片， 而且按照 RAID模式工作。 另外， 多个 flash芯片按照 RAID算法将数据和校验码按条带方式保存， 当某个 flash芯片不可用时 可以通过条带上其他 flash芯片读取的数据恢复出来， 从而提高了可靠性。 RAID有多种类别， SSD 中常用的是 MID4和 RAID5, 其中 RAID4是将校验码固定保存在某个通道的所有 flash芯片上， 而 RAID5是将校验码逐一保存在多个通道的所有 flash芯片上。
与上述 SSD控制器的情形类似， RAID控制器也是一种常用的提高存储系统性能和可靠性的器件， 它与主机一般通过 PCI或 PCIe接口相连， 然后通过多个通道 (例如 8个)与硬盘相连 (可以是机械硬 盘或 SSD) , 每个通道采用 SAS或 FC接口并且只能连接一个硬盘， 如图 5所示。 一个具体的应用场 景示例如图 6所示， 机架服务器当中其中一个扩展卡为 RAID卡， RAID卡中有 RAID控制器， 与多个 SSD硬盘盒 （包括 SSD控制器及多个 Flash) 中的 SSD控制器相连； 多个扩展卡仍然通过 PCIe接口 与底板相连。
RAID控制器按照 RAID算法将数据以条带方式保存在多个 SSD上， 当主机通过 PCI/PCIe接口向
RAID控制器下发读数据请求时， 如果某个 SSD正在执行 NAND flash的擦除及写操作并且不具备相 应的数据重建功能，那么在 RAID控制器和 SSD之间必须按照上述实施例中 SSD控制器和 NAND flash 芯片那种方式来重建数据， 即： RAID控制器通过命令査询各通道 SSD的忙 /闲状态， 对处于忙状态 的 SSD， RAID控制器内部的数据收发模块将该通道的数据置为错误， 结合其它通道得到的有效数据 一起上报给 RAID控制器内部的检错 /纠错模块， RAID控制器内部的检错 /纠错模块先对各通道的数 据进行检测， 发现上述忙状态的通道数据有误， 则按照 RAID算法通过其他通道的数据重建该错误数 据， 然后通过 PCI/PCIe接口统一上报给主机。
采用本实施例提供的技术方案， 通过从 ash芯片上读取到的数据置为错误的数据， 并根据错 误的数据以及从其它 flash芯片上读取的数据获得重建后的正确数据， 使 flash芯片处于忙状态时 能够避免读操作被擦除和写操作阻塞， 从而有效减少延时， 提高了存储系统的性能。
需要说明的是， 本领域普通技术人员可以理解实现上述各方法实施例中的全部或部分步骤是可 以通过程序来指令相关的硬件完成， 相应的程序可以存储于一种计算机可读存储介质中， 上述提到 的存储介质可以是只读存储器， 磁盘或光盘等。
本发明的实施例还提供了一种降低读延时的装置， 如图 7所示， 包括：
置错单元 71， 用于当读命令对应的一个或多个 flash芯片处于忙状态时， 将处于忙状态的一个 或多个 flash上读取到的数据置为错误的数据；
重建上报单元 72， 用于根据所述错误的数据以及从其它 flash芯片上读取的数据获得重建后的 正确数据， 并将所述正确数据上报。
本实施例可以对 SSD控制器 （如 FPGA或类似的硬件芯片） 或 RAID控制器进行相应的编程， 制 得能够完成相应的功能的单元模块。 其中， 降低读延时的装置的各单元模块可设置在如图 2所示的 SSD控制器中， 也可以设置在如图 5所示的 RAID控制器中。
可选的， 在置错单元 71中可以包括： 判断子单元， 用于通过检测每个 flash芯片的忙 /闲信号 电平、通过下发读状态命令、或者同时检测每个 flash芯片的忙 /闲信号电平及下发读状态命令确定 flash芯片是否处于忙状态。
可选的， 在置错单元 71中， 读取 flash芯片数据的读命令通过 SATA、 SAS或 PCIe接口接收。 可选的， 在置错单元 71 中还可以包括： 读取子单元， 用于根据读命令报文携带的地址字段与 SSD内部的 flash芯片地址的对应关系确定所述读命令与 flash芯片的对应关系。
可选的， 在置错单元 71中， 置为错误的数据包括： 将读取的数据置为任何不符合 flash数据校 验规则的数据组合。
可选的， 在重建上报单元 72中可以包括： 重建子单元， 用于 SSD控制器接收到发送来的错误的 数据并检测到数据错误后， 启动纠错功能， 利用多组 flash存储单元之间存在的数据约束关系， 获 得重建后的正确数据。
可选的， 该装置还可以包括： 错误计数单元， 用于当检测到读数据错误并且标识位是 0时， 错 误计数器加 1 ; 当检测到读数据错误并且标识位是 1时， 错误计数器不变。
采用本实施例的方案， 通过从 flash芯片上读取到的数据置为错误的数据， 并根据错误的数据 以及从其它 flash芯片上读取的数据获得重建后的正确数据， 使 flash芯片处于忙状态时能够避免 读操作被擦除和写操作阻塞， 从而有效减少延时， 提高了存储系统的性能。
上述降低读延时的装置中包含的各单元的处理功能的具体实施方式在之前的方法实施方式中己 经描述， 在此不再重复描述。
本发明方案可以在由计算机执行的计算机可执行指令的一般上下文中描述， 例如程序单元。 一 般地， 程序单元包括执行特定任务或实现特定抽象数据类型的例程、 程序、 对象、 组件、 数据结构 等等。 也可以在分布式计算环境中实践本发明方案， 在这些分布式计算环境中， 由通过通信网络而 被连接的远程处理设备来执行任务。 在分布式计算环境中， 程序单元可以位于包括存储设备在内的 本地和远程计算机存储介质中。
本说明书中的各个实施例均采用递进的方式描述， 各个实施例之间相同相似的部分互相参见即 可， 每个实施例重点说明的都是与其他实施例的不同之处。 尤其， 对于装置实施例而言， 由于其基 本相似于方法实施例， 所以描述得比较简单， 相关之处参见方法实施例的部分说明即可。 以上所描 述的装置实施例仅仅是示意性的， 其中所述作为分离部件说明的单元可以是或者也可以不是物理上 分开的， 作为单元显示的部件可以是或者也可以不是物理单元， 即可以位于一个地方， 或者也可以 分布到多个网络单元上。 可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的 目的。 本领域普通技术人员在不付出创造性劳动的情况下， 即可以理解并实施。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤， 能够以电子硬件、 或者计算机软件和电子硬件的结合来实现。 这些功能究竟以硬件还是软件方式来 执行， 取决于技术方案的特定应用和设计约束条件。 专业技术人员可以对每个特定的应用来使用不 同方法来实现所描述的功能， 但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到， 为描述的方便和简洁， 上述描述的系统、 装置和单元 的具体工作过程， 可以参考前述方法实施例中的对应过程， 在此不再赘述。
在本申请所提供的几个实施例中， 应该理解到， 所揭露的系统、 装置和方法， 可以通过其它的 方式实现。 例如， 以上所描述的装置实施例仅仅是示意性的， 例如， 所述单元的划分， 仅仅为一种 逻辑功能划分， 实际实现时可以有另外的划分方式， 例如多个单元或组件可以结合或者可以集成到 另一个系统， 或一些特征可以忽略， 或不执行。 另一点， 所显示或讨论的相互之间的耦合或直接耦 合或通信连接可以是通过一些接口， 装置或单元的间接耦合或通信连接， 可以是电性， 机械或其它 的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的， 作为单元显示的部件可以 是或者也可以不是物理单元， 即可以位于一个地方， 或者也可以分布到多个网络单元上。 可以根据 实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外， 在本发明各个实施例中的各功能单元可以集成在一个处理单元中， 也可以是各个单元单 独物理存在， 也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时， 可以存储在一个计 算机可读取存储介质中。 基于这样的理解， 本发明的技术方案本质上或者说对现有技术做出贡献的 部分或者该技术方案的部分可以以软件产品的形式体现出来， 该计算机软件产品存储在一个存储介 质中， 包括若干指令用以使得一台计算机设备 （可以是个人计算机， 服务器， 或者网络设备等） 执 行本发明各个实施例所述方法的全部或部分步骤。 而前述的存储介质包括： U盘、 移动硬盘、 只读 存储器 （ROM, Read-Only Memory) 、 随机存取存储器 （RAM, Random Access Memory) 、 磁碟或者 光盘等各种可以存储程序代码的介质。
通过以上的实施方式的描述， 所属领域的技术人员可以清楚地了解到本发明可借助软件加必需 的通用硬件的方式来实现， 通用硬件包括通用集成电路、 通用 CPU、 通用存储器、 通用元器件等， 当然也可以通过专用硬件包括专用集成电路、 专用 CPU、 专用存储器、 专用元器件等来实现， 但很 多情况下前者是更佳的实施方式。 基于这样的理解， 本发明的技术方案本质上或者说对现有技术做 出贡献的部分可以以软件产品的形式体现出来， 该计算机软件产品存储在可读取的存储介质中， 如 计算机的软盘， 硬盘或光盘等， 包括若干指令用以使得一台计算机设备 （可以是个人计算机， 服务 器， 或者网络设备等） 执行本发明各个实施例的方法。
以上所述， 仅为本发明较佳的具体实施方式， 但本发明的保护范围并不局限于此， 任何熟悉本 技术领域的技术人员在本发明揭露的技术范围内， 可轻易想到的变化或替换， 都应涵盖在本发明的 保护范围之内。 因此， 本发明的保护范围应该以权利要求的保护范围为准。

Claims

权利要求
1、 一种降低读延时的方法， 其特征在于， 包括- 当读命令对应的一个或多个 ash芯片处于忙状态时， 将处于忙状态的一个或多个 flash上读 取到的数据置为错误的数据；
根据所述错误的数据以及从其它 flash芯片上读取的数据获得重建后的正确数据， 并将所述正 确数据上报。
2、 根据权利要求 1所述的方法， 其特征在于， 所述判断 flash芯片处于忙状态包括： 通过检测每个 flash芯片的忙 /闲信号电平、通过下发读状态命令、或者同时检测每个 flash芯 片的忙 /闲信号电平及下发读状态命令确定 flash芯片是否处于忙状态。
3、 根据权利要求 2所述的方法， 其特征在于， 所述读取 flash芯片数据的读命令通过 SATA、
SAS或 PCIe接口接收。
4、 根据权利要求 2或 3所述的方法， 其特征在于， 该方法还包括： 根据读命令报文携带的地址 字段与 SSD内部的 flash芯片地址的对应关系确定所述读命令与 flash芯片的对应关系。
5、根据权利要求 1所述的方法， 其特征在于， 所述置为错误的数据包括： 将读取的数据置为任 何不符合 flash数据校验规则的数据组合。
6、 根据权利要求 1所述的方法， 其特征在于， 所述获得重建后的正确数据包括：
SSD控制器接收到发送来的错误的数据并检测到数据错误后， 启动纠错功能， 利用多组 flash 存储单元之间存在的数据约束关系， 获得重建后的正确数据。
7、 根据权利要求 1所述的控制方法， 其特征在于， 该方法还包括：
当检测到读数据错误并且标识位是 0时， 错误计数器加 1 ; 当检测到读数据错误并且标识位是 1 时， 错误计数器不变。
8、 一种降低读延时的装置， 其特征在于， 包括：
置错单元， 用于当读命令对应的一个或多个 flash芯片处于忙状态时， 将处于忙状态的一个或 多个 flash上读取到的数据置为错误的数据；
重建上报单元， 用于根据所述错误的数据以及从其它 flash芯片上读取的数据获得重建后的正 确数据， 并将所述正确数据上报。
9、 根据权利要求 8所述的装置， 其特征在于， 在置错单元中包括：
判断子单元， 用于通过检测每个 flash芯片的忙 /闲信号电平、通过下发读状态命令、 或者同时 检测每个 flash芯片的忙 /闲信号电平及下发读状态命令确定 flash芯片是否处于忙状态。
10、 根据权利要求 9所述的装置， 其特征在于， 在置错单元中， 所述读取 flash芯片数据的读 命令通过 SATA、 SAS或 PCIe接口接收。
11、 根据权利要求 9或 10所述的装置， 其特征在于， 在置错单元中还包括：
读取子单元， 用于根据读命令报文携带的地址字段与 SSD内部的 flash芯片地址的对应关系确 定所述读命令与 flash芯片的对应关系。
12、 根据权利要求 8所述的装置， 其特征在于， 在置错单元中， 所述置为错误的数据包括： 将 读取的数据置为任何不符合 flash数据校验规则的数据组合。
13、 根据权利要求 8所述的装置， 其特征在于， 在重建上报单元中包括：
重建子单元，用于 SSD控制器接收到发送来的错误的数据并检测到数据错误后， 启动纠错功能, 利用多组 flash存储单元之间存在的数据约束关系， 获得重建后的正确数据。
14、 根据权利要求 8所述的装置， 其特征在于， 该装置还包括：
错误计数单元， 用于当检测到读数据错误并且标识位是 0时， 错误计数器加 1 ; 当检测到读数 据错误并且标识位是 1时， 错误计数器不变。
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